2 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
4 * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
6 * Special thanks to Fintek for providing hardware and spec sheets.
7 * This driver is based upon the nuvoton, ite and ene drivers for
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pnp.h>
32 #include <linux/interrupt.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <media/rc-core.h>
36 #include <linux/pci_ids.h>
38 #include "fintek-cir.h"
40 /* write val to config reg */
41 static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
43 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
44 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
45 outb(reg, fintek->cr_ip);
46 outb(val, fintek->cr_dp);
49 /* read val from config reg */
50 static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
54 outb(reg, fintek->cr_ip);
55 val = inb(fintek->cr_dp);
57 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
58 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
62 /* update config register bit without changing other bits */
63 static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
65 u8 tmp = fintek_cr_read(fintek, reg) | val;
66 fintek_cr_write(fintek, tmp, reg);
69 /* clear config register bit without changing other bits */
70 static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
72 u8 tmp = fintek_cr_read(fintek, reg) & ~val;
73 fintek_cr_write(fintek, tmp, reg);
76 /* enter config mode */
77 static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
79 /* Enabling Config Mode explicitly requires writing 2x */
80 outb(CONFIG_REG_ENABLE, fintek->cr_ip);
81 outb(CONFIG_REG_ENABLE, fintek->cr_ip);
84 /* exit config mode */
85 static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
87 outb(CONFIG_REG_DISABLE, fintek->cr_ip);
91 * When you want to address a specific logical device, write its logical
92 * device number to GCR_LOGICAL_DEV_NO
94 static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
96 fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
99 /* write val to cir config register */
100 static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
102 outb(val, fintek->cir_addr + offset);
105 /* read val from cir config register */
106 static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
110 val = inb(fintek->cir_addr + offset);
115 /* dump current cir register contents */
116 static void cir_dump_regs(struct fintek_dev *fintek)
118 fintek_config_mode_enable(fintek);
119 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
121 pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
122 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
123 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
124 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
125 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
126 fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
128 fintek_config_mode_disable(fintek);
130 pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
131 pr_info(" * STATUS: 0x%x\n",
132 fintek_cir_reg_read(fintek, CIR_STATUS));
133 pr_info(" * CONTROL: 0x%x\n",
134 fintek_cir_reg_read(fintek, CIR_CONTROL));
135 pr_info(" * RX_DATA: 0x%x\n",
136 fintek_cir_reg_read(fintek, CIR_RX_DATA));
137 pr_info(" * TX_CONTROL: 0x%x\n",
138 fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
139 pr_info(" * TX_DATA: 0x%x\n",
140 fintek_cir_reg_read(fintek, CIR_TX_DATA));
143 /* detect hardware features */
144 static int fintek_hw_detect(struct fintek_dev *fintek)
147 u8 chip_major, chip_minor;
148 u8 vendor_major, vendor_minor;
149 u8 portsel, ir_class;
153 fintek_config_mode_enable(fintek);
155 /* Check if we're using config port 0x4e or 0x2e */
156 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
157 if (portsel == 0xff) {
158 fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
159 fintek_config_mode_disable(fintek);
160 fintek->cr_ip = CR_INDEX_PORT2;
161 fintek->cr_dp = CR_DATA_PORT2;
162 fintek_config_mode_enable(fintek);
163 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
165 fit_dbg("portsel reg: 0x%02x", portsel);
167 ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
168 fit_dbg("ir_class reg: 0x%02x", ir_class);
173 fintek->hw_tx_capable = true;
177 fintek->hw_tx_capable = false;
181 chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
182 chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
183 chip = chip_major << 8 | chip_minor;
185 vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
186 vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
187 vendor = vendor_major << 8 | vendor_minor;
189 if (vendor != VENDOR_ID_FINTEK)
190 fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
192 fit_dbg("Read Fintek vendor ID from chip");
194 fintek_config_mode_disable(fintek);
196 spin_lock_irqsave(&fintek->fintek_lock, flags);
197 fintek->chip_major = chip_major;
198 fintek->chip_minor = chip_minor;
199 fintek->chip_vendor = vendor;
202 * Newer reviews of this chipset uses port 8 instead of 5
204 if ((chip != 0x0408) && (chip != 0x0804))
205 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
207 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;
209 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
214 static void fintek_cir_ldev_init(struct fintek_dev *fintek)
216 /* Select CIR logical device and enable */
217 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
218 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
220 /* Write allocated CIR address and IRQ information to hardware */
221 fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
222 fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);
224 fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);
226 fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
227 fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
230 /* enable CIR interrupts */
231 static void fintek_enable_cir_irq(struct fintek_dev *fintek)
233 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
236 static void fintek_cir_regs_init(struct fintek_dev *fintek)
238 /* clear any and all stray interrupts */
239 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
241 /* and finally, enable interrupts */
242 fintek_enable_cir_irq(fintek);
245 static void fintek_enable_wake(struct fintek_dev *fintek)
247 fintek_config_mode_enable(fintek);
248 fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);
250 /* Allow CIR PME's to wake system */
251 fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
252 /* Enable CIR PME's */
253 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
254 /* Clear CIR PME status register */
255 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
257 fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);
259 fintek_config_mode_disable(fintek);
262 static int fintek_cmdsize(u8 cmd, u8 subcmd)
267 case BUF_COMMAND_NULL:
268 if (subcmd == BUF_HW_CMD_HEADER)
271 case BUF_HW_CMD_HEADER:
272 if (subcmd == BUF_CMD_G_REVISION)
275 case BUF_COMMAND_HEADER:
277 case BUF_CMD_S_CARRIER:
278 case BUF_CMD_S_TIMEOUT:
279 case BUF_RSP_PULSE_COUNT:
282 case BUF_CMD_SIG_END:
283 case BUF_CMD_S_TXMASK:
284 case BUF_CMD_S_RXSENSOR:
293 /* process ir data stored in driver buffer */
294 static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
296 DEFINE_IR_RAW_EVENT(rawir);
300 for (i = 0; i < fintek->pkts; i++) {
301 sample = fintek->buf[i];
302 switch (fintek->parser_state) {
304 fintek->cmd = sample;
305 if ((fintek->cmd == BUF_COMMAND_HEADER) ||
306 ((fintek->cmd & BUF_COMMAND_MASK) !=
308 fintek->parser_state = SUBCMD;
311 fintek->rem = (fintek->cmd & BUF_LEN_MASK);
312 fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
314 fintek->parser_state = PARSE_IRDATA;
316 ir_raw_event_reset(fintek->rdev);
319 fintek->rem = fintek_cmdsize(fintek->cmd, sample);
320 fintek->parser_state = CMD_DATA;
327 init_ir_raw_event(&rawir);
328 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
329 rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK)
330 * CIR_SAMPLE_PERIOD);
332 fit_dbg("Storing %s with duration %d",
333 rawir.pulse ? "pulse" : "space",
335 ir_raw_event_store_with_filter(fintek->rdev, &rawir);
339 if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
340 fintek->parser_state = CMD_HEADER;
345 fit_dbg("Calling ir_raw_event_handle");
346 ir_raw_event_handle(fintek->rdev);
349 /* copy data from hardware rx register into driver buffer */
350 static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
355 spin_lock_irqsave(&fintek->fintek_lock, flags);
358 * We must read data from CIR_RX_DATA until the hardware IR buffer
359 * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
360 * the CIR_STATUS register
363 sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
364 fit_dbg("%s: sample: 0x%02x", __func__, sample);
366 fintek->buf[fintek->pkts] = sample;
369 status = fintek_cir_reg_read(fintek, CIR_STATUS);
370 if (!(status & CIR_STATUS_IRQ_EN))
372 } while (status & rx_irqs);
374 fintek_process_rx_ir_data(fintek);
376 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
379 static void fintek_cir_log_irqs(u8 status)
381 fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
382 status & CIR_STATUS_IRQ_EN ? " IRQEN" : "",
383 status & CIR_STATUS_TX_FINISH ? " TXF" : "",
384 status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "",
385 status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "",
386 status & CIR_STATUS_RX_RECEIVE ? " RXOK" : "");
389 /* interrupt service routine for incoming and outgoing CIR data */
390 static irqreturn_t fintek_cir_isr(int irq, void *data)
392 struct fintek_dev *fintek = data;
395 fit_dbg_verbose("%s firing", __func__);
397 fintek_config_mode_enable(fintek);
398 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
399 fintek_config_mode_disable(fintek);
402 * Get IR Status register contents. Write 1 to ack/clear
404 * bit: reg name - description
405 * 3: TX_FINISH - TX is finished
406 * 2: TX_UNDERRUN - TX underrun
407 * 1: RX_TIMEOUT - RX data timeout
408 * 0: RX_RECEIVE - RX data received
410 status = fintek_cir_reg_read(fintek, CIR_STATUS);
411 if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) {
412 fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
413 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
414 return IRQ_RETVAL(IRQ_NONE);
418 fintek_cir_log_irqs(status);
420 rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT);
422 fintek_get_rx_ir_data(fintek, rx_irqs);
424 /* ack/clear all irq flags we've got */
425 fintek_cir_reg_write(fintek, status, CIR_STATUS);
427 fit_dbg_verbose("%s done", __func__);
428 return IRQ_RETVAL(IRQ_HANDLED);
431 static void fintek_enable_cir(struct fintek_dev *fintek)
433 /* set IRQ enabled */
434 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
436 fintek_config_mode_enable(fintek);
438 /* enable the CIR logical device */
439 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
440 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
442 fintek_config_mode_disable(fintek);
444 /* clear all pending interrupts */
445 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
447 /* enable interrupts */
448 fintek_enable_cir_irq(fintek);
451 static void fintek_disable_cir(struct fintek_dev *fintek)
453 fintek_config_mode_enable(fintek);
455 /* disable the CIR logical device */
456 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
457 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
459 fintek_config_mode_disable(fintek);
462 static int fintek_open(struct rc_dev *dev)
464 struct fintek_dev *fintek = dev->priv;
467 spin_lock_irqsave(&fintek->fintek_lock, flags);
468 fintek_enable_cir(fintek);
469 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
474 static void fintek_close(struct rc_dev *dev)
476 struct fintek_dev *fintek = dev->priv;
479 spin_lock_irqsave(&fintek->fintek_lock, flags);
480 fintek_disable_cir(fintek);
481 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
484 /* Allocate memory, probe hardware, and initialize everything */
485 static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
487 struct fintek_dev *fintek;
491 fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
495 /* input device for IR remote (and tx) */
496 rdev = rc_allocate_device();
501 /* validate pnp resources */
502 if (!pnp_port_valid(pdev, 0)) {
503 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
507 if (!pnp_irq_valid(pdev, 0)) {
508 dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
512 fintek->cir_addr = pnp_port_start(pdev, 0);
513 fintek->cir_irq = pnp_irq(pdev, 0);
514 fintek->cir_port_len = pnp_port_len(pdev, 0);
516 fintek->cr_ip = CR_INDEX_PORT;
517 fintek->cr_dp = CR_DATA_PORT;
519 spin_lock_init(&fintek->fintek_lock);
521 pnp_set_drvdata(pdev, fintek);
524 ret = fintek_hw_detect(fintek);
528 /* Initialize CIR & CIR Wake Logical Devices */
529 fintek_config_mode_enable(fintek);
530 fintek_cir_ldev_init(fintek);
531 fintek_config_mode_disable(fintek);
533 /* Initialize CIR & CIR Wake Config Registers */
534 fintek_cir_regs_init(fintek);
536 /* Set up the rc device */
538 rdev->driver_type = RC_DRIVER_IR_RAW;
539 rdev->allowed_protos = RC_TYPE_ALL;
540 rdev->open = fintek_open;
541 rdev->close = fintek_close;
542 rdev->input_name = FINTEK_DESCRIPTION;
543 rdev->input_phys = "fintek/cir0";
544 rdev->input_id.bustype = BUS_HOST;
545 rdev->input_id.vendor = VENDOR_ID_FINTEK;
546 rdev->input_id.product = fintek->chip_major;
547 rdev->input_id.version = fintek->chip_minor;
548 rdev->dev.parent = &pdev->dev;
549 rdev->driver_name = FINTEK_DRIVER_NAME;
550 rdev->map_name = RC_MAP_RC6_MCE;
551 rdev->timeout = US_TO_NS(1000);
552 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
553 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
556 /* now claim resources */
557 if (!request_region(fintek->cir_addr,
558 fintek->cir_port_len, FINTEK_DRIVER_NAME))
561 if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
562 FINTEK_DRIVER_NAME, (void *)fintek))
565 ret = rc_register_device(rdev);
569 device_init_wakeup(&pdev->dev, true);
571 fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
573 cir_dump_regs(fintek);
578 free_irq(fintek->cir_irq, fintek);
580 release_region(fintek->cir_addr, fintek->cir_port_len);
582 rc_free_device(rdev);
588 static void __devexit fintek_remove(struct pnp_dev *pdev)
590 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
593 spin_lock_irqsave(&fintek->fintek_lock, flags);
595 fintek_disable_cir(fintek);
596 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
597 /* enable CIR Wake (for IR power-on) */
598 fintek_enable_wake(fintek);
599 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
602 free_irq(fintek->cir_irq, fintek);
603 release_region(fintek->cir_addr, fintek->cir_port_len);
605 rc_unregister_device(fintek->rdev);
610 static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
612 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
615 fit_dbg("%s called", __func__);
617 spin_lock_irqsave(&fintek->fintek_lock, flags);
619 /* disable all CIR interrupts */
620 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
622 spin_unlock_irqrestore(&fintek->fintek_lock, flags);
624 fintek_config_mode_enable(fintek);
626 /* disable cir logical dev */
627 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
628 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
630 fintek_config_mode_disable(fintek);
632 /* make sure wake is enabled */
633 fintek_enable_wake(fintek);
638 static int fintek_resume(struct pnp_dev *pdev)
641 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
643 fit_dbg("%s called", __func__);
646 fintek_enable_cir_irq(fintek);
648 /* Enable CIR logical device */
649 fintek_config_mode_enable(fintek);
650 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
651 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
653 fintek_config_mode_disable(fintek);
655 fintek_cir_regs_init(fintek);
660 static void fintek_shutdown(struct pnp_dev *pdev)
662 struct fintek_dev *fintek = pnp_get_drvdata(pdev);
663 fintek_enable_wake(fintek);
666 static const struct pnp_device_id fintek_ids[] = {
667 { "FIT0002", 0 }, /* CIR */
671 static struct pnp_driver fintek_driver = {
672 .name = FINTEK_DRIVER_NAME,
673 .id_table = fintek_ids,
674 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
675 .probe = fintek_probe,
676 .remove = __devexit_p(fintek_remove),
677 .suspend = fintek_suspend,
678 .resume = fintek_resume,
679 .shutdown = fintek_shutdown,
682 int fintek_init(void)
684 return pnp_register_driver(&fintek_driver);
687 void fintek_exit(void)
689 pnp_unregister_driver(&fintek_driver);
692 module_param(debug, int, S_IRUGO | S_IWUSR);
693 MODULE_PARM_DESC(debug, "Enable debugging output");
695 MODULE_DEVICE_TABLE(pnp, fintek_ids);
696 MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");
698 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
699 MODULE_LICENSE("GPL");
701 module_init(fintek_init);
702 module_exit(fintek_exit);