2 * Rockchip RK3288 VPU codec driver
4 * Copyright (C) 2014 Rockchip Electronics Co., Ltd.
5 * Alpha Lin <Alpha.Lin@rock-chips.com>
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
8 * Copyright (C) 2014 Google, Inc.
9 * Tomasz Figa <tfiga@chromium.org>
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include "rockchip_vpu_common.h"
23 #include <linux/types.h>
24 #include <linux/sort.h>
26 #include "rk3288_vpu_regs.h"
27 #include "rockchip_vpu_hw.h"
29 /* Various parameters specific to VP8 encoder. */
30 #define VP8_CABAC_CTX_OFFSET 192
31 #define VP8_CABAC_CTX_SIZE ((55 + 96) << 3)
33 #define VP8_KEY_FRAME_HDR_SIZE 10
34 #define VP8_INTER_FRAME_HDR_SIZE 3
36 #define VP8_FRAME_TAG_KEY_FRAME_BIT BIT(0)
37 #define VP8_FRAME_TAG_LENGTH_SHIFT 5
38 #define VP8_FRAME_TAG_LENGTH_MASK (0x7ffff << 5)
41 * struct rk3288_vpu_vp8e_ctrl_buf - hardware control buffer layout
42 * @ext_hdr_size: Ext header size in bytes (written by hardware).
43 * @dct_size: DCT partition size (written by hardware).
44 * @rsvd: Reserved for hardware.
46 struct rk3288_vpu_vp8e_ctrl_buf {
53 * The hardware takes care only of ext hdr and dct partition. The software
54 * must take care of frame header.
56 * Buffer layout as received from hardware:
57 * |<--gap-->|<--ext hdr-->|<-gap->|<---dct part---
58 * |<-------dct part offset------->|
60 * Required buffer layout:
61 * |<--hdr-->|<--ext hdr-->|<---dct part---
63 void rk3288_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
64 struct rockchip_vpu_buf *dst_buf)
66 struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&dst_buf->vb.vb2_buf);
67 size_t ext_hdr_size = dst_buf->vp8e.ext_hdr_size;
68 size_t dct_size = dst_buf->vp8e.dct_size;
69 size_t hdr_size = dst_buf->vp8e.hdr_size;
75 dst_size = vb2_plane_size(&dst_buf->vb.vb2_buf, 0);
76 dst = vb2_plane_vaddr(&dst_buf->vb.vb2_buf, 0);
77 tag = dst; /* To access frame tag words. */
79 if (WARN_ON(hdr_size + ext_hdr_size + dct_size > dst_size))
81 if (WARN_ON(dst_buf->vp8e.dct_offset + dct_size > dst_size))
84 memmove(dst + hdr_size + ext_hdr_size,
85 dst + dst_buf->vp8e.dct_offset, dct_size);
86 memcpy(dst, dst_buf->vp8e.header, hdr_size);
88 /* Patch frame tag at first 32-bit word of the frame. */
89 if (vb2_dst->flags & V4L2_BUF_FLAG_KEYFRAME) {
90 tag_size = VP8_KEY_FRAME_HDR_SIZE;
91 tag[0] &= ~VP8_FRAME_TAG_KEY_FRAME_BIT;
93 tag_size = VP8_INTER_FRAME_HDR_SIZE;
94 tag[0] |= VP8_FRAME_TAG_KEY_FRAME_BIT;
97 tag[0] &= ~VP8_FRAME_TAG_LENGTH_MASK;
98 tag[0] |= (hdr_size + ext_hdr_size - tag_size)
99 << VP8_FRAME_TAG_LENGTH_SHIFT;
101 vb2_set_plane_payload(&dst_buf->vb.vb2_buf, 0,
102 hdr_size + ext_hdr_size + dct_size);
105 static inline unsigned int ref_luma_size(unsigned int w, unsigned int h)
107 return round_up(w, MB_DIM) * round_up(h, MB_DIM);
110 int rk3288_vpu_vp8e_init(struct rockchip_vpu_ctx *ctx)
112 struct rockchip_vpu_dev *vpu = ctx->dev;
113 size_t height = ctx->src_fmt.height;
114 size_t width = ctx->src_fmt.width;
119 ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ctrl_buf,
120 sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
122 vpu_err("failed to allocate ctrl buffer\n");
126 mv_size = DIV_ROUND_UP(width, 16) * DIV_ROUND_UP(height, 16) / 4;
127 ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.mv_buf, mv_size);
129 vpu_err("failed to allocate MV buffer\n");
133 ref_buf_size = ref_luma_size(width, height) * 3 / 2;
134 ret = rockchip_vpu_aux_buf_alloc(vpu, &ctx->hw.vp8e.ext_buf,
137 vpu_err("failed to allocate ext buffer\n");
144 rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
146 rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
151 void rk3288_vpu_vp8e_exit(struct rockchip_vpu_ctx *ctx)
153 struct rockchip_vpu_dev *vpu = ctx->dev;
155 rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ext_buf);
156 rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.mv_buf);
157 rockchip_vpu_aux_buf_free(vpu, &ctx->hw.vp8e.ctrl_buf);
160 static inline u32 enc_in_img_ctrl(struct rockchip_vpu_ctx *ctx)
162 struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
163 struct v4l2_rect *crop = &ctx->src_crop;
164 unsigned bytes_per_line, overfill_r, overfill_b;
167 * The hardware needs only the value for luma plane, because
168 * values of other planes are calculated internally based on
171 bytes_per_line = pix_fmt->plane_fmt[0].bytesperline;
172 overfill_r = (pix_fmt->width - crop->width) / 4;
173 overfill_b = pix_fmt->height - crop->height;
175 return VEPU_REG_IN_IMG_CTRL_ROW_LEN(bytes_per_line)
176 | VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(overfill_r)
177 | VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(overfill_b)
178 | VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
181 static void rk3288_vpu_vp8e_set_buffers(struct rockchip_vpu_dev *vpu,
182 struct rockchip_vpu_ctx *ctx)
184 struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&ctx->run.dst->vb.vb2_buf);
185 const struct rk3288_vp8e_reg_params *params =
186 (struct rk3288_vp8e_reg_params *)ctx->run.vp8e.reg_params;
187 dma_addr_t ref_buf_dma, rec_buf_dma;
188 dma_addr_t stream_dma;
194 rounded_size = ref_luma_size(ctx->src_fmt.width,
195 ctx->src_fmt.height);
197 ref_buf_dma = rec_buf_dma = ctx->hw.vp8e.ext_buf.dma;
198 if (ctx->hw.vp8e.ref_rec_ptr)
199 ref_buf_dma += rounded_size * 3 / 2;
201 rec_buf_dma += rounded_size * 3 / 2;
202 ctx->hw.vp8e.ref_rec_ptr ^= 1;
204 if (rockchip_vpu_ctx_is_dummy_encode(ctx)) {
205 dst_dma = vpu->dummy_encode_dst.dma;
206 dst_size = vpu->dummy_encode_dst.size;
208 dst_dma = vb2_dma_contig_plane_dma_addr(&ctx->run.dst->vb.vb2_buf, 0);
209 dst_size = vb2_plane_size(&ctx->run.dst->vb.vb2_buf, 0);
214 * align 64bits->|<-start offset->|
215 * |<---------header size-------->|<---dst buf---
217 start_offset = (params->rlc_ctrl & VEPU_REG_RLC_CTRL_STR_OFFS_MASK)
218 >> VEPU_REG_RLC_CTRL_STR_OFFS_SHIFT;
219 stream_dma = dst_dma + params->hdr_len;
222 * Userspace will pass 8 bytes aligned size(round_down) to us,
223 * so we need to plus start offset to get real header size.
225 * |<-aligned size->|<-start offset->|
226 * |<----------header size---------->|
228 ctx->run.dst->vp8e.hdr_size = params->hdr_len + (start_offset >> 3);
230 if (params->enc_ctrl & VEPU_REG_ENC_CTRL_KEYFRAME_BIT)
231 vb2_dst->flags |= V4L2_BUF_FLAG_KEYFRAME;
233 vb2_dst->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
236 * We assume here that 1/10 of the buffer is enough for headers.
237 * DCT partition will be placed in remaining 9/10 of the buffer.
239 ctx->run.dst->vp8e.dct_offset = round_up(dst_size / 10, 8);
241 /* Destination buffer. */
242 vepu_write_relaxed(vpu, stream_dma, VEPU_REG_ADDR_OUTPUT_STREAM);
243 vepu_write_relaxed(vpu, dst_dma + ctx->run.dst->vp8e.dct_offset,
244 VEPU_REG_ADDR_VP8_DCT_PART(0));
245 vepu_write_relaxed(vpu, dst_size - ctx->run.dst->vp8e.dct_offset,
246 VEPU_REG_STR_BUF_LIMIT);
248 /* Auxilliary buffers. */
249 vepu_write_relaxed(vpu, ctx->hw.vp8e.ctrl_buf.dma,
250 VEPU_REG_ADDR_OUTPUT_CTRL);
251 vepu_write_relaxed(vpu, ctx->hw.vp8e.mv_buf.dma,
252 VEPU_REG_ADDR_MV_OUT);
253 vepu_write_relaxed(vpu, ctx->run.priv_dst.dma,
254 VEPU_REG_ADDR_VP8_PROB_CNT);
255 vepu_write_relaxed(vpu, ctx->run.priv_src.dma + VP8_CABAC_CTX_OFFSET,
256 VEPU_REG_ADDR_CABAC_TBL);
257 vepu_write_relaxed(vpu, ctx->run.priv_src.dma
258 + VP8_CABAC_CTX_OFFSET + VP8_CABAC_CTX_SIZE,
259 VEPU_REG_ADDR_VP8_SEG_MAP);
261 /* Reference buffers. */
262 vepu_write_relaxed(vpu, ref_buf_dma,
263 VEPU_REG_ADDR_REF_LUMA);
264 vepu_write_relaxed(vpu, ref_buf_dma + rounded_size,
265 VEPU_REG_ADDR_REF_CHROMA);
267 /* Reconstruction buffers. */
268 vepu_write_relaxed(vpu, rec_buf_dma,
269 VEPU_REG_ADDR_REC_LUMA);
270 vepu_write_relaxed(vpu, rec_buf_dma + rounded_size,
271 VEPU_REG_ADDR_REC_CHROMA);
274 if (rockchip_vpu_ctx_is_dummy_encode(ctx)) {
275 vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_Y].dma,
276 VEPU_REG_ADDR_IN_LUMA);
277 vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_CB].dma,
278 VEPU_REG_ADDR_IN_CB);
279 vepu_write_relaxed(vpu, vpu->dummy_encode_src[PLANE_CR].dma,
280 VEPU_REG_ADDR_IN_CR);
282 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(
283 &ctx->run.src->vb.vb2_buf, PLANE_Y),
284 VEPU_REG_ADDR_IN_LUMA);
285 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(
286 &ctx->run.src->vb.vb2_buf, PLANE_CB),
287 VEPU_REG_ADDR_IN_CB);
288 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(
289 &ctx->run.src->vb.vb2_buf, PLANE_CR),
290 VEPU_REG_ADDR_IN_CR);
293 /* Source parameters. */
294 vepu_write_relaxed(vpu, enc_in_img_ctrl(ctx), VEPU_REG_IN_IMG_CTRL);
297 static void rk3288_vpu_vp8e_set_params(struct rockchip_vpu_dev *vpu,
298 struct rockchip_vpu_ctx *ctx)
300 const struct rk3288_vp8e_reg_params *params =
301 (struct rk3288_vp8e_reg_params *)ctx->run.vp8e.reg_params;
304 vepu_write_relaxed(vpu, params->enc_ctrl0, VEPU_REG_ENC_CTRL0);
305 vepu_write_relaxed(vpu, params->enc_ctrl1, VEPU_REG_ENC_CTRL1);
306 vepu_write_relaxed(vpu, params->enc_ctrl2, VEPU_REG_ENC_CTRL2);
307 vepu_write_relaxed(vpu, params->enc_ctrl3, VEPU_REG_ENC_CTRL3);
308 vepu_write_relaxed(vpu, params->enc_ctrl5, VEPU_REG_ENC_CTRL5);
309 vepu_write_relaxed(vpu, params->enc_ctrl4, VEPU_REG_ENC_CTRL4);
310 vepu_write_relaxed(vpu, params->str_hdr_rem_msb,
311 VEPU_REG_STR_HDR_REM_MSB);
312 vepu_write_relaxed(vpu, params->str_hdr_rem_lsb,
313 VEPU_REG_STR_HDR_REM_LSB);
314 vepu_write_relaxed(vpu, params->mad_ctrl, VEPU_REG_MAD_CTRL);
316 for (i = 0; i < ARRAY_SIZE(params->qp_val); ++i)
317 vepu_write_relaxed(vpu, params->qp_val[i],
318 VEPU_REG_VP8_QP_VAL(i));
320 vepu_write_relaxed(vpu, params->bool_enc, VEPU_REG_VP8_BOOL_ENC);
321 vepu_write_relaxed(vpu, params->vp8_ctrl0, VEPU_REG_VP8_CTRL0);
322 vepu_write_relaxed(vpu, params->rlc_ctrl, VEPU_REG_RLC_CTRL);
323 vepu_write_relaxed(vpu, params->mb_ctrl, VEPU_REG_MB_CTRL);
325 for (i = 0; i < ARRAY_SIZE(params->rgb_yuv_coeff); ++i)
326 vepu_write_relaxed(vpu, params->rgb_yuv_coeff[i],
327 VEPU_REG_RGB_YUV_COEFF(i));
329 vepu_write_relaxed(vpu, params->rgb_mask_msb,
330 VEPU_REG_RGB_MASK_MSB);
331 vepu_write_relaxed(vpu, params->intra_area_ctrl,
332 VEPU_REG_INTRA_AREA_CTRL);
333 vepu_write_relaxed(vpu, params->cir_intra_ctrl,
334 VEPU_REG_CIR_INTRA_CTRL);
335 vepu_write_relaxed(vpu, params->first_roi_area,
336 VEPU_REG_FIRST_ROI_AREA);
337 vepu_write_relaxed(vpu, params->second_roi_area,
338 VEPU_REG_SECOND_ROI_AREA);
339 vepu_write_relaxed(vpu, params->mvc_ctrl,
342 for (i = 0; i < ARRAY_SIZE(params->intra_penalty); ++i)
343 vepu_write_relaxed(vpu, params->intra_penalty[i],
344 VEPU_REG_VP8_INTRA_PENALTY(i));
346 for (i = 0; i < ARRAY_SIZE(params->seg_qp); ++i)
347 vepu_write_relaxed(vpu, params->seg_qp[i],
348 VEPU_REG_VP8_SEG_QP(i));
350 for (i = 0; i < ARRAY_SIZE(params->dmv_4p_1p_penalty); ++i)
351 vepu_write_relaxed(vpu, params->dmv_4p_1p_penalty[i],
352 VEPU_REG_DMV_4P_1P_PENALTY(i));
354 for (i = 0; i < ARRAY_SIZE(params->dmv_qpel_penalty); ++i)
355 vepu_write_relaxed(vpu, params->dmv_qpel_penalty[i],
356 VEPU_REG_DMV_QPEL_PENALTY(i));
358 vepu_write_relaxed(vpu, params->vp8_ctrl1, VEPU_REG_VP8_CTRL1);
359 vepu_write_relaxed(vpu, params->bit_cost_golden,
360 VEPU_REG_VP8_BIT_COST_GOLDEN);
362 for (i = 0; i < ARRAY_SIZE(params->loop_flt_delta); ++i)
363 vepu_write_relaxed(vpu, params->loop_flt_delta[i],
364 VEPU_REG_VP8_LOOP_FLT_DELTA(i));
367 void rk3288_vpu_vp8e_run(struct rockchip_vpu_ctx *ctx)
369 struct vb2_v4l2_buffer *vb2_dst = to_vb2_v4l2_buffer(&ctx->run.dst->vb.vb2_buf);
370 struct rockchip_vpu_dev *vpu = ctx->dev;
373 /* The hardware expects the control buffer to be zeroed. */
374 memset(ctx->hw.vp8e.ctrl_buf.cpu, 0,
375 sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
378 * Program the hardware.
380 rockchip_vpu_power_on(vpu);
382 vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_VP8,
385 rk3288_vpu_vp8e_set_params(vpu, ctx);
386 rk3288_vpu_vp8e_set_buffers(vpu, ctx);
388 /* Make sure that all registers are written at this point. */
391 /* Set the watchdog. */
392 schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
394 /* Start the hardware. */
395 reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16
396 | VEPU_REG_AXI_CTRL_INPUT_SWAP16
397 | VEPU_REG_AXI_CTRL_BURST_LEN(16)
398 | VEPU_REG_AXI_CTRL_GATE_BIT
399 | VEPU_REG_AXI_CTRL_OUTPUT_SWAP32
400 | VEPU_REG_AXI_CTRL_INPUT_SWAP32
401 | VEPU_REG_AXI_CTRL_OUTPUT_SWAP8
402 | VEPU_REG_AXI_CTRL_INPUT_SWAP8;
403 vepu_write(vpu, reg, VEPU_REG_AXI_CTRL);
405 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
407 reg = VEPU_REG_ENC_CTRL_NAL_MODE_BIT
408 | VEPU_REG_ENC_CTRL_WIDTH(MB_WIDTH(ctx->src_fmt.width))
409 | VEPU_REG_ENC_CTRL_HEIGHT(MB_HEIGHT(ctx->src_fmt.height))
410 | VEPU_REG_ENC_CTRL_ENC_MODE_VP8
411 | VEPU_REG_ENC_CTRL_EN_BIT;
413 if (vb2_dst->flags & V4L2_BUF_FLAG_KEYFRAME)
414 reg |= VEPU_REG_ENC_CTRL_KEYFRAME_BIT;
416 vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
419 void rk3288_vpu_vp8e_done(struct rockchip_vpu_ctx *ctx,
420 enum vb2_buffer_state result)
422 struct rk3288_vpu_vp8e_ctrl_buf *ctrl_buf = ctx->hw.vp8e.ctrl_buf.cpu;
424 /* Read length information of this run from utility buffer. */
425 ctx->run.dst->vp8e.ext_hdr_size = ctrl_buf->ext_hdr_size;
426 ctx->run.dst->vp8e.dct_size = ctrl_buf->dct_size;
428 rockchip_vpu_run_done(ctx, result);
432 * WAR for encoder state corruption after decoding
435 static const struct rockchip_reg_params dummy_encode_reg_params = {
437 /* 00000014 */ .hdr_len = 0x00000000,
438 /* 00000038 */ .enc_ctrl = VEPU_REG_ENC_CTRL_KEYFRAME_BIT,
439 /* 00000040 */ .enc_ctrl0 = 0x00000000,
440 /* 00000044 */ .enc_ctrl1 = 0x00000000,
441 /* 00000048 */ .enc_ctrl2 = 0x00040014,
442 /* 0000004c */ .enc_ctrl3 = 0x404083c0,
443 /* 00000050 */ .enc_ctrl5 = 0x01006bff,
444 /* 00000054 */ .enc_ctrl4 = 0x00000039,
445 /* 00000058 */ .str_hdr_rem_msb = 0x85848805,
446 /* 0000005c */ .str_hdr_rem_lsb = 0x02000000,
447 /* 00000064 */ .mad_ctrl = 0x00000000,
448 /* 0000006c */ .qp_val = {
449 /* 0000006c */ 0x020213b1,
450 /* 00000070 */ 0x02825249,
451 /* 00000074 */ 0x048409d8,
452 /* 00000078 */ 0x03834c30,
453 /* 0000007c */ 0x020213b1,
454 /* 00000080 */ 0x02825249,
455 /* 00000084 */ 0x00340e0d,
456 /* 00000088 */ 0x401c1a15,
458 /* 0000008c */ .bool_enc = 0x00018140,
459 /* 00000090 */ .vp8_ctrl0 = 0x000695c0,
460 /* 00000094 */ .rlc_ctrl = 0x14000000,
461 /* 00000098 */ .mb_ctrl = 0x00000000,
462 /* 000000d4 */ .rgb_yuv_coeff = {
463 /* 000000d4 */ 0x962b4c85,
464 /* 000000d8 */ 0x90901d50,
466 /* 000000dc */ .rgb_mask_msb = 0x0000b694,
467 /* 000000e0 */ .intra_area_ctrl = 0xffffffff,
468 /* 000000e4 */ .cir_intra_ctrl = 0x00000000,
469 /* 000000f0 */ .first_roi_area = 0xffffffff,
470 /* 000000f4 */ .second_roi_area = 0xffffffff,
471 /* 000000f8 */ .mvc_ctrl = 0x01780000,
472 /* 00000100 */ .intra_penalty = {
473 /* 00000100 */ 0x00010005,
474 /* 00000104 */ 0x00015011,
475 /* 00000108 */ 0x0000c005,
476 /* 0000010c */ 0x00016010,
477 /* 00000110 */ 0x0001a018,
478 /* 00000114 */ 0x00018015,
479 /* 00000118 */ 0x0001d01a,
481 /* 00000120 */ .seg_qp = {
482 /* 00000120 */ 0x020213b1,
483 /* 00000124 */ 0x02825249,
484 /* 00000128 */ 0x048409d8,
485 /* 0000012c */ 0x03834c30,
486 /* 00000130 */ 0x020213b1,
487 /* 00000134 */ 0x02825249,
488 /* 00000138 */ 0x00340e0d,
489 /* 0000013c */ 0x341c1a15,
490 /* 00000140 */ 0x020213b1,
491 /* 00000144 */ 0x02825249,
492 /* 00000148 */ 0x048409d8,
493 /* 0000014c */ 0x03834c30,
494 /* 00000150 */ 0x020213b1,
495 /* 00000154 */ 0x02825249,
496 /* 00000158 */ 0x00340e0d,
497 /* 0000015c */ 0x341c1a15,
498 /* 00000160 */ 0x020213b1,
499 /* 00000164 */ 0x02825249,
500 /* 00000168 */ 0x048409d8,
501 /* 0000016c */ 0x03834c30,
502 /* 00000170 */ 0x020213b1,
503 /* 00000174 */ 0x02825249,
504 /* 00000178 */ 0x00340e0d,
505 /* 0000017c */ 0x341c1a15,
507 /* 00000180 */ .dmv_4p_1p_penalty = {
508 /* 00000180 */ 0x00020406,
509 /* 00000184 */ 0x080a0c0e,
510 /* 00000188 */ 0x10121416,
511 /* 0000018c */ 0x181a1c1e,
512 /* 00000190 */ 0x20222426,
513 /* 00000194 */ 0x282a2c2e,
514 /* 00000198 */ 0x30323436,
515 /* 0000019c */ 0x383a3c3e,
516 /* 000001a0 */ 0x40424446,
517 /* 000001a4 */ 0x484a4c4e,
518 /* 000001a8 */ 0x50525456,
519 /* 000001ac */ 0x585a5c5e,
520 /* 000001b0 */ 0x60626466,
521 /* 000001b4 */ 0x686a6c6e,
522 /* 000001b8 */ 0x70727476,
523 /* NOTE: Further 17 registers set to 0. */
526 * NOTE: Following registers all set to 0:
527 * - dmv_qpel_penalty,
535 const struct rockchip_reg_params *rk3288_vpu_vp8e_get_dummy_params(void)
537 return &dummy_encode_reg_params;