drivers/media/platform/rk-isp10/cif_isp10_rk3399.c

   1 /*
   2  *************************************************************************
   3  * Rockchip driver for CIF ISP 1.0
   4  * (Based on Intel driver for sofiaxxx)
   5  *
   6  * Copyright (C) 2015 Intel Mobile Communications GmbH
   7  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
   8  *
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *************************************************************************
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/regmap.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <linux/clk.h>
  22 #include <linux/reset.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/kernel.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/platform_data/rk_isp10_platform.h>
  28
  29 #define VI_IRCL               0x0014
  30 #define MRV_MIPI_BASE         0x1C00
  31 #define MRV_MIPI_CTRL         0x00
  32 /*
  33  * GRF_IO_VSEL
  34  */
  35 #define GRF_IO_VSEL_OFFSET    (0x0900)
  36 #define DVP_V18SEL            ((1 << 1) | (1 << 17))
  37 #define DVP_V33SEL            ((0 << 1) | (1 << 17))
  38 /*
  39  * GRF_IO_VSEL
  40  */
  41 #define GRF_GPIO2B_E_OFFSET   (0x0204)
  42 #define CIF_CLKOUT_STRENGTH(a)  \
  43                         ((((a) & 0x03) << 3) | (0x03 << 19))
  44 #define GRF_SOC_STATUS1       (0x0e2a4)
  45
  46 #define GRF_SOC_CON9_OFFSET   (0x6224)
  47 #define DPHY_RX0_TURNREQUEST_MASK     (0xF << 16)
  48 #define DPHY_RX0_TURNREQUEST_BIT      (0)
  49
  50 #define GRF_SOC_CON21_OFFSET          (0x6254)
  51 #define DPHY_RX0_FORCERXMODE_MASK     (0xF << 20)
  52 #define DPHY_RX0_FORCERXMODE_BIT      (4)
  53 #define DPHY_RX0_FORCETXSTOPMODE_MASK (0xF << 24)
  54 #define DPHY_RX0_FORCETXSTOPMODE_BIT  (8)
  55 #define DPHY_RX0_TURNDISABLE_MASK     (0xF << 28)
  56 #define DPHY_RX0_TURNDISABLE_BIT      (12)
  57 #define DPHY_RX0_ENABLE_MASK          (0xF << 16)
  58 #define DPHY_RX0_ENABLE_BIT           (0)
  59
  60 #define GRF_SOC_CON23_OFFSET          (0x625c)
  61 #define DPHY_TX1RX1_TURNDISABLE_MASK  (0xF << 28)
  62 #define DPHY_TX1RX1_TURNDISABLE_BIT   (12)
  63 #define DPHY_TX1RX1_FORCERXMODE_MASK  (0xF << 20)
  64 #define DPHY_TX1RX1_FORCERXMODE_BIT   (4)
  65 #define DPHY_TX1RX1_FORCETXSTOPMODE_MASK   (0xF << 24)
  66 #define DPHY_TX1RX1_FORCETXSTOPMODE_BIT    (8)
  67 #define DPHY_TX1RX1_ENABLE_MASK            (0xF << 16)
  68 #define DPHY_TX1RX1_ENABLE_BIT             (0)
  69
  70 #define GRF_SOC_CON24_OFFSET               (0x6260)
  71 #define DPHY_TX1RX1_MASTERSLAVEZ_MASK      (0x1 << 23)
  72 #define DPHY_TX1RX1_MASTERSLAVEZ_BIT       (7)
  73 #define DPHY_TX1RX1_BASEDIR_MASK           (0x1 << 21)
  74 #define DPHY_TX1RX1_BASEDIR_BIT            (5)
  75 #define DPHY_RX1_MASK                      (0x1 << 20)
  76 #define DPHY_RX1_SEL_BIT                   (4)
  77
  78 #define GRF_SOC_CON25_OFFSET               (0x6264)
  79 #define DPHY_RX0_TESTCLK_MASK              (0x1 << 25)
  80 #define DPHY_RX0_TESTCLK_BIT               (9)
  81 #define DPHY_RX0_TESTCLR_MASK              (0x1 << 26)
  82 #define DPHY_RX0_TESTCLR_BIT               (10)
  83 #define DPHY_RX0_TESTDIN_MASK              (0xFF << 16)
  84 #define DPHY_RX0_TESTDIN_BIT               (0)
  85 #define DPHY_RX0_TESTEN_MASK               (0x1 << 24)
  86 #define DPHY_RX0_TESTEN_BIT                (8)
  87
  88 #define DPHY_TX1RX1_TURNREQUEST_MASK       (0xF << 16)
  89 #define DPHY_TX1RX1_TURNREQUEST_BIT        (0)
  90
  91 #define DSIHOST_PHY_SHUTDOWNZ              (0x00a0)
  92 #define DSIHOST_DPHY_RSTZ                  (0x00a0)
  93 #define DSIHOST_PHY_TEST_CTRL0             (0x00b4)
  94 #define DSIHOST_PHY_TEST_CTRL1             (0x00b8)
  95
  96 #define write_cifisp_reg(addr, val)     \
  97                 __raw_writel(val, (addr) + rk3399->isp_base)
  98 #define read_cifisp_reg(addr)   \
  99                 __raw_readl((addr) + rk3399->isp_base)
 100
 101 #define write_grf_reg(addr, val)        \
 102                 regmap_write(rk3399->regmap_grf, addr, val)
 103 #define read_grf_reg(addr, val) \
 104                 regmap_read(rk3399->regmap_grf, addr, val)
 105
 106 #define write_dsihost_reg(addr, val)    \
 107                 __raw_writel(val, (addr) + rk3399->dsihost_base)
 108 #define read_dsihost_reg(addr)  \
 109                 __raw_readl((addr) + rk3399->dsihost_base)
 110
 111 struct cif_isp10_clk_rst_rk3399 {
 112         struct clk      *hclk_isp0_noc;
 113         struct clk      *hclk_isp0_wrapper;
 114         struct clk      *hclk_isp1_noc;
 115         struct clk      *hclk_isp1_wrapper;
 116         struct clk      *aclk_isp0_noc;
 117         struct clk      *aclk_isp0_wrapper;
 118         struct clk      *aclk_isp1_noc;
 119         struct clk      *aclk_isp1_wrapper;
 120         struct clk      *clk_isp0;
 121         struct clk      *clk_isp1;
 122         struct clk      *pclkin_isp1;
 123         struct clk      *pclk_dphy_ref;
 124         struct clk      *pclk_dphytxrx;
 125         struct clk      *pclk_dphyrx;
 126         struct clk      *cif_clk_out;
 127         struct clk      *cif_clk_pll;
 128         struct clk      *cif_clk_mipi_dsi;
 129         struct clk      *cif_clk_mipi_dphy_cfg;
 130 };
 131
 132 struct cif_isp10_rk3399 {
 133         struct regmap *regmap_grf;
 134         void __iomem *dsihost_base;
 135         void __iomem *isp_base;
 136         struct cif_isp10_clk_rst_rk3399 clk_rst;
 137         struct cif_isp10_device *cif_isp10;
 138 };
 139
 140 struct mipi_dphy_hsfreqrange {
 141         unsigned int range_l;
 142         unsigned int range_h;
 143         unsigned char cfg_bit;
 144 };
 145
 146 static struct mipi_dphy_hsfreqrange mipi_dphy_hsfreq_range[] = {
 147         {80, 90, 0x00},
 148         {90, 100, 0x10},
 149         {100, 110, 0x20},
 150         {110, 130, 0x01},
 151         {130, 140, 0x11},
 152         {140, 150, 0x21},
 153         {150, 170, 0x02},
 154         {170, 180, 0x12},
 155         {180, 200, 0x22},
 156         {200, 220, 0x03},
 157         {220, 240, 0x13},
 158         {240, 250, 0x23},
 159         {250, 270, 0x4},
 160         {270, 300, 0x14},
 161         {300, 330, 0x5},
 162         {330, 360, 0x15},
 163         {360, 400, 0x25},
 164         {400, 450, 0x06},
 165         {450, 500, 0x16},
 166         {500, 550, 0x07},
 167         {550, 600, 0x17},
 168         {600, 650, 0x08},
 169         {650, 700, 0x18},
 170         {700, 750, 0x09},
 171         {750, 800, 0x19},
 172         {800, 850, 0x29},
 173         {850, 900, 0x39},
 174         {900, 950, 0x0a},
 175         {950, 1000, 0x1a},
 176         {1000, 1050, 0x2a},
 177         {1100, 1150, 0x3a},
 178         {1150, 1200, 0x0b},
 179         {1200, 1250, 0x1b},
 180         {1250, 1300, 0x2b},
 181         {1300, 1350, 0x0c},
 182         {1350, 1400, 0x1c},
 183         {1400, 1450, 0x2c},
 184         {1450, 1500, 0x3c}
 185 };
 186
 187 static struct cif_isp10_rk3399 *rk3399;
 188 static int mipi_dphy0_wr_reg(unsigned char addr, unsigned char data)
 189 {
 190         /*
 191          * TESTCLK=1
 192          * TESTEN =1,TESTDIN=addr
 193          * TESTCLK=0
 194          */
 195         write_grf_reg(GRF_SOC_CON25_OFFSET,
 196                 DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
 197         write_grf_reg(GRF_SOC_CON25_OFFSET,
 198                 ((addr << DPHY_RX0_TESTDIN_BIT) | DPHY_RX0_TESTDIN_MASK
 199                  | (1 << DPHY_RX0_TESTEN_BIT) | DPHY_RX0_TESTEN_MASK));
 200         write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
 201
 202         /*
 203          * write data:
 204          * TESTEN =0,TESTDIN=data
 205          * TESTCLK=1
 206          */
 207         if (data != 0xff) {
 208                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 209                         ((data << DPHY_RX0_TESTDIN_BIT) |
 210                         DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
 211                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 212                         DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
 213         }
 214         return 0;
 215 }
 216
 217 static int mipi_dphy0_rd_reg(unsigned char addr)
 218 {
 219         int val = 0;
 220         /*TESTCLK=1*/
 221         write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
 222                                 (1 << DPHY_RX0_TESTCLK_BIT));
 223         /*TESTEN =1,TESTDIN=addr*/
 224         write_grf_reg(GRF_SOC_CON25_OFFSET,
 225                                 ((addr << DPHY_RX0_TESTDIN_BIT) |
 226                                 DPHY_RX0_TESTDIN_MASK |
 227                                 (1 << DPHY_RX0_TESTEN_BIT) |
 228                                 DPHY_RX0_TESTEN_MASK));
 229         /*TESTCLK=0*/
 230         write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
 231         read_grf_reg(GRF_SOC_STATUS1, &val);
 232         return val & 0xff;
 233 }
 234
 235 static int mipi_dphy1_wr_reg(unsigned char addr, unsigned char data)
 236 {
 237         /*
 238          * TESTEN =1,TESTDIN=addr
 239          * TESTCLK=0
 240          * TESTEN =0,TESTDIN=data
 241          * TESTCLK=1
 242          */
 243         write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
 244         write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
 245         write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
 246         write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
 247
 248         return 0;
 249 }
 250
 251 static int mipi_dphy1_rd_reg(unsigned char addr)
 252 {
 253         /* TESTEN =1,TESTDIN=addr */
 254         write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
 255         /* TESTCLK=0 */
 256         write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
 257         return (read_dsihost_reg(DSIHOST_PHY_TEST_CTRL1) >> 8);
 258 }
 259
 260 static int mipi_dphy_cfg(struct pltfrm_cam_mipi_config *para)
 261 {
 262         unsigned char hsfreqrange = 0xff, i;
 263         struct mipi_dphy_hsfreqrange *hsfreqrange_p;
 264         unsigned char datalane_en, input_sel;
 265
 266         hsfreqrange_p = mipi_dphy_hsfreq_range;
 267         for (i = 0;
 268                 i < (sizeof(mipi_dphy_hsfreq_range) /
 269                 sizeof(struct mipi_dphy_hsfreqrange));
 270                 i++) {
 271                 if ((para->bit_rate > hsfreqrange_p->range_l) &&
 272                          (para->bit_rate <= hsfreqrange_p->range_h)) {
 273                         hsfreqrange = hsfreqrange_p->cfg_bit;
 274                         break;
 275                 }
 276                 hsfreqrange_p++;
 277         }
 278
 279         if (hsfreqrange == 0xff)
 280                 hsfreqrange = 0x00;
 281
 282         hsfreqrange <<= 1;
 283
 284         input_sel = para->dphy_index;
 285         datalane_en = 0;
 286         for (i = 0; i < para->nb_lanes; i++)
 287                 datalane_en |= (1 << i);
 288
 289         if (input_sel == 0) {
 290                 write_grf_reg(GRF_SOC_CON21_OFFSET,
 291                                         DPHY_RX0_FORCERXMODE_MASK |
 292                                         (0x0 << DPHY_RX0_FORCERXMODE_BIT) |
 293                                         DPHY_RX0_FORCETXSTOPMODE_MASK |
 294                                         (0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
 295
 296                 /* set lane num */
 297                 write_grf_reg(GRF_SOC_CON21_OFFSET,
 298                         DPHY_RX0_ENABLE_MASK |
 299                         (datalane_en << DPHY_RX0_ENABLE_BIT));
 300
 301                 /* set lan turndisab as 1 */
 302                 write_grf_reg(GRF_SOC_CON21_OFFSET,
 303                         DPHY_RX0_TURNDISABLE_MASK |
 304                         (0xf << DPHY_RX0_TURNDISABLE_BIT));
 305                 write_grf_reg(GRF_SOC_CON21_OFFSET, (0x0 << 4) | (0xf << 20));
 306
 307                 /* set lan turnrequest as 0 */
 308                 write_grf_reg(GRF_SOC_CON9_OFFSET,
 309                         DPHY_RX0_TURNREQUEST_MASK |
 310                         (0x0 << DPHY_RX0_TURNREQUEST_BIT));
 311
 312                 /* phy start */
 313                 /*
 314                  * TESTCLK=1
 315                  * TESTCLR=1
 316                  * delay 100us
 317                  * TESTCLR=0
 318                  */
 319                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 320                         DPHY_RX0_TESTCLK_MASK |
 321                         (0x1 << DPHY_RX0_TESTCLK_BIT)); /* TESTCLK=1 */
 322                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 323                         DPHY_RX0_TESTCLR_MASK |
 324                         (0x1 << DPHY_RX0_TESTCLR_BIT));   /* TESTCLR=1 */
 325                 usleep_range(100, 150);
 326                 /* TESTCLR=0  zyc */
 327                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 328                         DPHY_RX0_TESTCLR_MASK);
 329                 usleep_range(100, 150);
 330
 331                 /* set clock lane */
 332                 mipi_dphy0_wr_reg
 333                         (0x34, 0);
 334                 /* HS hsfreqrange & lane 0  settle bypass */
 335                 mipi_dphy0_wr_reg(0x44, hsfreqrange);
 336                 mipi_dphy0_wr_reg(0x54, 0);
 337                 mipi_dphy0_wr_reg(0x84, 0);
 338                 mipi_dphy0_wr_reg(0x94, 0);
 339                 mipi_dphy0_wr_reg(0x75, 0x04);
 340                 mipi_dphy0_rd_reg(0x75);
 341
 342                 /* Normal operation */
 343                 /*
 344                  * TESTCLK=1
 345                  * TESTEN =0
 346                  */
 347                 mipi_dphy0_wr_reg(0x0, -1);
 348                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 349                         DPHY_RX0_TESTCLK_MASK | (1 << DPHY_RX0_TESTCLK_BIT));
 350                 write_grf_reg(GRF_SOC_CON25_OFFSET,
 351                         (DPHY_RX0_TESTEN_MASK));
 352
 353                 write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
 354                         read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL)
 355                         | (0x0f << 8));
 356
 357         } else if (input_sel == 1) {
 358                 write_grf_reg(GRF_SOC_CON23_OFFSET,
 359                         DPHY_RX0_FORCERXMODE_MASK |
 360                         (0x0 << DPHY_RX0_FORCERXMODE_BIT) |
 361                         DPHY_RX0_FORCETXSTOPMODE_MASK |
 362                         (0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
 363                 write_grf_reg(GRF_SOC_CON24_OFFSET,
 364                         DPHY_TX1RX1_MASTERSLAVEZ_MASK |
 365                         (0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
 366                         DPHY_TX1RX1_BASEDIR_MASK |
 367                         (0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
 368                         DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
 369
 370                 /* set lane num */
 371                 write_grf_reg(GRF_SOC_CON23_OFFSET,
 372                         DPHY_TX1RX1_ENABLE_MASK |
 373                         (datalane_en << DPHY_TX1RX1_ENABLE_BIT));
 374
 375                 /* set lan turndisab as 1 */
 376                 write_grf_reg(GRF_SOC_CON23_OFFSET,
 377                         DPHY_TX1RX1_TURNDISABLE_MASK |
 378                         (0xf << DPHY_TX1RX1_TURNDISABLE_BIT));
 379                 write_grf_reg(GRF_SOC_CON23_OFFSET, (0x0 << 4) | (0xf << 20));
 380
 381                 /* set lan turnrequest as 0   */
 382                 write_grf_reg(GRF_SOC_CON24_OFFSET,
 383                         DPHY_TX1RX1_TURNREQUEST_MASK |
 384                         (0x0 << DPHY_TX1RX1_TURNREQUEST_BIT));
 385
 386                 /* phy1 start */
 387                 /*
 388                  * SHUTDOWNZ=0
 389                  * RSTZ=0
 390                  * TESTCLK=1
 391                  * TESTCLR=1 TESTCLK=1
 392                  * TESTCLR=0 TESTCLK=1
 393                  */
 394                 write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, 0x00000000);
 395                 write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000000);
 396                 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
 397                 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000003);
 398                 usleep_range(100, 150);
 399                 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
 400                 usleep_range(100, 150);
 401
 402                 /* set clock lane */
 403                 mipi_dphy1_wr_reg(0x34, 0x00);
 404                 mipi_dphy1_wr_reg(0x44, hsfreqrange);
 405                 mipi_dphy1_wr_reg(0x54, 0);
 406                 mipi_dphy1_wr_reg(0x84, 0);
 407                 mipi_dphy1_wr_reg(0x94, 0);
 408                 mipi_dphy1_wr_reg(0x75, 0x04);
 409
 410                 mipi_dphy1_rd_reg(0x0);
 411                 /*
 412                  * TESTCLK=1
 413                  * TESTEN =0
 414                  * SHUTDOWNZ=1
 415                  * RSTZ=1
 416                  */
 417                 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
 418                 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000000);
 419                 write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, 0x00000001);
 420                 write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000001);
 421         } else {
 422                 goto fail;
 423         }
 424
 425         return 0;
 426 fail:
 427         return -1;
 428 }
 429
 430 static int soc_clk_enable(void)
 431 {
 432         struct cif_isp10_clk_rst_rk3399 *clk_rst = &rk3399->clk_rst;
 433
 434         clk_prepare_enable(clk_rst->hclk_isp0_noc);
 435         clk_prepare_enable(clk_rst->hclk_isp0_wrapper);
 436         clk_prepare_enable(clk_rst->aclk_isp0_noc);
 437         clk_prepare_enable(clk_rst->aclk_isp0_wrapper);
 438         clk_prepare_enable(clk_rst->clk_isp0);
 439         clk_prepare_enable(clk_rst->cif_clk_out);
 440         clk_prepare_enable(clk_rst->pclk_dphyrx);
 441         clk_prepare_enable(clk_rst->pclk_dphy_ref);
 442
 443         return 0;
 444 }
 445
 446 static int soc_clk_disable(void)
 447 {
 448         struct cif_isp10_clk_rst_rk3399 *clk_rst = &rk3399->clk_rst;
 449
 450         clk_disable_unprepare(clk_rst->hclk_isp0_noc);
 451         clk_disable_unprepare(clk_rst->hclk_isp0_wrapper);
 452         clk_disable_unprepare(clk_rst->aclk_isp0_noc);
 453         clk_disable_unprepare(clk_rst->aclk_isp0_wrapper);
 454         clk_disable_unprepare(clk_rst->clk_isp0);
 455         clk_disable_unprepare(clk_rst->pclk_dphyrx);
 456         clk_disable_unprepare(clk_rst->pclk_dphy_ref);
 457         if (!IS_ERR_OR_NULL(clk_rst->cif_clk_pll)) {
 458                 clk_set_parent(clk_rst->cif_clk_out,
 459                         clk_rst->cif_clk_pll);
 460         }
 461         clk_disable_unprepare(clk_rst->cif_clk_out);
 462
 463         return 0;
 464 }
 465
 466 static int soc_init(struct pltfrm_soc_init_para *init)
 467 {
 468         struct cif_isp10_clk_rst_rk3399 *clk_rst;
 469         struct platform_device *pdev = init->pdev;
 470         struct device_node *np = pdev->dev.of_node, *node;
 471         struct resource *res;
 472         int err;
 473
 474         rk3399 = (struct cif_isp10_rk3399 *)devm_kzalloc(
 475                                 &pdev->dev,
 476                                 sizeof(struct cif_isp10_rk3399),
 477                                 GFP_KERNEL);
 478         if (!rk3399) {
 479                 dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3399\n");
 480                 err = -ENOMEM;
 481                 goto alloc_failed;
 482         }
 483
 484         node = of_parse_phandle(np, "rockchip,grf", 0);
 485         if (node) {
 486                 rk3399->regmap_grf = syscon_node_to_regmap(node);
 487                 if (IS_ERR(rk3399->regmap_grf)) {
 488                         dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3399\n");
 489                         err = -ENODEV;
 490                         goto regmap_failed;
 491                 }
 492         }
 493
 494         res = platform_get_resource_byname(pdev,
 495                                 IORESOURCE_MEM, "dsihost-register");
 496         if (!res) {
 497                 dev_err(&pdev->dev,
 498                         "platform_get_resource_byname dsihost-register failed\n");
 499                 err = -ENODEV;
 500                 goto regmap_failed;
 501         }
 502         rk3399->dsihost_base = devm_ioremap_resource(&pdev->dev, res);
 503         if (IS_ERR_OR_NULL(rk3399->dsihost_base)) {
 504                 dev_err(&pdev->dev, "devm_ioremap_resource failed\n");
 505                 if (IS_ERR(rk3399->dsihost_base))
 506                         err = PTR_ERR(rk3399->dsihost_base);
 507                 else
 508                         err = -ENODEV;
 509                 goto regmap_failed;
 510         }
 511
 512         clk_rst = &rk3399->clk_rst;
 513
 514         clk_rst->hclk_isp0_noc     =
 515                 devm_clk_get(&pdev->dev, "hclk_isp0_noc");
 516         clk_rst->hclk_isp0_wrapper =
 517                 devm_clk_get(&pdev->dev, "hclk_isp0_wrapper");
 518         clk_rst->aclk_isp0_noc     =
 519                 devm_clk_get(&pdev->dev, "aclk_isp0_noc");
 520         clk_rst->aclk_isp0_wrapper =
 521                 devm_clk_get(&pdev->dev, "aclk_isp0_wrapper");
 522         clk_rst->clk_isp0                  =
 523                 devm_clk_get(&pdev->dev, "clk_isp0");
 524         clk_rst->cif_clk_out       =
 525                 devm_clk_get(&pdev->dev, "clk_cif_out");
 526         clk_rst->cif_clk_pll       =
 527                 devm_clk_get(&pdev->dev, "cif_clk_pll");
 528         clk_rst->pclk_dphyrx       =
 529                 devm_clk_get(&pdev->dev, "pclk_dphyrx");
 530         clk_rst->pclk_dphy_ref     =
 531                 devm_clk_get(&pdev->dev, "pclk_dphy_ref");
 532
 533         if (IS_ERR_OR_NULL(clk_rst->hclk_isp0_noc)               ||
 534                 IS_ERR_OR_NULL(clk_rst->hclk_isp0_wrapper)       ||
 535                 IS_ERR_OR_NULL(clk_rst->aclk_isp0_noc)           ||
 536                 IS_ERR_OR_NULL(clk_rst->aclk_isp0_wrapper)       ||
 537                 IS_ERR_OR_NULL(clk_rst->clk_isp0)                        ||
 538                 IS_ERR_OR_NULL(clk_rst->cif_clk_out)             ||
 539                 IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref)           ||
 540                 IS_ERR_OR_NULL(clk_rst->pclk_dphyrx)) {
 541                 dev_err(&pdev->dev, "Get rk3399 cif isp10 clock resouce failed !\n");
 542                 err = -EINVAL;
 543                 goto clk_failed;
 544         }
 545
 546         clk_set_rate(clk_rst->clk_isp0, 420000000);
 547
 548         rk3399->isp_base = init->isp_base;
 549         return 0;
 550
 551 clk_failed:
 552         if (!IS_ERR_OR_NULL(clk_rst->hclk_isp0_noc))
 553                 devm_clk_put(&pdev->dev, clk_rst->hclk_isp0_noc);
 554
 555         if (!IS_ERR_OR_NULL(clk_rst->hclk_isp0_wrapper))
 556                 devm_clk_put(&pdev->dev, clk_rst->hclk_isp0_wrapper);
 557
 558         if (!IS_ERR_OR_NULL(clk_rst->aclk_isp0_noc))
 559                 devm_clk_put(&pdev->dev, clk_rst->aclk_isp0_noc);
 560
 561         if (!IS_ERR_OR_NULL(clk_rst->aclk_isp0_wrapper))
 562                 devm_clk_put(&pdev->dev, clk_rst->aclk_isp0_wrapper);
 563
 564         if (!IS_ERR_OR_NULL(clk_rst->clk_isp0))
 565                 devm_clk_put(&pdev->dev, clk_rst->clk_isp0);
 566
 567         if (!IS_ERR_OR_NULL(clk_rst->cif_clk_out))
 568                 devm_clk_put(&pdev->dev, clk_rst->cif_clk_out);
 569
 570         if (!IS_ERR_OR_NULL(clk_rst->cif_clk_pll))
 571                 devm_clk_put(&pdev->dev, clk_rst->cif_clk_pll);
 572
 573         if (!IS_ERR_OR_NULL(clk_rst->pclk_dphyrx))
 574                 devm_clk_put(&pdev->dev, clk_rst->pclk_dphyrx);
 575
 576         if (!IS_ERR_OR_NULL(clk_rst->pclk_dphy_ref))
 577                 devm_clk_put(&pdev->dev, clk_rst->pclk_dphy_ref);
 578
 579 regmap_failed:
 580
 581 alloc_failed:
 582
 583         return err;
 584 }
 585
 586 int pltfrm_rk3399_cfg(
 587                 struct pltfrm_soc_cfg_para *cfg)
 588 {
 589         switch (cfg->cmd) {
 590         case PLTFRM_MCLK_CFG: {
 591                 struct pltfrm_soc_mclk_para *mclk_para;
 592
 593                 mclk_para = (struct pltfrm_soc_mclk_para *)cfg->cfg_para;
 594                 if (mclk_para->io_voltage == PLTFRM_IO_1V8)
 595                         write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V18SEL);
 596                 else
 597                         write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V33SEL);
 598
 599                 write_grf_reg(GRF_GPIO2B_E_OFFSET,
 600                         CIF_CLKOUT_STRENGTH(mclk_para->drv_strength));
 601                 break;
 602         }
 603         case PLTFRM_MIPI_DPHY_CFG:
 604                 mipi_dphy_cfg((struct pltfrm_cam_mipi_config *)cfg->cfg_para);
 605                 break;
 606
 607         case PLTFRM_CLKEN:
 608                 soc_clk_enable();
 609                 break;
 610
 611         case PLTFRM_CLKDIS:
 612                 soc_clk_disable();
 613                 break;
 614
 615         case PLTFRM_CLKRST:
 616                 write_cifisp_reg(VI_IRCL, 0x80);
 617                 usleep_range(10, 15);
 618                 write_cifisp_reg(VI_IRCL, 0x00);
 619                 break;
 620
 621         case PLTFRM_SOC_INIT:
 622                 soc_init((struct pltfrm_soc_init_para *)cfg->cfg_para);
 623                 break;
 624
 625         default:
 626                 break;
 627         }
 628
 629         return 0;
 630 }