drivers/media/platform/rk-isp10/cif_isp10_rk3288.c

   1 /*
   2  *************************************************************************
   3  * Rockchip driver for CIF ISP 1.0
   4  * (Based on Intel driver for sofiaxxx)
   5  *
   6  * Copyright (C) 2015 Intel Mobile Communications GmbH
   7  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
   8  *
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *************************************************************************
  15  */
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/clk.h>
  21 #include <linux/reset.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/platform_data/rk_isp10_platform.h>
  27
  28 #define ONE_LANE_ENABLE_BIT     0x1
  29 #define TWO_LANE_ENABLE_BIT     0x2
  30 #define FOUR_LANE_ENABLE_BIT    0x4
  31
  32 #define MRV_MIPI_BASE           0x1C00
  33 #define MRV_MIPI_CTRL           0x00
  34
  35 /*
  36  * GRF_SOC_CON14
  37  * bit 0     dphy_rx0_testclr
  38  * bit 1     dphy_rx0_testclk
  39  * bit 2     dphy_rx0_testen
  40  * bit 3:10 dphy_rx0_testdin
  41  */
  42 #define GRF_SOC_CON14_OFFSET    (0x027c)
  43 #define DPHY_RX0_TESTCLR_MASK   (0x1 << 16)
  44 #define DPHY_RX0_TESTCLK_MASK   (0x1 << 17)
  45 #define DPHY_RX0_TESTEN_MASK    (0x1 << 18)
  46 #define DPHY_RX0_TESTDIN_MASK   (0xff << 19)
  47
  48 #define DPHY_RX0_TESTCLR         BIT(0)
  49 #define DPHY_RX0_TESTCLK         BIT(1)
  50 #define DPHY_RX0_TESTEN          BIT(2)
  51 #define DPHY_RX0_TESTDIN_OFFSET  (3)
  52
  53 #define DPHY_TX1RX1_ENABLECLK_MASK    (0x1 << 28)
  54 #define DPHY_RX1_SRC_SEL_MASK         (0x1 << 29)
  55 #define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 30)
  56 #define DPHY_TX1RX1_BASEDIR_OFFSET    (0x1 << 31)
  57
  58 #define DPHY_TX1RX1_ENABLECLK         (0x1 << 12)
  59 #define DPHY_TX1RX1_DISABLECLK        (0x0 << 12)
  60 #define DPHY_RX1_SRC_SEL_ISP          (0x1 << 13)
  61 #define DPHY_TX1RX1_SLAVEZ            (0x0 << 14)
  62 #define DPHY_TX1RX1_BASEDIR_REC       (0x1 << 15)
  63
  64 /*
  65  * GRF_SOC_CON6
  66  * bit 0 grf_con_disable_isp
  67  * bit 1 grf_con_isp_dphy_sel  1'b0 mipi phy rx0
  68  */
  69 #define GRF_SOC_CON6_OFFSET            (0x025c)
  70 #define MIPI_PHY_DISABLE_ISP_MASK      (0x1 << 16)
  71 #define MIPI_PHY_DISABLE_ISP           (0x0 << 0)
  72
  73 #define DSI_CSI_TESTBUS_SEL_MASK       (0x1 << 30)
  74 #define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
  75
  76 #define MIPI_PHY_DPHYSEL_OFFSET_MASK   (0x1 << 17)
  77 #define MIPI_PHY_DPHYSEL_OFFSET_BIT    (0x1)
  78
  79 /*
  80  * GRF_SOC_CON10
  81  * bit12:15 grf_dphy_rx0_enable
  82  * bit 0:3 turn disable
  83  */
  84 #define GRF_SOC_CON10_OFFSET                (0x026c)
  85 #define DPHY_RX0_TURN_DISABLE_MASK          (0xf << 16)
  86 #define DPHY_RX0_TURN_DISABLE_OFFSET_BITS   (0x0)
  87 #define DPHY_RX0_ENABLE_MASK                (0xf << 28)
  88 #define DPHY_RX0_ENABLE_OFFSET_BITS         (12)
  89
  90 /*
  91  * GRF_SOC_CON9
  92  * bit12:15 grf_dphy_rx0_enable
  93  * bit 0:3 turn disable
  94  */
  95 #define GRF_SOC_CON9_OFFSET                    (0x0268)
  96 #define DPHY_TX1RX1_TURN_DISABLE_MASK          (0xf << 16)
  97 #define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS   (0x0)
  98 #define DPHY_TX1RX1_ENABLE_MASK                (0xf << 28)
  99 #define DPHY_TX1RX1_ENABLE_OFFSET_BITS         (12)
 100
 101 /*
 102  * GRF_SOC_CON15
 103  * bit 0:3   turn request
 104  */
 105 #define GRF_SOC_CON15_OFFSET                (0x03a4)
 106 #define DPHY_RX0_TURN_REQUEST_MASK          (0xf << 16)
 107 #define DPHY_RX0_TURN_REQUEST_OFFSET_BITS   (0x0)
 108
 109 #define DPHY_TX1RX1_TURN_REQUEST_MASK          (0xf << 20)
 110 #define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS   (0x0)
 111
 112 /*
 113  * GRF_SOC_STATUS21
 114  * bit0:7   dphy_rx0_testdout
 115  */
 116 #define GRF_SOC_STATUS21_OFFSET      (0x2D4)
 117 #define DPHY_RX0_TESTDOUT(a)         ((a) & 0xff)
 118
 119 /*
 120  * GRF_IO_VSEL
 121  */
 122 #define GRF_IO_VSEL_OFFSET              (0x0380)
 123 #define DVP_V18SEL                      ((1 << 1) | (1 << 17))
 124 #define DVP_V33SEL                      ((0 << 1) | (1 << 17))
 125
 126 /*
 127  * GRF_IO_VSEL
 128  */
 129 #define GRF_GPIO2B_E_OFFSET       (0x0380)
 130 #define CIF_CLKOUT_STRENGTH(a)    ((((a) & 0x03) << 3) | (0x03 << 19))
 131
 132 /*
 133  * CSI HOST
 134  */
 135
 136 #define CSIHOST_PHY_TEST_CTRL0            (0x30)
 137 #define CSIHOST_PHY_TEST_CTRL1            (0x34)
 138 #define CSIHOST_PHY_SHUTDOWNZ             (0x08)
 139 #define CSIHOST_DPHY_RSTZ                 (0x0c)
 140 #define CSIHOST_N_LANES                   (0x04)
 141 #define CSIHOST_CSI2_RESETN               (0x10)
 142 #define CSIHOST_PHY_STATE                 (0x14)
 143 #define CSIHOST_DATA_IDS1                 (0x18)
 144 #define CSIHOST_DATA_IDS2                 (0x1C)
 145 #define CSIHOST_ERR1                      (0x20)
 146 #define CSIHOST_ERR2                      (0x24)
 147
 148 #define write_cifisp_reg(addr, val)     \
 149                 __raw_writel(val, (addr) + rk3288->isp_base)
 150 #define read_cifisp_reg(addr)   \
 151                 __raw_readl((addr) + rk3288->isp_base)
 152
 153 #define write_grf_reg(addr, val)        \
 154                 regmap_write(rk3288->regmap_grf, addr, val)
 155 #define read_grf_reg(addr, val) regmap_read(rk3288->regmap_grf, addr, val)
 156
 157 #define write_csihost_reg(addr, val)    \
 158                 __raw_writel(val, (addr) + rk3288->csihost_base)
 159 #define read_csihost_reg(addr)  __raw_readl((addr) + rk3288->csihost_base)
 160
 161 struct cif_isp10_clk_rst_rk3288 {
 162         struct clk      *aclk_isp;
 163         struct clk      *hclk_isp;
 164         struct clk      *sclk_isp;
 165         struct clk      *sclk_isp_jpe;
 166         struct clk *sclk_mipidsi_24m;
 167         struct clk *pclk_mipi_csi;
 168         struct clk *pclk_isp_in;
 169         struct reset_control *isp_rst;
 170 };
 171
 172 struct cif_isp10_rk3288 {
 173         struct regmap *regmap_grf;
 174         void __iomem *csihost_base;
 175         void __iomem *isp_base;
 176         struct cif_isp10_clk_rst_rk3288 clk_rst;
 177         struct cif_isp10_device *cif_isp10;
 178 };
 179
 180 struct mipi_dphy_hsfreqrange {
 181         unsigned int range_l;
 182         unsigned int range_h;
 183         unsigned char cfg_bit;
 184 };
 185
 186 static struct mipi_dphy_hsfreqrange mipi_dphy_hsfreq_range[] = {
 187         {80, 90, 0x00},
 188         {90, 100, 0x10},
 189         {100, 110, 0x20},
 190         {110, 130, 0x01},
 191         {130, 140, 0x11},
 192         {140, 150, 0x21},
 193         {150, 170, 0x02},
 194         {170, 180, 0x12},
 195         {180, 200, 0x22},
 196         {200, 220, 0x03},
 197         {220, 240, 0x13},
 198         {240, 250, 0x23},
 199         {250, 270, 0x4},
 200         {270, 300, 0x14},
 201         {300, 330, 0x5},
 202         {330, 360, 0x15},
 203         {360, 400, 0x25},
 204         {400, 450, 0x06},
 205         {450, 500, 0x16},
 206         {500, 550, 0x07},
 207         {550, 600, 0x17},
 208         {600, 650, 0x08},
 209         {650, 700, 0x18},
 210         {700, 750, 0x09},
 211         {750, 800, 0x19},
 212         {800, 850, 0x29},
 213         {850, 900, 0x39},
 214         {900, 950, 0x0a},
 215         {950, 1000, 0x1a}
 216 };
 217
 218 static struct cif_isp10_rk3288 *rk3288;
 219 static int mipi_dphy0_wr_reg(unsigned char addr, unsigned char data)
 220 {
 221         /*
 222          * TESTCLK=1
 223          * TESTEN =1,TESTDIN=addr
 224          * TESTCLK=0
 225          */
 226         write_grf_reg(GRF_SOC_CON14_OFFSET,
 227                 DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
 228         write_grf_reg(GRF_SOC_CON14_OFFSET,
 229                 ((addr << DPHY_RX0_TESTDIN_OFFSET) | DPHY_RX0_TESTDIN_MASK
 230                  | DPHY_RX0_TESTEN | DPHY_RX0_TESTEN_MASK));
 231         write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
 232
 233         /*
 234          * write data:
 235          * TESTEN =0,TESTDIN=data
 236          * TESTCLK=1
 237          */
 238         if (data != 0xff) {
 239                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 240                         ((data << DPHY_RX0_TESTDIN_OFFSET) |
 241                         DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
 242                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 243                         DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
 244         }
 245         return 0;
 246 }
 247
 248 static int mipi_dphy1_wr_reg(unsigned char addr, unsigned char data)
 249 {
 250         /*
 251          * TESTEN =1,TESTDIN=addr
 252          * TESTCLK=0
 253          * TESTEN =0,TESTDIN=data
 254          * TESTCLK=1
 255          */
 256         write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
 257         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
 258         write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
 259         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 260
 261         return 0;
 262 }
 263
 264 static int mipi_dphy1_rd_reg(unsigned char addr)
 265 {
 266         return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1) & 0xff00)) >> 8);
 267 }
 268
 269 static int mipi_dphy_cfg(struct pltfrm_cam_mipi_config *para)
 270 {
 271         unsigned char hsfreqrange = 0xff, i;
 272         struct mipi_dphy_hsfreqrange *hsfreqrange_p;
 273         unsigned char datalane_en, input_sel;
 274
 275         hsfreqrange_p = mipi_dphy_hsfreq_range;
 276         for (i = 0;
 277                 i < (sizeof(mipi_dphy_hsfreq_range) /
 278                 sizeof(struct mipi_dphy_hsfreqrange));
 279                 i++) {
 280                 if ((para->bit_rate > hsfreqrange_p->range_l) &&
 281                          (para->bit_rate <= hsfreqrange_p->range_h)) {
 282                         hsfreqrange = hsfreqrange_p->cfg_bit;
 283                         break;
 284                 }
 285                 hsfreqrange_p++;
 286         }
 287
 288         if (hsfreqrange == 0xff)
 289                 hsfreqrange = 0x00;
 290
 291         hsfreqrange <<= 1;
 292
 293         input_sel = para->dphy_index;
 294         datalane_en = 0;
 295         for (i = 0; i < para->nb_lanes; i++)
 296                 datalane_en |= (1 << i);
 297
 298         if (input_sel == 0) {
 299                 write_grf_reg(GRF_SOC_CON6_OFFSET,
 300                         MIPI_PHY_DPHYSEL_OFFSET_MASK |
 301                         (input_sel << MIPI_PHY_DPHYSEL_OFFSET_BIT));
 302                 /* set lane num */
 303                 write_grf_reg(GRF_SOC_CON10_OFFSET,
 304                         DPHY_RX0_ENABLE_MASK |
 305                         (datalane_en << DPHY_RX0_ENABLE_OFFSET_BITS));
 306                 /* set lan turndisab as 1 */
 307                 write_grf_reg(GRF_SOC_CON10_OFFSET,
 308                         DPHY_RX0_TURN_DISABLE_MASK |
 309                         (0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
 310                 write_grf_reg(GRF_SOC_CON10_OFFSET,
 311                 (0x0 << 4) | (0xf << 20));
 312                 /* set lan turnrequest as 0 */
 313                 write_grf_reg(GRF_SOC_CON15_OFFSET,
 314                         DPHY_RX0_TURN_REQUEST_MASK |
 315                         (0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
 316
 317                 /* phy start */
 318                 /*
 319                  * TESTCLK=1
 320                  * TESTCLR=1
 321                  * delay 100us
 322                  * TESTCLR=0
 323                  */
 324                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 325                         DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
 326                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 327                         DPHY_RX0_TESTCLR_MASK | DPHY_RX0_TESTCLR);
 328                 usleep_range(100, 150);
 329                 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK);
 330                 usleep_range(100, 150);
 331
 332                 /* set clock lane */
 333                 mipi_dphy0_wr_reg(0x34, 0x15);
 334                 if (datalane_en == ONE_LANE_ENABLE_BIT) {
 335                         mipi_dphy0_wr_reg(0x44, hsfreqrange);
 336                 } else if (datalane_en == TWO_LANE_ENABLE_BIT) {
 337                         mipi_dphy0_wr_reg(0x44, hsfreqrange);
 338                         mipi_dphy0_wr_reg(0x54, hsfreqrange);
 339                 } else if (datalane_en == FOUR_LANE_ENABLE_BIT) {
 340                         mipi_dphy0_wr_reg(0x44, hsfreqrange);
 341                         mipi_dphy0_wr_reg(0x54, hsfreqrange);
 342                         mipi_dphy0_wr_reg(0x84, hsfreqrange);
 343                         mipi_dphy0_wr_reg(0x94, hsfreqrange);
 344                 }
 345
 346                 /* Normal operation */
 347                 /*
 348                  * TESTCLK=1
 349                  * TESTEN =0
 350                  */
 351                 mipi_dphy0_wr_reg(0x0, -1);
 352                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 353                         DPHY_RX0_TESTCLK_MASK | DPHY_RX0_TESTCLK);
 354                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 355                         (DPHY_RX0_TESTEN_MASK));
 356
 357                 write_cifisp_reg((MRV_MIPI_BASE + MRV_MIPI_CTRL),
 358                         read_cifisp_reg(MRV_MIPI_BASE + MRV_MIPI_CTRL) |
 359                         (0x0f << 8));
 360
 361         } else if (input_sel == 1) {
 362                 write_grf_reg(GRF_SOC_CON6_OFFSET,
 363                         MIPI_PHY_DPHYSEL_OFFSET_MASK |
 364                         (input_sel << MIPI_PHY_DPHYSEL_OFFSET_BIT));
 365                 write_grf_reg(GRF_SOC_CON6_OFFSET,
 366                         DSI_CSI_TESTBUS_SEL_MASK |
 367                         (1 << DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
 368
 369                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 370                         DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
 371                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 372                         DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
 373                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 374                         DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
 375
 376                 /* set lane num */
 377                 write_grf_reg(GRF_SOC_CON9_OFFSET,
 378                         DPHY_TX1RX1_ENABLE_MASK |
 379                         (datalane_en << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
 380                 /* set lan turndisab as 1 */
 381                 write_grf_reg(GRF_SOC_CON9_OFFSET,
 382                         DPHY_TX1RX1_TURN_DISABLE_MASK |
 383                         (0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
 384                 /* set lan turnrequest as 0   */
 385                 write_grf_reg(GRF_SOC_CON15_OFFSET,
 386                         DPHY_TX1RX1_TURN_REQUEST_MASK |
 387                         (0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
 388
 389                 /* phy1 start */
 390                 /*
 391                  * SHUTDOWNZ=0
 392                  * RSTZ=0
 393                  * TESTCLK=1
 394                  * TESTCLR=1 TESTCLK=1
 395                  * TESTCLR=0 TESTCLK=1
 396                  */
 397                 write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
 398                 write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
 399                 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 400                 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000003);
 401                 usleep_range(100, 150);
 402                 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 403                 usleep_range(100, 150);
 404
 405                 /* set clock lane */
 406                 mipi_dphy1_wr_reg(0x34, 0x15);
 407
 408                 if (datalane_en == ONE_LANE_ENABLE_BIT) {
 409                         mipi_dphy1_wr_reg(0x44, hsfreqrange);
 410                 } else if (datalane_en == TWO_LANE_ENABLE_BIT) {
 411                         mipi_dphy1_wr_reg(0x44, hsfreqrange);
 412                         mipi_dphy1_wr_reg(0x54, hsfreqrange);
 413                 } else if (datalane_en == FOUR_LANE_ENABLE_BIT) {
 414                         mipi_dphy1_wr_reg(0x44, hsfreqrange);
 415                         mipi_dphy1_wr_reg(0x54, hsfreqrange);
 416                         mipi_dphy1_wr_reg(0x84, hsfreqrange);
 417                         mipi_dphy1_wr_reg(0x94, hsfreqrange);
 418                 }
 419
 420                 mipi_dphy1_rd_reg(0x0);
 421                 /*
 422                  * TESTCLK=1
 423                  * TESTEN =0
 424                  * SHUTDOWNZ=1
 425                  * RSTZ=1
 426                  */
 427                 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 428                 write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, 0x00000000);
 429                 write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000001);
 430                 write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000001);
 431         } else {
 432                 goto fail;
 433         }
 434
 435         return 0;
 436 fail:
 437         return -1;
 438 }
 439
 440 static int soc_clk_enable(void)
 441 {
 442         struct cif_isp10_clk_rst_rk3288 *clk_rst = &rk3288->clk_rst;
 443
 444         clk_prepare_enable(clk_rst->hclk_isp);
 445         clk_prepare_enable(clk_rst->aclk_isp);
 446         clk_prepare_enable(clk_rst->sclk_isp);
 447         clk_prepare_enable(clk_rst->sclk_isp_jpe);
 448         clk_prepare_enable(clk_rst->sclk_mipidsi_24m);
 449         clk_prepare_enable(clk_rst->pclk_isp_in);
 450         clk_prepare_enable(clk_rst->pclk_mipi_csi);
 451         return 0;
 452 }
 453
 454 static int soc_clk_disable(void)
 455 {
 456         struct cif_isp10_clk_rst_rk3288 *clk_rst = &rk3288->clk_rst;
 457
 458         clk_disable_unprepare(clk_rst->hclk_isp);
 459         clk_disable_unprepare(clk_rst->aclk_isp);
 460         clk_disable_unprepare(clk_rst->sclk_isp);
 461         clk_disable_unprepare(clk_rst->sclk_isp_jpe);
 462         clk_disable_unprepare(clk_rst->sclk_mipidsi_24m);
 463         clk_disable_unprepare(clk_rst->pclk_isp_in);
 464         clk_disable_unprepare(clk_rst->pclk_mipi_csi);
 465         return 0;
 466 }
 467
 468 static int soc_init(struct pltfrm_soc_init_para *init)
 469 {
 470         struct cif_isp10_clk_rst_rk3288 *clk_rst;
 471         struct platform_device *pdev = init->pdev;
 472         struct device_node *np = pdev->dev.of_node, *node;
 473         struct resource *res;
 474         int err;
 475
 476         rk3288 = (struct cif_isp10_rk3288 *)devm_kzalloc(
 477                                 &pdev->dev,
 478                                 sizeof(struct cif_isp10_rk3288),
 479                                 GFP_KERNEL);
 480         if (!rk3288) {
 481                 dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3288\n");
 482                 err = -ENOMEM;
 483                 goto alloc_failed;
 484         }
 485
 486         node = of_parse_phandle(np, "rockchip,grf", 0);
 487         if (node) {
 488                 rk3288->regmap_grf = syscon_node_to_regmap(node);
 489                 if (IS_ERR(rk3288->regmap_grf)) {
 490                         dev_err(&pdev->dev, "Can't allocate cif_isp10_rk3288\n");
 491                         err = -ENODEV;
 492                         goto regmap_failed;
 493                 }
 494         }
 495
 496         res = platform_get_resource_byname(pdev,
 497                                 IORESOURCE_MEM, "csihost-register");
 498         if (!res) {
 499                 dev_err(&pdev->dev,
 500                         "platform_get_resource_byname csihost-register failed\n");
 501                 err = -ENODEV;
 502                 goto regmap_failed;
 503         }
 504         rk3288->csihost_base = devm_ioremap_resource(&pdev->dev, res);
 505         if (IS_ERR_OR_NULL(rk3288->csihost_base)) {
 506                 dev_err(&pdev->dev, "devm_ioremap_resource failed\n");
 507                 if (IS_ERR(rk3288->csihost_base))
 508                         err = PTR_ERR(rk3288->csihost_base);
 509                 else
 510                         err = -ENODEV;
 511                 goto regmap_failed;
 512         }
 513
 514         clk_rst = &rk3288->clk_rst;
 515         clk_rst->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
 516         clk_rst->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
 517         clk_rst->sclk_isp = devm_clk_get(&pdev->dev, "sclk_isp");
 518         clk_rst->sclk_isp_jpe = devm_clk_get(&pdev->dev, "sclk_isp_jpe");
 519         clk_rst->sclk_mipidsi_24m =
 520                         devm_clk_get(&pdev->dev, "sclk_mipidsi_24m");
 521         clk_rst->pclk_mipi_csi = devm_clk_get(&pdev->dev, "pclk_mipi_csi");
 522         clk_rst->isp_rst = devm_reset_control_get(&pdev->dev, "rst_isp");
 523         clk_rst->pclk_isp_in = devm_clk_get(&pdev->dev, "pclk_isp_in");
 524
 525         if (IS_ERR_OR_NULL(clk_rst->aclk_isp) ||
 526                 IS_ERR_OR_NULL(clk_rst->hclk_isp) ||
 527                 IS_ERR_OR_NULL(clk_rst->sclk_isp) ||
 528                 IS_ERR_OR_NULL(clk_rst->sclk_isp_jpe) ||
 529                 IS_ERR_OR_NULL(clk_rst->pclk_mipi_csi) ||
 530                 IS_ERR_OR_NULL(clk_rst->isp_rst) ||
 531                 IS_ERR_OR_NULL(clk_rst->pclk_isp_in) ||
 532                 IS_ERR_OR_NULL(clk_rst->sclk_mipidsi_24m)) {
 533                 dev_err(&pdev->dev, "Get rk3288 cif isp10 clock resouce failed !\n");
 534                 err = -EINVAL;
 535                 goto clk_failed;
 536         }
 537
 538         clk_set_rate(clk_rst->sclk_isp, 400000000);
 539         clk_set_rate(clk_rst->sclk_isp_jpe, 400000000);
 540         reset_control_deassert(clk_rst->isp_rst);
 541
 542         rk3288->isp_base = init->isp_base;
 543         return 0;
 544
 545 clk_failed:
 546         if (!IS_ERR_OR_NULL(clk_rst->aclk_isp))
 547                 devm_clk_put(&pdev->dev, clk_rst->aclk_isp);
 548         if (!IS_ERR_OR_NULL(clk_rst->hclk_isp))
 549                 devm_clk_put(&pdev->dev, clk_rst->hclk_isp);
 550         if (!IS_ERR_OR_NULL(clk_rst->sclk_isp))
 551                 devm_clk_put(&pdev->dev, clk_rst->sclk_isp);
 552         if (!IS_ERR_OR_NULL(clk_rst->sclk_isp_jpe))
 553                 devm_clk_put(&pdev->dev, clk_rst->sclk_isp_jpe);
 554         if (!IS_ERR_OR_NULL(clk_rst->pclk_mipi_csi))
 555                 devm_clk_put(&pdev->dev, clk_rst->pclk_mipi_csi);
 556         if (!IS_ERR_OR_NULL(clk_rst->pclk_isp_in))
 557                 devm_clk_put(&pdev->dev, clk_rst->pclk_isp_in);
 558         if (!IS_ERR_OR_NULL(clk_rst->sclk_mipidsi_24m))
 559                 devm_clk_put(&pdev->dev, clk_rst->sclk_mipidsi_24m);
 560
 561         if (!IS_ERR_OR_NULL(clk_rst->isp_rst))
 562                 reset_control_put(clk_rst->isp_rst);
 563
 564 regmap_failed:
 565
 566 alloc_failed:
 567
 568         return err;
 569 }
 570
 571 int pltfrm_rk3288_cfg(
 572                 struct pltfrm_soc_cfg_para *cfg)
 573 {
 574         switch (cfg->cmd) {
 575         case PLTFRM_MCLK_CFG: {
 576                 struct pltfrm_soc_mclk_para *mclk_para;
 577
 578                 mclk_para = (struct pltfrm_soc_mclk_para *)cfg->cfg_para;
 579                 if (mclk_para->io_voltage == PLTFRM_IO_1V8)
 580                         write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V18SEL);
 581                 else
 582                         write_grf_reg(GRF_IO_VSEL_OFFSET, DVP_V33SEL);
 583
 584                 write_grf_reg(GRF_GPIO2B_E_OFFSET,
 585                         CIF_CLKOUT_STRENGTH(mclk_para->drv_strength));
 586                 break;
 587         }
 588         case PLTFRM_MIPI_DPHY_CFG:
 589                 mipi_dphy_cfg((struct pltfrm_cam_mipi_config *)cfg->cfg_para);
 590                 break;
 591
 592         case PLTFRM_CLKEN:
 593                 soc_clk_enable();
 594                 break;
 595
 596         case PLTFRM_CLKDIS:
 597                 soc_clk_disable();
 598                 break;
 599
 600         case PLTFRM_CLKRST:
 601                 reset_control_assert(rk3288->clk_rst.isp_rst);
 602                 usleep_range(10, 15);
 603                 reset_control_deassert(rk3288->clk_rst.isp_rst);
 604                 break;
 605
 606         case PLTFRM_SOC_INIT:
 607                 soc_init((struct pltfrm_soc_init_para *)cfg->cfg_para);
 608                 break;
 609
 610         default:
 611                 break;
 612         }
 613
 614         return 0;
 615 }
 616