2 *************************************************************************
3 * Rockchip driver for CIF ISP 1.0
4 * (Based on Intel driver for sofiaxxx)
6 * Copyright (C) 2015 Intel Mobile Communications GmbH
7 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *************************************************************************
17 #ifndef _CIF_ISP10_PLTFRM_H
18 #define _CIF_ISP10_PLTFRM_H
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/wait.h>
24 #include <linux/string.h>
25 #include <linux/platform_data/rk_isp10_platform.h>
27 struct cif_isp10_strm_fmt;
28 struct cif_isp10_csi_config;
29 struct cif_isp10_device;
30 struct cif_isp10_img_src;
31 struct pltfrm_cam_itf;
32 enum cif_isp10_pinctrl_state;
34 enum cif_isp10_pm_state;
36 #define CIF_ISP10_PLTFRM_DEVICE struct device *
37 #define CIF_ISP10_PLTFRM_MEM_IO_ADDR void __iomem *
38 #define CIF_ISP10_PLTFRM_EVENT wait_queue_head_t
40 extern spinlock_t iowrite32_verify_lock;
41 #ifdef CONFIG_CIF_ISP10_REG_TRACE
43 cif_isp10_pltfrm_rtrace_printf(
49 cif_isp10_pltfrm_ftrace_printf(
55 #define cif_isp10_pltfrm_rtrace_printf(dev, str, ...)
56 #define cif_isp10_pltfrm_ftrace_printf(dev, str, ...)
59 #define cif_isp10_pltfrm_pr_dbg(dev, fmt, arg...) \
61 pr_debug("%s: " fmt, \
63 cif_isp10_pltfrm_ftrace_printf(dev, "%s: " fmt, \
66 #define cif_isp10_pltfrm_pr_info(dev, fmt, arg...) \
70 cif_isp10_pltfrm_ftrace_printf(dev, "%s: " fmt, \
73 #define cif_isp10_pltfrm_pr_warn(dev, fmt, arg...) \
75 pr_warn("%s WARN: " fmt, \
77 cif_isp10_pltfrm_ftrace_printf(dev, "%s WARN: " fmt, \
80 #define cif_isp10_pltfrm_pr_err(dev, fmt, arg...) \
82 pr_err("%s(%d) ERR: " fmt, \
83 __func__, __LINE__, ## arg); \
84 cif_isp10_pltfrm_ftrace_printf(dev, "%s(%d) ERR: " fmt, \
85 __func__, __LINE__, ## arg); \
88 void cif_isp10_pltfrm_write_reg(
91 CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
93 void cif_isp10_pltfrm_write_reg_OR(
96 CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
98 void cif_isp10_pltfrm_write_reg_AND(
101 CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
103 u32 cif_isp10_pltfrm_read_reg(
105 CIF_ISP10_PLTFRM_MEM_IO_ADDR addr);
107 #define cif_iowrite32(d, a) \
108 cif_isp10_pltfrm_write_reg(NULL, (u32)(d), a)
109 #define cif_ioread32(a) \
110 cif_isp10_pltfrm_read_reg(NULL, a)
111 #define cif_iowrite32OR(d, a) \
112 cif_isp10_pltfrm_write_reg_OR(NULL, (u32)(d), a)
113 #define cif_iowrite32AND(d, a) \
114 cif_isp10_pltfrm_write_reg_AND(NULL, (u32)(d), a)
115 /* BUG: Register write seems to fail sometimes w/o read before write. */
116 #define cif_iowrite32_verify(d, a, mask) \
118 unsigned int i = 0; \
119 unsigned long flags = 0; \
120 spin_lock_irqsave(&iowrite32_verify_lock, flags); \
122 cif_iowrite32(d, a); \
125 pr_err("Error in writing %x@0x%p, read %x\n", \
126 (d) & (mask), a, ioread32(a)); \
129 } while ((ioread32(a) & mask) != ((d) & mask)); \
130 spin_unlock_irqrestore(&iowrite32_verify_lock, flags);\
132 #define cif_iowrite32OR_verify(d, a, mask) \
133 cif_iowrite32_verify((u32)(d) | cif_ioread32(a), a, mask)
134 #define cif_iowrite32AND_verify(d, a, mask) \
135 cif_iowrite32_verify((u32)(d) & cif_ioread32(a), a, mask)
137 #define cif_isp10_pltfrm_event_init(_dev, _event) \
138 init_waitqueue_head(_event)
140 #define cif_isp10_pltfrm_event_clear(_dev, _event)
142 #define cif_isp10_pltfrm_event_signal(_dev, _event) \
143 wake_up_interruptible(_event)
145 #define cif_isp10_pltfrm_event_wait_timeout( \
146 _dev, _event, _condition, _timeout_us) \
147 wait_event_interruptible_timeout( \
148 *(_event), _condition, ((_timeout_us) * HZ) / 1000000)
151 cif_isp10_pltfrm_debug_register_print_cb(
153 void (*print)(void *cntxt, const char *block_name),
156 int cif_isp10_pltfrm_dev_init(
157 struct cif_isp10_device *cif_isp_dev,
159 void __iomem **reg_base_addr);
161 void cif_isp10_pltfrm_dev_release(
164 int cif_isp10_pltfrm_pm_set_state(
166 enum cif_isp10_pm_state state);
168 int cif_isp10_pltfrm_write_cif_ana_bandgap_bias(
172 int cif_isp10_pltfrm_pinctrl_set_state(
174 enum cif_isp10_pinctrl_state pinctrl_state);
176 int cif_isp10_pltfrm_get_img_src_device(
178 struct cif_isp10_img_src **img_src_array,
179 unsigned int array_len);
181 int cif_isp10_pltfrm_g_interface_config(
182 struct cif_isp10_img_src *img_src,
183 struct pltfrm_cam_itf *cam_itf);
185 int cif_isp10_pltfrm_irq_register_isr(
188 int (*isr)(unsigned int mis, void *cntxt),
191 const char *cif_isp10_pltfrm_get_device_type(
194 const char *cif_isp10_pltfrm_dev_string(
197 int cif_isp10_pltfrm_soc_init(
198 struct cif_isp10_device *cif_isp10_dev,
199 struct pltfrm_soc_cfg *soc_cfg);
201 int cif_isp10_pltfrm_mipi_dphy_config(
202 struct cif_isp10_device *cif_isp10_dev);