drivers/media/platform/rk-isp10/cif_isp10.h

   1 /*
   2  *************************************************************************
   3  * Rockchip driver for CIF ISP 1.0
   4  * (Based on Intel driver for sofiaxxx)
   5  *
   6  * Copyright (C) 2015 Intel Mobile Communications GmbH
   7  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
   8  *
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *************************************************************************
  15  */
  16
  17 #ifndef _CIF_ISP10_H
  18 #define _CIF_ISP10_H
  19
  20 #include <linux/platform_device.h>
  21 #include "cif_isp10_pltfrm.h"
  22 #include "cif_isp10_img_src.h"
  23 #include "cif_isp10_isp.h"
  24 #include <linux/platform_data/rk_isp10_platform.h>
  25 #include <media/v4l2-device.h>
  26 #include <media/v4l2-controls_rockchip.h>
  27 /*****************************************************************************/
  28 /* Definitions */
  29
  30 #define CONFIG_CIF_ISP_AUTO_UPD_CFG_BUG
  31
  32 #define CIF_ISP10_NUM_INPUTS    10
  33
  34 /* FORMAT */
  35 #define MAX_NB_FORMATS          30
  36
  37 #define CONTRAST_DEF            0x80
  38 #define BRIGHTNESS_DEF          0x0
  39 #define HUE_DEF                 0x0
  40
  41 /*
  42  *      MIPI CSI2.0
  43  */
  44 #define CSI2_DT_YUV420_8b       (0x18)
  45 #define CSI2_DT_YUV420_10b      (0x19)
  46 #define CSI2_DT_YUV422_8b       (0x1E)
  47 #define CSI2_DT_YUV422_10b      (0x1F)
  48 #define CSI2_DT_RGB565          (0x22)
  49 #define CSI2_DT_RGB666          (0x23)
  50 #define CSI2_DT_RGB888          (0x24)
  51 #define CSI2_DT_RAW8            (0x2A)
  52 #define CSI2_DT_RAW10           (0x2B)
  53 #define CSI2_DT_RAW12           (0x2C)
  54
  55 enum cif_isp10_img_src_state {
  56         CIF_ISP10_IMG_SRC_STATE_OFF       = 0,
  57         CIF_ISP10_IMG_SRC_STATE_SW_STNDBY = 1,
  58         CIF_ISP10_IMG_SRC_STATE_STREAMING = 2
  59 };
  60
  61 enum cif_isp10_state {
  62         /* path not yet opened: */
  63         CIF_ISP10_STATE_DISABLED  = 0,
  64         /* path opened but not yet configured: */
  65         CIF_ISP10_STATE_INACTIVE  = 1,
  66         /* path opened and configured, ready for streaming: */
  67         CIF_ISP10_STATE_READY     = 2,
  68         /* path is streaming: */
  69         CIF_ISP10_STATE_STREAMING = 3
  70 };
  71
  72 enum cif_isp10_pm_state {
  73         CIF_ISP10_PM_STATE_OFF,
  74         CIF_ISP10_PM_STATE_SUSPENDED,
  75         CIF_ISP10_PM_STATE_SW_STNDBY,
  76         CIF_ISP10_PM_STATE_STREAMING
  77 };
  78
  79 enum cif_isp10_inp {
  80         CIF_ISP10_INP_CSI     = 0x10000000,
  81         CIF_ISP10_INP_CPI     = 0x20000000,
  82
  83         CIF_ISP10_INP_DMA     = 0x30000000, /* DMA -> ISP */
  84         CIF_ISP10_INP_DMA_IE  = 0x31000000, /* DMA -> IE */
  85         CIF_ISP10_INP_DMA_SP  = 0x32000000, /* DMA -> SP */
  86         CIF_ISP10_INP_DMA_MAX = 0x33000000,
  87
  88         CIF_ISP10_INP_MAX     = 0x7fffffff
  89 };
  90
  91 #define CIF_ISP10_INP_IS_DMA(inp) \
  92         (((inp) & 0xf0000000) == CIF_ISP10_INP_DMA)
  93 #define CIF_ISP10_INP_IS_MIPI(inp) \
  94         (((inp) & 0xf0000000) == CIF_ISP10_INP_CSI)
  95 #define CIF_ISP10_INP_IS_DVP(inp) \
  96         (((inp) & 0xf0000000) == CIF_ISP10_INP_CPI)
  97 #define CIF_ISP10_INP_NEED_ISP(inp) \
  98         ((inp) <  CIF_ISP10_INP_DMA_IE)
  99 #define CIF_ISP10_INP_DMA_CNT() \
 100         ((CIF_ISP10_INP_DMA_MAX -\
 101         CIF_ISP10_INP_DMA) >> 24)
 102
 103 enum cif_isp10_pinctrl_state {
 104         CIF_ISP10_PINCTRL_STATE_SLEEP,
 105         CIF_ISP10_PINCTRL_STATE_INACTIVE,
 106         CIF_ISP10_PINCTRL_STATE_DEFAULT,
 107         CIF_ISP10_PINCTRL_STATE_ACTIVE
 108 };
 109
 110 enum cif_isp10_flash_mode {
 111         CIF_ISP10_FLASH_MODE_OFF,
 112         CIF_ISP10_FLASH_MODE_FLASH,
 113         CIF_ISP10_FLASH_MODE_TORCH,
 114 };
 115
 116 enum cif_isp10_cid {
 117         CIF_ISP10_CID_FLASH_MODE                  = 0,
 118         CIF_ISP10_CID_EXPOSURE_TIME               = 1,
 119         CIF_ISP10_CID_ANALOG_GAIN                 = 2,
 120         CIF_ISP10_CID_WB_TEMPERATURE              = 3,
 121         CIF_ISP10_CID_BLACK_LEVEL                 = 4,
 122         CIF_ISP10_CID_AUTO_GAIN                   = 5,
 123         CIF_ISP10_CID_AUTO_EXPOSURE               = 6,
 124         CIF_ISP10_CID_AUTO_WHITE_BALANCE          = 7,
 125         CIF_ISP10_CID_FOCUS_ABSOLUTE              = 8,
 126         CIF_ISP10_CID_AUTO_N_PRESET_WHITE_BALANCE = 9,
 127         CIF_ISP10_CID_SCENE_MODE                  = 10,
 128         CIF_ISP10_CID_SUPER_IMPOSE                = 11,
 129         CIF_ISP10_CID_JPEG_QUALITY                = 12,
 130         CIF_ISP10_CID_IMAGE_EFFECT                = 13,
 131         CIF_ISP10_CID_HFLIP                       = 14,
 132         CIF_ISP10_CID_VFLIP                       = 15,
 133         CIF_ISP10_CID_AUTO_FPS                    = 16,
 134         CIF_ISP10_CID_VBLANKING                   = 17,
 135         CIF_ISP10_CID_ISO_SENSITIVITY             = 18,
 136
 137 };
 138
 139 /* correspond to bit field values */
 140 enum cif_isp10_image_effect {
 141         CIF_ISP10_IE_BW       = 0,
 142         CIF_ISP10_IE_NEGATIVE = 1,
 143         CIF_ISP10_IE_SEPIA    = 2,
 144         CIF_ISP10_IE_C_SEL    = 3,
 145         CIF_ISP10_IE_EMBOSS   = 4,
 146         CIF_ISP10_IE_SKETCH   = 5,
 147         CIF_ISP10_IE_NONE /* not a bit field value */
 148 };
 149
 150 #define CIF_ISP10_PIX_FMT_MASK                  0xf0000000
 151 #define CIF_ISP10_PIX_FMT_MASK_BPP              0x0003f000
 152 #define CIF_ISP10_PIX_FMT_YUV_MASK_CPLANES      0x00000003
 153 #define CIF_ISP10_PIX_FMT_YUV_MASK_UVSWAP       0x00000004
 154 #define CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP       0x00000008
 155 #define CIF_ISP10_PIX_FMT_YUV_MASK_X            0x00000f00
 156 #define CIF_ISP10_PIX_FMT_YUV_MASK_Y            0x000000f0
 157 #define CIF_ISP10_PIX_FMT_RGB_MASK_PAT          0x000000f0
 158 #define CIF_ISP10_PIX_FMT_BAYER_MASK_PAT        0x000000f0
 159 #define CIF_ISP10_PIX_FMT_GET_BPP(pix_fmt) \
 160         (((pix_fmt) & CIF_ISP10_PIX_FMT_MASK_BPP) >> 12)
 161 #define cif_isp10_pix_fmt_set_bpp(pix_fmt, bpp) \
 162         { \
 163                 pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_MASK_BPP) | \
 164                         (((bpp) << 12) & CIF_ISP10_PIX_FMT_MASK_BPP)); \
 165         }
 166
 167 #define CIF_ISP10_PIX_FMT_YUV_GET_NUM_CPLANES(pix_fmt) \
 168         ((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_CPLANES)
 169 #define CIF_ISP10_PIX_FMT_YUV_IS_YC_SWAPPED(pix_fmt) \
 170         ((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP)
 171 #define CIF_ISP10_PIX_FMT_YUV_IS_UV_SWAPPED(pix_fmt) \
 172                 ((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_UVSWAP)
 173 #define CIF_ISP10_PIX_FMT_YUV_GET_X_SUBS(pix_fmt) \
 174         (((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_X) >> 8)
 175 #define CIF_ISP10_PIX_FMT_YUV_GET_Y_SUBS(pix_fmt) \
 176         (((pix_fmt) & CIF_ISP10_PIX_FMT_YUV_MASK_Y) >> 4)
 177 #define cif_isp10_pix_fmt_set_y_subs(pix_fmt, y_subs) \
 178         { \
 179                 pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_YUV_MASK_Y) | \
 180                         ((y_subs << 4) & CIF_ISP10_PIX_FMT_YUV_MASK_Y)); \
 181         }
 182 #define cif_isp10_pix_fmt_set_x_subs(pix_fmt, x_subs) \
 183         { \
 184                 pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_YUV_MASK_X) | \
 185                         (((x_subs) << 8) & CIF_ISP10_PIX_FMT_YUV_MASK_X)); \
 186         }
 187 #define cif_isp10_pix_fmt_set_yc_swapped(pix_fmt, yc_swapped) \
 188         { \
 189                 pix_fmt = (((pix_fmt) & ~CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP) | \
 190                         (((yc_swapped) << 3) & \
 191                         CIF_ISP10_PIX_FMT_YUV_MASK_YCSWAP)); \
 192         }
 193
 194 #define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_BGGR(pix_fmt) \
 195         (((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x0)
 196 #define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_GBRG(pix_fmt) \
 197         (((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x10)
 198 #define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_GRBG(pix_fmt) \
 199         (((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x20)
 200 #define CIF_ISP10_PIX_FMT_BAYER_PAT_IS_RGGB(pix_fmt) \
 201         (((pix_fmt) & CIF_ISP10_PIX_FMT_BAYER_MASK_PAT) == 0x30)
 202
 203 #define CIF_ISP10_PIX_FMT_IS_YUV(pix_fmt) \
 204         (((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x10000000)
 205 #define CIF_ISP10_PIX_FMT_IS_RGB(pix_fmt) \
 206         (((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x20000000)
 207 #define CIF_ISP10_PIX_FMT_IS_RAW_BAYER(pix_fmt) \
 208         (((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x30000000)
 209 #define CIF_ISP10_PIX_FMT_IS_JPEG(pix_fmt) \
 210         (((pix_fmt) & CIF_ISP10_PIX_FMT_MASK) == 0x40000000)
 211
 212 #define CIF_ISP10_PIX_FMT_IS_INTERLEAVED(pix_fmt) \
 213         (!CIF_ISP10_PIX_FMT_IS_YUV(pix_fmt) ||\
 214         !CIF_ISP10_PIX_FMT_YUV_GET_NUM_CPLANES(pix_fmt))
 215
 216 enum cif_isp10_pix_fmt {
 217         /* YUV */
 218         CIF_YUV400                      = 0x10008000,
 219         CIF_YVU400                      = 0x10008004,
 220
 221         CIF_YUV420I                     = 0x1000c220,
 222         CIF_YUV420SP                    = 0x1000c221,   /* NV12 */
 223         CIF_YUV420P                     = 0x1000c222,
 224         CIF_YVU420I                     = 0x1000c224,
 225         CIF_YVU420SP                    = 0x1000c225,   /* NV21 */
 226         CIF_YVU420P                     = 0x1000c226,   /* YV12 */
 227
 228         CIF_YUV422I                     = 0x10010240,
 229         CIF_YUV422SP                    = 0x10010241,
 230         CIF_YUV422P                     = 0x10010242,
 231         CIF_YVU422I                     = 0x10010244,
 232         CIF_YVU422SP                    = 0x10010245,
 233         CIF_YVU422P                     = 0x10010246,
 234
 235         CIF_YUV444I                     = 0x10018440,
 236         CIF_YUV444SP                    = 0x10018441,
 237         CIF_YUV444P                     = 0x10018442,
 238         CIF_YVU444I                     = 0x10018444,
 239         CIF_YVU444SP                    = 0x10018445,
 240         CIF_YVU444P                     = 0x10018446,
 241
 242         CIF_UYV400                      = 0x10008008,
 243
 244         CIF_UYV420I                     = 0x1000c228,
 245         CIF_UYV420SP                    = 0x1000c229,
 246         CIF_UYV420P                     = 0x1000c22a,
 247         CIF_VYU420I                     = 0x1000c22c,
 248         CIF_VYU420SP                    = 0x1000c22d,
 249         CIF_VYU420P                     = 0x1000c22e,
 250
 251         CIF_UYV422I                     = 0x10010248,
 252         CIF_UYV422SP                    = 0x10010249,
 253         CIF_UYV422P                     = 0x1001024a,
 254         CIF_VYU422I                     = 0x1001024c,
 255         CIF_VYU422SP                    = 0x1001024d,
 256         CIF_VYU422P                     = 0x1001024e,
 257
 258         CIF_UYV444I                     = 0x10018448,
 259         CIF_UYV444SP                    = 0x10018449,
 260         CIF_UYV444P                     = 0x1001844a,
 261         CIF_VYU444I                     = 0x1001844c,
 262         CIF_VYU444SP                    = 0x1001844d,
 263         CIF_VYU444P                     = 0x1001844e,
 264
 265         /* RGB */
 266         CIF_RGB565                      = 0x20010000,
 267         CIF_RGB666                      = 0x20012000,
 268         CIF_RGB888                      = 0x20018000,
 269
 270         /* RAW Bayer */
 271         CIF_BAYER_SBGGR8                = 0x30008000,
 272         CIF_BAYER_SGBRG8                = 0x30008010,
 273         CIF_BAYER_SGRBG8                = 0x30008020,
 274         CIF_BAYER_SRGGB8                = 0x30008030,
 275
 276         CIF_BAYER_SBGGR10               = 0x3000a000,
 277         CIF_BAYER_SGBRG10               = 0x3000a010,
 278         CIF_BAYER_SGRBG10               = 0x3000a020,
 279         CIF_BAYER_SRGGB10               = 0x3000a030,
 280
 281         CIF_BAYER_SBGGR12               = 0x3000c000,
 282         CIF_BAYER_SGBRG12               = 0x3000c010,
 283         CIF_BAYER_SGRBG12               = 0x3000c020,
 284         CIF_BAYER_SRGGB12               = 0x3000c030,
 285
 286         /* JPEG */
 287         CIF_JPEG                        = 0x40008000,
 288
 289         /* Data */
 290         CIF_DATA                        = 0x70000000,
 291
 292         CIF_UNKNOWN_FORMAT              = 0x80000000
 293 };
 294
 295 enum cif_isp10_stream_id {
 296         CIF_ISP10_STREAM_SP     = 0x1,
 297         CIF_ISP10_STREAM_MP     = 0x2,
 298         CIF_ISP10_STREAM_DMA    = 0x4,
 299         CIF_ISP10_STREAM_ISP    = 0x8
 300 };
 301
 302 #define CIF_ISP10_ALL_STREAMS \
 303         (CIF_ISP10_STREAM_SP | \
 304         CIF_ISP10_STREAM_MP | \
 305         CIF_ISP10_STREAM_DMA)
 306
 307 enum cif_isp10_buff_fmt {
 308         /* values correspond to bitfield values */
 309         CIF_ISP10_BUFF_FMT_PLANAR       = 0,
 310         CIF_ISP10_BUFF_FMT_SEMIPLANAR   = 1,
 311         CIF_ISP10_BUFF_FMT_INTERLEAVED  = 2,
 312
 313         CIF_ISP10_BUFF_FMT_RAW8         = 0,
 314         CIF_ISP10_BUFF_FMT_RAW12        = 2
 315 };
 316
 317 enum cif_isp10_jpeg_header {
 318         CIF_ISP10_JPEG_HEADER_JFIF,
 319         CIF_ISP10_JPEG_HEADER_NONE
 320 };
 321
 322 struct cif_isp10_csi_config {
 323         u32 vc;
 324         u32 nb_lanes;
 325         u32 bit_rate;
 326         /* really used csi */
 327         u32 used_csi; /* xuhf@rock-chips.com: v1.0.4 */
 328 };
 329
 330 struct cif_isp10_paraport_config {
 331         u32 cif_vsync;
 332         u32 cif_hsync;
 333         u32 cif_pclk;
 334         /* really used csi */
 335         u32 used_csi; /* xuhf@rock-chips.com: v1.0.4 */
 336 };
 337
 338 struct cif_isp10_frm_intrvl {
 339         u32 numerator;
 340         u32 denominator;
 341 };
 342
 343 struct cif_isp10_frm_fmt {
 344         u32 width;
 345         u32 height;
 346         u32 stride;
 347         u32 std_id;
 348         enum cif_isp10_pix_fmt pix_fmt;
 349         enum cif_isp10_pix_fmt_quantization quantization;
 350         struct v4l2_rect defrect;
 351 };
 352
 353 struct cif_isp10_strm_fmt {
 354         struct cif_isp10_frm_fmt frm_fmt;
 355         struct cif_isp10_frm_intrvl frm_intrvl;
 356 };
 357
 358 struct cif_isp10_strm_fmt_desc {
 359         bool discrete_frmsize;
 360         struct {
 361                 u32 width;
 362                 u32 height;
 363         } min_frmsize;
 364         struct {
 365                 u32 width;
 366                 u32 height;
 367         } max_frmsize;
 368         enum cif_isp10_pix_fmt pix_fmt;
 369         bool discrete_intrvl;
 370         struct cif_isp10_frm_intrvl min_intrvl;
 371         struct cif_isp10_frm_intrvl max_intrvl;
 372         struct v4l2_rect defrect;
 373         u32 std_id;
 374 };
 375
 376 struct cif_isp10_rsz_config {
 377         struct cif_isp10_frm_fmt *input;
 378         struct cif_isp10_frm_fmt output;
 379         bool ycflt_adjust;
 380         bool ism_adjust;
 381 };
 382
 383 struct cif_isp10_dcrop_config {
 384         unsigned int h_offs;
 385         unsigned int v_offs;
 386         unsigned int h_size;
 387         unsigned int v_size;
 388 };
 389
 390 struct cif_isp10_sp_config {
 391         struct cif_isp10_rsz_config rsz_config;
 392         struct cif_isp10_dcrop_config dcrop;
 393 };
 394
 395 struct cif_isp10_mp_config {
 396         struct cif_isp10_rsz_config rsz_config;
 397         struct cif_isp10_dcrop_config dcrop;
 398 };
 399
 400 struct cif_isp10_mi_path_config {
 401         struct cif_isp10_frm_fmt *input;
 402         struct cif_isp10_frm_fmt output;
 403         u32 llength;
 404         u32 curr_buff_addr;
 405         u32 next_buff_addr;
 406         u32 cb_offs;
 407         u32 cr_offs;
 408         u32 y_size;
 409         u32 cb_size;
 410         u32 cr_size;
 411         bool busy;
 412 };
 413
 414 struct cif_isp10_zoom_buffer_info {
 415         u32 width;
 416         u32 height;
 417         unsigned long  buff_addr;
 418         u32 flags;
 419 };
 420
 421 struct cif_isp10_mi_config {
 422         bool raw_enable;
 423         u32 async_updt;
 424         struct cif_isp10_mi_path_config mp;
 425         struct cif_isp10_mi_path_config sp;
 426         struct cif_isp10_mi_path_config dma;
 427 };
 428
 429 #ifdef NO_YET
 430 struct cif_isp10_buffer {
 431         struct list_head list;
 432         u32 dma_addr;
 433         u32 size;
 434 };
 435 #else
 436 #define cif_isp10_buffer videobuf_buffer
 437 #endif
 438
 439 struct cif_isp10_metadata_s {
 440         unsigned int cnt;
 441         unsigned int vmas;
 442         unsigned char *d;
 443 };
 444
 445 struct cif_isp10_stream {
 446         enum cif_isp10_stream_id id;
 447         enum cif_isp10_state state;
 448         enum cif_isp10_state saved_state;
 449         struct list_head buf_queue;
 450         struct videobuf_buffer *curr_buf;
 451         struct videobuf_buffer *next_buf;
 452         bool updt_cfg;
 453         bool stall;
 454         bool stop;
 455         CIF_ISP10_PLTFRM_EVENT done;
 456         struct cif_isp10_metadata_s metadata;
 457 };
 458
 459 struct cif_isp10_jpeg_config {
 460         bool enable;
 461         bool busy;
 462         u32 ratio;
 463         struct cif_isp10_frm_fmt *input;
 464         enum cif_isp10_jpeg_header header;
 465 };
 466
 467 struct cif_isp10_ie_config {
 468         enum cif_isp10_image_effect effect;
 469 };
 470
 471 /* IS */
 472 struct cif_isp10_ism_params {
 473         unsigned int ctrl;
 474         unsigned int recenter;
 475         unsigned int h_offs;
 476         unsigned int v_offs;
 477         unsigned int h_size;
 478         unsigned int v_size;
 479         unsigned int max_dx;
 480         unsigned int max_dy;
 481         unsigned int displace;
 482 };
 483
 484 struct cif_isp10_ism_config {
 485         bool ism_en;
 486         struct cif_isp10_ism_params ism_params;
 487         bool ism_update_needed;
 488 };
 489
 490 struct cif_isp10_isp_config {
 491         bool si_enable;
 492         struct cif_isp10_ie_config ie_config;
 493         struct cif_isp10_ism_config ism_config;
 494         struct cif_isp10_frm_fmt *input;
 495         struct cif_isp10_frm_fmt output;
 496 };
 497
 498 struct cif_isp10_config {
 499         CIF_ISP10_PLTFRM_MEM_IO_ADDR base_addr;
 500         enum cif_isp10_flash_mode flash_mode;
 501         enum cif_isp10_inp input_sel;
 502         struct cif_isp10_jpeg_config jpeg_config;
 503         struct cif_isp10_mi_config mi_config;
 504         struct cif_isp10_sp_config sp_config;
 505         struct cif_isp10_mp_config mp_config;
 506         struct cif_isp10_strm_fmt img_src_output;
 507         struct cif_isp10_isp_config isp_config;
 508         struct pltfrm_cam_itf cam_itf;
 509         bool out_of_buffer_stall;
 510 };
 511
 512 struct cif_isp10_mi_state {
 513         unsigned long flags;
 514         unsigned int isp_ctrl;
 515         unsigned int y_base_ad;
 516         unsigned int y_size;
 517         unsigned int cb_base_ad;
 518         unsigned int cb_size;
 519         unsigned int cr_base_ad;
 520         unsigned int cr_size;
 521 };
 522
 523 struct cif_isp10_img_src_exp {
 524         struct list_head list;
 525         struct cif_isp10_img_src_ext_ctrl *exp;
 526 };
 527
 528 struct cif_isp10_img_src_data {
 529         unsigned int v_frame_id;
 530         struct isp_supplemental_sensor_mode_data data;
 531 };
 532
 533 struct cif_isp10_img_src_exps {
 534         spinlock_t lock;        /* protect list */
 535         struct list_head list;
 536
 537         struct mutex mutex;     /* protect frm_exp */
 538         struct cif_isp10_img_src_data data[2];
 539         unsigned char exp_valid_frms;
 540 };
 541
 542 enum cif_isp10_isp_vs_cmd {
 543         CIF_ISP10_VS_EXP = 0,
 544 };
 545
 546 struct cif_isp10_isp_vs_work {
 547         struct work_struct work;
 548         struct cif_isp10_device *dev;
 549         enum cif_isp10_isp_vs_cmd cmd;
 550         void *param;
 551 };
 552
 553 struct cif_isp10_fmt {
 554         char *name;
 555         u32 fourcc;
 556         int flags;
 557         int depth;
 558         unsigned char rotation;
 559         unsigned char overlay;
 560 };
 561
 562 struct cif_isp10_device {
 563         unsigned int dev_id;
 564         CIF_ISP10_PLTFRM_DEVICE dev;
 565         struct v4l2_device v4l2_dev;
 566         enum cif_isp10_pm_state pm_state;
 567         enum cif_isp10_img_src_state img_src_state;
 568
 569         spinlock_t vbq_lock;    /* spinlock for videobuf queues */
 570         spinlock_t vbreq_lock;  /* spinlock for videobuf requeues */
 571
 572         struct cif_isp10_img_src *img_src;
 573         struct cif_isp10_img_src *img_src_array[CIF_ISP10_NUM_INPUTS];
 574         unsigned int img_src_cnt;
 575         struct cif_isp10_img_src_exps img_src_exps;
 576
 577         struct cif_isp10_config config;
 578         struct cif_isp10_isp_dev isp_dev;
 579         struct cif_isp10_stream sp_stream;
 580         struct cif_isp10_stream mp_stream;
 581         struct cif_isp10_stream dma_stream;
 582
 583         struct workqueue_struct *vs_wq;
 584         void (*sof_event)(struct cif_isp10_device *dev, __u32 frame_sequence);
 585         /*
 586          * requeue_bufs() is used to clean and rebuild the local buffer
 587          * lists xx_stream.buf_queue. This is used e.g. in the CAPTURE use
 588          * case where we start MP and SP separately and needs to shortly
 589          * stop and start SP when start MP
 590          */
 591         void (*requeue_bufs)(struct cif_isp10_device *dev,
 592                                 enum cif_isp10_stream_id stream_id);
 593         bool   b_isp_frame_in;
 594         bool   b_mi_frame_end;
 595         int   otf_zsl_mode;
 596         struct flash_timeinfo_s flash_t;
 597
 598         struct pltfrm_soc_cfg *soc_cfg;
 599         void *nodes;
 600
 601 };
 602
 603 struct cif_isp10_fmt *get_cif_isp10_output_format(int index);
 604 int get_cif_isp10_output_format_size(void);
 605
 606 struct v4l2_fmtdesc *get_cif_isp10_output_format_desc(int index);
 607 int get_cif_isp10_output_format_desc_size(void);
 608
 609 /* Clean code starts from here */
 610
 611 struct cif_isp10_device *cif_isp10_create(
 612         CIF_ISP10_PLTFRM_DEVICE pdev,
 613         void (*sof_event)(struct cif_isp10_device *dev, __u32 frame_sequence),
 614         void (*requeue_bufs)(struct cif_isp10_device *dev,
 615                                 enum cif_isp10_stream_id stream_id),
 616         struct pltfrm_soc_cfg *soc_cfg);
 617
 618 void cif_isp10_destroy(
 619         struct cif_isp10_device *dev);
 620
 621 int cif_isp10_init(
 622         struct cif_isp10_device *dev,
 623         u32 stream_ids);
 624
 625 int cif_isp10_release(
 626         struct cif_isp10_device *dev,
 627         int stream_ids);
 628
 629 int cif_isp10_streamon(
 630         struct cif_isp10_device *dev,
 631         u32 stream_ids);
 632
 633 int cif_isp10_streamoff(
 634         struct cif_isp10_device *dev,
 635         u32 stream_ids);
 636
 637 int cif_isp10_s_input(
 638         struct cif_isp10_device *dev,
 639         enum cif_isp10_inp inp);
 640
 641 int cif_isp10_s_fmt(
 642         struct cif_isp10_device *dev,
 643         enum cif_isp10_stream_id stream_id,
 644         struct cif_isp10_strm_fmt *strm_fmt,
 645         u32 stride);
 646
 647 int cif_isp10_resume(
 648         struct cif_isp10_device *dev);
 649
 650 int cif_isp10_suspend(
 651         struct cif_isp10_device *dev);
 652
 653 int cif_isp10_qbuf(
 654         struct cif_isp10_device *dev,
 655         enum cif_isp10_stream_id stream,
 656         struct cif_isp10_buffer *buf);
 657
 658 int cif_isp10_reqbufs(
 659         struct cif_isp10_device *dev,
 660         enum cif_isp10_stream_id strm,
 661         struct v4l2_requestbuffers *req);
 662 int cif_isp10_mmap(
 663         struct cif_isp10_device *dev,
 664         enum cif_isp10_stream_id stream_id,
 665         struct vm_area_struct *vma);
 666
 667 int cif_isp10_get_target_frm_size(
 668         struct cif_isp10_device *dev,
 669         u32 *target_width,
 670         u32 *target_height);
 671
 672 int cif_isp10_calc_isp_cropping(
 673         struct cif_isp10_device *dev,
 674         u32 *width,
 675         u32 *height,
 676         u32 *h_offs,
 677         u32 *v_offs);
 678
 679 const char *cif_isp10_g_input_name(
 680         struct cif_isp10_device *dev,
 681         enum cif_isp10_inp inp);
 682
 683 int cif_isp10_calc_min_out_buff_size(
 684         struct cif_isp10_device *dev,
 685         enum cif_isp10_stream_id stream_id,
 686         u32 *size);
 687
 688 int cif_isp10_s_ctrl(
 689         struct cif_isp10_device *dev,
 690         const enum cif_isp10_cid id,
 691         int val);
 692
 693 void cif_isp10_dbgfs_fill_sensor_aec_para(
 694         struct cif_isp10_device *cif_isp10_dev,
 695         s32 exp_time,
 696         u16 gain);
 697
 698 int cif_isp10_s_isp_metadata(
 699         struct cif_isp10_device *dev,
 700         struct cif_isp10_isp_readout_work *readout_work,
 701         struct cifisp_isp_other_cfg *new_other,
 702         struct cifisp_isp_meas_cfg *new_meas,
 703         struct cifisp_stat_buffer *new_stats);
 704
 705 int cif_isp10_s_exp(
 706         struct cif_isp10_device *dev,
 707         struct cif_isp10_img_src_ext_ctrl *exp_ctrl);
 708
 709 void cif_isp10_sensor_mode_data_sync(
 710         struct cif_isp10_device *dev,
 711         unsigned int frame_id,
 712         struct isp_supplemental_sensor_mode_data *data);
 713 #endif