drivers/media/dvb/frontends/stv0367.c

   1 /*
   2  * stv0367.c
   3  *
   4  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2010,2011 NetUP Inc.
   8  * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/string.h>
  29 #include <linux/slab.h>
  30 #include <linux/i2c.h>
  31
  32 #include "stv0367.h"
  33 #include "stv0367_regs.h"
  34 #include "stv0367_priv.h"
  35
  36 static int stvdebug;
  37 module_param_named(debug, stvdebug, int, 0644);
  38
  39 static int i2cdebug;
  40 module_param_named(i2c_debug, i2cdebug, int, 0644);
  41
  42 #define dprintk(args...) \
  43         do { \
  44                 if (stvdebug) \
  45                         printk(KERN_DEBUG args); \
  46         } while (0)
  47         /* DVB-C */
  48
  49 struct stv0367cab_state {
  50         enum stv0367_cab_signal_type    state;
  51         u32     mclk;
  52         u32     adc_clk;
  53         s32     search_range;
  54         s32     derot_offset;
  55         /* results */
  56         int locked;                     /* channel found                */
  57         u32 freq_khz;                   /* found frequency (in kHz)     */
  58         u32 symbol_rate;                /* found symbol rate (in Bds)   */
  59         enum stv0367cab_mod modulation; /* modulation                   */
  60         fe_spectral_inversion_t spect_inv; /* Spectrum Inversion        */
  61 };
  62
  63 struct stv0367ter_state {
  64         /* DVB-T */
  65         enum stv0367_ter_signal_type state;
  66         enum stv0367_ter_if_iq_mode if_iq_mode;
  67         enum stv0367_ter_mode mode;/* mode 2K or 8K */
  68         fe_guard_interval_t guard;
  69         enum stv0367_ter_hierarchy hierarchy;
  70         u32 frequency;
  71         fe_spectral_inversion_t  sense; /*  current search spectrum */
  72         u8  force; /* force mode/guard */
  73         u8  bw; /* channel width 6, 7 or 8 in MHz */
  74         u8  pBW; /* channel width used during previous lock */
  75         u32 pBER;
  76         u32 pPER;
  77         u32 ucblocks;
  78         s8  echo_pos; /* echo position */
  79         u8  first_lock;
  80         u8  unlock_counter;
  81         u32 agc_val;
  82 };
  83
  84 struct stv0367_state {
  85         struct dvb_frontend fe;
  86         struct i2c_adapter *i2c;
  87         /* config settings */
  88         const struct stv0367_config *config;
  89         u8 chip_id;
  90         /* DVB-C */
  91         struct stv0367cab_state *cab_state;
  92         /* DVB-T */
  93         struct stv0367ter_state *ter_state;
  94 };
  95
  96 struct st_register {
  97         u16     addr;
  98         u8      value;
  99 };
 100
 101 /* values for STV4100 XTAL=30M int clk=53.125M*/
 102 static struct st_register def0367ter[STV0367TER_NBREGS] = {
 103         {R367TER_ID,            0x60},
 104         {R367TER_I2CRPT,        0xa0},
 105         /* {R367TER_I2CRPT,     0x22},*/
 106         {R367TER_TOPCTRL,       0x00},/* for xc5000; was 0x02 */
 107         {R367TER_IOCFG0,        0x40},
 108         {R367TER_DAC0R,         0x00},
 109         {R367TER_IOCFG1,        0x00},
 110         {R367TER_DAC1R,         0x00},
 111         {R367TER_IOCFG2,        0x62},
 112         {R367TER_SDFR,          0x00},
 113         {R367TER_STATUS,        0xf8},
 114         {R367TER_AUX_CLK,       0x0a},
 115         {R367TER_FREESYS1,      0x00},
 116         {R367TER_FREESYS2,      0x00},
 117         {R367TER_FREESYS3,      0x00},
 118         {R367TER_GPIO_CFG,      0x55},
 119         {R367TER_GPIO_CMD,      0x00},
 120         {R367TER_AGC2MAX,       0xff},
 121         {R367TER_AGC2MIN,       0x00},
 122         {R367TER_AGC1MAX,       0xff},
 123         {R367TER_AGC1MIN,       0x00},
 124         {R367TER_AGCR,          0xbc},
 125         {R367TER_AGC2TH,        0x00},
 126         {R367TER_AGC12C,        0x00},
 127         {R367TER_AGCCTRL1,      0x85},
 128         {R367TER_AGCCTRL2,      0x1f},
 129         {R367TER_AGC1VAL1,      0x00},
 130         {R367TER_AGC1VAL2,      0x00},
 131         {R367TER_AGC2VAL1,      0x6f},
 132         {R367TER_AGC2VAL2,      0x05},
 133         {R367TER_AGC2PGA,       0x00},
 134         {R367TER_OVF_RATE1,     0x00},
 135         {R367TER_OVF_RATE2,     0x00},
 136         {R367TER_GAIN_SRC1,     0xaa},/* for xc5000; was 0x2b */
 137         {R367TER_GAIN_SRC2,     0xd6},/* for xc5000; was 0x04 */
 138         {R367TER_INC_DEROT1,    0x55},
 139         {R367TER_INC_DEROT2,    0x55},
 140         {R367TER_PPM_CPAMP_DIR, 0x2c},
 141         {R367TER_PPM_CPAMP_INV, 0x00},
 142         {R367TER_FREESTFE_1,    0x00},
 143         {R367TER_FREESTFE_2,    0x1c},
 144         {R367TER_DCOFFSET,      0x00},
 145         {R367TER_EN_PROCESS,    0x05},
 146         {R367TER_SDI_SMOOTHER,  0x80},
 147         {R367TER_FE_LOOP_OPEN,  0x1c},
 148         {R367TER_FREQOFF1,      0x00},
 149         {R367TER_FREQOFF2,      0x00},
 150         {R367TER_FREQOFF3,      0x00},
 151         {R367TER_TIMOFF1,       0x00},
 152         {R367TER_TIMOFF2,       0x00},
 153         {R367TER_EPQ,           0x02},
 154         {R367TER_EPQAUTO,       0x01},
 155         {R367TER_SYR_UPDATE,    0xf5},
 156         {R367TER_CHPFREE,       0x00},
 157         {R367TER_PPM_STATE_MAC, 0x23},
 158         {R367TER_INR_THRESHOLD, 0xff},
 159         {R367TER_EPQ_TPS_ID_CELL, 0xf9},
 160         {R367TER_EPQ_CFG,       0x00},
 161         {R367TER_EPQ_STATUS,    0x01},
 162         {R367TER_AUTORELOCK,    0x81},
 163         {R367TER_BER_THR_VMSB,  0x00},
 164         {R367TER_BER_THR_MSB,   0x00},
 165         {R367TER_BER_THR_LSB,   0x00},
 166         {R367TER_CCD,           0x83},
 167         {R367TER_SPECTR_CFG,    0x00},
 168         {R367TER_CHC_DUMMY,     0x18},
 169         {R367TER_INC_CTL,       0x88},
 170         {R367TER_INCTHRES_COR1, 0xb4},
 171         {R367TER_INCTHRES_COR2, 0x96},
 172         {R367TER_INCTHRES_DET1, 0x0e},
 173         {R367TER_INCTHRES_DET2, 0x11},
 174         {R367TER_IIR_CELLNB,    0x8d},
 175         {R367TER_IIRCX_COEFF1_MSB, 0x00},
 176         {R367TER_IIRCX_COEFF1_LSB, 0x00},
 177         {R367TER_IIRCX_COEFF2_MSB, 0x09},
 178         {R367TER_IIRCX_COEFF2_LSB, 0x18},
 179         {R367TER_IIRCX_COEFF3_MSB, 0x14},
 180         {R367TER_IIRCX_COEFF3_LSB, 0x9c},
 181         {R367TER_IIRCX_COEFF4_MSB, 0x00},
 182         {R367TER_IIRCX_COEFF4_LSB, 0x00},
 183         {R367TER_IIRCX_COEFF5_MSB, 0x36},
 184         {R367TER_IIRCX_COEFF5_LSB, 0x42},
 185         {R367TER_FEPATH_CFG,    0x00},
 186         {R367TER_PMC1_FUNC,     0x65},
 187         {R367TER_PMC1_FOR,      0x00},
 188         {R367TER_PMC2_FUNC,     0x00},
 189         {R367TER_STATUS_ERR_DA, 0xe0},
 190         {R367TER_DIG_AGC_R,     0xfe},
 191         {R367TER_COMAGC_TARMSB, 0x0b},
 192         {R367TER_COM_AGC_TAR_ENMODE, 0x41},
 193         {R367TER_COM_AGC_CFG,   0x3e},
 194         {R367TER_COM_AGC_GAIN1, 0x39},
 195         {R367TER_AUT_AGC_TARGETMSB, 0x0b},
 196         {R367TER_LOCK_DET_MSB,  0x01},
 197         {R367TER_AGCTAR_LOCK_LSBS, 0x40},
 198         {R367TER_AUT_GAIN_EN,   0xf4},
 199         {R367TER_AUT_CFG,       0xf0},
 200         {R367TER_LOCKN,         0x23},
 201         {R367TER_INT_X_3,       0x00},
 202         {R367TER_INT_X_2,       0x03},
 203         {R367TER_INT_X_1,       0x8d},
 204         {R367TER_INT_X_0,       0xa0},
 205         {R367TER_MIN_ERRX_MSB,  0x00},
 206         {R367TER_COR_CTL,       0x23},
 207         {R367TER_COR_STAT,      0xf6},
 208         {R367TER_COR_INTEN,     0x00},
 209         {R367TER_COR_INTSTAT,   0x3f},
 210         {R367TER_COR_MODEGUARD, 0x03},
 211         {R367TER_AGC_CTL,       0x08},
 212         {R367TER_AGC_MANUAL1,   0x00},
 213         {R367TER_AGC_MANUAL2,   0x00},
 214         {R367TER_AGC_TARG,      0x16},
 215         {R367TER_AGC_GAIN1,     0x53},
 216         {R367TER_AGC_GAIN2,     0x1d},
 217         {R367TER_RESERVED_1,    0x00},
 218         {R367TER_RESERVED_2,    0x00},
 219         {R367TER_RESERVED_3,    0x00},
 220         {R367TER_CAS_CTL,       0x44},
 221         {R367TER_CAS_FREQ,      0xb3},
 222         {R367TER_CAS_DAGCGAIN,  0x12},
 223         {R367TER_SYR_CTL,       0x04},
 224         {R367TER_SYR_STAT,      0x10},
 225         {R367TER_SYR_NCO1,      0x00},
 226         {R367TER_SYR_NCO2,      0x00},
 227         {R367TER_SYR_OFFSET1,   0x00},
 228         {R367TER_SYR_OFFSET2,   0x00},
 229         {R367TER_FFT_CTL,       0x00},
 230         {R367TER_SCR_CTL,       0x70},
 231         {R367TER_PPM_CTL1,      0xf8},
 232         {R367TER_TRL_CTL,       0x14},/* for xc5000; was 0xac */
 233         {R367TER_TRL_NOMRATE1,  0xae},/* for xc5000; was 0x1e */
 234         {R367TER_TRL_NOMRATE2,  0x56},/* for xc5000; was 0x58 */
 235         {R367TER_TRL_TIME1,     0x1d},
 236         {R367TER_TRL_TIME2,     0xfc},
 237         {R367TER_CRL_CTL,       0x24},
 238         {R367TER_CRL_FREQ1,     0xad},
 239         {R367TER_CRL_FREQ2,     0x9d},
 240         {R367TER_CRL_FREQ3,     0xff},
 241         {R367TER_CHC_CTL,       0x01},
 242         {R367TER_CHC_SNR,       0xf0},
 243         {R367TER_BDI_CTL,       0x00},
 244         {R367TER_DMP_CTL,       0x00},
 245         {R367TER_TPS_RCVD1,     0x30},
 246         {R367TER_TPS_RCVD2,     0x02},
 247         {R367TER_TPS_RCVD3,     0x01},
 248         {R367TER_TPS_RCVD4,     0x00},
 249         {R367TER_TPS_ID_CELL1,  0x00},
 250         {R367TER_TPS_ID_CELL2,  0x00},
 251         {R367TER_TPS_RCVD5_SET1, 0x02},
 252         {R367TER_TPS_SET2,      0x02},
 253         {R367TER_TPS_SET3,      0x01},
 254         {R367TER_TPS_CTL,       0x00},
 255         {R367TER_CTL_FFTOSNUM,  0x34},
 256         {R367TER_TESTSELECT,    0x09},
 257         {R367TER_MSC_REV,       0x0a},
 258         {R367TER_PIR_CTL,       0x00},
 259         {R367TER_SNR_CARRIER1,  0xa1},
 260         {R367TER_SNR_CARRIER2,  0x9a},
 261         {R367TER_PPM_CPAMP,     0x2c},
 262         {R367TER_TSM_AP0,       0x00},
 263         {R367TER_TSM_AP1,       0x00},
 264         {R367TER_TSM_AP2 ,      0x00},
 265         {R367TER_TSM_AP3,       0x00},
 266         {R367TER_TSM_AP4,       0x00},
 267         {R367TER_TSM_AP5,       0x00},
 268         {R367TER_TSM_AP6,       0x00},
 269         {R367TER_TSM_AP7,       0x00},
 270         {R367TER_TSTRES,        0x00},
 271         {R367TER_ANACTRL,       0x0D},/* PLL stoped, restart at init!!! */
 272         {R367TER_TSTBUS,        0x00},
 273         {R367TER_TSTRATE,       0x00},
 274         {R367TER_CONSTMODE,     0x01},
 275         {R367TER_CONSTCARR1,    0x00},
 276         {R367TER_CONSTCARR2,    0x00},
 277         {R367TER_ICONSTEL,      0x0a},
 278         {R367TER_QCONSTEL,      0x15},
 279         {R367TER_TSTBISTRES0,   0x00},
 280         {R367TER_TSTBISTRES1,   0x00},
 281         {R367TER_TSTBISTRES2,   0x28},
 282         {R367TER_TSTBISTRES3,   0x00},
 283         {R367TER_RF_AGC1,       0xff},
 284         {R367TER_RF_AGC2,       0x83},
 285         {R367TER_ANADIGCTRL,    0x19},
 286         {R367TER_PLLMDIV,       0x01},/* for xc5000; was 0x0c */
 287         {R367TER_PLLNDIV,       0x06},/* for xc5000; was 0x55 */
 288         {R367TER_PLLSETUP,      0x18},
 289         {R367TER_DUAL_AD12,     0x0C},/* for xc5000 AGC voltage 1.6V */
 290         {R367TER_TSTBIST,       0x00},
 291         {R367TER_PAD_COMP_CTRL, 0x00},
 292         {R367TER_PAD_COMP_WR,   0x00},
 293         {R367TER_PAD_COMP_RD,   0xe0},
 294         {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
 295         {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
 296         {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
 297         {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
 298         {R367TER_SYR_FLAG,      0x00},
 299         {R367TER_CRL_TARGET1,   0x00},
 300         {R367TER_CRL_TARGET2,   0x00},
 301         {R367TER_CRL_TARGET3,   0x00},
 302         {R367TER_CRL_TARGET4,   0x00},
 303         {R367TER_CRL_FLAG,      0x00},
 304         {R367TER_TRL_TARGET1,   0x00},
 305         {R367TER_TRL_TARGET2,   0x00},
 306         {R367TER_TRL_CHC,       0x00},
 307         {R367TER_CHC_SNR_TARG,  0x00},
 308         {R367TER_TOP_TRACK,     0x00},
 309         {R367TER_TRACKER_FREE1, 0x00},
 310         {R367TER_ERROR_CRL1,    0x00},
 311         {R367TER_ERROR_CRL2,    0x00},
 312         {R367TER_ERROR_CRL3,    0x00},
 313         {R367TER_ERROR_CRL4,    0x00},
 314         {R367TER_DEC_NCO1,      0x2c},
 315         {R367TER_DEC_NCO2,      0x0f},
 316         {R367TER_DEC_NCO3,      0x20},
 317         {R367TER_SNR,           0xf1},
 318         {R367TER_SYR_FFTADJ1,   0x00},
 319         {R367TER_SYR_FFTADJ2,   0x00},
 320         {R367TER_SYR_CHCADJ1,   0x00},
 321         {R367TER_SYR_CHCADJ2,   0x00},
 322         {R367TER_SYR_OFF,       0x00},
 323         {R367TER_PPM_OFFSET1,   0x00},
 324         {R367TER_PPM_OFFSET2,   0x03},
 325         {R367TER_TRACKER_FREE2, 0x00},
 326         {R367TER_DEBG_LT10,     0x00},
 327         {R367TER_DEBG_LT11,     0x00},
 328         {R367TER_DEBG_LT12,     0x00},
 329         {R367TER_DEBG_LT13,     0x00},
 330         {R367TER_DEBG_LT14,     0x00},
 331         {R367TER_DEBG_LT15,     0x00},
 332         {R367TER_DEBG_LT16,     0x00},
 333         {R367TER_DEBG_LT17,     0x00},
 334         {R367TER_DEBG_LT18,     0x00},
 335         {R367TER_DEBG_LT19,     0x00},
 336         {R367TER_DEBG_LT1A,     0x00},
 337         {R367TER_DEBG_LT1B,     0x00},
 338         {R367TER_DEBG_LT1C,     0x00},
 339         {R367TER_DEBG_LT1D,     0x00},
 340         {R367TER_DEBG_LT1E,     0x00},
 341         {R367TER_DEBG_LT1F,     0x00},
 342         {R367TER_RCCFGH,        0x00},
 343         {R367TER_RCCFGM,        0x00},
 344         {R367TER_RCCFGL,        0x00},
 345         {R367TER_RCINSDELH,     0x00},
 346         {R367TER_RCINSDELM,     0x00},
 347         {R367TER_RCINSDELL,     0x00},
 348         {R367TER_RCSTATUS,      0x00},
 349         {R367TER_RCSPEED,       0x6f},
 350         {R367TER_RCDEBUGM,      0xe7},
 351         {R367TER_RCDEBUGL,      0x9b},
 352         {R367TER_RCOBSCFG,      0x00},
 353         {R367TER_RCOBSM,        0x00},
 354         {R367TER_RCOBSL,        0x00},
 355         {R367TER_RCFECSPY,      0x00},
 356         {R367TER_RCFSPYCFG,     0x00},
 357         {R367TER_RCFSPYDATA,    0x00},
 358         {R367TER_RCFSPYOUT,     0x00},
 359         {R367TER_RCFSTATUS,     0x00},
 360         {R367TER_RCFGOODPACK,   0x00},
 361         {R367TER_RCFPACKCNT,    0x00},
 362         {R367TER_RCFSPYMISC,    0x00},
 363         {R367TER_RCFBERCPT4,    0x00},
 364         {R367TER_RCFBERCPT3,    0x00},
 365         {R367TER_RCFBERCPT2,    0x00},
 366         {R367TER_RCFBERCPT1,    0x00},
 367         {R367TER_RCFBERCPT0,    0x00},
 368         {R367TER_RCFBERERR2,    0x00},
 369         {R367TER_RCFBERERR1,    0x00},
 370         {R367TER_RCFBERERR0,    0x00},
 371         {R367TER_RCFSTATESM,    0x00},
 372         {R367TER_RCFSTATESL,    0x00},
 373         {R367TER_RCFSPYBER,     0x00},
 374         {R367TER_RCFSPYDISTM,   0x00},
 375         {R367TER_RCFSPYDISTL,   0x00},
 376         {R367TER_RCFSPYOBS7,    0x00},
 377         {R367TER_RCFSPYOBS6,    0x00},
 378         {R367TER_RCFSPYOBS5,    0x00},
 379         {R367TER_RCFSPYOBS4,    0x00},
 380         {R367TER_RCFSPYOBS3,    0x00},
 381         {R367TER_RCFSPYOBS2,    0x00},
 382         {R367TER_RCFSPYOBS1,    0x00},
 383         {R367TER_RCFSPYOBS0,    0x00},
 384         {R367TER_TSGENERAL,     0x00},
 385         {R367TER_RC1SPEED,      0x6f},
 386         {R367TER_TSGSTATUS,     0x18},
 387         {R367TER_FECM,          0x01},
 388         {R367TER_VTH12,         0xff},
 389         {R367TER_VTH23,         0xa1},
 390         {R367TER_VTH34,         0x64},
 391         {R367TER_VTH56,         0x40},
 392         {R367TER_VTH67,         0x00},
 393         {R367TER_VTH78,         0x2c},
 394         {R367TER_VITCURPUN,     0x12},
 395         {R367TER_VERROR,        0x01},
 396         {R367TER_PRVIT,         0x3f},
 397         {R367TER_VAVSRVIT,      0x00},
 398         {R367TER_VSTATUSVIT,    0xbd},
 399         {R367TER_VTHINUSE,      0xa1},
 400         {R367TER_KDIV12,        0x20},
 401         {R367TER_KDIV23,        0x40},
 402         {R367TER_KDIV34,        0x20},
 403         {R367TER_KDIV56,        0x30},
 404         {R367TER_KDIV67,        0x00},
 405         {R367TER_KDIV78,        0x30},
 406         {R367TER_SIGPOWER,      0x54},
 407         {R367TER_DEMAPVIT,      0x40},
 408         {R367TER_VITSCALE,      0x00},
 409         {R367TER_FFEC1PRG,      0x00},
 410         {R367TER_FVITCURPUN,    0x12},
 411         {R367TER_FVERROR,       0x01},
 412         {R367TER_FVSTATUSVIT,   0xbd},
 413         {R367TER_DEBUG_LT1,     0x00},
 414         {R367TER_DEBUG_LT2,     0x00},
 415         {R367TER_DEBUG_LT3,     0x00},
 416         {R367TER_TSTSFMET,      0x00},
 417         {R367TER_SELOUT,        0x00},
 418         {R367TER_TSYNC,         0x00},
 419         {R367TER_TSTERR,        0x00},
 420         {R367TER_TSFSYNC,       0x00},
 421         {R367TER_TSTSFERR,      0x00},
 422         {R367TER_TSTTSSF1,      0x01},
 423         {R367TER_TSTTSSF2,      0x1f},
 424         {R367TER_TSTTSSF3,      0x00},
 425         {R367TER_TSTTS1,        0x00},
 426         {R367TER_TSTTS2,        0x1f},
 427         {R367TER_TSTTS3,        0x01},
 428         {R367TER_TSTTS4,        0x00},
 429         {R367TER_TSTTSRC,       0x00},
 430         {R367TER_TSTTSRS,       0x00},
 431         {R367TER_TSSTATEM,      0xb0},
 432         {R367TER_TSSTATEL,      0x40},
 433         {R367TER_TSCFGH,        0xC0},
 434         {R367TER_TSCFGM,        0xc0},/* for xc5000; was 0x00 */
 435         {R367TER_TSCFGL,        0x20},
 436         {R367TER_TSSYNC,        0x00},
 437         {R367TER_TSINSDELH,     0x00},
 438         {R367TER_TSINSDELM,     0x00},
 439         {R367TER_TSINSDELL,     0x00},
 440         {R367TER_TSDIVN,        0x03},
 441         {R367TER_TSDIVPM,       0x00},
 442         {R367TER_TSDIVPL,       0x00},
 443         {R367TER_TSDIVQM,       0x00},
 444         {R367TER_TSDIVQL,       0x00},
 445         {R367TER_TSDILSTKM,     0x00},
 446         {R367TER_TSDILSTKL,     0x00},
 447         {R367TER_TSSPEED,       0x40},/* for xc5000; was 0x6f */
 448         {R367TER_TSSTATUS,      0x81},
 449         {R367TER_TSSTATUS2,     0x6a},
 450         {R367TER_TSBITRATEM,    0x0f},
 451         {R367TER_TSBITRATEL,    0xc6},
 452         {R367TER_TSPACKLENM,    0x00},
 453         {R367TER_TSPACKLENL,    0xfc},
 454         {R367TER_TSBLOCLENM,    0x0a},
 455         {R367TER_TSBLOCLENL,    0x80},
 456         {R367TER_TSDLYH,        0x90},
 457         {R367TER_TSDLYM,        0x68},
 458         {R367TER_TSDLYL,        0x01},
 459         {R367TER_TSNPDAV,       0x00},
 460         {R367TER_TSBUFSTATH,    0x00},
 461         {R367TER_TSBUFSTATM,    0x00},
 462         {R367TER_TSBUFSTATL,    0x00},
 463         {R367TER_TSDEBUGM,      0xcf},
 464         {R367TER_TSDEBUGL,      0x1e},
 465         {R367TER_TSDLYSETH,     0x00},
 466         {R367TER_TSDLYSETM,     0x68},
 467         {R367TER_TSDLYSETL,     0x00},
 468         {R367TER_TSOBSCFG,      0x00},
 469         {R367TER_TSOBSM,        0x47},
 470         {R367TER_TSOBSL,        0x1f},
 471         {R367TER_ERRCTRL1,      0x95},
 472         {R367TER_ERRCNT1H,      0x80},
 473         {R367TER_ERRCNT1M,      0x00},
 474         {R367TER_ERRCNT1L,      0x00},
 475         {R367TER_ERRCTRL2,      0x95},
 476         {R367TER_ERRCNT2H,      0x00},
 477         {R367TER_ERRCNT2M,      0x00},
 478         {R367TER_ERRCNT2L,      0x00},
 479         {R367TER_FECSPY,        0x88},
 480         {R367TER_FSPYCFG,       0x2c},
 481         {R367TER_FSPYDATA,      0x3a},
 482         {R367TER_FSPYOUT,       0x06},
 483         {R367TER_FSTATUS,       0x61},
 484         {R367TER_FGOODPACK,     0xff},
 485         {R367TER_FPACKCNT,      0xff},
 486         {R367TER_FSPYMISC,      0x66},
 487         {R367TER_FBERCPT4,      0x00},
 488         {R367TER_FBERCPT3,      0x00},
 489         {R367TER_FBERCPT2,      0x36},
 490         {R367TER_FBERCPT1,      0x36},
 491         {R367TER_FBERCPT0,      0x14},
 492         {R367TER_FBERERR2,      0x00},
 493         {R367TER_FBERERR1,      0x03},
 494         {R367TER_FBERERR0,      0x28},
 495         {R367TER_FSTATESM,      0x00},
 496         {R367TER_FSTATESL,      0x02},
 497         {R367TER_FSPYBER,       0x00},
 498         {R367TER_FSPYDISTM,     0x01},
 499         {R367TER_FSPYDISTL,     0x9f},
 500         {R367TER_FSPYOBS7,      0xc9},
 501         {R367TER_FSPYOBS6,      0x99},
 502         {R367TER_FSPYOBS5,      0x08},
 503         {R367TER_FSPYOBS4,      0xec},
 504         {R367TER_FSPYOBS3,      0x01},
 505         {R367TER_FSPYOBS2,      0x0f},
 506         {R367TER_FSPYOBS1,      0xf5},
 507         {R367TER_FSPYOBS0,      0x08},
 508         {R367TER_SFDEMAP,       0x40},
 509         {R367TER_SFERROR,       0x00},
 510         {R367TER_SFAVSR,        0x30},
 511         {R367TER_SFECSTATUS,    0xcc},
 512         {R367TER_SFKDIV12,      0x20},
 513         {R367TER_SFKDIV23,      0x40},
 514         {R367TER_SFKDIV34,      0x20},
 515         {R367TER_SFKDIV56,      0x20},
 516         {R367TER_SFKDIV67,      0x00},
 517         {R367TER_SFKDIV78,      0x20},
 518         {R367TER_SFDILSTKM,     0x00},
 519         {R367TER_SFDILSTKL,     0x00},
 520         {R367TER_SFSTATUS,      0xb5},
 521         {R367TER_SFDLYH,        0x90},
 522         {R367TER_SFDLYM,        0x60},
 523         {R367TER_SFDLYL,        0x01},
 524         {R367TER_SFDLYSETH,     0xc0},
 525         {R367TER_SFDLYSETM,     0x60},
 526         {R367TER_SFDLYSETL,     0x00},
 527         {R367TER_SFOBSCFG,      0x00},
 528         {R367TER_SFOBSM,        0x47},
 529         {R367TER_SFOBSL,        0x05},
 530         {R367TER_SFECINFO,      0x40},
 531         {R367TER_SFERRCTRL,     0x74},
 532         {R367TER_SFERRCNTH,     0x80},
 533         {R367TER_SFERRCNTM ,    0x00},
 534         {R367TER_SFERRCNTL,     0x00},
 535         {R367TER_SYMBRATEM,     0x2f},
 536         {R367TER_SYMBRATEL,     0x50},
 537         {R367TER_SYMBSTATUS,    0x7f},
 538         {R367TER_SYMBCFG,       0x00},
 539         {R367TER_SYMBFIFOM,     0xf4},
 540         {R367TER_SYMBFIFOL,     0x0d},
 541         {R367TER_SYMBOFFSM,     0xf0},
 542         {R367TER_SYMBOFFSL,     0x2d},
 543         {R367TER_DEBUG_LT4,     0x00},
 544         {R367TER_DEBUG_LT5,     0x00},
 545         {R367TER_DEBUG_LT6,     0x00},
 546         {R367TER_DEBUG_LT7,     0x00},
 547         {R367TER_DEBUG_LT8,     0x00},
 548         {R367TER_DEBUG_LT9,     0x00},
 549 };
 550
 551 #define RF_LOOKUP_TABLE_SIZE  31
 552 #define RF_LOOKUP_TABLE2_SIZE 16
 553 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
 554 s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
 555         {/*AGC1*/
 556                 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
 557                 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
 558                 76, 77, 78, 80, 83, 85, 88,
 559         }, {/*RF(dbm)*/
 560                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 561                 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
 562                 49, 50, 52, 53, 54, 55, 56,
 563         }
 564 };
 565 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
 566 s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
 567         {/*AGC2*/
 568                 28, 29, 31, 32, 34, 35, 36, 37,
 569                 38, 39, 40, 41, 42, 43, 44, 45,
 570         }, {/*RF(dbm)*/
 571                 57, 58, 59, 60, 61, 62, 63, 64,
 572                 65, 66, 67, 68, 69, 70, 71, 72,
 573         }
 574 };
 575
 576 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
 577         {R367CAB_ID,            0x60},
 578         {R367CAB_I2CRPT,        0xa0},
 579         /*{R367CAB_I2CRPT,      0x22},*/
 580         {R367CAB_TOPCTRL,       0x10},
 581         {R367CAB_IOCFG0,        0x80},
 582         {R367CAB_DAC0R,         0x00},
 583         {R367CAB_IOCFG1,        0x00},
 584         {R367CAB_DAC1R,         0x00},
 585         {R367CAB_IOCFG2,        0x00},
 586         {R367CAB_SDFR,          0x00},
 587         {R367CAB_AUX_CLK,       0x00},
 588         {R367CAB_FREESYS1,      0x00},
 589         {R367CAB_FREESYS2,      0x00},
 590         {R367CAB_FREESYS3,      0x00},
 591         {R367CAB_GPIO_CFG,      0x55},
 592         {R367CAB_GPIO_CMD,      0x01},
 593         {R367CAB_TSTRES,        0x00},
 594         {R367CAB_ANACTRL,       0x0d},/* was 0x00 need to check - I.M.L.*/
 595         {R367CAB_TSTBUS,        0x00},
 596         {R367CAB_RF_AGC1,       0xea},
 597         {R367CAB_RF_AGC2,       0x82},
 598         {R367CAB_ANADIGCTRL,    0x0b},
 599         {R367CAB_PLLMDIV,       0x01},
 600         {R367CAB_PLLNDIV,       0x08},
 601         {R367CAB_PLLSETUP,      0x18},
 602         {R367CAB_DUAL_AD12,     0x0C}, /* for xc5000 AGC voltage 1.6V */
 603         {R367CAB_TSTBIST,       0x00},
 604         {R367CAB_CTRL_1,        0x00},
 605         {R367CAB_CTRL_2,        0x03},
 606         {R367CAB_IT_STATUS1,    0x2b},
 607         {R367CAB_IT_STATUS2,    0x08},
 608         {R367CAB_IT_EN1,        0x00},
 609         {R367CAB_IT_EN2,        0x00},
 610         {R367CAB_CTRL_STATUS,   0x04},
 611         {R367CAB_TEST_CTL,      0x00},
 612         {R367CAB_AGC_CTL,       0x73},
 613         {R367CAB_AGC_IF_CFG,    0x50},
 614         {R367CAB_AGC_RF_CFG,    0x00},
 615         {R367CAB_AGC_PWM_CFG,   0x03},
 616         {R367CAB_AGC_PWR_REF_L, 0x5a},
 617         {R367CAB_AGC_PWR_REF_H, 0x00},
 618         {R367CAB_AGC_RF_TH_L,   0xff},
 619         {R367CAB_AGC_RF_TH_H,   0x07},
 620         {R367CAB_AGC_IF_LTH_L,  0x00},
 621         {R367CAB_AGC_IF_LTH_H,  0x08},
 622         {R367CAB_AGC_IF_HTH_L,  0xff},
 623         {R367CAB_AGC_IF_HTH_H,  0x07},
 624         {R367CAB_AGC_PWR_RD_L,  0xa0},
 625         {R367CAB_AGC_PWR_RD_M,  0xe9},
 626         {R367CAB_AGC_PWR_RD_H,  0x03},
 627         {R367CAB_AGC_PWM_IFCMD_L,       0xe4},
 628         {R367CAB_AGC_PWM_IFCMD_H,       0x00},
 629         {R367CAB_AGC_PWM_RFCMD_L,       0xff},
 630         {R367CAB_AGC_PWM_RFCMD_H,       0x07},
 631         {R367CAB_IQDEM_CFG,     0x01},
 632         {R367CAB_MIX_NCO_LL,    0x22},
 633         {R367CAB_MIX_NCO_HL,    0x96},
 634         {R367CAB_MIX_NCO_HH,    0x55},
 635         {R367CAB_SRC_NCO_LL,    0xff},
 636         {R367CAB_SRC_NCO_LH,    0x0c},
 637         {R367CAB_SRC_NCO_HL,    0xf5},
 638         {R367CAB_SRC_NCO_HH,    0x20},
 639         {R367CAB_IQDEM_GAIN_SRC_L,      0x06},
 640         {R367CAB_IQDEM_GAIN_SRC_H,      0x01},
 641         {R367CAB_IQDEM_DCRM_CFG_LL,     0xfe},
 642         {R367CAB_IQDEM_DCRM_CFG_LH,     0xff},
 643         {R367CAB_IQDEM_DCRM_CFG_HL,     0x0f},
 644         {R367CAB_IQDEM_DCRM_CFG_HH,     0x00},
 645         {R367CAB_IQDEM_ADJ_COEFF0,      0x34},
 646         {R367CAB_IQDEM_ADJ_COEFF1,      0xae},
 647         {R367CAB_IQDEM_ADJ_COEFF2,      0x46},
 648         {R367CAB_IQDEM_ADJ_COEFF3,      0x77},
 649         {R367CAB_IQDEM_ADJ_COEFF4,      0x96},
 650         {R367CAB_IQDEM_ADJ_COEFF5,      0x69},
 651         {R367CAB_IQDEM_ADJ_COEFF6,      0xc7},
 652         {R367CAB_IQDEM_ADJ_COEFF7,      0x01},
 653         {R367CAB_IQDEM_ADJ_EN,  0x04},
 654         {R367CAB_IQDEM_ADJ_AGC_REF,     0x94},
 655         {R367CAB_ALLPASSFILT1,  0xc9},
 656         {R367CAB_ALLPASSFILT2,  0x2d},
 657         {R367CAB_ALLPASSFILT3,  0xa3},
 658         {R367CAB_ALLPASSFILT4,  0xfb},
 659         {R367CAB_ALLPASSFILT5,  0xf6},
 660         {R367CAB_ALLPASSFILT6,  0x45},
 661         {R367CAB_ALLPASSFILT7,  0x6f},
 662         {R367CAB_ALLPASSFILT8,  0x7e},
 663         {R367CAB_ALLPASSFILT9,  0x05},
 664         {R367CAB_ALLPASSFILT10, 0x0a},
 665         {R367CAB_ALLPASSFILT11, 0x51},
 666         {R367CAB_TRL_AGC_CFG,   0x20},
 667         {R367CAB_TRL_LPF_CFG,   0x28},
 668         {R367CAB_TRL_LPF_ACQ_GAIN,      0x44},
 669         {R367CAB_TRL_LPF_TRK_GAIN,      0x22},
 670         {R367CAB_TRL_LPF_OUT_GAIN,      0x03},
 671         {R367CAB_TRL_LOCKDET_LTH,       0x04},
 672         {R367CAB_TRL_LOCKDET_HTH,       0x11},
 673         {R367CAB_TRL_LOCKDET_TRGVAL,    0x20},
 674         {R367CAB_IQ_QAM,        0x01},
 675         {R367CAB_FSM_STATE,     0xa0},
 676         {R367CAB_FSM_CTL,       0x08},
 677         {R367CAB_FSM_STS,       0x0c},
 678         {R367CAB_FSM_SNR0_HTH,  0x00},
 679         {R367CAB_FSM_SNR1_HTH,  0x00},
 680         {R367CAB_FSM_SNR2_HTH,  0x23},/* 0x00 */
 681         {R367CAB_FSM_SNR0_LTH,  0x00},
 682         {R367CAB_FSM_SNR1_LTH,  0x00},
 683         {R367CAB_FSM_EQA1_HTH,  0x00},
 684         {R367CAB_FSM_TEMPO,     0x32},
 685         {R367CAB_FSM_CONFIG,    0x03},
 686         {R367CAB_EQU_I_TESTTAP_L,       0x11},
 687         {R367CAB_EQU_I_TESTTAP_M,       0x00},
 688         {R367CAB_EQU_I_TESTTAP_H,       0x00},
 689         {R367CAB_EQU_TESTAP_CFG,        0x00},
 690         {R367CAB_EQU_Q_TESTTAP_L,       0xff},
 691         {R367CAB_EQU_Q_TESTTAP_M,       0x00},
 692         {R367CAB_EQU_Q_TESTTAP_H,       0x00},
 693         {R367CAB_EQU_TAP_CTRL,  0x00},
 694         {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
 695         {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
 696         {R367CAB_EQU_CTR_HIPOW_L,       0x00},
 697         {R367CAB_EQU_CTR_HIPOW_H,       0x00},
 698         {R367CAB_EQU_I_EQU_LO,  0xef},
 699         {R367CAB_EQU_I_EQU_HI,  0x00},
 700         {R367CAB_EQU_Q_EQU_LO,  0xee},
 701         {R367CAB_EQU_Q_EQU_HI,  0x00},
 702         {R367CAB_EQU_MAPPER,    0xc5},
 703         {R367CAB_EQU_SWEEP_RATE,        0x80},
 704         {R367CAB_EQU_SNR_LO,    0x64},
 705         {R367CAB_EQU_SNR_HI,    0x03},
 706         {R367CAB_EQU_GAMMA_LO,  0x00},
 707         {R367CAB_EQU_GAMMA_HI,  0x00},
 708         {R367CAB_EQU_ERR_GAIN,  0x36},
 709         {R367CAB_EQU_RADIUS,    0xaa},
 710         {R367CAB_EQU_FFE_MAINTAP,       0x00},
 711         {R367CAB_EQU_FFE_LEAKAGE,       0x63},
 712         {R367CAB_EQU_FFE_MAINTAP_POS,   0xdf},
 713         {R367CAB_EQU_GAIN_WIDE, 0x88},
 714         {R367CAB_EQU_GAIN_NARROW,       0x41},
 715         {R367CAB_EQU_CTR_LPF_GAIN,      0xd1},
 716         {R367CAB_EQU_CRL_LPF_GAIN,      0xa7},
 717         {R367CAB_EQU_GLOBAL_GAIN,       0x06},
 718         {R367CAB_EQU_CRL_LD_SEN,        0x85},
 719         {R367CAB_EQU_CRL_LD_VAL,        0xe2},
 720         {R367CAB_EQU_CRL_TFR,   0x20},
 721         {R367CAB_EQU_CRL_BISTH_LO,      0x00},
 722         {R367CAB_EQU_CRL_BISTH_HI,      0x00},
 723         {R367CAB_EQU_SWEEP_RANGE_LO,    0x00},
 724         {R367CAB_EQU_SWEEP_RANGE_HI,    0x00},
 725         {R367CAB_EQU_CRL_LIMITER,       0x40},
 726         {R367CAB_EQU_MODULUS_MAP,       0x90},
 727         {R367CAB_EQU_PNT_GAIN,  0xa7},
 728         {R367CAB_FEC_AC_CTR_0,  0x16},
 729         {R367CAB_FEC_AC_CTR_1,  0x0b},
 730         {R367CAB_FEC_AC_CTR_2,  0x88},
 731         {R367CAB_FEC_AC_CTR_3,  0x02},
 732         {R367CAB_FEC_STATUS,    0x12},
 733         {R367CAB_RS_COUNTER_0,  0x7d},
 734         {R367CAB_RS_COUNTER_1,  0xd0},
 735         {R367CAB_RS_COUNTER_2,  0x19},
 736         {R367CAB_RS_COUNTER_3,  0x0b},
 737         {R367CAB_RS_COUNTER_4,  0xa3},
 738         {R367CAB_RS_COUNTER_5,  0x00},
 739         {R367CAB_BERT_0,        0x01},
 740         {R367CAB_BERT_1,        0x25},
 741         {R367CAB_BERT_2,        0x41},
 742         {R367CAB_BERT_3,        0x39},
 743         {R367CAB_OUTFORMAT_0,   0xc2},
 744         {R367CAB_OUTFORMAT_1,   0x22},
 745         {R367CAB_SMOOTHER_2,    0x28},
 746         {R367CAB_TSMF_CTRL_0,   0x01},
 747         {R367CAB_TSMF_CTRL_1,   0xc6},
 748         {R367CAB_TSMF_CTRL_3,   0x43},
 749         {R367CAB_TS_ON_ID_0,    0x00},
 750         {R367CAB_TS_ON_ID_1,    0x00},
 751         {R367CAB_TS_ON_ID_2,    0x00},
 752         {R367CAB_TS_ON_ID_3,    0x00},
 753         {R367CAB_RE_STATUS_0,   0x00},
 754         {R367CAB_RE_STATUS_1,   0x00},
 755         {R367CAB_RE_STATUS_2,   0x00},
 756         {R367CAB_RE_STATUS_3,   0x00},
 757         {R367CAB_TS_STATUS_0,   0x00},
 758         {R367CAB_TS_STATUS_1,   0x00},
 759         {R367CAB_TS_STATUS_2,   0xa0},
 760         {R367CAB_TS_STATUS_3,   0x00},
 761         {R367CAB_T_O_ID_0,      0x00},
 762         {R367CAB_T_O_ID_1,      0x00},
 763         {R367CAB_T_O_ID_2,      0x00},
 764         {R367CAB_T_O_ID_3,      0x00},
 765 };
 766
 767 static
 768 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
 769 {
 770         u8 buf[len + 2];
 771         struct i2c_msg msg = {
 772                 .addr = state->config->demod_address,
 773                 .flags = 0,
 774                 .buf = buf,
 775                 .len = len + 2
 776         };
 777         int ret;
 778
 779         buf[0] = MSB(reg);
 780         buf[1] = LSB(reg);
 781         memcpy(buf + 2, data, len);
 782
 783         if (i2cdebug)
 784                 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]);
 785
 786         ret = i2c_transfer(state->i2c, &msg, 1);
 787         if (ret != 1)
 788                 printk(KERN_ERR "%s: i2c write error!\n", __func__);
 789
 790         return (ret != 1) ? -EREMOTEIO : 0;
 791 }
 792
 793 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
 794 {
 795         return stv0367_writeregs(state, reg, &data, 1);
 796 }
 797
 798 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
 799 {
 800         u8 b0[] = { 0, 0 };
 801         u8 b1[] = { 0 };
 802         struct i2c_msg msg[] = {
 803                 {
 804                         .addr = state->config->demod_address,
 805                         .flags = 0,
 806                         .buf = b0,
 807                         .len = 2
 808                 }, {
 809                         .addr = state->config->demod_address,
 810                         .flags = I2C_M_RD,
 811                         .buf = b1,
 812                         .len = 1
 813                 }
 814         };
 815         int ret;
 816
 817         b0[0] = MSB(reg);
 818         b0[1] = LSB(reg);
 819
 820         ret = i2c_transfer(state->i2c, msg, 2);
 821         if (ret != 2)
 822                 printk(KERN_ERR "%s: i2c read error\n", __func__);
 823
 824         if (i2cdebug)
 825                 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]);
 826
 827         return b1[0];
 828 }
 829
 830 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 831 {
 832         u8 position = 0, i = 0;
 833
 834         (*mask) = label & 0xff;
 835
 836         while ((position == 0) && (i < 8)) {
 837                 position = ((*mask) >> i) & 0x01;
 838                 i++;
 839         }
 840
 841         (*pos) = (i - 1);
 842 }
 843
 844 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
 845 {
 846         u8 reg, mask, pos;
 847
 848         reg = stv0367_readreg(state, (label >> 16) & 0xffff);
 849         extract_mask_pos(label, &mask, &pos);
 850
 851         val = mask & (val << pos);
 852
 853         reg = (reg & (~mask)) | val;
 854         stv0367_writereg(state, (label >> 16) & 0xffff, reg);
 855
 856 }
 857
 858 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
 859 {
 860         u8 mask, pos;
 861
 862         extract_mask_pos(label, &mask, &pos);
 863
 864         val = mask & (val << pos);
 865
 866         (*reg) = ((*reg) & (~mask)) | val;
 867 }
 868
 869 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
 870 {
 871         u8 val = 0xff;
 872         u8 mask, pos;
 873
 874         extract_mask_pos(label, &mask, &pos);
 875
 876         val = stv0367_readreg(state, label >> 16);
 877         val = (val & mask) >> pos;
 878
 879         return val;
 880 }
 881
 882 u8 stv0367_getbits(u8 reg, u32 label)
 883 {
 884         u8 mask, pos;
 885
 886         extract_mask_pos(label, &mask, &pos);
 887
 888         return (reg & mask) >> pos;
 889 }
 890
 891 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
 892 {
 893         struct stv0367_state *state = fe->demodulator_priv;
 894         u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
 895
 896         dprintk("%s:\n", __func__);
 897
 898         if (enable) {
 899                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
 900                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
 901         } else {
 902                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
 903                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
 904         }
 905
 906         stv0367_writereg(state, R367TER_I2CRPT, tmp);
 907
 908         return 0;
 909 }
 910
 911 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
 912 {
 913         struct dvb_frontend_ops *frontend_ops = NULL;
 914         struct dvb_tuner_ops    *tuner_ops = NULL;
 915         u32 freq = 0;
 916         int err = 0;
 917
 918         dprintk("%s:\n", __func__);
 919
 920
 921         if (&fe->ops)
 922                 frontend_ops = &fe->ops;
 923         if (&frontend_ops->tuner_ops)
 924                 tuner_ops = &frontend_ops->tuner_ops;
 925         if (tuner_ops->get_frequency) {
 926                 err = tuner_ops->get_frequency(fe, &freq);
 927                 if (err < 0) {
 928                         printk(KERN_ERR "%s: Invalid parameter\n", __func__);
 929                         return err;
 930                 }
 931
 932                 dprintk("%s: frequency=%d\n", __func__, freq);
 933
 934         } else
 935                 return -1;
 936
 937         return freq;
 938 }
 939
 940 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
 941         {
 942                 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
 943                 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
 944                 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
 945                 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
 946                 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
 947                 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
 948         }, {
 949                 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
 950                 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
 951                 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
 952                 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
 953                 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
 954                 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
 955         }, {
 956                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 957                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 958                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 959                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 960                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 961                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 962         }
 963 };
 964
 965 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
 966         {
 967                 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
 968                 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
 969                 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
 970                 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
 971                 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
 972                 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
 973         }, {
 974                 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
 975                 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
 976                 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
 977                 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
 978                 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
 979                 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
 980         }, {
 981                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 982                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 983                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 984                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 985                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 986                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 987         }
 988 };
 989
 990 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
 991         {
 992                 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
 993                 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
 994                 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
 995                 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
 996                 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
 997                 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
 998         }, {
 999                 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1000                 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1001                 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1002                 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1003                 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1004                 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1005
1006         }, {
1007                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1008                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1009                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1010                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1011                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1012                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1013         }
1014 };
1015
1016 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1017 {
1018         u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1019         u32 m, n, p;
1020
1021         dprintk("%s:\n", __func__);
1022
1023         if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1024                 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1025                 if (n == 0)
1026                         n = n + 1;
1027
1028                 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1029                 if (m == 0)
1030                         m = m + 1;
1031
1032                 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1033                 if (p > 5)
1034                         p = 5;
1035
1036                 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1037
1038                 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1039                                 n, m, p, mclk_Hz, ExtClk_Hz);
1040         } else
1041                 mclk_Hz = ExtClk_Hz;
1042
1043         dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1044
1045         return mclk_Hz;
1046 }
1047
1048 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1049                                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1050 {
1051         int i, j, k, freq;
1052
1053         dprintk("%s:\n", __func__);
1054
1055         freq = stv0367ter_get_mclk(state, DemodXtal);
1056
1057         if (freq == 53125000)
1058                 k = 1; /* equivalent to Xtal 25M on 362*/
1059         else if (freq == 54000000)
1060                 k = 0; /* equivalent to Xtal 27M on 362*/
1061         else if (freq == 52500000)
1062                 k = 2; /* equivalent to Xtal 30M on 362*/
1063         else
1064                 return 0;
1065
1066         for (i = 1; i <= 6; i++) {
1067                 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1068
1069                 for (j = 1; j <= 5; j++) {
1070                         stv0367_writereg(state,
1071                                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1072                                 MSB(CellsCoeffs[k][i-1][j-1]));
1073                         stv0367_writereg(state,
1074                                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1075                                 LSB(CellsCoeffs[k][i-1][j-1]));
1076                 }
1077         }
1078
1079         return 1;
1080
1081 }
1082
1083 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1084 {
1085         dprintk("%s:\n", __func__);
1086
1087         stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1088
1089         /* Lock detect 1 */
1090         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1091         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1092         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1093
1094         /* Lock detect 2 */
1095         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1096         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1097         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1098
1099         /* Lock detect 3 */
1100         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1101         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1102         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1103
1104         /* Lock detect 4 */
1105         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1106         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1107         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1108
1109 }
1110
1111 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1112                                                         u32 DemodXtalValue)
1113 {
1114         dprintk("%s:\n", __func__);
1115
1116         stv0367_writebits(state, F367TER_NRST_IIR, 0);
1117
1118         switch (Bandwidth) {
1119         case 6:
1120                 if (!stv0367ter_filt_coeff_init(state,
1121                                 CellsCoeffs_6MHz_367cofdm,
1122                                 DemodXtalValue))
1123                         return 0;
1124                 break;
1125         case 7:
1126                 if (!stv0367ter_filt_coeff_init(state,
1127                                 CellsCoeffs_7MHz_367cofdm,
1128                                 DemodXtalValue))
1129                         return 0;
1130                 break;
1131         case 8:
1132                 if (!stv0367ter_filt_coeff_init(state,
1133                                 CellsCoeffs_8MHz_367cofdm,
1134                                 DemodXtalValue))
1135                         return 0;
1136                 break;
1137         default:
1138                 return 0;
1139         }
1140
1141         stv0367_writebits(state, F367TER_NRST_IIR, 1);
1142
1143         return 1;
1144 }
1145
1146 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1147 {
1148
1149         u8 com_n;
1150
1151         dprintk("%s:\n", __func__);
1152
1153         com_n = stv0367_readbits(state, F367TER_COM_N);
1154
1155         stv0367_writebits(state, F367TER_COM_N, 0x07);
1156
1157         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1158         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1159
1160         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1161         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1162
1163         stv0367_writebits(state, F367TER_COM_N, com_n);
1164
1165 }
1166
1167 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1168 {
1169         int local_tempo = 0;
1170         switch (mode) {
1171         case 0:
1172                 local_tempo = tempo1;
1173                 break;
1174         case 1:
1175                 local_tempo = tempo2;
1176                 break ;
1177
1178         case 2:
1179                 local_tempo = tempo3;
1180                 break;
1181
1182         default:
1183                 break;
1184         }
1185         /*      msleep(local_tempo);  */
1186         return local_tempo;
1187 }
1188
1189 static enum
1190 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1191 {
1192         int wd = 100;
1193         unsigned short int SYR_var;
1194         s32 SYRStatus;
1195
1196         dprintk("%s:\n", __func__);
1197
1198         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1199
1200         while ((!SYR_var) && (wd > 0)) {
1201                 usleep_range(2000, 3000);
1202                 wd -= 2;
1203                 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1204         }
1205
1206         if (!SYR_var)
1207                 SYRStatus = FE_TER_NOSYMBOL;
1208         else
1209                 SYRStatus =  FE_TER_SYMBOLOK;
1210
1211         dprintk("stv0367ter_check_syr SYRStatus %s\n",
1212                                 SYR_var == 0 ? "No Symbol" : "OK");
1213
1214         return SYRStatus;
1215 }
1216
1217 static enum
1218 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1219                                                                 s32 FFTmode)
1220 {
1221
1222         s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1223         int wd = 0;
1224
1225         dprintk("%s:\n", __func__);
1226
1227         switch (FFTmode) {
1228         case 0: /*2k mode*/
1229                 CPAMPMin = 20;
1230                 wd = 10;
1231                 break;
1232         case 1: /*8k mode*/
1233                 CPAMPMin = 80;
1234                 wd = 55;
1235                 break;
1236         case 2: /*4k mode*/
1237                 CPAMPMin = 40;
1238                 wd = 30;
1239                 break;
1240         default:
1241                 CPAMPMin = 0xffff;  /*drives to NOCPAMP */
1242                 break;
1243         }
1244
1245         dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1246
1247         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1248         while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1249                 usleep_range(1000, 2000);
1250                 wd -= 1;
1251                 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1252                 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1253         }
1254         dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1255         if (CPAMPvalue < CPAMPMin) {
1256                 CPAMPStatus = FE_TER_NOCPAMP;
1257                 printk(KERN_ERR "CPAMP failed\n");
1258         } else {
1259                 printk(KERN_ERR "CPAMP OK !\n");
1260                 CPAMPStatus = FE_TER_CPAMPOK;
1261         }
1262
1263         return CPAMPStatus;
1264 }
1265
1266 enum
1267 stv0367_ter_signal_type stv0367ter_lock_algo(struct stv0367_state *state)
1268 {
1269         enum stv0367_ter_signal_type ret_flag;
1270         short int wd, tempo;
1271         u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1272         u8 tmp, tmp2;
1273
1274         dprintk("%s:\n", __func__);
1275
1276         if (state == NULL)
1277                 return FE_TER_SWNOK;
1278
1279         try = 0;
1280         do {
1281                 ret_flag = FE_TER_LOCKOK;
1282
1283                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1284
1285                 if (state->config->if_iq_mode != 0)
1286                         stv0367_writebits(state, F367TER_COM_N, 0x07);
1287
1288                 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1289                 stv0367_writebits(state, F367TER_MODE, 0);
1290                 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1291                 usleep_range(5000, 10000);
1292
1293                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1294
1295
1296                 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1297                         return FE_TER_NOSYMBOL;
1298                 else { /*
1299                         if chip locked on wrong mode first try,
1300                         it must lock correctly second try */
1301                         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1302                         if (stv0367ter_check_cpamp(state, mode) ==
1303                                                         FE_TER_NOCPAMP) {
1304                                 if (try == 0)
1305                                         ret_flag = FE_TER_NOCPAMP;
1306
1307                         }
1308                 }
1309
1310                 try++;
1311         } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1312
1313         tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
1314         tmp2 = stv0367_readreg(state, R367TER_STATUS);
1315         dprintk("state=%p\n", state);
1316         dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1317                                                         mode, tmp, tmp2);
1318
1319         tmp  = stv0367_readreg(state, R367TER_PRVIT);
1320         tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1321         dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1322
1323         tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
1324         dprintk("GAIN_SRC1=0x%x\n", tmp);
1325
1326         if ((mode != 0) && (mode != 1) && (mode != 2))
1327                 return FE_TER_SWNOK;
1328
1329         /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1330
1331         /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1332         and set channel predictor in automatic */
1333 #if 0
1334         switch (guard) {
1335
1336         case 0:
1337         case 1:
1338                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1339                 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1340                 break;
1341         case 2:
1342         case 3:
1343                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1344                 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1345                 break;
1346
1347         default:
1348                 return FE_TER_SWNOK;
1349         }
1350 #endif
1351
1352         /*reset fec an reedsolo FOR 367 only*/
1353         stv0367_writebits(state, F367TER_RST_SFEC, 1);
1354         stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1355         usleep_range(1000, 2000);
1356         stv0367_writebits(state, F367TER_RST_SFEC, 0);
1357         stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1358
1359         u_var1 = stv0367_readbits(state, F367TER_LK);
1360         u_var2 = stv0367_readbits(state, F367TER_PRF);
1361         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1362         /*      u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1363
1364         wd = stv0367ter_duration(mode, 125, 500, 250);
1365         tempo = stv0367ter_duration(mode, 4, 16, 8);
1366
1367         /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
1368         while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1369                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1370                 wd -= tempo;
1371                 u_var1 = stv0367_readbits(state, F367TER_LK);
1372                 u_var2 = stv0367_readbits(state, F367TER_PRF);
1373                 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1374                 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1375         }
1376
1377         if (!u_var1)
1378                 return FE_TER_NOLOCK;
1379
1380
1381         if (!u_var2)
1382                 return FE_TER_NOPRFOUND;
1383
1384         if (!u_var3)
1385                 return FE_TER_NOTPS;
1386
1387         guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1388         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1389         switch (guard) {
1390         case 0:
1391         case 1:
1392                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1393                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1394                 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1395                 break;
1396         case 2:
1397         case 3:
1398                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1399                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1400                 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1401                 break;
1402
1403         default:
1404                 return FE_TER_SWNOK;
1405         }
1406
1407         /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1408         if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1409                         (mode == 1) &&
1410                         (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1411                 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1412                 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1413                 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1414         } else
1415                 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1416
1417         wd = stv0367ter_duration(mode, 125, 500, 250);
1418         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1419
1420         while ((!u_var4) && (wd >= 0)) {
1421                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1422                 wd -= tempo;
1423                 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1424         }
1425
1426         if (!u_var4)
1427                 return FE_TER_NOLOCK;
1428
1429         /* for 367 leave COM_N at 0x7 for IQ_mode*/
1430         /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1431                 tempo=0;
1432                 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1433                 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1434                         ChipWaitOrAbort(state,1);
1435                         tempo+=1;
1436                 }
1437
1438                 stv0367_writebits(state,F367TER_COM_N,0x17);
1439         } */
1440
1441         stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1442
1443         dprintk("FE_TER_LOCKOK !!!\n");
1444
1445         return  FE_TER_LOCKOK;
1446
1447 }
1448
1449 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1450                                         enum stv0367_ts_mode PathTS)
1451 {
1452
1453         dprintk("%s:\n", __func__);
1454
1455         if (state == NULL)
1456                 return;
1457
1458         stv0367_writebits(state, F367TER_TS_DIS, 0);
1459         switch (PathTS) {
1460         default:
1461                 /*for removing warning :default we can assume in parallel mode*/
1462         case STV0367_PARALLEL_PUNCT_CLOCK:
1463                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1464                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1465                 break;
1466         case STV0367_SERIAL_PUNCT_CLOCK:
1467                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1468                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1469                 break;
1470         }
1471 }
1472
1473 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1474                                         enum stv0367_clk_pol clock)
1475 {
1476
1477         dprintk("%s:\n", __func__);
1478
1479         if (state == NULL)
1480                 return;
1481
1482         switch (clock) {
1483         case STV0367_RISINGEDGE_CLOCK:
1484                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1485                 break;
1486         case STV0367_FALLINGEDGE_CLOCK:
1487                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1488                 break;
1489                 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1490         default:
1491                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1492                 break;
1493         }
1494 }
1495
1496 #if 0
1497 static void stv0367ter_core_sw(struct stv0367_state *state)
1498 {
1499
1500         dprintk("%s:\n", __func__);
1501
1502         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1503         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1504         msleep(350);
1505 }
1506 #endif
1507 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1508 {
1509         struct stv0367_state *state = fe->demodulator_priv;
1510
1511         dprintk("%s:\n", __func__);
1512
1513         if (standby_on) {
1514                 stv0367_writebits(state, F367TER_STDBY, 1);
1515                 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1516                 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1517         } else {
1518                 stv0367_writebits(state, F367TER_STDBY, 0);
1519                 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1520                 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1521         }
1522
1523         return 0;
1524 }
1525
1526 static int stv0367ter_sleep(struct dvb_frontend *fe)
1527 {
1528         return stv0367ter_standby(fe, 1);
1529 }
1530
1531 int stv0367ter_init(struct dvb_frontend *fe)
1532 {
1533         struct stv0367_state *state = fe->demodulator_priv;
1534         struct stv0367ter_state *ter_state = state->ter_state;
1535         int i;
1536
1537         dprintk("%s:\n", __func__);
1538
1539         ter_state->pBER = 0;
1540
1541         for (i = 0; i < STV0367TER_NBREGS; i++)
1542                 stv0367_writereg(state, def0367ter[i].addr,
1543                                         def0367ter[i].value);
1544
1545         switch (state->config->xtal) {
1546                 /*set internal freq to 53.125MHz */
1547         case 25000000:
1548                 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1549                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1550                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1551                 break;
1552         default:
1553         case 27000000:
1554                 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1555                 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1556                 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1557                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1558                 break;
1559         case 30000000:
1560                 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1561                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1562                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1563                 break;
1564         }
1565
1566         stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1567         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1568
1569         /*Set TS1 and TS2 to serial or parallel mode */
1570         stv0367ter_set_ts_mode(state, state->config->ts_mode);
1571         stv0367ter_set_clk_pol(state, state->config->clk_pol);
1572
1573         state->chip_id = stv0367_readreg(state, R367TER_ID);
1574         ter_state->first_lock = 0;
1575         ter_state->unlock_counter = 2;
1576
1577         return 0;
1578 }
1579
1580 static int stv0367ter_algo(struct dvb_frontend *fe)
1581 {
1582         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1583         struct stv0367_state *state = fe->demodulator_priv;
1584         struct stv0367ter_state *ter_state = state->ter_state;
1585         int offset = 0, tempo = 0;
1586         u8 u_var;
1587         u8 /*constell,*/ counter;
1588         s8 step;
1589         s32 timing_offset = 0;
1590         u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1591
1592         dprintk("%s:\n", __func__);
1593
1594         ter_state->frequency = p->frequency;
1595         ter_state->force = FE_TER_FORCENONE
1596                         + stv0367_readbits(state, F367TER_FORCE) * 2;
1597         ter_state->if_iq_mode = state->config->if_iq_mode;
1598         switch (state->config->if_iq_mode) {
1599         case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1600                 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1601                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1602                 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1603                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1604                 break;
1605         case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1606                 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1607                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1608                 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1609                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1610                 break;
1611         case FE_TER_IQ_TUNER:  /* IQ mode */
1612                 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1613                 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1614                 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1615                 break;
1616         default:
1617                 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1618                 return -EINVAL;
1619         }
1620
1621         usleep_range(5000, 7000);
1622
1623         switch (p->inversion) {
1624         case INVERSION_AUTO:
1625         default:
1626                 dprintk("%s: inversion AUTO\n", __func__);
1627                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1628                         stv0367_writebits(state, F367TER_IQ_INVERT,
1629                                                 ter_state->sense);
1630                 else
1631                         stv0367_writebits(state, F367TER_INV_SPECTR,
1632                                                 ter_state->sense);
1633
1634                 break;
1635         case INVERSION_ON:
1636         case INVERSION_OFF:
1637                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1638                         stv0367_writebits(state, F367TER_IQ_INVERT,
1639                                                 p->inversion);
1640                 else
1641                         stv0367_writebits(state, F367TER_INV_SPECTR,
1642                                                 p->inversion);
1643
1644                 break;
1645         }
1646
1647         if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1648                                 (ter_state->pBW != ter_state->bw)) {
1649                 stv0367ter_agc_iir_lock_detect_set(state);
1650
1651                 /*set fine agc target to 180 for LPIF or IQ mode*/
1652                 /* set Q_AGCTarget */
1653                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1654                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1655                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1656
1657                 /* set Q_AGCTarget */
1658                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1659                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1660                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1661
1662                 if (!stv0367_iir_filt_init(state, ter_state->bw,
1663                                                 state->config->xtal))
1664                         return -EINVAL;
1665                 /*set IIR filter once for 6,7 or 8MHz BW*/
1666                 ter_state->pBW = ter_state->bw;
1667
1668                 stv0367ter_agc_iir_rst(state);
1669         }
1670
1671         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1672                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1673         else
1674                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1675
1676         InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1677         temp = (int)
1678                 ((((ter_state->bw * 64 * (1 << 15) * 100)
1679                                                 / (InternalFreq)) * 10) / 7);
1680
1681         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1682         temp = temp / 2;
1683         stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1684         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1685
1686         temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1687                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1688                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1689         temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1690         stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1691         stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1692         temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1693                         stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1694
1695         temp = (int)
1696                 ((InternalFreq - state->config->if_khz) * (1 << 16)
1697                                                         / (InternalFreq));
1698
1699         dprintk("DEROT temp=0x%x\n", temp);
1700         stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1701         stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1702
1703         ter_state->echo_pos = 0;
1704         ter_state->ucblocks = 0; /* liplianin */
1705         ter_state->pBER = 0; /* liplianin */
1706         stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1707
1708         if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1709                 return 0;
1710
1711         ter_state->state = FE_TER_LOCKOK;
1712
1713         ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1714         ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1715
1716         ter_state->first_lock = 1; /* we know sense now :) */
1717
1718         ter_state->agc_val =
1719                         (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1720                         (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1721                         stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1722                         (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1723
1724         /* Carrier offset calculation */
1725         stv0367_writebits(state, F367TER_FREEZE, 1);
1726         offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1727         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1728         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1729         stv0367_writebits(state, F367TER_FREEZE, 0);
1730         if (offset > 8388607)
1731                 offset -= 16777216;
1732
1733         offset = offset * 2 / 16384;
1734
1735         if (ter_state->mode == FE_TER_MODE_2K)
1736                 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1737         else if (ter_state->mode == FE_TER_MODE_4K)
1738                 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1739         else  if (ter_state->mode == FE_TER_MODE_8K)
1740                 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1741
1742         if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1743                 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1744                                 (stv0367_readbits(state,
1745                                         F367TER_STATUS_INV_SPECRUM) == 1)))
1746                         offset = offset * -1;
1747         }
1748
1749         if (ter_state->bw == 6)
1750                 offset = (offset * 6) / 8;
1751         else if (ter_state->bw == 7)
1752                 offset = (offset * 7) / 8;
1753
1754         ter_state->frequency += offset;
1755
1756         tempo = 10;  /* exit even if timing_offset stays null */
1757         while ((timing_offset == 0) && (tempo > 0)) {
1758                 usleep_range(10000, 20000);     /*was 20ms  */
1759                 /* fine tuning of timing offset if required */
1760                 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1761                                 + 256 * stv0367_readbits(state,
1762                                                         F367TER_TRL_TOFFSET_HI);
1763                 if (timing_offset >= 32768)
1764                         timing_offset -= 65536;
1765                 trl_nomrate = (512 * stv0367_readbits(state,
1766                                                         F367TER_TRL_NOMRATE_HI)
1767                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1768                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1769
1770                 timing_offset = ((signed)(1000000 / trl_nomrate) *
1771                                                         timing_offset) / 2048;
1772                 tempo--;
1773         }
1774
1775         if (timing_offset <= 0) {
1776                 timing_offset = (timing_offset - 11) / 22;
1777                 step = -1;
1778         } else {
1779                 timing_offset = (timing_offset + 11) / 22;
1780                 step = 1;
1781         }
1782
1783         for (counter = 0; counter < abs(timing_offset); counter++) {
1784                 trl_nomrate += step;
1785                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1786                                                 trl_nomrate % 2);
1787                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1788                                                 trl_nomrate / 2);
1789                 usleep_range(1000, 2000);
1790         }
1791
1792         usleep_range(5000, 6000);
1793         /* unlocks could happen in case of trl centring big step,
1794         then a core off/on restarts demod */
1795         u_var = stv0367_readbits(state, F367TER_LK);
1796
1797         if (!u_var) {
1798                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1799                 msleep(20);
1800                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1801         }
1802
1803         return 0;
1804 }
1805
1806 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1807 {
1808         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1809         struct stv0367_state *state = fe->demodulator_priv;
1810         struct stv0367ter_state *ter_state = state->ter_state;
1811
1812         /*u8 trials[2]; */
1813         s8 num_trials, index;
1814         u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1815
1816         stv0367ter_init(fe);
1817
1818         if (fe->ops.tuner_ops.set_params) {
1819                 if (fe->ops.i2c_gate_ctrl)
1820                         fe->ops.i2c_gate_ctrl(fe, 1);
1821                 fe->ops.tuner_ops.set_params(fe);
1822                 if (fe->ops.i2c_gate_ctrl)
1823                         fe->ops.i2c_gate_ctrl(fe, 0);
1824         }
1825
1826         switch (p->transmission_mode) {
1827         default:
1828         case TRANSMISSION_MODE_AUTO:
1829         case TRANSMISSION_MODE_2K:
1830                 ter_state->mode = FE_TER_MODE_2K;
1831                 break;
1832 /*      case TRANSMISSION_MODE_4K:
1833                 pLook.mode = FE_TER_MODE_4K;
1834                 break;*/
1835         case TRANSMISSION_MODE_8K:
1836                 ter_state->mode = FE_TER_MODE_8K;
1837                 break;
1838         }
1839
1840         switch (p->guard_interval) {
1841         default:
1842         case GUARD_INTERVAL_1_32:
1843         case GUARD_INTERVAL_1_16:
1844         case GUARD_INTERVAL_1_8:
1845         case GUARD_INTERVAL_1_4:
1846                 ter_state->guard = p->guard_interval;
1847                 break;
1848         case GUARD_INTERVAL_AUTO:
1849                 ter_state->guard = GUARD_INTERVAL_1_32;
1850                 break;
1851         }
1852
1853         switch (p->bandwidth_hz) {
1854         case 6000000:
1855                 ter_state->bw = FE_TER_CHAN_BW_6M;
1856                 break;
1857         case 7000000:
1858                 ter_state->bw = FE_TER_CHAN_BW_7M;
1859                 break;
1860         case 8000000:
1861         default:
1862                 ter_state->bw = FE_TER_CHAN_BW_8M;
1863         }
1864
1865         ter_state->hierarchy = FE_TER_HIER_NONE;
1866
1867         switch (p->inversion) {
1868         case INVERSION_OFF:
1869         case INVERSION_ON:
1870                 num_trials = 1;
1871                 break;
1872         default:
1873                 num_trials = 2;
1874                 if (ter_state->first_lock)
1875                         num_trials = 1;
1876                 break;
1877         }
1878
1879         ter_state->state = FE_TER_NOLOCK;
1880         index = 0;
1881
1882         while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1883                 if (!ter_state->first_lock) {
1884                         if (p->inversion == INVERSION_AUTO)
1885                                 ter_state->sense = SenseTrials[index];
1886
1887                 }
1888                 stv0367ter_algo(fe);
1889
1890                 if ((ter_state->state == FE_TER_LOCKOK) &&
1891                                 (p->inversion == INVERSION_AUTO) &&
1892                                                                 (index == 1)) {
1893                         /* invert spectrum sense */
1894                         SenseTrials[index] = SenseTrials[0];
1895                         SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1896                 }
1897
1898                 index++;
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1905 {
1906         struct stv0367_state *state = fe->demodulator_priv;
1907         struct stv0367ter_state *ter_state = state->ter_state;
1908         u32 errs = 0;
1909
1910         /*wait for counting completion*/
1911         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1912                 errs =
1913                         ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1914                         * (1 << 16))
1915                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1916                         * (1 << 8))
1917                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1918                 ter_state->ucblocks = errs;
1919         }
1920
1921         (*ucblocks) = ter_state->ucblocks;
1922
1923         return 0;
1924 }
1925
1926 static int stv0367ter_get_frontend(struct dvb_frontend *fe)
1927 {
1928         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1929         struct stv0367_state *state = fe->demodulator_priv;
1930         struct stv0367ter_state *ter_state = state->ter_state;
1931
1932         int error = 0;
1933         enum stv0367_ter_mode mode;
1934         int constell = 0,/* snr = 0,*/ Data = 0;
1935
1936         p->frequency = stv0367_get_tuner_freq(fe);
1937         if ((int)p->frequency < 0)
1938                 p->frequency = -p->frequency;
1939
1940         constell = stv0367_readbits(state, F367TER_TPS_CONST);
1941         if (constell == 0)
1942                 p->modulation = QPSK;
1943         else if (constell == 1)
1944                 p->modulation = QAM_16;
1945         else
1946                 p->modulation = QAM_64;
1947
1948         p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1949
1950         /* Get the Hierarchical mode */
1951         Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1952
1953         switch (Data) {
1954         case 0:
1955                 p->hierarchy = HIERARCHY_NONE;
1956                 break;
1957         case 1:
1958                 p->hierarchy = HIERARCHY_1;
1959                 break;
1960         case 2:
1961                 p->hierarchy = HIERARCHY_2;
1962                 break;
1963         case 3:
1964                 p->hierarchy = HIERARCHY_4;
1965                 break;
1966         default:
1967                 p->hierarchy = HIERARCHY_AUTO;
1968                 break; /* error */
1969         }
1970
1971         /* Get the FEC Rate */
1972         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1973                 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1974         else
1975                 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1976
1977         switch (Data) {
1978         case 0:
1979                 p->code_rate_HP = FEC_1_2;
1980                 break;
1981         case 1:
1982                 p->code_rate_HP = FEC_2_3;
1983                 break;
1984         case 2:
1985                 p->code_rate_HP = FEC_3_4;
1986                 break;
1987         case 3:
1988                 p->code_rate_HP = FEC_5_6;
1989                 break;
1990         case 4:
1991                 p->code_rate_HP = FEC_7_8;
1992                 break;
1993         default:
1994                 p->code_rate_HP = FEC_AUTO;
1995                 break; /* error */
1996         }
1997
1998         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1999
2000         switch (mode) {
2001         case FE_TER_MODE_2K:
2002                 p->transmission_mode = TRANSMISSION_MODE_2K;
2003                 break;
2004 /*      case FE_TER_MODE_4K:
2005                 p->transmission_mode = TRANSMISSION_MODE_4K;
2006                 break;*/
2007         case FE_TER_MODE_8K:
2008                 p->transmission_mode = TRANSMISSION_MODE_8K;
2009                 break;
2010         default:
2011                 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2012         }
2013
2014         p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2015
2016         return error;
2017 }
2018
2019 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2020 {
2021         struct stv0367_state *state = fe->demodulator_priv;
2022         u32 snru32 = 0;
2023         int cpt = 0;
2024         u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2025
2026         while (cpt < 10) {
2027                 usleep_range(2000, 3000);
2028                 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2029                         snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2030                 else /*cu2.0*/
2031                         snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2032
2033                 cpt++;
2034         }
2035
2036         snru32 /= 10;/*average on 10 values*/
2037
2038         *snr = snru32 / 1000;
2039
2040         return 0;
2041 }
2042
2043 #if 0
2044 static int stv0367ter_status(struct dvb_frontend *fe)
2045 {
2046
2047         struct stv0367_state *state = fe->demodulator_priv;
2048         struct stv0367ter_state *ter_state = state->ter_state;
2049         int locked = FALSE;
2050
2051         locked = (stv0367_readbits(state, F367TER_LK));
2052         if (!locked)
2053                 ter_state->unlock_counter += 1;
2054         else
2055                 ter_state->unlock_counter = 0;
2056
2057         if (ter_state->unlock_counter > 2) {
2058                 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2059                                 (!stv0367_readbits(state, F367TER_LK))) {
2060                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2061                         usleep_range(2000, 3000);
2062                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2063                         msleep(350);
2064                         locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2065                                         (stv0367_readbits(state, F367TER_LK));
2066                 }
2067
2068         }
2069
2070         return locked;
2071 }
2072 #endif
2073 static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status)
2074 {
2075         struct stv0367_state *state = fe->demodulator_priv;
2076
2077         dprintk("%s:\n", __func__);
2078
2079         *status = 0;
2080
2081         if (stv0367_readbits(state, F367TER_LK)) {
2082                 *status |= FE_HAS_LOCK;
2083                 dprintk("%s: stv0367 has locked\n", __func__);
2084         }
2085
2086         return 0;
2087 }
2088
2089 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2090 {
2091         struct stv0367_state *state = fe->demodulator_priv;
2092         struct stv0367ter_state *ter_state = state->ter_state;
2093         u32 Errors = 0, tber = 0, temporary = 0;
2094         int abc = 0, def = 0;
2095
2096
2097         /*wait for counting completion*/
2098         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2099                 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2100                         * (1 << 16))
2101                         + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2102                         * (1 << 8))
2103                         + ((u32)stv0367_readbits(state,
2104                                                 F367TER_SFEC_ERR_CNT_LO));
2105         /*measurement not completed, load previous value*/
2106         else {
2107                 tber = ter_state->pBER;
2108                 return 0;
2109         }
2110
2111         abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2112         def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2113
2114         if (Errors == 0) {
2115                 tber = 0;
2116         } else if (abc == 0x7) {
2117                 if (Errors <= 4) {
2118                         temporary = (Errors * 1000000000) / (8 * (1 << 14));
2119                         temporary =  temporary;
2120                 } else if (Errors <= 42) {
2121                         temporary = (Errors * 100000000) / (8 * (1 << 14));
2122                         temporary = temporary * 10;
2123                 } else if (Errors <= 429) {
2124                         temporary = (Errors * 10000000) / (8 * (1 << 14));
2125                         temporary = temporary * 100;
2126                 } else if (Errors <= 4294) {
2127                         temporary = (Errors * 1000000) / (8 * (1 << 14));
2128                         temporary = temporary * 1000;
2129                 } else if (Errors <= 42949) {
2130                         temporary = (Errors * 100000) / (8 * (1 << 14));
2131                         temporary = temporary * 10000;
2132                 } else if (Errors <= 429496) {
2133                         temporary = (Errors * 10000) / (8 * (1 << 14));
2134                         temporary = temporary * 100000;
2135                 } else { /*if (Errors<4294967) 2^22 max error*/
2136                         temporary = (Errors * 1000) / (8 * (1 << 14));
2137                         temporary = temporary * 100000; /* still to *10 */
2138                 }
2139
2140                 /* Byte error*/
2141                 if (def == 2)
2142                         /*tber=Errors/(8*(1 <<14));*/
2143                         tber = temporary;
2144                 else if (def == 3)
2145                         /*tber=Errors/(8*(1 <<16));*/
2146                         tber = temporary / 4;
2147                 else if (def == 4)
2148                         /*tber=Errors/(8*(1 <<18));*/
2149                         tber = temporary / 16;
2150                 else if (def == 5)
2151                         /*tber=Errors/(8*(1 <<20));*/
2152                         tber = temporary / 64;
2153                 else if (def == 6)
2154                         /*tber=Errors/(8*(1 <<22));*/
2155                         tber = temporary / 256;
2156                 else
2157                         /* should not pass here*/
2158                         tber = 0;
2159
2160                 if ((Errors < 4294967) && (Errors > 429496))
2161                         tber *= 10;
2162
2163         }
2164
2165         /* save actual value */
2166         ter_state->pBER = tber;
2167
2168         (*ber) = tber;
2169
2170         return 0;
2171 }
2172 #if 0
2173 static u32 stv0367ter_get_per(struct stv0367_state *state)
2174 {
2175         struct stv0367ter_state *ter_state = state->ter_state;
2176         u32 Errors = 0, Per = 0, temporary = 0;
2177         int abc = 0, def = 0, cpt = 0;
2178
2179         while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2180                         (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2181                 usleep_range(1000, 2000);
2182                 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2183                         * (1 << 16))
2184                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2185                         * (1 << 8))
2186                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2187                 cpt++;
2188         }
2189         abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2190         def = stv0367_readbits(state, F367TER_NUM_EVT1);
2191
2192         if (Errors == 0)
2193                 Per = 0;
2194         else if (abc == 0x9) {
2195                 if (Errors <= 4) {
2196                         temporary = (Errors * 1000000000) / (8 * (1 << 8));
2197                         temporary =  temporary;
2198                 } else if (Errors <= 42) {
2199                         temporary = (Errors * 100000000) / (8 * (1 << 8));
2200                         temporary = temporary * 10;
2201                 } else if (Errors <= 429) {
2202                         temporary = (Errors * 10000000) / (8 * (1 << 8));
2203                         temporary = temporary * 100;
2204                 } else if (Errors <= 4294) {
2205                         temporary = (Errors * 1000000) / (8 * (1 << 8));
2206                         temporary = temporary * 1000;
2207                 } else if (Errors <= 42949) {
2208                         temporary = (Errors * 100000) / (8 * (1 << 8));
2209                         temporary = temporary * 10000;
2210                 } else { /*if(Errors<=429496)  2^16 errors max*/
2211                         temporary = (Errors * 10000) / (8 * (1 << 8));
2212                         temporary = temporary * 100000;
2213                 }
2214
2215                 /* pkt error*/
2216                 if (def == 2)
2217                         /*Per=Errors/(1 << 8);*/
2218                         Per = temporary;
2219                 else if (def == 3)
2220                         /*Per=Errors/(1 << 10);*/
2221                         Per = temporary / 4;
2222                 else if (def == 4)
2223                         /*Per=Errors/(1 << 12);*/
2224                         Per = temporary / 16;
2225                 else if (def == 5)
2226                         /*Per=Errors/(1 << 14);*/
2227                         Per = temporary / 64;
2228                 else if (def == 6)
2229                         /*Per=Errors/(1 << 16);*/
2230                         Per = temporary / 256;
2231                 else
2232                         Per = 0;
2233
2234         }
2235         /* save actual value */
2236         ter_state->pPER = Per;
2237
2238         return Per;
2239 }
2240 #endif
2241 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2242                                         struct dvb_frontend_tune_settings
2243                                         *fe_tune_settings)
2244 {
2245         fe_tune_settings->min_delay_ms = 1000;
2246         fe_tune_settings->step_size = 0;
2247         fe_tune_settings->max_drift = 0;
2248
2249         return 0;
2250 }
2251
2252 static void stv0367_release(struct dvb_frontend *fe)
2253 {
2254         struct stv0367_state *state = fe->demodulator_priv;
2255
2256         kfree(state->ter_state);
2257         kfree(state->cab_state);
2258         kfree(state);
2259 }
2260
2261 static struct dvb_frontend_ops stv0367ter_ops = {
2262         .delsys = { SYS_DVBT },
2263         .info = {
2264                 .name                   = "ST STV0367 DVB-T",
2265                 .frequency_min          = 47000000,
2266                 .frequency_max          = 862000000,
2267                 .frequency_stepsize     = 15625,
2268                 .frequency_tolerance    = 0,
2269                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2270                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2271                         FE_CAN_FEC_AUTO |
2272                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2273                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2274                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2275                         FE_CAN_INVERSION_AUTO |
2276                         FE_CAN_MUTE_TS
2277         },
2278         .release = stv0367_release,
2279         .init = stv0367ter_init,
2280         .sleep = stv0367ter_sleep,
2281         .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2282         .set_frontend = stv0367ter_set_frontend,
2283         .get_frontend = stv0367ter_get_frontend,
2284         .get_tune_settings = stv0367_get_tune_settings,
2285         .read_status = stv0367ter_read_status,
2286         .read_ber = stv0367ter_read_ber,/* too slow */
2287 /*      .read_signal_strength = stv0367_read_signal_strength,*/
2288         .read_snr = stv0367ter_read_snr,
2289         .read_ucblocks = stv0367ter_read_ucblocks,
2290 };
2291
2292 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2293                                    struct i2c_adapter *i2c)
2294 {
2295         struct stv0367_state *state = NULL;
2296         struct stv0367ter_state *ter_state = NULL;
2297
2298         /* allocate memory for the internal state */
2299         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2300         if (state == NULL)
2301                 goto error;
2302         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2303         if (ter_state == NULL)
2304                 goto error;
2305
2306         /* setup the state */
2307         state->i2c = i2c;
2308         state->config = config;
2309         state->ter_state = ter_state;
2310         state->fe.ops = stv0367ter_ops;
2311         state->fe.demodulator_priv = state;
2312         state->chip_id = stv0367_readreg(state, 0xf000);
2313
2314         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2315
2316         /* check if the demod is there */
2317         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2318                 goto error;
2319
2320         return &state->fe;
2321
2322 error:
2323         kfree(ter_state);
2324         kfree(state);
2325         return NULL;
2326 }
2327 EXPORT_SYMBOL(stv0367ter_attach);
2328
2329 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2330 {
2331         struct stv0367_state *state = fe->demodulator_priv;
2332
2333         dprintk("%s:\n", __func__);
2334
2335         stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2336
2337         return 0;
2338 }
2339
2340 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2341 {
2342         struct stv0367_state *state = fe->demodulator_priv;
2343         u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2344         u32 M, N, P;
2345
2346
2347         if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2348                 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2349                 if (N == 0)
2350                         N = N + 1;
2351
2352                 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2353                 if (M == 0)
2354                         M = M + 1;
2355
2356                 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2357
2358                 if (P > 5)
2359                         P = 5;
2360
2361                 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2362                 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2363                                                                 mclk_Hz);
2364         } else
2365                 mclk_Hz = ExtClk_Hz;
2366
2367         dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2368
2369         return mclk_Hz;
2370 }
2371
2372 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2373 {
2374         u32 ADCClk_Hz = ExtClk_Hz;
2375
2376         ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2377
2378         return ADCClk_Hz;
2379 }
2380
2381 enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2382                                         u32 SymbolRate,
2383                                         enum stv0367cab_mod QAMSize)
2384 {
2385         /* Set QAM size */
2386         stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2387
2388         /* Set Registers settings specific to the QAM size */
2389         switch (QAMSize) {
2390         case FE_CAB_MOD_QAM4:
2391                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2392                 break;
2393         case FE_CAB_MOD_QAM16:
2394                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2395                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2396                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2397                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2398                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2399                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2400                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2401                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2402                 break;
2403         case FE_CAB_MOD_QAM32:
2404                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2405                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2406                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2407                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2408                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2409                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2410                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2411                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2412                 break;
2413         case FE_CAB_MOD_QAM64:
2414                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2415                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2416                 if (SymbolRate > 45000000) {
2417                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2418                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2419                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2420                 } else if (SymbolRate > 25000000) {
2421                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2422                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2423                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2424                 } else {
2425                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2426                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2427                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2428                 }
2429                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2430                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2431                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2432                 break;
2433         case FE_CAB_MOD_QAM128:
2434                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2435                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2436                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2437                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2438                 if (SymbolRate > 45000000)
2439                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2440                 else if (SymbolRate > 25000000)
2441                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2442                 else
2443                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2444
2445                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2446                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2447                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2448                 break;
2449         case FE_CAB_MOD_QAM256:
2450                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2451                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2452                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2453                 if (SymbolRate > 45000000)
2454                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2455                 else if (SymbolRate > 25000000)
2456                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2457                 else
2458                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2459
2460                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2461                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2462                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2463                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2464                 break;
2465         case FE_CAB_MOD_QAM512:
2466                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2467                 break;
2468         case FE_CAB_MOD_QAM1024:
2469                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2470                 break;
2471         default:
2472                 break;
2473         }
2474
2475         return QAMSize;
2476 }
2477
2478 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2479                                         u32 adc_hz, s32 derot_hz)
2480 {
2481         u32 sampled_if = 0;
2482         u32 adc_khz;
2483
2484         adc_khz = adc_hz / 1000;
2485
2486         dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2487
2488         if (adc_khz != 0) {
2489                 if (derot_hz < 1000000)
2490                         derot_hz = adc_hz / 4; /* ZIF operation */
2491                 if (derot_hz > adc_hz)
2492                         derot_hz = derot_hz - adc_hz;
2493                 sampled_if = (u32)derot_hz / 1000;
2494                 sampled_if *= 32768;
2495                 sampled_if /= adc_khz;
2496                 sampled_if *= 256;
2497         }
2498
2499         if (sampled_if > 8388607)
2500                 sampled_if = 8388607;
2501
2502         dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2503
2504         stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2505         stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2506         stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2507
2508         return derot_hz;
2509 }
2510
2511 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2512 {
2513         u32 sampled_if;
2514
2515         sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2516                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2517                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2518
2519         sampled_if /= 256;
2520         sampled_if *= (adc_hz / 1000);
2521         sampled_if += 1;
2522         sampled_if /= 32768;
2523
2524         return sampled_if;
2525 }
2526
2527 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2528                         u32 mclk_hz, u32 SymbolRate,
2529                         enum stv0367cab_mod QAMSize)
2530 {
2531         u32 QamSizeCorr = 0;
2532         u32 u32_tmp = 0, u32_tmp1 = 0;
2533         u32 adp_khz;
2534
2535         dprintk("%s:\n", __func__);
2536
2537         /* Set Correction factor of SRC gain */
2538         switch (QAMSize) {
2539         case FE_CAB_MOD_QAM4:
2540                 QamSizeCorr = 1110;
2541                 break;
2542         case FE_CAB_MOD_QAM16:
2543                 QamSizeCorr = 1032;
2544                 break;
2545         case FE_CAB_MOD_QAM32:
2546                 QamSizeCorr =  954;
2547                 break;
2548         case FE_CAB_MOD_QAM64:
2549                 QamSizeCorr =  983;
2550                 break;
2551         case FE_CAB_MOD_QAM128:
2552                 QamSizeCorr =  957;
2553                 break;
2554         case FE_CAB_MOD_QAM256:
2555                 QamSizeCorr =  948;
2556                 break;
2557         case FE_CAB_MOD_QAM512:
2558                 QamSizeCorr =    0;
2559                 break;
2560         case FE_CAB_MOD_QAM1024:
2561                 QamSizeCorr =  944;
2562                 break;
2563         default:
2564                 break;
2565         }
2566
2567         /* Transfer ratio calculation */
2568         if (adc_hz != 0) {
2569                 u32_tmp = 256 * SymbolRate;
2570                 u32_tmp = u32_tmp / adc_hz;
2571         }
2572         stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2573
2574         /* Symbol rate and SRC gain calculation */
2575         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2576         if (adp_khz != 0) {
2577                 u32_tmp = SymbolRate;
2578                 u32_tmp1 = SymbolRate;
2579
2580                 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2581                         /* Symbol rate calculation */
2582                         u32_tmp *= 2048; /* 2048 = 2^11 */
2583                         u32_tmp = u32_tmp / adp_khz;
2584                         u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2585                         u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2586                         u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2587
2588                         /* SRC Gain Calculation */
2589                         u32_tmp1 *= 2048; /* *2*2^10 */
2590                         u32_tmp1 /= 439; /* *2/878 */
2591                         u32_tmp1 *= 256; /* *2^8 */
2592                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2593                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2594                         u32_tmp1 = u32_tmp1 / 10000000;
2595
2596                 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2597                         /* Symbol rate calculation */
2598                         u32_tmp *= 1024 ; /* 1024 = 2**10 */
2599                         u32_tmp = u32_tmp / adp_khz;
2600                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2601                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2602                         u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2603
2604                         /* SRC Gain Calculation */
2605                         u32_tmp1 *= 1024; /* *2*2^9 */
2606                         u32_tmp1 /= 439; /* *2/878 */
2607                         u32_tmp1 *= 256; /* *2^8 */
2608                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2609                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2610                         u32_tmp1 = u32_tmp1 / 5000000;
2611                 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2612                         /* Symbol rate calculation */
2613                         u32_tmp *= 512 ; /* 512 = 2**9 */
2614                         u32_tmp = u32_tmp / adp_khz;
2615                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2616                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2617                         u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2618
2619                         /* SRC Gain Calculation */
2620                         u32_tmp1 *= 512; /* *2*2^8 */
2621                         u32_tmp1 /= 439; /* *2/878 */
2622                         u32_tmp1 *= 256; /* *2^8 */
2623                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2624                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2625                         u32_tmp1 = u32_tmp1 / 2500000;
2626                 } else {
2627                         /* Symbol rate calculation */
2628                         u32_tmp *= 256 ; /* 256 = 2**8 */
2629                         u32_tmp = u32_tmp / adp_khz;
2630                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2631                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2632                         u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2633
2634                         /* SRC Gain Calculation */
2635                         u32_tmp1 *= 256; /* 2*2^7 */
2636                         u32_tmp1 /= 439; /* *2/878 */
2637                         u32_tmp1 *= 256; /* *2^8 */
2638                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2639                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2640                         u32_tmp1 = u32_tmp1 / 1250000;
2641                 }
2642         }
2643 #if 0
2644         /* Filters' coefficients are calculated and written
2645         into registers only if the filters are enabled */
2646         if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2647                 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2648                                                                 SymbolRate);
2649                 /* AllPass filter must be enabled
2650                 when the adjacents filter is used */
2651                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2652                 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2653         } else
2654                 /* AllPass filter must be disabled
2655                 when the adjacents filter is not used */
2656 #endif
2657         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2658
2659         stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2660         stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2661         stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2662         stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2663
2664         stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2665         stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2666
2667         return SymbolRate ;
2668 }
2669
2670 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2671 {
2672         u32 regsym;
2673         u32 adp_khz;
2674
2675         regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2676                 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2677                 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2678                 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2679
2680         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2681
2682         if (regsym < 134217728) {               /* 134217728L = 2**27*/
2683                 regsym = regsym * 32;           /* 32 = 2**5 */
2684                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2685                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2686                 regsym = regsym / 128;          /* 128 = 2**7 */
2687                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2688                 regsym /= 2048 ;                /* 2048 = 2**11 */
2689         } else if (regsym < 268435456) {        /* 268435456L = 2**28 */
2690                 regsym = regsym * 16;           /* 16 = 2**4 */
2691                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2692                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2693                 regsym = regsym / 128;          /* 128 = 2**7 */
2694                 regsym *= 125 ;                 /* 125 = 1000/2**3*/
2695                 regsym /= 1024 ;                /* 256 = 2**10*/
2696         } else if (regsym < 536870912) {        /* 536870912L = 2**29*/
2697                 regsym = regsym * 8;            /* 8 = 2**3 */
2698                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2699                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2700                 regsym = regsym / 128;          /* 128 = 2**7 */
2701                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2702                 regsym /= 512 ;                 /* 128 = 2**9 */
2703         } else {
2704                 regsym = regsym * 4;            /* 4 = 2**2 */
2705                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2706                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2707                 regsym = regsym / 128;          /* 128 = 2**7 */
2708                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2709                 regsym /= 256 ;                 /* 64 = 2**8 */
2710         }
2711
2712         return regsym;
2713 }
2714
2715 static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status)
2716 {
2717         struct stv0367_state *state = fe->demodulator_priv;
2718
2719         dprintk("%s:\n", __func__);
2720
2721         *status = 0;
2722
2723         if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2724                 *status |= FE_HAS_LOCK;
2725                 dprintk("%s: stv0367 has locked\n", __func__);
2726         }
2727
2728         return 0;
2729 }
2730
2731 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2732 {
2733         struct stv0367_state *state = fe->demodulator_priv;
2734
2735         dprintk("%s:\n", __func__);
2736
2737         if (standby_on) {
2738                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2739                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2740                 stv0367_writebits(state, F367CAB_STDBY, 1);
2741                 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2742                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2743                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2744                 stv0367_writebits(state, F367CAB_POFFQ, 1);
2745                 stv0367_writebits(state, F367CAB_POFFI, 1);
2746         } else {
2747                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2748                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2749                 stv0367_writebits(state, F367CAB_STDBY, 0);
2750                 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2751                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2752                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2753                 stv0367_writebits(state, F367CAB_POFFQ, 0);
2754                 stv0367_writebits(state, F367CAB_POFFI, 0);
2755         }
2756
2757         return 0;
2758 }
2759
2760 static int stv0367cab_sleep(struct dvb_frontend *fe)
2761 {
2762         return stv0367cab_standby(fe, 1);
2763 }
2764
2765 int stv0367cab_init(struct dvb_frontend *fe)
2766 {
2767         struct stv0367_state *state = fe->demodulator_priv;
2768         struct stv0367cab_state *cab_state = state->cab_state;
2769         int i;
2770
2771         dprintk("%s:\n", __func__);
2772
2773         for (i = 0; i < STV0367CAB_NBREGS; i++)
2774                 stv0367_writereg(state, def0367cab[i].addr,
2775                                                 def0367cab[i].value);
2776
2777         switch (state->config->ts_mode) {
2778         case STV0367_DVBCI_CLOCK:
2779                 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2780                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2781                 break;
2782         case STV0367_SERIAL_PUNCT_CLOCK:
2783         case STV0367_SERIAL_CONT_CLOCK:
2784                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2785                 break;
2786         case STV0367_PARALLEL_PUNCT_CLOCK:
2787         case STV0367_OUTPUTMODE_DEFAULT:
2788                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2789                 break;
2790         }
2791
2792         switch (state->config->clk_pol) {
2793         case STV0367_RISINGEDGE_CLOCK:
2794                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2795                 break;
2796         case STV0367_FALLINGEDGE_CLOCK:
2797         case STV0367_CLOCKPOLARITY_DEFAULT:
2798                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2799                 break;
2800         }
2801
2802         stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2803
2804         stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2805
2806         stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2807
2808         stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2809
2810         stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2811
2812         cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2813         cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2814
2815         return 0;
2816 }
2817 static
2818 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2819                                              struct dtv_frontend_properties *p)
2820 {
2821         struct stv0367cab_state *cab_state = state->cab_state;
2822         enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2823         u32     QAMFEC_Lock, QAM_Lock, u32_tmp,
2824                 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2825                 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2826         u8      TrackAGCAccum;
2827         s32     tmp;
2828
2829         dprintk("%s:\n", __func__);
2830
2831         /* Timeouts calculation */
2832         /* A max lock time of 25 ms is allowed for delayed AGC */
2833         AGCTimeOut = 25;
2834         /* 100000 symbols needed by the TRL as a maximum value */
2835         TRLTimeOut = 100000000 / p->symbol_rate;
2836         /* CRLSymbols is the needed number of symbols to achieve a lock
2837            within [-4%, +4%] of the symbol rate.
2838            CRL timeout is calculated
2839            for a lock within [-search_range, +search_range].
2840            EQL timeout can be changed depending on
2841            the micro-reflections we want to handle.
2842            A characterization must be performed
2843            with these echoes to get new timeout values.
2844         */
2845         switch (p->modulation) {
2846         case QAM_16:
2847                 CRLSymbols = 150000;
2848                 EQLTimeOut = 100;
2849                 break;
2850         case QAM_32:
2851                 CRLSymbols = 250000;
2852                 EQLTimeOut = 100;
2853                 break;
2854         case QAM_64:
2855                 CRLSymbols = 200000;
2856                 EQLTimeOut = 100;
2857                 break;
2858         case QAM_128:
2859                 CRLSymbols = 250000;
2860                 EQLTimeOut = 100;
2861                 break;
2862         case QAM_256:
2863                 CRLSymbols = 250000;
2864                 EQLTimeOut = 100;
2865                 break;
2866         default:
2867                 CRLSymbols = 200000;
2868                 EQLTimeOut = 100;
2869                 break;
2870         }
2871 #if 0
2872         if (pIntParams->search_range < 0) {
2873                 CRLTimeOut = (25 * CRLSymbols *
2874                                 (-pIntParams->search_range / 1000)) /
2875                                         (pIntParams->symbol_rate / 1000);
2876         } else
2877 #endif
2878         CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2879                                         (p->symbol_rate / 1000);
2880
2881         CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2882         /* Timeouts below 50ms are coerced */
2883         if (CRLTimeOut < 50)
2884                 CRLTimeOut = 50;
2885         /* A maximum of 100 TS packets is needed to get FEC lock even in case
2886         the spectrum inversion needs to be changed.
2887            This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2888         */
2889         FECTimeOut = 20;
2890         DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2891
2892         dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2893
2894         /* Reset the TRL to ensure nothing starts until the
2895            AGC is stable which ensures a better lock time
2896         */
2897         stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2898         /* Set AGC accumulation time to minimum and lock threshold to maximum
2899         in order to speed up the AGC lock */
2900         TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2901         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2902         /* Modulus Mapper is disabled */
2903         stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2904         /* Disable the sweep function */
2905         stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2906         /* The sweep function is never used, Sweep rate must be set to 0 */
2907         /* Set the derotator frequency in Hz */
2908         stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2909                 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2910         /* Disable the Allpass Filter when the symbol rate is out of range */
2911         if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2912                 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2913                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2914         }
2915 #if 0
2916         /* Check if the tuner is locked */
2917         tuner_lock = stv0367cab_tuner_get_status(fe);
2918         if (tuner_lock == 0)
2919                 return FE_367CAB_NOTUNER;
2920 #endif
2921         /* Relase the TRL to start demodulator acquisition */
2922         /* Wait for QAM lock */
2923         LockTime = 0;
2924         stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2925         do {
2926                 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2927                 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2928                                                         (QAM_Lock == 0x04))
2929                         /*
2930                          * We don't wait longer, the frequency/phase offset
2931                          * must be too big
2932                          */
2933                         LockTime = DemodTimeOut;
2934                 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2935                                                         (QAM_Lock == 0x02))
2936                         /*
2937                          * We don't wait longer, either there is no signal or
2938                          * it is not the right symbol rate or it is an analog
2939                          * carrier
2940                          */
2941                 {
2942                         LockTime = DemodTimeOut;
2943                         u32_tmp = stv0367_readbits(state,
2944                                                 F367CAB_AGC_PWR_WORD_LO) +
2945                                         (stv0367_readbits(state,
2946                                                 F367CAB_AGC_PWR_WORD_ME) << 8) +
2947                                         (stv0367_readbits(state,
2948                                                 F367CAB_AGC_PWR_WORD_HI) << 16);
2949                         if (u32_tmp >= 131072)
2950                                 u32_tmp = 262144 - u32_tmp;
2951                         u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2952                                                         F367CAB_AGC_IF_BWSEL)));
2953
2954                         if (u32_tmp < stv0367_readbits(state,
2955                                                 F367CAB_AGC_PWRREF_LO) +
2956                                         256 * stv0367_readbits(state,
2957                                                 F367CAB_AGC_PWRREF_HI) - 10)
2958                                 QAM_Lock = 0x0f;
2959                 } else {
2960                         usleep_range(10000, 20000);
2961                         LockTime += 10;
2962                 }
2963                 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2964                 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2965
2966                 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2967
2968         } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2969                                                 (LockTime < DemodTimeOut));
2970
2971         dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2972
2973         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2974         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2975         tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2976         dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2977
2978         tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2979         dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2980
2981         if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2982                 /* Wait for FEC lock */
2983                 LockTime = 0;
2984                 do {
2985                         usleep_range(5000, 7000);
2986                         LockTime += 5;
2987                         QAMFEC_Lock = stv0367_readbits(state,
2988                                                         F367CAB_QAMFEC_LOCK);
2989                 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2990         } else
2991                 QAMFEC_Lock = 0;
2992
2993         if (QAMFEC_Lock) {
2994                 signalType = FE_CAB_DATAOK;
2995                 cab_state->modulation = p->modulation;
2996                 cab_state->spect_inv = stv0367_readbits(state,
2997                                                         F367CAB_QUAD_INV);
2998 #if 0
2999 /* not clear for me */
3000                 if (state->config->if_khz != 0) {
3001                         if (state->config->if_khz > cab_state->adc_clk / 1000) {
3002                                 cab_state->freq_khz =
3003                                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3004                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3005                                 - cab_state->adc_clk / 1000 + state->config->if_khz;
3006                         } else {
3007                                 cab_state->freq_khz =
3008                                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3009                                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3010                                                                                 + state->config->if_khz;
3011                         }
3012                 } else {
3013                         cab_state->freq_khz =
3014                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3015                                 stv0367cab_get_derot_freq(state,
3016                                                         cab_state->adc_clk) -
3017                                 cab_state->adc_clk / 4000;
3018                 }
3019 #endif
3020                 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3021                                                         cab_state->mclk);
3022                 cab_state->locked = 1;
3023
3024                 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3025         } else {
3026                 switch (QAM_Lock) {
3027                 case 1:
3028                         signalType = FE_CAB_NOAGC;
3029                         break;
3030                 case 2:
3031                         signalType = FE_CAB_NOTIMING;
3032                         break;
3033                 case 3:
3034                         signalType = FE_CAB_TIMINGOK;
3035                         break;
3036                 case 4:
3037                         signalType = FE_CAB_NOCARRIER;
3038                         break;
3039                 case 5:
3040                         signalType = FE_CAB_CARRIEROK;
3041                         break;
3042                 case 7:
3043                         signalType = FE_CAB_NOBLIND;
3044                         break;
3045                 case 8:
3046                         signalType = FE_CAB_BLINDOK;
3047                         break;
3048                 case 10:
3049                         signalType = FE_CAB_NODEMOD;
3050                         break;
3051                 case 11:
3052                         signalType = FE_CAB_DEMODOK;
3053                         break;
3054                 case 12:
3055                         signalType = FE_CAB_DEMODOK;
3056                         break;
3057                 case 13:
3058                         signalType = FE_CAB_NODEMOD;
3059                         break;
3060                 case 14:
3061                         signalType = FE_CAB_NOBLIND;
3062                         break;
3063                 case 15:
3064                         signalType = FE_CAB_NOSIGNAL;
3065                         break;
3066                 default:
3067                         break;
3068                 }
3069
3070         }
3071
3072         /* Set the AGC control values to tracking values */
3073         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3074         return signalType;
3075 }
3076
3077 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3078 {
3079         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3080         struct stv0367_state *state = fe->demodulator_priv;
3081         struct stv0367cab_state *cab_state = state->cab_state;
3082         enum stv0367cab_mod QAMSize = 0;
3083
3084         dprintk("%s: freq = %d, srate = %d\n", __func__,
3085                                         p->frequency, p->symbol_rate);
3086
3087         cab_state->derot_offset = 0;
3088
3089         switch (p->modulation) {
3090         case QAM_16:
3091                 QAMSize = FE_CAB_MOD_QAM16;
3092                 break;
3093         case QAM_32:
3094                 QAMSize = FE_CAB_MOD_QAM32;
3095                 break;
3096         case QAM_64:
3097                 QAMSize = FE_CAB_MOD_QAM64;
3098                 break;
3099         case QAM_128:
3100                 QAMSize = FE_CAB_MOD_QAM128;
3101                 break;
3102         case QAM_256:
3103                 QAMSize = FE_CAB_MOD_QAM256;
3104                 break;
3105         default:
3106                 break;
3107         }
3108
3109         stv0367cab_init(fe);
3110
3111         /* Tuner Frequency Setting */
3112         if (fe->ops.tuner_ops.set_params) {
3113                 if (fe->ops.i2c_gate_ctrl)
3114                         fe->ops.i2c_gate_ctrl(fe, 1);
3115                 fe->ops.tuner_ops.set_params(fe);
3116                 if (fe->ops.i2c_gate_ctrl)
3117                         fe->ops.i2c_gate_ctrl(fe, 0);
3118         }
3119
3120         stv0367cab_SetQamSize(
3121                         state,
3122                         p->symbol_rate,
3123                         QAMSize);
3124
3125         stv0367cab_set_srate(state,
3126                         cab_state->adc_clk,
3127                         cab_state->mclk,
3128                         p->symbol_rate,
3129                         QAMSize);
3130         /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3131         cab_state->state = stv0367cab_algo(state, p);
3132         return 0;
3133 }
3134
3135 static int stv0367cab_get_frontend(struct dvb_frontend *fe)
3136 {
3137         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3138         struct stv0367_state *state = fe->demodulator_priv;
3139         struct stv0367cab_state *cab_state = state->cab_state;
3140
3141         enum stv0367cab_mod QAMSize;
3142
3143         dprintk("%s:\n", __func__);
3144
3145         p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3146
3147         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3148         switch (QAMSize) {
3149         case FE_CAB_MOD_QAM16:
3150                 p->modulation = QAM_16;
3151                 break;
3152         case FE_CAB_MOD_QAM32:
3153                 p->modulation = QAM_32;
3154                 break;
3155         case FE_CAB_MOD_QAM64:
3156                 p->modulation = QAM_64;
3157                 break;
3158         case FE_CAB_MOD_QAM128:
3159                 p->modulation = QAM_128;
3160                 break;
3161         case QAM_256:
3162                 p->modulation = QAM_256;
3163                 break;
3164         default:
3165                 break;
3166         }
3167
3168         p->frequency = stv0367_get_tuner_freq(fe);
3169
3170         dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3171
3172         if (state->config->if_khz == 0) {
3173                 p->frequency +=
3174                         (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3175                         cab_state->adc_clk / 4000);
3176                 return 0;
3177         }
3178
3179         if (state->config->if_khz > cab_state->adc_clk / 1000)
3180                 p->frequency += (state->config->if_khz
3181                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3182                         - cab_state->adc_clk / 1000);
3183         else
3184                 p->frequency += (state->config->if_khz
3185                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3186
3187         return 0;
3188 }
3189
3190 #if 0
3191 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3192                         u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3193 {
3194         stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3195         stv0367cab_GetPacketsCount(state, Monitor_results);
3196
3197         return;
3198 }
3199
3200 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3201 {
3202         struct stv0367_state *state = fe->demodulator_priv;
3203
3204         return 0;
3205 }
3206 #endif
3207 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3208 {
3209         s32 rfLevel = 0;
3210         s32 RfAgcPwm = 0, IfAgcPwm = 0;
3211         u8 i;
3212
3213         stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3214
3215         RfAgcPwm =
3216                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3217                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3218         RfAgcPwm = 100 * RfAgcPwm / 1023;
3219
3220         IfAgcPwm =
3221                 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3222                 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3223         if (IfAgcPwm >= 2048)
3224                 IfAgcPwm -= 2048;
3225         else
3226                 IfAgcPwm += 2048;
3227
3228         IfAgcPwm = 100 * IfAgcPwm / 4095;
3229
3230         /* For DTT75467 on NIM */
3231         if (RfAgcPwm < 90  && IfAgcPwm < 28) {
3232                 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3233                         if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3234                                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3235                                 break;
3236                         }
3237                 }
3238                 if (i == RF_LOOKUP_TABLE_SIZE)
3239                         rfLevel = -56;
3240         } else { /*if IF AGC>10*/
3241                 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3242                         if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3243                                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3244                                 break;
3245                         }
3246                 }
3247                 if (i == RF_LOOKUP_TABLE2_SIZE)
3248                         rfLevel = -72;
3249         }
3250         return rfLevel;
3251 }
3252
3253 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3254 {
3255         struct stv0367_state *state = fe->demodulator_priv;
3256
3257         s32 signal =  stv0367cab_get_rf_lvl(state);
3258
3259         dprintk("%s: signal=%d dBm\n", __func__, signal);
3260
3261         if (signal <= -72)
3262                 *strength = 65535;
3263         else
3264                 *strength = (22 + signal) * (-1311);
3265
3266         dprintk("%s: strength=%d\n", __func__, (*strength));
3267
3268         return 0;
3269 }
3270
3271 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3272 {
3273         struct stv0367_state *state = fe->demodulator_priv;
3274         u32 noisepercentage;
3275         enum stv0367cab_mod QAMSize;
3276         u32 regval = 0, temp = 0;
3277         int power, i;
3278
3279         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3280         switch (QAMSize) {
3281         case FE_CAB_MOD_QAM4:
3282                 power = 21904;
3283                 break;
3284         case FE_CAB_MOD_QAM16:
3285                 power = 20480;
3286                 break;
3287         case FE_CAB_MOD_QAM32:
3288                 power = 23040;
3289                 break;
3290         case FE_CAB_MOD_QAM64:
3291                 power = 21504;
3292                 break;
3293         case FE_CAB_MOD_QAM128:
3294                 power = 23616;
3295                 break;
3296         case FE_CAB_MOD_QAM256:
3297                 power = 21760;
3298                 break;
3299         case FE_CAB_MOD_QAM512:
3300                 power = 1;
3301                 break;
3302         case FE_CAB_MOD_QAM1024:
3303                 power = 21280;
3304                 break;
3305         default:
3306                 power = 1;
3307                 break;
3308         }
3309
3310         for (i = 0; i < 10; i++) {
3311                 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3312                         + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3313         }
3314
3315         regval /= 10; /*for average over 10 times in for loop above*/
3316         if (regval != 0) {
3317                 temp = power
3318                         * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3319                 temp /= regval;
3320         }
3321
3322         /* table values, not needed to calculate logarithms */
3323         if (temp >= 5012)
3324                 noisepercentage = 100;
3325         else if (temp >= 3981)
3326                 noisepercentage = 93;
3327         else if (temp >= 3162)
3328                 noisepercentage = 86;
3329         else if (temp >= 2512)
3330                 noisepercentage = 79;
3331         else if (temp >= 1995)
3332                 noisepercentage = 72;
3333         else if (temp >= 1585)
3334                 noisepercentage = 65;
3335         else if (temp >= 1259)
3336                 noisepercentage = 58;
3337         else if (temp >= 1000)
3338                 noisepercentage = 50;
3339         else if (temp >= 794)
3340                 noisepercentage = 43;
3341         else if (temp >= 501)
3342                 noisepercentage = 36;
3343         else if (temp >= 316)
3344                 noisepercentage = 29;
3345         else if (temp >= 200)
3346                 noisepercentage = 22;
3347         else if (temp >= 158)
3348                 noisepercentage = 14;
3349         else if (temp >= 126)
3350                 noisepercentage = 7;
3351         else
3352                 noisepercentage = 0;
3353
3354         dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3355
3356         *snr = (noisepercentage * 65535) / 100;
3357
3358         return 0;
3359 }
3360
3361 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3362 {
3363         struct stv0367_state *state = fe->demodulator_priv;
3364         int corrected, tscount;
3365
3366         *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3367                         | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3368         corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3369                         | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3370         tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3371                         | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3372
3373         dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3374                                 __func__, *ucblocks, corrected, tscount);
3375
3376         return 0;
3377 };
3378
3379 static struct dvb_frontend_ops stv0367cab_ops = {
3380         .delsys = { SYS_DVBC_ANNEX_A },
3381         .info = {
3382                 .name = "ST STV0367 DVB-C",
3383                 .frequency_min = 47000000,
3384                 .frequency_max = 862000000,
3385                 .frequency_stepsize = 62500,
3386                 .symbol_rate_min = 870000,
3387                 .symbol_rate_max = 11700000,
3388                 .caps = 0x400 |/* FE_CAN_QAM_4 */
3389                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3390                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3391                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3392         },
3393         .release                                = stv0367_release,
3394         .init                                   = stv0367cab_init,
3395         .sleep                                  = stv0367cab_sleep,
3396         .i2c_gate_ctrl                          = stv0367cab_gate_ctrl,
3397         .set_frontend                           = stv0367cab_set_frontend,
3398         .get_frontend                           = stv0367cab_get_frontend,
3399         .read_status                            = stv0367cab_read_status,
3400 /*      .read_ber                               = stv0367cab_read_ber, */
3401         .read_signal_strength                   = stv0367cab_read_strength,
3402         .read_snr                               = stv0367cab_read_snr,
3403         .read_ucblocks                          = stv0367cab_read_ucblcks,
3404         .get_tune_settings                      = stv0367_get_tune_settings,
3405 };
3406
3407 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3408                                    struct i2c_adapter *i2c)
3409 {
3410         struct stv0367_state *state = NULL;
3411         struct stv0367cab_state *cab_state = NULL;
3412
3413         /* allocate memory for the internal state */
3414         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3415         if (state == NULL)
3416                 goto error;
3417         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3418         if (cab_state == NULL)
3419                 goto error;
3420
3421         /* setup the state */
3422         state->i2c = i2c;
3423         state->config = config;
3424         cab_state->search_range = 280000;
3425         state->cab_state = cab_state;
3426         state->fe.ops = stv0367cab_ops;
3427         state->fe.demodulator_priv = state;
3428         state->chip_id = stv0367_readreg(state, 0xf000);
3429
3430         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3431
3432         /* check if the demod is there */
3433         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3434                 goto error;
3435
3436         return &state->fe;
3437
3438 error:
3439         kfree(cab_state);
3440         kfree(state);
3441         return NULL;
3442 }
3443 EXPORT_SYMBOL(stv0367cab_attach);
3444
3445 MODULE_PARM_DESC(debug, "Set debug");
3446 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3447
3448 MODULE_AUTHOR("Igor M. Liplianin");
3449 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3450 MODULE_LICENSE("GPL");