drivers/media/dvb/frontends/rtl2832.c

   1 /*
   2  * Realtek RTL2832 DVB-T demodulator driver
   3  *
   4  * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
   5  *
   6  *      This program is free software; you can redistribute it and/or modify
   7  *      it under the terms of the GNU General Public License as published by
   8  *      the Free Software Foundation; either version 2 of the License, or
   9  *      (at your option) any later version.
  10  *
  11  *      This program is distributed in the hope that it will be useful,
  12  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *      GNU General Public License for more details.
  15  *
  16  *      You should have received a copy of the GNU General Public License along
  17  *      with this program; if not, write to the Free Software Foundation, Inc.,
  18  *      51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include "rtl2832_priv.h"
  22 #include <linux/bitops.h>
  23
  24 int rtl2832_debug;
  25 module_param_named(debug, rtl2832_debug, int, 0644);
  26 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  27
  28 #define REG_MASK(b) (BIT(b + 1) - 1)
  29
  30 static const struct rtl2832_reg_entry registers[] = {
  31         [DVBT_SOFT_RST]         = {0x1, 0x1,   2, 2},
  32         [DVBT_IIC_REPEAT]       = {0x1, 0x1,   3, 3},
  33         [DVBT_TR_WAIT_MIN_8K]   = {0x1, 0x88, 11, 2},
  34         [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
  35         [DVBT_EN_BK_TRK]        = {0x1, 0xa6,  7, 7},
  36         [DVBT_AD_EN_REG]        = {0x0, 0x8,   7, 7},
  37         [DVBT_AD_EN_REG1]       = {0x0, 0x8,   6, 6},
  38         [DVBT_EN_BBIN]          = {0x1, 0xb1,  0, 0},
  39         [DVBT_MGD_THD0]         = {0x1, 0x95,  7, 0},
  40         [DVBT_MGD_THD1]         = {0x1, 0x96,  7, 0},
  41         [DVBT_MGD_THD2]         = {0x1, 0x97,  7, 0},
  42         [DVBT_MGD_THD3]         = {0x1, 0x98,  7, 0},
  43         [DVBT_MGD_THD4]         = {0x1, 0x99,  7, 0},
  44         [DVBT_MGD_THD5]         = {0x1, 0x9a,  7, 0},
  45         [DVBT_MGD_THD6]         = {0x1, 0x9b,  7, 0},
  46         [DVBT_MGD_THD7]         = {0x1, 0x9c,  7, 0},
  47         [DVBT_EN_CACQ_NOTCH]    = {0x1, 0x61,  4, 4},
  48         [DVBT_AD_AV_REF]        = {0x0, 0x9,   6, 0},
  49         [DVBT_REG_PI]           = {0x0, 0xa,   2, 0},
  50         [DVBT_PIP_ON]           = {0x0, 0x21,  3, 3},
  51         [DVBT_SCALE1_B92]       = {0x2, 0x92,  7, 0},
  52         [DVBT_SCALE1_B93]       = {0x2, 0x93,  7, 0},
  53         [DVBT_SCALE1_BA7]       = {0x2, 0xa7,  7, 0},
  54         [DVBT_SCALE1_BA9]       = {0x2, 0xa9,  7, 0},
  55         [DVBT_SCALE1_BAA]       = {0x2, 0xaa,  7, 0},
  56         [DVBT_SCALE1_BAB]       = {0x2, 0xab,  7, 0},
  57         [DVBT_SCALE1_BAC]       = {0x2, 0xac,  7, 0},
  58         [DVBT_SCALE1_BB0]       = {0x2, 0xb0,  7, 0},
  59         [DVBT_SCALE1_BB1]       = {0x2, 0xb1,  7, 0},
  60         [DVBT_KB_P1]            = {0x1, 0x64,  3, 1},
  61         [DVBT_KB_P2]            = {0x1, 0x64,  6, 4},
  62         [DVBT_KB_P3]            = {0x1, 0x65,  2, 0},
  63         [DVBT_OPT_ADC_IQ]       = {0x0, 0x6,   5, 4},
  64         [DVBT_AD_AVI]           = {0x0, 0x9,   1, 0},
  65         [DVBT_AD_AVQ]           = {0x0, 0x9,   3, 2},
  66         [DVBT_K1_CR_STEP12]     = {0x2, 0xad,  9, 4},
  67         [DVBT_TRK_KS_P2]        = {0x1, 0x6f,  2, 0},
  68         [DVBT_TRK_KS_I2]        = {0x1, 0x70,  5, 3},
  69         [DVBT_TR_THD_SET2]      = {0x1, 0x72,  3, 0},
  70         [DVBT_TRK_KC_P2]        = {0x1, 0x73,  5, 3},
  71         [DVBT_TRK_KC_I2]        = {0x1, 0x75,  2, 0},
  72         [DVBT_CR_THD_SET2]      = {0x1, 0x76,  7, 6},
  73         [DVBT_PSET_IFFREQ]      = {0x1, 0x19, 21, 0},
  74         [DVBT_SPEC_INV]         = {0x1, 0x15,  0, 0},
  75         [DVBT_RSAMP_RATIO]      = {0x1, 0x9f, 27, 2},
  76         [DVBT_CFREQ_OFF_RATIO]  = {0x1, 0x9d, 23, 4},
  77         [DVBT_FSM_STAGE]        = {0x3, 0x51,  6, 3},
  78         [DVBT_RX_CONSTEL]       = {0x3, 0x3c,  3, 2},
  79         [DVBT_RX_HIER]          = {0x3, 0x3c,  6, 4},
  80         [DVBT_RX_C_RATE_LP]     = {0x3, 0x3d,  2, 0},
  81         [DVBT_RX_C_RATE_HP]     = {0x3, 0x3d,  5, 3},
  82         [DVBT_GI_IDX]           = {0x3, 0x51,  1, 0},
  83         [DVBT_FFT_MODE_IDX]     = {0x3, 0x51,  2, 2},
  84         [DVBT_RSD_BER_EST]      = {0x3, 0x4e, 15, 0},
  85         [DVBT_CE_EST_EVM]       = {0x4, 0xc,  15, 0},
  86         [DVBT_RF_AGC_VAL]       = {0x3, 0x5b, 13, 0},
  87         [DVBT_IF_AGC_VAL]       = {0x3, 0x59, 13, 0},
  88         [DVBT_DAGC_VAL]         = {0x3, 0x5,   7, 0},
  89         [DVBT_SFREQ_OFF]        = {0x3, 0x18, 13, 0},
  90         [DVBT_CFREQ_OFF]        = {0x3, 0x5f, 17, 0},
  91         [DVBT_POLAR_RF_AGC]     = {0x0, 0xe,   1, 1},
  92         [DVBT_POLAR_IF_AGC]     = {0x0, 0xe,   0, 0},
  93         [DVBT_AAGC_HOLD]        = {0x1, 0x4,   5, 5},
  94         [DVBT_EN_RF_AGC]        = {0x1, 0x4,   6, 6},
  95         [DVBT_EN_IF_AGC]        = {0x1, 0x4,   7, 7},
  96         [DVBT_IF_AGC_MIN]       = {0x1, 0x8,   7, 0},
  97         [DVBT_IF_AGC_MAX]       = {0x1, 0x9,   7, 0},
  98         [DVBT_RF_AGC_MIN]       = {0x1, 0xa,   7, 0},
  99         [DVBT_RF_AGC_MAX]       = {0x1, 0xb,   7, 0},
 100         [DVBT_IF_AGC_MAN]       = {0x1, 0xc,   6, 6},
 101         [DVBT_IF_AGC_MAN_VAL]   = {0x1, 0xc,  13, 0},
 102         [DVBT_RF_AGC_MAN]       = {0x1, 0xe,   6, 6},
 103         [DVBT_RF_AGC_MAN_VAL]   = {0x1, 0xe,  13, 0},
 104         [DVBT_DAGC_TRG_VAL]     = {0x1, 0x12,  7, 0},
 105         [DVBT_AGC_TARG_VAL_0]   = {0x1, 0x2,   0, 0},
 106         [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3,   7, 0},
 107         [DVBT_AAGC_LOOP_GAIN]   = {0x1, 0xc7,  5, 1},
 108         [DVBT_LOOP_GAIN2_3_0]   = {0x1, 0x4,   4, 1},
 109         [DVBT_LOOP_GAIN2_4]     = {0x1, 0x5,   7, 7},
 110         [DVBT_LOOP_GAIN3]       = {0x1, 0xc8,  4, 0},
 111         [DVBT_VTOP1]            = {0x1, 0x6,   5, 0},
 112         [DVBT_VTOP2]            = {0x1, 0xc9,  5, 0},
 113         [DVBT_VTOP3]            = {0x1, 0xca,  5, 0},
 114         [DVBT_KRF1]             = {0x1, 0xcb,  7, 0},
 115         [DVBT_KRF2]             = {0x1, 0x7,   7, 0},
 116         [DVBT_KRF3]             = {0x1, 0xcd,  7, 0},
 117         [DVBT_KRF4]             = {0x1, 0xce,  7, 0},
 118         [DVBT_EN_GI_PGA]        = {0x1, 0xe5,  0, 0},
 119         [DVBT_THD_LOCK_UP]      = {0x1, 0xd9,  8, 0},
 120         [DVBT_THD_LOCK_DW]      = {0x1, 0xdb,  8, 0},
 121         [DVBT_THD_UP1]          = {0x1, 0xdd,  7, 0},
 122         [DVBT_THD_DW1]          = {0x1, 0xde,  7, 0},
 123         [DVBT_INTER_CNT_LEN]    = {0x1, 0xd8,  3, 0},
 124         [DVBT_GI_PGA_STATE]     = {0x1, 0xe6,  3, 3},
 125         [DVBT_EN_AGC_PGA]       = {0x1, 0xd7,  0, 0},
 126         [DVBT_CKOUTPAR]         = {0x1, 0x7b,  5, 5},
 127         [DVBT_CKOUT_PWR]        = {0x1, 0x7b,  6, 6},
 128         [DVBT_SYNC_DUR]         = {0x1, 0x7b,  7, 7},
 129         [DVBT_ERR_DUR]          = {0x1, 0x7c,  0, 0},
 130         [DVBT_SYNC_LVL]         = {0x1, 0x7c,  1, 1},
 131         [DVBT_ERR_LVL]          = {0x1, 0x7c,  2, 2},
 132         [DVBT_VAL_LVL]          = {0x1, 0x7c,  3, 3},
 133         [DVBT_SERIAL]           = {0x1, 0x7c,  4, 4},
 134         [DVBT_SER_LSB]          = {0x1, 0x7c,  5, 5},
 135         [DVBT_CDIV_PH0]         = {0x1, 0x7d,  3, 0},
 136         [DVBT_CDIV_PH1]         = {0x1, 0x7d,  7, 4},
 137         [DVBT_MPEG_IO_OPT_2_2]  = {0x0, 0x6,   7, 7},
 138         [DVBT_MPEG_IO_OPT_1_0]  = {0x0, 0x7,   7, 6},
 139         [DVBT_CKOUTPAR_PIP]     = {0x0, 0xb7,  4, 4},
 140         [DVBT_CKOUT_PWR_PIP]    = {0x0, 0xb7,  3, 3},
 141         [DVBT_SYNC_LVL_PIP]     = {0x0, 0xb7,  2, 2},
 142         [DVBT_ERR_LVL_PIP]      = {0x0, 0xb7,  1, 1},
 143         [DVBT_VAL_LVL_PIP]      = {0x0, 0xb7,  0, 0},
 144         [DVBT_CKOUTPAR_PID]     = {0x0, 0xb9,  4, 4},
 145         [DVBT_CKOUT_PWR_PID]    = {0x0, 0xb9,  3, 3},
 146         [DVBT_SYNC_LVL_PID]     = {0x0, 0xb9,  2, 2},
 147         [DVBT_ERR_LVL_PID]      = {0x0, 0xb9,  1, 1},
 148         [DVBT_VAL_LVL_PID]      = {0x0, 0xb9,  0, 0},
 149         [DVBT_SM_PASS]          = {0x1, 0x93, 11, 0},
 150         [DVBT_AD7_SETTING]      = {0x0, 0x11, 15, 0},
 151         [DVBT_RSSI_R]           = {0x3, 0x1,   6, 0},
 152         [DVBT_ACI_DET_IND]      = {0x3, 0x12,  0, 0},
 153         [DVBT_REG_MON]          = {0x0, 0xd,   1, 0},
 154         [DVBT_REG_MONSEL]       = {0x0, 0xd,   2, 2},
 155         [DVBT_REG_GPE]          = {0x0, 0xd,   7, 7},
 156         [DVBT_REG_GPO]          = {0x0, 0x10,  0, 0},
 157         [DVBT_REG_4MSEL]        = {0x0, 0x13,  0, 0},
 158 };
 159
 160 /* write multiple hardware registers */
 161 static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
 162 {
 163         int ret;
 164         u8 buf[1+len];
 165         struct i2c_msg msg[1] = {
 166                 {
 167                         .addr = priv->cfg.i2c_addr,
 168                         .flags = 0,
 169                         .len = 1+len,
 170                         .buf = buf,
 171                 }
 172         };
 173
 174         buf[0] = reg;
 175         memcpy(&buf[1], val, len);
 176
 177         ret = i2c_transfer(priv->i2c, msg, 1);
 178         if (ret == 1) {
 179                 ret = 0;
 180         } else {
 181                 warn("i2c wr failed=%d reg=%02x len=%d", ret, reg, len);
 182                 ret = -EREMOTEIO;
 183         }
 184         return ret;
 185 }
 186
 187 /* read multiple hardware registers */
 188 static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
 189 {
 190         int ret;
 191         struct i2c_msg msg[2] = {
 192                 {
 193                         .addr = priv->cfg.i2c_addr,
 194                         .flags = 0,
 195                         .len = 1,
 196                         .buf = &reg,
 197                 }, {
 198                         .addr = priv->cfg.i2c_addr,
 199                         .flags = I2C_M_RD,
 200                         .len = len,
 201                         .buf = val,
 202                 }
 203         };
 204
 205         ret = i2c_transfer(priv->i2c, msg, 2);
 206         if (ret == 2) {
 207                 ret = 0;
 208         } else {
 209                 warn("i2c rd failed=%d reg=%02x len=%d", ret, reg, len);
 210                 ret = -EREMOTEIO;
 211 }
 212 return ret;
 213 }
 214
 215 /* write multiple registers */
 216 static int rtl2832_wr_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
 217         int len)
 218 {
 219         int ret;
 220
 221
 222         /* switch bank if needed */
 223         if (page != priv->page) {
 224                 ret = rtl2832_wr(priv, 0x00, &page, 1);
 225                 if (ret)
 226                         return ret;
 227
 228                 priv->page = page;
 229 }
 230
 231 return rtl2832_wr(priv, reg, val, len);
 232 }
 233
 234 /* read multiple registers */
 235 static int rtl2832_rd_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
 236         int len)
 237 {
 238         int ret;
 239
 240         /* switch bank if needed */
 241         if (page != priv->page) {
 242                 ret = rtl2832_wr(priv, 0x00, &page, 1);
 243                 if (ret)
 244                         return ret;
 245
 246                 priv->page = page;
 247         }
 248
 249         return rtl2832_rd(priv, reg, val, len);
 250 }
 251
 252 #if 0 /* currently not used */
 253 /* write single register */
 254 static int rtl2832_wr_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 val)
 255 {
 256         return rtl2832_wr_regs(priv, reg, page, &val, 1);
 257 }
 258 #endif
 259
 260 /* read single register */
 261 static int rtl2832_rd_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val)
 262 {
 263         return rtl2832_rd_regs(priv, reg, page, val, 1);
 264 }
 265
 266 int rtl2832_rd_demod_reg(struct rtl2832_priv *priv, int reg, u32 *val)
 267 {
 268         int ret;
 269
 270         u8 reg_start_addr;
 271         u8 msb, lsb;
 272         u8 page;
 273         u8 reading[4];
 274         u32 reading_tmp;
 275         int i;
 276
 277         u8 len;
 278         u32 mask;
 279
 280         reg_start_addr = registers[reg].start_address;
 281         msb = registers[reg].msb;
 282         lsb = registers[reg].lsb;
 283         page = registers[reg].page;
 284
 285         len = (msb >> 3) + 1;
 286         mask = REG_MASK(msb - lsb);
 287
 288         ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
 289         if (ret)
 290                 goto err;
 291
 292         reading_tmp = 0;
 293         for (i = 0; i < len; i++)
 294                 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
 295
 296         *val = (reading_tmp >> lsb) & mask;
 297
 298         return ret;
 299
 300 err:
 301         dbg("%s: failed=%d", __func__, ret);
 302         return ret;
 303
 304 }
 305
 306 int rtl2832_wr_demod_reg(struct rtl2832_priv *priv, int reg, u32 val)
 307 {
 308         int ret, i;
 309         u8 len;
 310         u8 reg_start_addr;
 311         u8 msb, lsb;
 312         u8 page;
 313         u32 mask;
 314
 315
 316         u8 reading[4];
 317         u8 writing[4];
 318         u32 reading_tmp;
 319         u32 writing_tmp;
 320
 321
 322         reg_start_addr = registers[reg].start_address;
 323         msb = registers[reg].msb;
 324         lsb = registers[reg].lsb;
 325         page = registers[reg].page;
 326
 327         len = (msb >> 3) + 1;
 328         mask = REG_MASK(msb - lsb);
 329
 330
 331         ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
 332         if (ret)
 333                 goto err;
 334
 335         reading_tmp = 0;
 336         for (i = 0; i < len; i++)
 337                 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
 338
 339         writing_tmp = reading_tmp & ~(mask << lsb);
 340         writing_tmp |= ((val & mask) << lsb);
 341
 342
 343         for (i = 0; i < len; i++)
 344                 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
 345
 346         ret = rtl2832_wr_regs(priv, reg_start_addr, page, &writing[0], len);
 347         if (ret)
 348                 goto err;
 349
 350         return ret;
 351
 352 err:
 353         dbg("%s: failed=%d", __func__, ret);
 354         return ret;
 355
 356 }
 357
 358
 359 static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 360 {
 361         int ret;
 362         struct rtl2832_priv *priv = fe->demodulator_priv;
 363
 364         dbg("%s: enable=%d", __func__, enable);
 365
 366         /* gate already open or close */
 367         if (priv->i2c_gate_state == enable)
 368                 return 0;
 369
 370         ret = rtl2832_wr_demod_reg(priv, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
 371         if (ret)
 372                 goto err;
 373
 374         priv->i2c_gate_state = enable;
 375
 376         return ret;
 377 err:
 378         dbg("%s: failed=%d", __func__, ret);
 379         return ret;
 380 }
 381
 382
 383
 384 static int rtl2832_init(struct dvb_frontend *fe)
 385 {
 386         struct rtl2832_priv *priv = fe->demodulator_priv;
 387         int i, ret;
 388
 389         u8 en_bbin;
 390         u64 pset_iffreq;
 391
 392         /* initialization values for the demodulator registers */
 393         struct rtl2832_reg_value rtl2832_initial_regs[] = {
 394                 {DVBT_AD_EN_REG,                0x1},
 395                 {DVBT_AD_EN_REG1,               0x1},
 396                 {DVBT_RSD_BER_FAIL_VAL,         0x2800},
 397                 {DVBT_MGD_THD0,                 0x10},
 398                 {DVBT_MGD_THD1,                 0x20},
 399                 {DVBT_MGD_THD2,                 0x20},
 400                 {DVBT_MGD_THD3,                 0x40},
 401                 {DVBT_MGD_THD4,                 0x22},
 402                 {DVBT_MGD_THD5,                 0x32},
 403                 {DVBT_MGD_THD6,                 0x37},
 404                 {DVBT_MGD_THD7,                 0x39},
 405                 {DVBT_EN_BK_TRK,                0x0},
 406                 {DVBT_EN_CACQ_NOTCH,            0x0},
 407                 {DVBT_AD_AV_REF,                0x2a},
 408                 {DVBT_REG_PI,                   0x6},
 409                 {DVBT_PIP_ON,                   0x0},
 410                 {DVBT_CDIV_PH0,                 0x8},
 411                 {DVBT_CDIV_PH1,                 0x8},
 412                 {DVBT_SCALE1_B92,               0x4},
 413                 {DVBT_SCALE1_B93,               0xb0},
 414                 {DVBT_SCALE1_BA7,               0x78},
 415                 {DVBT_SCALE1_BA9,               0x28},
 416                 {DVBT_SCALE1_BAA,               0x59},
 417                 {DVBT_SCALE1_BAB,               0x83},
 418                 {DVBT_SCALE1_BAC,               0xd4},
 419                 {DVBT_SCALE1_BB0,               0x65},
 420                 {DVBT_SCALE1_BB1,               0x43},
 421                 {DVBT_KB_P1,                    0x1},
 422                 {DVBT_KB_P2,                    0x4},
 423                 {DVBT_KB_P3,                    0x7},
 424                 {DVBT_K1_CR_STEP12,             0xa},
 425                 {DVBT_REG_GPE,                  0x1},
 426                 {DVBT_SERIAL,                   0x0},
 427                 {DVBT_CDIV_PH0,                 0x9},
 428                 {DVBT_CDIV_PH1,                 0x9},
 429                 {DVBT_MPEG_IO_OPT_2_2,          0x0},
 430                 {DVBT_MPEG_IO_OPT_1_0,          0x0},
 431                 {DVBT_TRK_KS_P2,                0x4},
 432                 {DVBT_TRK_KS_I2,                0x7},
 433                 {DVBT_TR_THD_SET2,              0x6},
 434                 {DVBT_TRK_KC_I2,                0x5},
 435                 {DVBT_CR_THD_SET2,              0x1},
 436                 {DVBT_SPEC_INV,                 0x0},
 437                 {DVBT_DAGC_TRG_VAL,             0x5a},
 438                 {DVBT_AGC_TARG_VAL_0,           0x0},
 439                 {DVBT_AGC_TARG_VAL_8_1,         0x5a},
 440                 {DVBT_AAGC_LOOP_GAIN,           0x16},
 441                 {DVBT_LOOP_GAIN2_3_0,           0x6},
 442                 {DVBT_LOOP_GAIN2_4,             0x1},
 443                 {DVBT_LOOP_GAIN3,               0x16},
 444                 {DVBT_VTOP1,                    0x35},
 445                 {DVBT_VTOP2,                    0x21},
 446                 {DVBT_VTOP3,                    0x21},
 447                 {DVBT_KRF1,                     0x0},
 448                 {DVBT_KRF2,                     0x40},
 449                 {DVBT_KRF3,                     0x10},
 450                 {DVBT_KRF4,                     0x10},
 451                 {DVBT_IF_AGC_MIN,               0x80},
 452                 {DVBT_IF_AGC_MAX,               0x7f},
 453                 {DVBT_RF_AGC_MIN,               0x80},
 454                 {DVBT_RF_AGC_MAX,               0x7f},
 455                 {DVBT_POLAR_RF_AGC,             0x0},
 456                 {DVBT_POLAR_IF_AGC,             0x0},
 457                 {DVBT_AD7_SETTING,              0xe9bf},
 458                 {DVBT_EN_GI_PGA,                0x0},
 459                 {DVBT_THD_LOCK_UP,              0x0},
 460                 {DVBT_THD_LOCK_DW,              0x0},
 461                 {DVBT_THD_UP1,                  0x11},
 462                 {DVBT_THD_DW1,                  0xef},
 463                 {DVBT_INTER_CNT_LEN,            0xc},
 464                 {DVBT_GI_PGA_STATE,             0x0},
 465                 {DVBT_EN_AGC_PGA,               0x1},
 466                 {DVBT_IF_AGC_MAN,               0x0},
 467         };
 468
 469
 470         dbg("%s", __func__);
 471
 472         en_bbin = (priv->cfg.if_dvbt == 0 ? 0x1 : 0x0);
 473
 474         /*
 475         * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
 476         *               / CrystalFreqHz)
 477         */
 478         pset_iffreq = priv->cfg.if_dvbt % priv->cfg.xtal;
 479         pset_iffreq *= 0x400000;
 480         pset_iffreq = div_u64(pset_iffreq, priv->cfg.xtal);
 481         pset_iffreq = pset_iffreq & 0x3fffff;
 482
 483
 484
 485         for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
 486                 ret = rtl2832_wr_demod_reg(priv, rtl2832_initial_regs[i].reg,
 487                         rtl2832_initial_regs[i].value);
 488                 if (ret)
 489                         goto err;
 490         }
 491
 492         /* if frequency settings */
 493         ret = rtl2832_wr_demod_reg(priv, DVBT_EN_BBIN, en_bbin);
 494                 if (ret)
 495                         goto err;
 496
 497         ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq);
 498                 if (ret)
 499                         goto err;
 500
 501         priv->sleeping = false;
 502
 503         return ret;
 504
 505 err:
 506         dbg("%s: failed=%d", __func__, ret);
 507         return ret;
 508 }
 509
 510 static int rtl2832_sleep(struct dvb_frontend *fe)
 511 {
 512         struct rtl2832_priv *priv = fe->demodulator_priv;
 513
 514         dbg("%s", __func__);
 515         priv->sleeping = true;
 516         return 0;
 517 }
 518
 519 int rtl2832_get_tune_settings(struct dvb_frontend *fe,
 520         struct dvb_frontend_tune_settings *s)
 521 {
 522         dbg("%s", __func__);
 523         s->min_delay_ms = 1000;
 524         s->step_size = fe->ops.info.frequency_stepsize * 2;
 525         s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
 526         return 0;
 527 }
 528
 529 static int rtl2832_set_frontend(struct dvb_frontend *fe)
 530 {
 531         struct rtl2832_priv *priv = fe->demodulator_priv;
 532         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 533         int ret, i, j;
 534         u64 bw_mode, num, num2;
 535         u32 resamp_ratio, cfreq_off_ratio;
 536
 537
 538         static u8 bw_params[3][32] = {
 539         /* 6 MHz bandwidth */
 540                 {
 541                 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
 542                 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
 543                 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
 544                 0x19, 0xe0,
 545                 },
 546
 547         /*  7 MHz bandwidth */
 548                 {
 549                 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
 550                 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
 551                 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
 552                 0x19, 0x10,
 553                 },
 554
 555         /*  8 MHz bandwidth */
 556                 {
 557                 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
 558                 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
 559                 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
 560                 0x19, 0xe0,
 561                 },
 562         };
 563
 564
 565         dbg("%s: frequency=%d bandwidth_hz=%d inversion=%d", __func__,
 566                 c->frequency, c->bandwidth_hz, c->inversion);
 567
 568
 569         /* program tuner */
 570         if (fe->ops.tuner_ops.set_params)
 571                 fe->ops.tuner_ops.set_params(fe);
 572
 573
 574         switch (c->bandwidth_hz) {
 575         case 6000000:
 576                 i = 0;
 577                 bw_mode = 48000000;
 578                 break;
 579         case 7000000:
 580                 i = 1;
 581                 bw_mode = 56000000;
 582                 break;
 583         case 8000000:
 584                 i = 2;
 585                 bw_mode = 64000000;
 586                 break;
 587         default:
 588                 dbg("invalid bandwidth");
 589                 return -EINVAL;
 590         }
 591
 592         for (j = 0; j < sizeof(bw_params[j]); j++) {
 593                 ret = rtl2832_wr_regs(priv, 0x1c+j, 1, &bw_params[i][j], 1);
 594                 if (ret)
 595                         goto err;
 596         }
 597
 598         /* calculate and set resample ratio
 599         * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
 600         *       / ConstWithBandwidthMode)
 601         */
 602         num = priv->cfg.xtal * 7;
 603         num *= 0x400000;
 604         num = div_u64(num, bw_mode);
 605         resamp_ratio =  num & 0x3ffffff;
 606         ret = rtl2832_wr_demod_reg(priv, DVBT_RSAMP_RATIO, resamp_ratio);
 607         if (ret)
 608                 goto err;
 609
 610         /* calculate and set cfreq off ratio
 611         * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
 612         *       / (CrystalFreqHz * 7))
 613         */
 614         num = bw_mode << 20;
 615         num2 = priv->cfg.xtal * 7;
 616         num = div_u64(num, num2);
 617         num = -num;
 618         cfreq_off_ratio = num & 0xfffff;
 619         ret = rtl2832_wr_demod_reg(priv, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
 620         if (ret)
 621                 goto err;
 622
 623
 624         /* soft reset */
 625         ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
 626         if (ret)
 627                 goto err;
 628
 629         ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
 630         if (ret)
 631                 goto err;
 632
 633         return ret;
 634 err:
 635         info("%s: failed=%d", __func__, ret);
 636         return ret;
 637 }
 638
 639 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
 640 {
 641         struct rtl2832_priv *priv = fe->demodulator_priv;
 642         int ret;
 643         u32 tmp;
 644         *status = 0;
 645
 646
 647         dbg("%s", __func__);
 648         if (priv->sleeping)
 649                 return 0;
 650
 651         ret = rtl2832_rd_demod_reg(priv, DVBT_FSM_STAGE, &tmp);
 652         if (ret)
 653                 goto err;
 654
 655         if (tmp == 11) {
 656                 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
 657                                 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 658         }
 659         /* TODO find out if this is also true for rtl2832? */
 660         /*else if (tmp == 10) {
 661                 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
 662                                 FE_HAS_VITERBI;
 663         }*/
 664
 665         return ret;
 666 err:
 667         info("%s: failed=%d", __func__, ret);
 668         return ret;
 669 }
 670
 671 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
 672 {
 673         *snr = 0;
 674         return 0;
 675 }
 676
 677 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
 678 {
 679         *ber = 0;
 680         return 0;
 681 }
 682
 683 static int rtl2832_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 684 {
 685         *ucblocks = 0;
 686         return 0;
 687 }
 688
 689
 690 static int rtl2832_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 691 {
 692         *strength = 0;
 693         return 0;
 694 }
 695
 696 static struct dvb_frontend_ops rtl2832_ops;
 697
 698 static void rtl2832_release(struct dvb_frontend *fe)
 699 {
 700         struct rtl2832_priv *priv = fe->demodulator_priv;
 701
 702         dbg("%s", __func__);
 703         kfree(priv);
 704 }
 705
 706 struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg,
 707         struct i2c_adapter *i2c)
 708 {
 709         struct rtl2832_priv *priv = NULL;
 710         int ret = 0;
 711         u8 tmp;
 712
 713         dbg("%s", __func__);
 714
 715         /* allocate memory for the internal state */
 716         priv = kzalloc(sizeof(struct rtl2832_priv), GFP_KERNEL);
 717         if (priv == NULL)
 718                 goto err;
 719
 720         /* setup the priv */
 721         priv->i2c = i2c;
 722         priv->tuner = cfg->tuner;
 723         memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config));
 724
 725         /* check if the demod is there */
 726         ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp);
 727         if (ret)
 728                 goto err;
 729
 730         /* create dvb_frontend */
 731         memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
 732         priv->fe.demodulator_priv = priv;
 733
 734         /* TODO implement sleep mode */
 735         priv->sleeping = true;
 736
 737         return &priv->fe;
 738 err:
 739         dbg("%s: failed=%d", __func__, ret);
 740         kfree(priv);
 741         return NULL;
 742 }
 743 EXPORT_SYMBOL(rtl2832_attach);
 744
 745 static struct dvb_frontend_ops rtl2832_ops = {
 746         .delsys = { SYS_DVBT },
 747         .info = {
 748                 .name = "Realtek RTL2832 (DVB-T)",
 749                 .frequency_min    = 174000000,
 750                 .frequency_max    = 862000000,
 751                 .frequency_stepsize = 166667,
 752                 .caps = FE_CAN_FEC_1_2 |
 753                         FE_CAN_FEC_2_3 |
 754                         FE_CAN_FEC_3_4 |
 755                         FE_CAN_FEC_5_6 |
 756                         FE_CAN_FEC_7_8 |
 757                         FE_CAN_FEC_AUTO |
 758                         FE_CAN_QPSK |
 759                         FE_CAN_QAM_16 |
 760                         FE_CAN_QAM_64 |
 761                         FE_CAN_QAM_AUTO |
 762                         FE_CAN_TRANSMISSION_MODE_AUTO |
 763                         FE_CAN_GUARD_INTERVAL_AUTO |
 764                         FE_CAN_HIERARCHY_AUTO |
 765                         FE_CAN_RECOVER |
 766                         FE_CAN_MUTE_TS
 767          },
 768
 769         .release = rtl2832_release,
 770
 771         .init = rtl2832_init,
 772         .sleep = rtl2832_sleep,
 773
 774         .get_tune_settings = rtl2832_get_tune_settings,
 775
 776         .set_frontend = rtl2832_set_frontend,
 777
 778         .read_status = rtl2832_read_status,
 779         .read_snr = rtl2832_read_snr,
 780         .read_ber = rtl2832_read_ber,
 781         .read_ucblocks = rtl2832_read_ucblocks,
 782         .read_signal_strength = rtl2832_read_signal_strength,
 783         .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
 784 };
 785
 786 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
 787 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
 788 MODULE_LICENSE("GPL");
 789 MODULE_VERSION("0.5");