drivers/irqchip/irq-gic-v3-its.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/bitmap.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/log2.h>
  23 #include <linux/mm.h>
  24 #include <linux/msi.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_pci.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/percpu.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/irqchip.h>
  34 #include <linux/irqchip/arm-gic-v3.h>
  35
  36 #include <asm/cacheflush.h>
  37 #include <asm/cputype.h>
  38 #include <asm/exception.h>
  39
  40 #include "irq-gic-common.h"
  41
  42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  44
  45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  46
  47 /*
  48  * Collection structure - just an ID, and a redistributor address to
  49  * ping. We use one per CPU as a bag of interrupts assigned to this
  50  * CPU.
  51  */
  52 struct its_collection {
  53         u64                     target_address;
  54         u16                     col_id;
  55 };
  56
  57 /*
  58  * The ITS structure - contains most of the infrastructure, with the
  59  * top-level MSI domain, the command queue, the collections, and the
  60  * list of devices writing to it.
  61  */
  62 struct its_node {
  63         raw_spinlock_t          lock;
  64         struct list_head        entry;
  65         void __iomem            *base;
  66         unsigned long           phys_base;
  67         struct its_cmd_block    *cmd_base;
  68         struct its_cmd_block    *cmd_write;
  69         void                    *tables[GITS_BASER_NR_REGS];
  70         struct its_collection   *collections;
  71         struct list_head        its_device_list;
  72         u64                     flags;
  73         u32                     ite_size;
  74 };
  75
  76 #define ITS_ITT_ALIGN           SZ_256
  77
  78 struct event_lpi_map {
  79         unsigned long           *lpi_map;
  80         u16                     *col_map;
  81         irq_hw_number_t         lpi_base;
  82         int                     nr_lpis;
  83 };
  84
  85 /*
  86  * The ITS view of a device - belongs to an ITS, a collection, owns an
  87  * interrupt translation table, and a list of interrupts.
  88  */
  89 struct its_device {
  90         struct list_head        entry;
  91         struct its_node         *its;
  92         struct event_lpi_map    event_map;
  93         void                    *itt;
  94         u32                     nr_ites;
  95         u32                     device_id;
  96 };
  97
  98 static LIST_HEAD(its_nodes);
  99 static DEFINE_SPINLOCK(its_lock);
 100 static struct device_node *gic_root_node;
 101 static struct rdists *gic_rdists;
 102
 103 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 104 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 105
 106 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 107                                                u32 event)
 108 {
 109         struct its_node *its = its_dev->its;
 110
 111         return its->collections + its_dev->event_map.col_map[event];
 112 }
 113
 114 /*
 115  * ITS command descriptors - parameters to be encoded in a command
 116  * block.
 117  */
 118 struct its_cmd_desc {
 119         union {
 120                 struct {
 121                         struct its_device *dev;
 122                         u32 event_id;
 123                 } its_inv_cmd;
 124
 125                 struct {
 126                         struct its_device *dev;
 127                         u32 event_id;
 128                 } its_int_cmd;
 129
 130                 struct {
 131                         struct its_device *dev;
 132                         int valid;
 133                 } its_mapd_cmd;
 134
 135                 struct {
 136                         struct its_collection *col;
 137                         int valid;
 138                 } its_mapc_cmd;
 139
 140                 struct {
 141                         struct its_device *dev;
 142                         u32 phys_id;
 143                         u32 event_id;
 144                 } its_mapvi_cmd;
 145
 146                 struct {
 147                         struct its_device *dev;
 148                         struct its_collection *col;
 149                         u32 event_id;
 150                 } its_movi_cmd;
 151
 152                 struct {
 153                         struct its_device *dev;
 154                         u32 event_id;
 155                 } its_discard_cmd;
 156
 157                 struct {
 158                         struct its_collection *col;
 159                 } its_invall_cmd;
 160         };
 161 };
 162
 163 /*
 164  * The ITS command block, which is what the ITS actually parses.
 165  */
 166 struct its_cmd_block {
 167         u64     raw_cmd[4];
 168 };
 169
 170 #define ITS_CMD_QUEUE_SZ                SZ_64K
 171 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 172
 173 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
 174                                                     struct its_cmd_desc *);
 175
 176 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 177 {
 178         cmd->raw_cmd[0] &= ~0xffUL;
 179         cmd->raw_cmd[0] |= cmd_nr;
 180 }
 181
 182 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 183 {
 184         cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
 185         cmd->raw_cmd[0] |= ((u64)devid) << 32;
 186 }
 187
 188 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 189 {
 190         cmd->raw_cmd[1] &= ~0xffffffffUL;
 191         cmd->raw_cmd[1] |= id;
 192 }
 193
 194 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 195 {
 196         cmd->raw_cmd[1] &= 0xffffffffUL;
 197         cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
 198 }
 199
 200 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 201 {
 202         cmd->raw_cmd[1] &= ~0x1fUL;
 203         cmd->raw_cmd[1] |= size & 0x1f;
 204 }
 205
 206 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 207 {
 208         cmd->raw_cmd[2] &= ~0xffffffffffffUL;
 209         cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
 210 }
 211
 212 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 213 {
 214         cmd->raw_cmd[2] &= ~(1UL << 63);
 215         cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
 216 }
 217
 218 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 219 {
 220         cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
 221         cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
 222 }
 223
 224 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 225 {
 226         cmd->raw_cmd[2] &= ~0xffffUL;
 227         cmd->raw_cmd[2] |= col;
 228 }
 229
 230 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 231 {
 232         /* Let's fixup BE commands */
 233         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 234         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 235         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 236         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 237 }
 238
 239 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
 240                                                  struct its_cmd_desc *desc)
 241 {
 242         unsigned long itt_addr;
 243         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 244
 245         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 246         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 247
 248         its_encode_cmd(cmd, GITS_CMD_MAPD);
 249         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 250         its_encode_size(cmd, size - 1);
 251         its_encode_itt(cmd, itt_addr);
 252         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 253
 254         its_fixup_cmd(cmd);
 255
 256         return NULL;
 257 }
 258
 259 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
 260                                                  struct its_cmd_desc *desc)
 261 {
 262         its_encode_cmd(cmd, GITS_CMD_MAPC);
 263         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 264         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 265         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 266
 267         its_fixup_cmd(cmd);
 268
 269         return desc->its_mapc_cmd.col;
 270 }
 271
 272 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
 273                                                   struct its_cmd_desc *desc)
 274 {
 275         struct its_collection *col;
 276
 277         col = dev_event_to_col(desc->its_mapvi_cmd.dev,
 278                                desc->its_mapvi_cmd.event_id);
 279
 280         its_encode_cmd(cmd, GITS_CMD_MAPVI);
 281         its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
 282         its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
 283         its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
 284         its_encode_collection(cmd, col->col_id);
 285
 286         its_fixup_cmd(cmd);
 287
 288         return col;
 289 }
 290
 291 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
 292                                                  struct its_cmd_desc *desc)
 293 {
 294         struct its_collection *col;
 295
 296         col = dev_event_to_col(desc->its_movi_cmd.dev,
 297                                desc->its_movi_cmd.event_id);
 298
 299         its_encode_cmd(cmd, GITS_CMD_MOVI);
 300         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 301         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 302         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 303
 304         its_fixup_cmd(cmd);
 305
 306         return col;
 307 }
 308
 309 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
 310                                                     struct its_cmd_desc *desc)
 311 {
 312         struct its_collection *col;
 313
 314         col = dev_event_to_col(desc->its_discard_cmd.dev,
 315                                desc->its_discard_cmd.event_id);
 316
 317         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 318         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 319         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 320
 321         its_fixup_cmd(cmd);
 322
 323         return col;
 324 }
 325
 326 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
 327                                                 struct its_cmd_desc *desc)
 328 {
 329         struct its_collection *col;
 330
 331         col = dev_event_to_col(desc->its_inv_cmd.dev,
 332                                desc->its_inv_cmd.event_id);
 333
 334         its_encode_cmd(cmd, GITS_CMD_INV);
 335         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 336         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 337
 338         its_fixup_cmd(cmd);
 339
 340         return col;
 341 }
 342
 343 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
 344                                                    struct its_cmd_desc *desc)
 345 {
 346         its_encode_cmd(cmd, GITS_CMD_INVALL);
 347         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 348
 349         its_fixup_cmd(cmd);
 350
 351         return NULL;
 352 }
 353
 354 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 355                                  struct its_cmd_block *ptr)
 356 {
 357         return (ptr - its->cmd_base) * sizeof(*ptr);
 358 }
 359
 360 static int its_queue_full(struct its_node *its)
 361 {
 362         int widx;
 363         int ridx;
 364
 365         widx = its->cmd_write - its->cmd_base;
 366         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 367
 368         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 369         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 370                 return 1;
 371
 372         return 0;
 373 }
 374
 375 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 376 {
 377         struct its_cmd_block *cmd;
 378         u32 count = 1000000;    /* 1s! */
 379
 380         while (its_queue_full(its)) {
 381                 count--;
 382                 if (!count) {
 383                         pr_err_ratelimited("ITS queue not draining\n");
 384                         return NULL;
 385                 }
 386                 cpu_relax();
 387                 udelay(1);
 388         }
 389
 390         cmd = its->cmd_write++;
 391
 392         /* Handle queue wrapping */
 393         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 394                 its->cmd_write = its->cmd_base;
 395
 396         return cmd;
 397 }
 398
 399 static struct its_cmd_block *its_post_commands(struct its_node *its)
 400 {
 401         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 402
 403         writel_relaxed(wr, its->base + GITS_CWRITER);
 404
 405         return its->cmd_write;
 406 }
 407
 408 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 409 {
 410         /*
 411          * Make sure the commands written to memory are observable by
 412          * the ITS.
 413          */
 414         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 415                 __flush_dcache_area(cmd, sizeof(*cmd));
 416         else
 417                 dsb(ishst);
 418 }
 419
 420 static void its_wait_for_range_completion(struct its_node *its,
 421                                           struct its_cmd_block *from,
 422                                           struct its_cmd_block *to)
 423 {
 424         u64 rd_idx, from_idx, to_idx;
 425         u32 count = 1000000;    /* 1s! */
 426
 427         from_idx = its_cmd_ptr_to_offset(its, from);
 428         to_idx = its_cmd_ptr_to_offset(its, to);
 429
 430         while (1) {
 431                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 432                 if (rd_idx >= to_idx || rd_idx < from_idx)
 433                         break;
 434
 435                 count--;
 436                 if (!count) {
 437                         pr_err_ratelimited("ITS queue timeout\n");
 438                         return;
 439                 }
 440                 cpu_relax();
 441                 udelay(1);
 442         }
 443 }
 444
 445 static void its_send_single_command(struct its_node *its,
 446                                     its_cmd_builder_t builder,
 447                                     struct its_cmd_desc *desc)
 448 {
 449         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
 450         struct its_collection *sync_col;
 451         unsigned long flags;
 452
 453         raw_spin_lock_irqsave(&its->lock, flags);
 454
 455         cmd = its_allocate_entry(its);
 456         if (!cmd) {             /* We're soooooo screewed... */
 457                 pr_err_ratelimited("ITS can't allocate, dropping command\n");
 458                 raw_spin_unlock_irqrestore(&its->lock, flags);
 459                 return;
 460         }
 461         sync_col = builder(cmd, desc);
 462         its_flush_cmd(its, cmd);
 463
 464         if (sync_col) {
 465                 sync_cmd = its_allocate_entry(its);
 466                 if (!sync_cmd) {
 467                         pr_err_ratelimited("ITS can't SYNC, skipping\n");
 468                         goto post;
 469                 }
 470                 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 471                 its_encode_target(sync_cmd, sync_col->target_address);
 472                 its_fixup_cmd(sync_cmd);
 473                 its_flush_cmd(its, sync_cmd);
 474         }
 475
 476 post:
 477         next_cmd = its_post_commands(its);
 478         raw_spin_unlock_irqrestore(&its->lock, flags);
 479
 480         its_wait_for_range_completion(its, cmd, next_cmd);
 481 }
 482
 483 static void its_send_inv(struct its_device *dev, u32 event_id)
 484 {
 485         struct its_cmd_desc desc;
 486
 487         desc.its_inv_cmd.dev = dev;
 488         desc.its_inv_cmd.event_id = event_id;
 489
 490         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 491 }
 492
 493 static void its_send_mapd(struct its_device *dev, int valid)
 494 {
 495         struct its_cmd_desc desc;
 496
 497         desc.its_mapd_cmd.dev = dev;
 498         desc.its_mapd_cmd.valid = !!valid;
 499
 500         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 501 }
 502
 503 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 504                           int valid)
 505 {
 506         struct its_cmd_desc desc;
 507
 508         desc.its_mapc_cmd.col = col;
 509         desc.its_mapc_cmd.valid = !!valid;
 510
 511         its_send_single_command(its, its_build_mapc_cmd, &desc);
 512 }
 513
 514 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
 515 {
 516         struct its_cmd_desc desc;
 517
 518         desc.its_mapvi_cmd.dev = dev;
 519         desc.its_mapvi_cmd.phys_id = irq_id;
 520         desc.its_mapvi_cmd.event_id = id;
 521
 522         its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
 523 }
 524
 525 static void its_send_movi(struct its_device *dev,
 526                           struct its_collection *col, u32 id)
 527 {
 528         struct its_cmd_desc desc;
 529
 530         desc.its_movi_cmd.dev = dev;
 531         desc.its_movi_cmd.col = col;
 532         desc.its_movi_cmd.event_id = id;
 533
 534         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 535 }
 536
 537 static void its_send_discard(struct its_device *dev, u32 id)
 538 {
 539         struct its_cmd_desc desc;
 540
 541         desc.its_discard_cmd.dev = dev;
 542         desc.its_discard_cmd.event_id = id;
 543
 544         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 545 }
 546
 547 static void its_send_invall(struct its_node *its, struct its_collection *col)
 548 {
 549         struct its_cmd_desc desc;
 550
 551         desc.its_invall_cmd.col = col;
 552
 553         its_send_single_command(its, its_build_invall_cmd, &desc);
 554 }
 555
 556 /*
 557  * irqchip functions - assumes MSI, mostly.
 558  */
 559
 560 static inline u32 its_get_event_id(struct irq_data *d)
 561 {
 562         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 563         return d->hwirq - its_dev->event_map.lpi_base;
 564 }
 565
 566 static void lpi_set_config(struct irq_data *d, bool enable)
 567 {
 568         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 569         irq_hw_number_t hwirq = d->hwirq;
 570         u32 id = its_get_event_id(d);
 571         u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
 572
 573         if (enable)
 574                 *cfg |= LPI_PROP_ENABLED;
 575         else
 576                 *cfg &= ~LPI_PROP_ENABLED;
 577
 578         /*
 579          * Make the above write visible to the redistributors.
 580          * And yes, we're flushing exactly: One. Single. Byte.
 581          * Humpf...
 582          */
 583         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
 584                 __flush_dcache_area(cfg, sizeof(*cfg));
 585         else
 586                 dsb(ishst);
 587         its_send_inv(its_dev, id);
 588 }
 589
 590 static void its_mask_irq(struct irq_data *d)
 591 {
 592         lpi_set_config(d, false);
 593 }
 594
 595 static void its_unmask_irq(struct irq_data *d)
 596 {
 597         lpi_set_config(d, true);
 598 }
 599
 600 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 601                             bool force)
 602 {
 603         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 604         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 605         struct its_collection *target_col;
 606         u32 id = its_get_event_id(d);
 607
 608         if (cpu >= nr_cpu_ids)
 609                 return -EINVAL;
 610
 611         target_col = &its_dev->its->collections[cpu];
 612         its_send_movi(its_dev, target_col, id);
 613         its_dev->event_map.col_map[id] = cpu;
 614
 615         return IRQ_SET_MASK_OK_DONE;
 616 }
 617
 618 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 619 {
 620         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 621         struct its_node *its;
 622         u64 addr;
 623
 624         its = its_dev->its;
 625         addr = its->phys_base + GITS_TRANSLATER;
 626
 627         msg->address_lo         = addr & ((1UL << 32) - 1);
 628         msg->address_hi         = addr >> 32;
 629         msg->data               = its_get_event_id(d);
 630 }
 631
 632 static struct irq_chip its_irq_chip = {
 633         .name                   = "ITS",
 634         .irq_mask               = its_mask_irq,
 635         .irq_unmask             = its_unmask_irq,
 636         .irq_eoi                = irq_chip_eoi_parent,
 637         .irq_set_affinity       = its_set_affinity,
 638         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
 639 };
 640
 641 /*
 642  * How we allocate LPIs:
 643  *
 644  * The GIC has id_bits bits for interrupt identifiers. From there, we
 645  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
 646  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
 647  * bits to the right.
 648  *
 649  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
 650  */
 651 #define IRQS_PER_CHUNK_SHIFT    5
 652 #define IRQS_PER_CHUNK          (1 << IRQS_PER_CHUNK_SHIFT)
 653
 654 static unsigned long *lpi_bitmap;
 655 static u32 lpi_chunks;
 656 static DEFINE_SPINLOCK(lpi_lock);
 657
 658 static int its_lpi_to_chunk(int lpi)
 659 {
 660         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
 661 }
 662
 663 static int its_chunk_to_lpi(int chunk)
 664 {
 665         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
 666 }
 667
 668 static int its_lpi_init(u32 id_bits)
 669 {
 670         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
 671
 672         lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
 673                              GFP_KERNEL);
 674         if (!lpi_bitmap) {
 675                 lpi_chunks = 0;
 676                 return -ENOMEM;
 677         }
 678
 679         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
 680         return 0;
 681 }
 682
 683 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
 684 {
 685         unsigned long *bitmap = NULL;
 686         int chunk_id;
 687         int nr_chunks;
 688         int i;
 689
 690         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
 691
 692         spin_lock(&lpi_lock);
 693
 694         do {
 695                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
 696                                                       0, nr_chunks, 0);
 697                 if (chunk_id < lpi_chunks)
 698                         break;
 699
 700                 nr_chunks--;
 701         } while (nr_chunks > 0);
 702
 703         if (!nr_chunks)
 704                 goto out;
 705
 706         bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
 707                          GFP_ATOMIC);
 708         if (!bitmap)
 709                 goto out;
 710
 711         for (i = 0; i < nr_chunks; i++)
 712                 set_bit(chunk_id + i, lpi_bitmap);
 713
 714         *base = its_chunk_to_lpi(chunk_id);
 715         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
 716
 717 out:
 718         spin_unlock(&lpi_lock);
 719
 720         if (!bitmap)
 721                 *base = *nr_ids = 0;
 722
 723         return bitmap;
 724 }
 725
 726 static void its_lpi_free(struct event_lpi_map *map)
 727 {
 728         int base = map->lpi_base;
 729         int nr_ids = map->nr_lpis;
 730         int lpi;
 731
 732         spin_lock(&lpi_lock);
 733
 734         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
 735                 int chunk = its_lpi_to_chunk(lpi);
 736                 BUG_ON(chunk > lpi_chunks);
 737                 if (test_bit(chunk, lpi_bitmap)) {
 738                         clear_bit(chunk, lpi_bitmap);
 739                 } else {
 740                         pr_err("Bad LPI chunk %d\n", chunk);
 741                 }
 742         }
 743
 744         spin_unlock(&lpi_lock);
 745
 746         kfree(map->lpi_map);
 747         kfree(map->col_map);
 748 }
 749
 750 /*
 751  * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
 752  * deal with (one configuration byte per interrupt). PENDBASE has to
 753  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 754  */
 755 #define LPI_PROPBASE_SZ         SZ_64K
 756 #define LPI_PENDBASE_SZ         (LPI_PROPBASE_SZ / 8 + SZ_1K)
 757
 758 /*
 759  * This is how many bits of ID we need, including the useless ones.
 760  */
 761 #define LPI_NRBITS              ilog2(LPI_PROPBASE_SZ + SZ_8K)
 762
 763 #define LPI_PROP_DEFAULT_PRIO   0xa0
 764
 765 static int __init its_alloc_lpi_tables(void)
 766 {
 767         phys_addr_t paddr;
 768
 769         gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
 770                                            get_order(LPI_PROPBASE_SZ));
 771         if (!gic_rdists->prop_page) {
 772                 pr_err("Failed to allocate PROPBASE\n");
 773                 return -ENOMEM;
 774         }
 775
 776         paddr = page_to_phys(gic_rdists->prop_page);
 777         pr_info("GIC: using LPI property table @%pa\n", &paddr);
 778
 779         /* Priority 0xa0, Group-1, disabled */
 780         memset(page_address(gic_rdists->prop_page),
 781                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
 782                LPI_PROPBASE_SZ);
 783
 784         /* Make sure the GIC will observe the written configuration */
 785         __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
 786
 787         return 0;
 788 }
 789
 790 static const char *its_base_type_string[] = {
 791         [GITS_BASER_TYPE_DEVICE]        = "Devices",
 792         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
 793         [GITS_BASER_TYPE_CPU]           = "Physical CPUs",
 794         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
 795         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
 796         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
 797         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
 798 };
 799
 800 static void its_free_tables(struct its_node *its)
 801 {
 802         int i;
 803
 804         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 805                 if (its->tables[i]) {
 806                         free_page((unsigned long)its->tables[i]);
 807                         its->tables[i] = NULL;
 808                 }
 809         }
 810 }
 811
 812 static int its_alloc_tables(const char *node_name, struct its_node *its)
 813 {
 814         int err;
 815         int i;
 816         int psz = SZ_64K;
 817         u64 shr = GITS_BASER_InnerShareable;
 818         u64 cache;
 819         u64 typer;
 820         u32 ids;
 821
 822         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
 823                 /*
 824                  * erratum 22375: only alloc 8MB table size
 825                  * erratum 24313: ignore memory access type
 826                  */
 827                 cache   = 0;
 828                 ids     = 0x14;                 /* 20 bits, 8MB */
 829         } else {
 830                 cache   = GITS_BASER_WaWb;
 831                 typer   = readq_relaxed(its->base + GITS_TYPER);
 832                 ids     = GITS_TYPER_DEVBITS(typer);
 833         }
 834
 835         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 836                 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
 837                 u64 type = GITS_BASER_TYPE(val);
 838                 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
 839                 int order = get_order(psz);
 840                 int alloc_size;
 841                 int alloc_pages;
 842                 u64 tmp;
 843                 void *base;
 844
 845                 if (type == GITS_BASER_TYPE_NONE)
 846                         continue;
 847
 848                 /*
 849                  * Allocate as many entries as required to fit the
 850                  * range of device IDs that the ITS can grok... The ID
 851                  * space being incredibly sparse, this results in a
 852                  * massive waste of memory.
 853                  *
 854                  * For other tables, only allocate a single page.
 855                  */
 856                 if (type == GITS_BASER_TYPE_DEVICE) {
 857                         /*
 858                          * 'order' was initialized earlier to the default page
 859                          * granule of the the ITS.  We can't have an allocation
 860                          * smaller than that.  If the requested allocation
 861                          * is smaller, round up to the default page granule.
 862                          */
 863                         order = max(get_order((1UL << ids) * entry_size),
 864                                     order);
 865                         if (order >= MAX_ORDER) {
 866                                 order = MAX_ORDER - 1;
 867                                 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
 868                                         node_name, order);
 869                         }
 870                 }
 871
 872                 alloc_size = (1 << order) * PAGE_SIZE;
 873                 alloc_pages = (alloc_size / psz);
 874                 if (alloc_pages > GITS_BASER_PAGES_MAX) {
 875                         alloc_pages = GITS_BASER_PAGES_MAX;
 876                         order = get_order(GITS_BASER_PAGES_MAX * psz);
 877                         pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
 878                                 node_name, order, alloc_pages);
 879                 }
 880
 881                 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
 882                 if (!base) {
 883                         err = -ENOMEM;
 884                         goto out_free;
 885                 }
 886
 887                 its->tables[i] = base;
 888
 889 retry_baser:
 890                 val = (virt_to_phys(base)                                |
 891                        (type << GITS_BASER_TYPE_SHIFT)                   |
 892                        ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
 893                        cache                                             |
 894                        shr                                               |
 895                        GITS_BASER_VALID);
 896
 897                 switch (psz) {
 898                 case SZ_4K:
 899                         val |= GITS_BASER_PAGE_SIZE_4K;
 900                         break;
 901                 case SZ_16K:
 902                         val |= GITS_BASER_PAGE_SIZE_16K;
 903                         break;
 904                 case SZ_64K:
 905                         val |= GITS_BASER_PAGE_SIZE_64K;
 906                         break;
 907                 }
 908
 909                 val |= alloc_pages - 1;
 910
 911                 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
 912                 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
 913
 914                 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 915                         /*
 916                          * Shareability didn't stick. Just use
 917                          * whatever the read reported, which is likely
 918                          * to be the only thing this redistributor
 919                          * supports. If that's zero, make it
 920                          * non-cacheable as well.
 921                          */
 922                         shr = tmp & GITS_BASER_SHAREABILITY_MASK;
 923                         if (!shr) {
 924                                 cache = GITS_BASER_nC;
 925                                 __flush_dcache_area(base, alloc_size);
 926                         }
 927                         goto retry_baser;
 928                 }
 929
 930                 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
 931                         /*
 932                          * Page size didn't stick. Let's try a smaller
 933                          * size and retry. If we reach 4K, then
 934                          * something is horribly wrong...
 935                          */
 936                         switch (psz) {
 937                         case SZ_16K:
 938                                 psz = SZ_4K;
 939                                 goto retry_baser;
 940                         case SZ_64K:
 941                                 psz = SZ_16K;
 942                                 goto retry_baser;
 943                         }
 944                 }
 945
 946                 if (val != tmp) {
 947                         pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
 948                                node_name, i,
 949                                (unsigned long) val, (unsigned long) tmp);
 950                         err = -ENXIO;
 951                         goto out_free;
 952                 }
 953
 954                 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
 955                         (int)(alloc_size / entry_size),
 956                         its_base_type_string[type],
 957                         (unsigned long)virt_to_phys(base),
 958                         psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
 959         }
 960
 961         return 0;
 962
 963 out_free:
 964         its_free_tables(its);
 965
 966         return err;
 967 }
 968
 969 static int its_alloc_collections(struct its_node *its)
 970 {
 971         its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
 972                                    GFP_KERNEL);
 973         if (!its->collections)
 974                 return -ENOMEM;
 975
 976         return 0;
 977 }
 978
 979 static void its_cpu_init_lpis(void)
 980 {
 981         void __iomem *rbase = gic_data_rdist_rd_base();
 982         struct page *pend_page;
 983         u64 val, tmp;
 984
 985         /* If we didn't allocate the pending table yet, do it now */
 986         pend_page = gic_data_rdist()->pend_page;
 987         if (!pend_page) {
 988                 phys_addr_t paddr;
 989                 /*
 990                  * The pending pages have to be at least 64kB aligned,
 991                  * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
 992                  */
 993                 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
 994                                         get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
 995                 if (!pend_page) {
 996                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
 997                                smp_processor_id());
 998                         return;
 999                 }
1000
1001                 /* Make sure the GIC will observe the zero-ed page */
1002                 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1003
1004                 paddr = page_to_phys(pend_page);
1005                 pr_info("CPU%d: using LPI pending table @%pa\n",
1006                         smp_processor_id(), &paddr);
1007                 gic_data_rdist()->pend_page = pend_page;
1008         }
1009
1010         /* Disable LPIs */
1011         val = readl_relaxed(rbase + GICR_CTLR);
1012         val &= ~GICR_CTLR_ENABLE_LPIS;
1013         writel_relaxed(val, rbase + GICR_CTLR);
1014
1015         /*
1016          * Make sure any change to the table is observable by the GIC.
1017          */
1018         dsb(sy);
1019
1020         /* set PROPBASE */
1021         val = (page_to_phys(gic_rdists->prop_page) |
1022                GICR_PROPBASER_InnerShareable |
1023                GICR_PROPBASER_WaWb |
1024                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1025
1026         writeq_relaxed(val, rbase + GICR_PROPBASER);
1027         tmp = readq_relaxed(rbase + GICR_PROPBASER);
1028
1029         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1030                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1031                         /*
1032                          * The HW reports non-shareable, we must
1033                          * remove the cacheability attributes as
1034                          * well.
1035                          */
1036                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1037                                  GICR_PROPBASER_CACHEABILITY_MASK);
1038                         val |= GICR_PROPBASER_nC;
1039                         writeq_relaxed(val, rbase + GICR_PROPBASER);
1040                 }
1041                 pr_info_once("GIC: using cache flushing for LPI property table\n");
1042                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1043         }
1044
1045         /* set PENDBASE */
1046         val = (page_to_phys(pend_page) |
1047                GICR_PENDBASER_InnerShareable |
1048                GICR_PENDBASER_WaWb);
1049
1050         writeq_relaxed(val, rbase + GICR_PENDBASER);
1051         tmp = readq_relaxed(rbase + GICR_PENDBASER);
1052
1053         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1054                 /*
1055                  * The HW reports non-shareable, we must remove the
1056                  * cacheability attributes as well.
1057                  */
1058                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1059                          GICR_PENDBASER_CACHEABILITY_MASK);
1060                 val |= GICR_PENDBASER_nC;
1061                 writeq_relaxed(val, rbase + GICR_PENDBASER);
1062         }
1063
1064         /* Enable LPIs */
1065         val = readl_relaxed(rbase + GICR_CTLR);
1066         val |= GICR_CTLR_ENABLE_LPIS;
1067         writel_relaxed(val, rbase + GICR_CTLR);
1068
1069         /* Make sure the GIC has seen the above */
1070         dsb(sy);
1071 }
1072
1073 static void its_cpu_init_collection(void)
1074 {
1075         struct its_node *its;
1076         int cpu;
1077
1078         spin_lock(&its_lock);
1079         cpu = smp_processor_id();
1080
1081         list_for_each_entry(its, &its_nodes, entry) {
1082                 u64 target;
1083
1084                 /*
1085                  * We now have to bind each collection to its target
1086                  * redistributor.
1087                  */
1088                 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1089                         /*
1090                          * This ITS wants the physical address of the
1091                          * redistributor.
1092                          */
1093                         target = gic_data_rdist()->phys_base;
1094                 } else {
1095                         /*
1096                          * This ITS wants a linear CPU number.
1097                          */
1098                         target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1099                         target = GICR_TYPER_CPU_NUMBER(target) << 16;
1100                 }
1101
1102                 /* Perform collection mapping */
1103                 its->collections[cpu].target_address = target;
1104                 its->collections[cpu].col_id = cpu;
1105
1106                 its_send_mapc(its, &its->collections[cpu], 1);
1107                 its_send_invall(its, &its->collections[cpu]);
1108         }
1109
1110         spin_unlock(&its_lock);
1111 }
1112
1113 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1114 {
1115         struct its_device *its_dev = NULL, *tmp;
1116         unsigned long flags;
1117
1118         raw_spin_lock_irqsave(&its->lock, flags);
1119
1120         list_for_each_entry(tmp, &its->its_device_list, entry) {
1121                 if (tmp->device_id == dev_id) {
1122                         its_dev = tmp;
1123                         break;
1124                 }
1125         }
1126
1127         raw_spin_unlock_irqrestore(&its->lock, flags);
1128
1129         return its_dev;
1130 }
1131
1132 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1133                                             int nvecs)
1134 {
1135         struct its_device *dev;
1136         unsigned long *lpi_map;
1137         unsigned long flags;
1138         u16 *col_map = NULL;
1139         void *itt;
1140         int lpi_base;
1141         int nr_lpis;
1142         int nr_ites;
1143         int sz;
1144
1145         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1146         /*
1147          * At least one bit of EventID is being used, hence a minimum
1148          * of two entries. No, the architecture doesn't let you
1149          * express an ITT with a single entry.
1150          */
1151         nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1152         sz = nr_ites * its->ite_size;
1153         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1154         itt = kzalloc(sz, GFP_KERNEL);
1155         lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1156         if (lpi_map)
1157                 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1158
1159         if (!dev || !itt || !lpi_map || !col_map) {
1160                 kfree(dev);
1161                 kfree(itt);
1162                 kfree(lpi_map);
1163                 kfree(col_map);
1164                 return NULL;
1165         }
1166
1167         __flush_dcache_area(itt, sz);
1168
1169         dev->its = its;
1170         dev->itt = itt;
1171         dev->nr_ites = nr_ites;
1172         dev->event_map.lpi_map = lpi_map;
1173         dev->event_map.col_map = col_map;
1174         dev->event_map.lpi_base = lpi_base;
1175         dev->event_map.nr_lpis = nr_lpis;
1176         dev->device_id = dev_id;
1177         INIT_LIST_HEAD(&dev->entry);
1178
1179         raw_spin_lock_irqsave(&its->lock, flags);
1180         list_add(&dev->entry, &its->its_device_list);
1181         raw_spin_unlock_irqrestore(&its->lock, flags);
1182
1183         /* Map device to its ITT */
1184         its_send_mapd(dev, 1);
1185
1186         return dev;
1187 }
1188
1189 static void its_free_device(struct its_device *its_dev)
1190 {
1191         unsigned long flags;
1192
1193         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1194         list_del(&its_dev->entry);
1195         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1196         kfree(its_dev->itt);
1197         kfree(its_dev);
1198 }
1199
1200 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1201 {
1202         int idx;
1203
1204         idx = find_first_zero_bit(dev->event_map.lpi_map,
1205                                   dev->event_map.nr_lpis);
1206         if (idx == dev->event_map.nr_lpis)
1207                 return -ENOSPC;
1208
1209         *hwirq = dev->event_map.lpi_base + idx;
1210         set_bit(idx, dev->event_map.lpi_map);
1211
1212         return 0;
1213 }
1214
1215 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1216                            int nvec, msi_alloc_info_t *info)
1217 {
1218         struct its_node *its;
1219         struct its_device *its_dev;
1220         struct msi_domain_info *msi_info;
1221         u32 dev_id;
1222
1223         /*
1224          * We ignore "dev" entierely, and rely on the dev_id that has
1225          * been passed via the scratchpad. This limits this domain's
1226          * usefulness to upper layers that definitely know that they
1227          * are built on top of the ITS.
1228          */
1229         dev_id = info->scratchpad[0].ul;
1230
1231         msi_info = msi_get_domain_info(domain);
1232         its = msi_info->data;
1233
1234         its_dev = its_find_device(its, dev_id);
1235         if (its_dev) {
1236                 /*
1237                  * We already have seen this ID, probably through
1238                  * another alias (PCI bridge of some sort). No need to
1239                  * create the device.
1240                  */
1241                 pr_debug("Reusing ITT for devID %x\n", dev_id);
1242                 goto out;
1243         }
1244
1245         its_dev = its_create_device(its, dev_id, nvec);
1246         if (!its_dev)
1247                 return -ENOMEM;
1248
1249         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1250 out:
1251         info->scratchpad[0].ptr = its_dev;
1252         return 0;
1253 }
1254
1255 static struct msi_domain_ops its_msi_domain_ops = {
1256         .msi_prepare    = its_msi_prepare,
1257 };
1258
1259 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1260                                     unsigned int virq,
1261                                     irq_hw_number_t hwirq)
1262 {
1263         struct irq_fwspec fwspec;
1264
1265         if (irq_domain_get_of_node(domain->parent)) {
1266                 fwspec.fwnode = domain->parent->fwnode;
1267                 fwspec.param_count = 3;
1268                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1269                 fwspec.param[1] = hwirq;
1270                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1271         } else {
1272                 return -EINVAL;
1273         }
1274
1275         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1276 }
1277
1278 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1279                                 unsigned int nr_irqs, void *args)
1280 {
1281         msi_alloc_info_t *info = args;
1282         struct its_device *its_dev = info->scratchpad[0].ptr;
1283         irq_hw_number_t hwirq;
1284         int err;
1285         int i;
1286
1287         for (i = 0; i < nr_irqs; i++) {
1288                 err = its_alloc_device_irq(its_dev, &hwirq);
1289                 if (err)
1290                         return err;
1291
1292                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1293                 if (err)
1294                         return err;
1295
1296                 irq_domain_set_hwirq_and_chip(domain, virq + i,
1297                                               hwirq, &its_irq_chip, its_dev);
1298                 pr_debug("ID:%d pID:%d vID:%d\n",
1299                          (int)(hwirq - its_dev->event_map.lpi_base),
1300                          (int) hwirq, virq + i);
1301         }
1302
1303         return 0;
1304 }
1305
1306 static void its_irq_domain_activate(struct irq_domain *domain,
1307                                     struct irq_data *d)
1308 {
1309         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1310         u32 event = its_get_event_id(d);
1311
1312         /* Bind the LPI to the first possible CPU */
1313         its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1314
1315         /* Map the GIC IRQ and event to the device */
1316         its_send_mapvi(its_dev, d->hwirq, event);
1317 }
1318
1319 static void its_irq_domain_deactivate(struct irq_domain *domain,
1320                                       struct irq_data *d)
1321 {
1322         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1323         u32 event = its_get_event_id(d);
1324
1325         /* Stop the delivery of interrupts */
1326         its_send_discard(its_dev, event);
1327 }
1328
1329 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1330                                 unsigned int nr_irqs)
1331 {
1332         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1333         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1334         int i;
1335
1336         for (i = 0; i < nr_irqs; i++) {
1337                 struct irq_data *data = irq_domain_get_irq_data(domain,
1338                                                                 virq + i);
1339                 u32 event = its_get_event_id(data);
1340
1341                 /* Mark interrupt index as unused */
1342                 clear_bit(event, its_dev->event_map.lpi_map);
1343
1344                 /* Nuke the entry in the domain */
1345                 irq_domain_reset_irq_data(data);
1346         }
1347
1348         /* If all interrupts have been freed, start mopping the floor */
1349         if (bitmap_empty(its_dev->event_map.lpi_map,
1350                          its_dev->event_map.nr_lpis)) {
1351                 its_lpi_free(&its_dev->event_map);
1352
1353                 /* Unmap device/itt */
1354                 its_send_mapd(its_dev, 0);
1355                 its_free_device(its_dev);
1356         }
1357
1358         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1359 }
1360
1361 static const struct irq_domain_ops its_domain_ops = {
1362         .alloc                  = its_irq_domain_alloc,
1363         .free                   = its_irq_domain_free,
1364         .activate               = its_irq_domain_activate,
1365         .deactivate             = its_irq_domain_deactivate,
1366 };
1367
1368 static int its_force_quiescent(void __iomem *base)
1369 {
1370         u32 count = 1000000;    /* 1s */
1371         u32 val;
1372
1373         val = readl_relaxed(base + GITS_CTLR);
1374         if (val & GITS_CTLR_QUIESCENT)
1375                 return 0;
1376
1377         /* Disable the generation of all interrupts to this ITS */
1378         val &= ~GITS_CTLR_ENABLE;
1379         writel_relaxed(val, base + GITS_CTLR);
1380
1381         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1382         while (1) {
1383                 val = readl_relaxed(base + GITS_CTLR);
1384                 if (val & GITS_CTLR_QUIESCENT)
1385                         return 0;
1386
1387                 count--;
1388                 if (!count)
1389                         return -EBUSY;
1390
1391                 cpu_relax();
1392                 udelay(1);
1393         }
1394 }
1395
1396 static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1397 {
1398         struct its_node *its = data;
1399
1400         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1401 }
1402
1403 static const struct gic_quirk its_quirks[] = {
1404 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1405         {
1406                 .desc   = "ITS: Cavium errata 22375, 24313",
1407                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
1408                 .mask   = 0xffff0fff,
1409                 .init   = its_enable_quirk_cavium_22375,
1410         },
1411 #endif
1412         {
1413         }
1414 };
1415
1416 static void its_enable_quirks(struct its_node *its)
1417 {
1418         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1419
1420         gic_enable_quirks(iidr, its_quirks, its);
1421 }
1422
1423 static int its_probe(struct device_node *node, struct irq_domain *parent)
1424 {
1425         struct resource res;
1426         struct its_node *its;
1427         void __iomem *its_base;
1428         struct irq_domain *inner_domain;
1429         u32 val;
1430         u64 baser, tmp;
1431         int err;
1432
1433         err = of_address_to_resource(node, 0, &res);
1434         if (err) {
1435                 pr_warn("%s: no regs?\n", node->full_name);
1436                 return -ENXIO;
1437         }
1438
1439         its_base = ioremap(res.start, resource_size(&res));
1440         if (!its_base) {
1441                 pr_warn("%s: unable to map registers\n", node->full_name);
1442                 return -ENOMEM;
1443         }
1444
1445         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1446         if (val != 0x30 && val != 0x40) {
1447                 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1448                 err = -ENODEV;
1449                 goto out_unmap;
1450         }
1451
1452         err = its_force_quiescent(its_base);
1453         if (err) {
1454                 pr_warn("%s: failed to quiesce, giving up\n",
1455                         node->full_name);
1456                 goto out_unmap;
1457         }
1458
1459         pr_info("ITS: %s\n", node->full_name);
1460
1461         its = kzalloc(sizeof(*its), GFP_KERNEL);
1462         if (!its) {
1463                 err = -ENOMEM;
1464                 goto out_unmap;
1465         }
1466
1467         raw_spin_lock_init(&its->lock);
1468         INIT_LIST_HEAD(&its->entry);
1469         INIT_LIST_HEAD(&its->its_device_list);
1470         its->base = its_base;
1471         its->phys_base = res.start;
1472         its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1473
1474         its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1475         if (!its->cmd_base) {
1476                 err = -ENOMEM;
1477                 goto out_free_its;
1478         }
1479         its->cmd_write = its->cmd_base;
1480
1481         its_enable_quirks(its);
1482
1483         err = its_alloc_tables(node->full_name, its);
1484         if (err)
1485                 goto out_free_cmd;
1486
1487         err = its_alloc_collections(its);
1488         if (err)
1489                 goto out_free_tables;
1490
1491         baser = (virt_to_phys(its->cmd_base)    |
1492                  GITS_CBASER_WaWb               |
1493                  GITS_CBASER_InnerShareable     |
1494                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1495                  GITS_CBASER_VALID);
1496
1497         writeq_relaxed(baser, its->base + GITS_CBASER);
1498         tmp = readq_relaxed(its->base + GITS_CBASER);
1499
1500         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1501                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1502                         /*
1503                          * The HW reports non-shareable, we must
1504                          * remove the cacheability attributes as
1505                          * well.
1506                          */
1507                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1508                                    GITS_CBASER_CACHEABILITY_MASK);
1509                         baser |= GITS_CBASER_nC;
1510                         writeq_relaxed(baser, its->base + GITS_CBASER);
1511                 }
1512                 pr_info("ITS: using cache flushing for cmd queue\n");
1513                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1514         }
1515
1516         writeq_relaxed(0, its->base + GITS_CWRITER);
1517         writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1518
1519         if (of_property_read_bool(node, "msi-controller")) {
1520                 struct msi_domain_info *info;
1521
1522                 info = kzalloc(sizeof(*info), GFP_KERNEL);
1523                 if (!info) {
1524                         err = -ENOMEM;
1525                         goto out_free_tables;
1526                 }
1527
1528                 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1529                 if (!inner_domain) {
1530                         err = -ENOMEM;
1531                         kfree(info);
1532                         goto out_free_tables;
1533                 }
1534
1535                 inner_domain->parent = parent;
1536                 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1537                 info->ops = &its_msi_domain_ops;
1538                 info->data = its;
1539                 inner_domain->host_data = info;
1540         }
1541
1542         spin_lock(&its_lock);
1543         list_add(&its->entry, &its_nodes);
1544         spin_unlock(&its_lock);
1545
1546         return 0;
1547
1548 out_free_tables:
1549         its_free_tables(its);
1550 out_free_cmd:
1551         kfree(its->cmd_base);
1552 out_free_its:
1553         kfree(its);
1554 out_unmap:
1555         iounmap(its_base);
1556         pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1557         return err;
1558 }
1559
1560 static bool gic_rdists_supports_plpis(void)
1561 {
1562         return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1563 }
1564
1565 int its_cpu_init(void)
1566 {
1567         if (!list_empty(&its_nodes)) {
1568                 if (!gic_rdists_supports_plpis()) {
1569                         pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1570                         return -ENXIO;
1571                 }
1572                 its_cpu_init_lpis();
1573                 its_cpu_init_collection();
1574         }
1575
1576         return 0;
1577 }
1578
1579 static struct of_device_id its_device_id[] = {
1580         {       .compatible     = "arm,gic-v3-its",     },
1581         {},
1582 };
1583
1584 int its_init(struct device_node *node, struct rdists *rdists,
1585              struct irq_domain *parent_domain)
1586 {
1587         struct device_node *np;
1588
1589         for (np = of_find_matching_node(node, its_device_id); np;
1590              np = of_find_matching_node(np, its_device_id)) {
1591                 its_probe(np, parent_domain);
1592         }
1593
1594         if (list_empty(&its_nodes)) {
1595                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1596                 return -ENXIO;
1597         }
1598
1599         gic_rdists = rdists;
1600         gic_root_node = node;
1601
1602         its_alloc_lpi_tables();
1603         its_lpi_init(rdists->id_bits);
1604
1605         return 0;
1606 }