drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include "mlx5_ib.h"
  36 #include "user.h"
  37
  38 /* not supported currently */
  39 static int wq_signature;
  40
  41 enum {
  42         MLX5_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  48         MLX5_IB_LINK_TYPE_IB            = 0,
  49         MLX5_IB_LINK_TYPE_ETH           = 1
  50 };
  51
  52 enum {
  53         MLX5_IB_SQ_STRIDE       = 6,
  54         MLX5_IB_CACHE_LINE_SIZE = 64,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  60         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  61         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  62         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  63         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  64         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  65         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  66         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  67         [IB_WR_FAST_REG_MR]                     = MLX5_OPCODE_UMR,
  68         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  69         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  70         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  71 };
  72
  73
  74 static int is_qp0(enum ib_qp_type qp_type)
  75 {
  76         return qp_type == IB_QPT_SMI;
  77 }
  78
  79 static int is_qp1(enum ib_qp_type qp_type)
  80 {
  81         return qp_type == IB_QPT_GSI;
  82 }
  83
  84 static int is_sqp(enum ib_qp_type qp_type)
  85 {
  86         return is_qp0(qp_type) || is_qp1(qp_type);
  87 }
  88
  89 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  90 {
  91         return mlx5_buf_offset(&qp->buf, offset);
  92 }
  93
  94 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
  95 {
  96         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
  97 }
  98
  99 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 100 {
 101         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 102 }
 103
 104 /**
 105  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 106  *
 107  * @qp: QP to copy from.
 108  * @send: copy from the send queue when non-zero, use the receive queue
 109  *        otherwise.
 110  * @wqe_index:  index to start copying from. For send work queues, the
 111  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 112  *              For receive work queue, it is the number of work queue
 113  *              element in the queue.
 114  * @buffer: destination buffer.
 115  * @length: maximum number of bytes to copy.
 116  *
 117  * Copies at least a single WQE, but may copy more data.
 118  *
 119  * Return: the number of bytes copied, or an error code.
 120  */
 121 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 122                           void *buffer, u32 length)
 123 {
 124         struct ib_device *ibdev = qp->ibqp.device;
 125         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 126         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 127         size_t offset;
 128         size_t wq_end;
 129         struct ib_umem *umem = qp->umem;
 130         u32 first_copy_length;
 131         int wqe_length;
 132         int ret;
 133
 134         if (wq->wqe_cnt == 0) {
 135                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 136                             qp->ibqp.qp_type);
 137                 return -EINVAL;
 138         }
 139
 140         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 141         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 142
 143         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 144                 return -EINVAL;
 145
 146         if (offset > umem->length ||
 147             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 148                 return -EINVAL;
 149
 150         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 151         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 152         if (ret)
 153                 return ret;
 154
 155         if (send) {
 156                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 157                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 158
 159                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 160         } else {
 161                 wqe_length = 1 << wq->wqe_shift;
 162         }
 163
 164         if (wqe_length <= first_copy_length)
 165                 return first_copy_length;
 166
 167         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 168                                 wqe_length - first_copy_length);
 169         if (ret)
 170                 return ret;
 171
 172         return wqe_length;
 173 }
 174
 175 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 176 {
 177         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 178         struct ib_event event;
 179
 180         if (type == MLX5_EVENT_TYPE_PATH_MIG)
 181                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 182
 183         if (ibqp->event_handler) {
 184                 event.device     = ibqp->device;
 185                 event.element.qp = ibqp;
 186                 switch (type) {
 187                 case MLX5_EVENT_TYPE_PATH_MIG:
 188                         event.event = IB_EVENT_PATH_MIG;
 189                         break;
 190                 case MLX5_EVENT_TYPE_COMM_EST:
 191                         event.event = IB_EVENT_COMM_EST;
 192                         break;
 193                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 194                         event.event = IB_EVENT_SQ_DRAINED;
 195                         break;
 196                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 197                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 198                         break;
 199                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 200                         event.event = IB_EVENT_QP_FATAL;
 201                         break;
 202                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 203                         event.event = IB_EVENT_PATH_MIG_ERR;
 204                         break;
 205                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 206                         event.event = IB_EVENT_QP_REQ_ERR;
 207                         break;
 208                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 209                         event.event = IB_EVENT_QP_ACCESS_ERR;
 210                         break;
 211                 default:
 212                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 213                         return;
 214                 }
 215
 216                 ibqp->event_handler(&event, ibqp->qp_context);
 217         }
 218 }
 219
 220 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 221                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 222 {
 223         int wqe_size;
 224         int wq_size;
 225
 226         /* Sanity check RQ size before proceeding */
 227         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 228                 return -EINVAL;
 229
 230         if (!has_rq) {
 231                 qp->rq.max_gs = 0;
 232                 qp->rq.wqe_cnt = 0;
 233                 qp->rq.wqe_shift = 0;
 234         } else {
 235                 if (ucmd) {
 236                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 237                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 238                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 239                         qp->rq.max_post = qp->rq.wqe_cnt;
 240                 } else {
 241                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 242                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 243                         wqe_size = roundup_pow_of_two(wqe_size);
 244                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 245                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 246                         qp->rq.wqe_cnt = wq_size / wqe_size;
 247                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 248                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 249                                             wqe_size,
 250                                             MLX5_CAP_GEN(dev->mdev,
 251                                                          max_wqe_sz_rq));
 252                                 return -EINVAL;
 253                         }
 254                         qp->rq.wqe_shift = ilog2(wqe_size);
 255                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 256                         qp->rq.max_post = qp->rq.wqe_cnt;
 257                 }
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int sq_overhead(enum ib_qp_type qp_type)
 264 {
 265         int size = 0;
 266
 267         switch (qp_type) {
 268         case IB_QPT_XRC_INI:
 269                 size += sizeof(struct mlx5_wqe_xrc_seg);
 270                 /* fall through */
 271         case IB_QPT_RC:
 272                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 273                         sizeof(struct mlx5_wqe_atomic_seg) +
 274                         sizeof(struct mlx5_wqe_raddr_seg);
 275                 break;
 276
 277         case IB_QPT_XRC_TGT:
 278                 return 0;
 279
 280         case IB_QPT_UC:
 281                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 282                         sizeof(struct mlx5_wqe_raddr_seg) +
 283                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 284                         sizeof(struct mlx5_mkey_seg);
 285                 break;
 286
 287         case IB_QPT_UD:
 288         case IB_QPT_SMI:
 289         case IB_QPT_GSI:
 290                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 291                         sizeof(struct mlx5_wqe_datagram_seg);
 292                 break;
 293
 294         case MLX5_IB_QPT_REG_UMR:
 295                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 296                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 297                         sizeof(struct mlx5_mkey_seg);
 298                 break;
 299
 300         default:
 301                 return -EINVAL;
 302         }
 303
 304         return size;
 305 }
 306
 307 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 308 {
 309         int inl_size = 0;
 310         int size;
 311
 312         size = sq_overhead(attr->qp_type);
 313         if (size < 0)
 314                 return size;
 315
 316         if (attr->cap.max_inline_data) {
 317                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 318                         attr->cap.max_inline_data;
 319         }
 320
 321         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 322         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 323             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 324                         return MLX5_SIG_WQE_SIZE;
 325         else
 326                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 327 }
 328
 329 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 330                         struct mlx5_ib_qp *qp)
 331 {
 332         int wqe_size;
 333         int wq_size;
 334
 335         if (!attr->cap.max_send_wr)
 336                 return 0;
 337
 338         wqe_size = calc_send_wqe(attr);
 339         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 340         if (wqe_size < 0)
 341                 return wqe_size;
 342
 343         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 344                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 345                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 346                 return -EINVAL;
 347         }
 348
 349         qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
 350                 sizeof(struct mlx5_wqe_inline_seg);
 351         attr->cap.max_inline_data = qp->max_inline_data;
 352
 353         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 354                 qp->signature_en = true;
 355
 356         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 357         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 358         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 359                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 360                             qp->sq.wqe_cnt,
 361                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 362                 return -ENOMEM;
 363         }
 364         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 365         qp->sq.max_gs = attr->cap.max_send_sge;
 366         qp->sq.max_post = wq_size / wqe_size;
 367         attr->cap.max_send_wr = qp->sq.max_post;
 368
 369         return wq_size;
 370 }
 371
 372 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 373                             struct mlx5_ib_qp *qp,
 374                             struct mlx5_ib_create_qp *ucmd)
 375 {
 376         int desc_sz = 1 << qp->sq.wqe_shift;
 377
 378         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 379                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 380                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 381                 return -EINVAL;
 382         }
 383
 384         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 385                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 386                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 387                 return -EINVAL;
 388         }
 389
 390         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 391
 392         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 393                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 394                              qp->sq.wqe_cnt,
 395                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 396                 return -EINVAL;
 397         }
 398
 399         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 400                 (qp->sq.wqe_cnt << 6);
 401
 402         return 0;
 403 }
 404
 405 static int qp_has_rq(struct ib_qp_init_attr *attr)
 406 {
 407         if (attr->qp_type == IB_QPT_XRC_INI ||
 408             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 409             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 410             !attr->cap.max_recv_wr)
 411                 return 0;
 412
 413         return 1;
 414 }
 415
 416 static int first_med_uuar(void)
 417 {
 418         return 1;
 419 }
 420
 421 static int next_uuar(int n)
 422 {
 423         n++;
 424
 425         while (((n % 4) & 2))
 426                 n++;
 427
 428         return n;
 429 }
 430
 431 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 432 {
 433         int n;
 434
 435         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 436                 uuari->num_low_latency_uuars - 1;
 437
 438         return n >= 0 ? n : 0;
 439 }
 440
 441 static int max_uuari(struct mlx5_uuar_info *uuari)
 442 {
 443         return uuari->num_uars * 4;
 444 }
 445
 446 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 447 {
 448         int med;
 449         int i;
 450         int t;
 451
 452         med = num_med_uuar(uuari);
 453         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 454                 t++;
 455                 if (t == med)
 456                         return next_uuar(i);
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 463 {
 464         int i;
 465
 466         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 467                 if (!test_bit(i, uuari->bitmap)) {
 468                         set_bit(i, uuari->bitmap);
 469                         uuari->count[i]++;
 470                         return i;
 471                 }
 472         }
 473
 474         return -ENOMEM;
 475 }
 476
 477 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 478 {
 479         int minidx = first_med_uuar();
 480         int i;
 481
 482         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 483                 if (uuari->count[i] < uuari->count[minidx])
 484                         minidx = i;
 485         }
 486
 487         uuari->count[minidx]++;
 488         return minidx;
 489 }
 490
 491 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 492                       enum mlx5_ib_latency_class lat)
 493 {
 494         int uuarn = -EINVAL;
 495
 496         mutex_lock(&uuari->lock);
 497         switch (lat) {
 498         case MLX5_IB_LATENCY_CLASS_LOW:
 499                 uuarn = 0;
 500                 uuari->count[uuarn]++;
 501                 break;
 502
 503         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 504                 if (uuari->ver < 2)
 505                         uuarn = -ENOMEM;
 506                 else
 507                         uuarn = alloc_med_class_uuar(uuari);
 508                 break;
 509
 510         case MLX5_IB_LATENCY_CLASS_HIGH:
 511                 if (uuari->ver < 2)
 512                         uuarn = -ENOMEM;
 513                 else
 514                         uuarn = alloc_high_class_uuar(uuari);
 515                 break;
 516
 517         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 518                 uuarn = 2;
 519                 break;
 520         }
 521         mutex_unlock(&uuari->lock);
 522
 523         return uuarn;
 524 }
 525
 526 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 527 {
 528         clear_bit(uuarn, uuari->bitmap);
 529         --uuari->count[uuarn];
 530 }
 531
 532 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 533 {
 534         clear_bit(uuarn, uuari->bitmap);
 535         --uuari->count[uuarn];
 536 }
 537
 538 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 539 {
 540         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 541         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 542
 543         mutex_lock(&uuari->lock);
 544         if (uuarn == 0) {
 545                 --uuari->count[uuarn];
 546                 goto out;
 547         }
 548
 549         if (uuarn < high_uuar) {
 550                 free_med_class_uuar(uuari, uuarn);
 551                 goto out;
 552         }
 553
 554         free_high_class_uuar(uuari, uuarn);
 555
 556 out:
 557         mutex_unlock(&uuari->lock);
 558 }
 559
 560 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 561 {
 562         switch (state) {
 563         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 564         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 565         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 566         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 567         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 568         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 569         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 570         default:                return -1;
 571         }
 572 }
 573
 574 static int to_mlx5_st(enum ib_qp_type type)
 575 {
 576         switch (type) {
 577         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 578         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 579         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 580         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 581         case IB_QPT_XRC_INI:
 582         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 583         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 584         case IB_QPT_GSI:                return MLX5_QP_ST_QP1;
 585         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 586         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 587         case IB_QPT_RAW_PACKET:
 588         case IB_QPT_MAX:
 589         default:                return -EINVAL;
 590         }
 591 }
 592
 593 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 594 {
 595         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 596 }
 597
 598 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 599                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 600                           struct mlx5_create_qp_mbox_in **in,
 601                           struct mlx5_ib_create_qp_resp *resp, int *inlen)
 602 {
 603         struct mlx5_ib_ucontext *context;
 604         struct mlx5_ib_create_qp ucmd;
 605         int page_shift = 0;
 606         int uar_index;
 607         int npages;
 608         u32 offset = 0;
 609         int uuarn;
 610         int ncont = 0;
 611         int err;
 612
 613         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 614         if (err) {
 615                 mlx5_ib_dbg(dev, "copy failed\n");
 616                 return err;
 617         }
 618
 619         context = to_mucontext(pd->uobject->context);
 620         /*
 621          * TBD: should come from the verbs when we have the API
 622          */
 623         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 624         if (uuarn < 0) {
 625                 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 626                 mlx5_ib_dbg(dev, "reverting to medium latency\n");
 627                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 628                 if (uuarn < 0) {
 629                         mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 630                         mlx5_ib_dbg(dev, "reverting to high latency\n");
 631                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 632                         if (uuarn < 0) {
 633                                 mlx5_ib_warn(dev, "uuar allocation failed\n");
 634                                 return uuarn;
 635                         }
 636                 }
 637         }
 638
 639         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 640         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 641
 642         qp->rq.offset = 0;
 643         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 644         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 645
 646         err = set_user_buf_size(dev, qp, &ucmd);
 647         if (err)
 648                 goto err_uuar;
 649
 650         if (ucmd.buf_addr && qp->buf_size) {
 651                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 652                                        qp->buf_size, 0, 0);
 653                 if (IS_ERR(qp->umem)) {
 654                         mlx5_ib_dbg(dev, "umem_get failed\n");
 655                         err = PTR_ERR(qp->umem);
 656                         goto err_uuar;
 657                 }
 658         } else {
 659                 qp->umem = NULL;
 660         }
 661
 662         if (qp->umem) {
 663                 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
 664                                    &ncont, NULL);
 665                 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
 666                 if (err) {
 667                         mlx5_ib_warn(dev, "bad offset\n");
 668                         goto err_umem;
 669                 }
 670                 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
 671                             ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
 672         }
 673
 674         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 675         *in = mlx5_vzalloc(*inlen);
 676         if (!*in) {
 677                 err = -ENOMEM;
 678                 goto err_umem;
 679         }
 680         if (qp->umem)
 681                 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
 682         (*in)->ctx.log_pg_sz_remote_qpn =
 683                 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 684         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 685
 686         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 687         resp->uuar_index = uuarn;
 688         qp->uuarn = uuarn;
 689
 690         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 691         if (err) {
 692                 mlx5_ib_dbg(dev, "map failed\n");
 693                 goto err_free;
 694         }
 695
 696         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 697         if (err) {
 698                 mlx5_ib_dbg(dev, "copy failed\n");
 699                 goto err_unmap;
 700         }
 701         qp->create_type = MLX5_QP_USER;
 702
 703         return 0;
 704
 705 err_unmap:
 706         mlx5_ib_db_unmap_user(context, &qp->db);
 707
 708 err_free:
 709         kvfree(*in);
 710
 711 err_umem:
 712         if (qp->umem)
 713                 ib_umem_release(qp->umem);
 714
 715 err_uuar:
 716         free_uuar(&context->uuari, uuarn);
 717         return err;
 718 }
 719
 720 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
 721 {
 722         struct mlx5_ib_ucontext *context;
 723
 724         context = to_mucontext(pd->uobject->context);
 725         mlx5_ib_db_unmap_user(context, &qp->db);
 726         if (qp->umem)
 727                 ib_umem_release(qp->umem);
 728         free_uuar(&context->uuari, qp->uuarn);
 729 }
 730
 731 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 732                             struct ib_qp_init_attr *init_attr,
 733                             struct mlx5_ib_qp *qp,
 734                             struct mlx5_create_qp_mbox_in **in, int *inlen)
 735 {
 736         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 737         struct mlx5_uuar_info *uuari;
 738         int uar_index;
 739         int uuarn;
 740         int err;
 741
 742         uuari = &dev->mdev->priv.uuari;
 743         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
 744                 return -EINVAL;
 745
 746         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 747                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 748
 749         uuarn = alloc_uuar(uuari, lc);
 750         if (uuarn < 0) {
 751                 mlx5_ib_dbg(dev, "\n");
 752                 return -ENOMEM;
 753         }
 754
 755         qp->bf = &uuari->bfs[uuarn];
 756         uar_index = qp->bf->uar->index;
 757
 758         err = calc_sq_size(dev, init_attr, qp);
 759         if (err < 0) {
 760                 mlx5_ib_dbg(dev, "err %d\n", err);
 761                 goto err_uuar;
 762         }
 763
 764         qp->rq.offset = 0;
 765         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 766         qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 767
 768         err = mlx5_buf_alloc(dev->mdev, qp->buf_size, &qp->buf);
 769         if (err) {
 770                 mlx5_ib_dbg(dev, "err %d\n", err);
 771                 goto err_uuar;
 772         }
 773
 774         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 775         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 776         *in = mlx5_vzalloc(*inlen);
 777         if (!*in) {
 778                 err = -ENOMEM;
 779                 goto err_buf;
 780         }
 781         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 782         (*in)->ctx.log_pg_sz_remote_qpn =
 783                 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 784         /* Set "fast registration enabled" for all kernel QPs */
 785         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 786         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 787
 788         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 789
 790         err = mlx5_db_alloc(dev->mdev, &qp->db);
 791         if (err) {
 792                 mlx5_ib_dbg(dev, "err %d\n", err);
 793                 goto err_free;
 794         }
 795
 796         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 797         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 798         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 799         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 800         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 801
 802         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 803             !qp->sq.w_list || !qp->sq.wqe_head) {
 804                 err = -ENOMEM;
 805                 goto err_wrid;
 806         }
 807         qp->create_type = MLX5_QP_KERNEL;
 808
 809         return 0;
 810
 811 err_wrid:
 812         mlx5_db_free(dev->mdev, &qp->db);
 813         kfree(qp->sq.wqe_head);
 814         kfree(qp->sq.w_list);
 815         kfree(qp->sq.wrid);
 816         kfree(qp->sq.wr_data);
 817         kfree(qp->rq.wrid);
 818
 819 err_free:
 820         kvfree(*in);
 821
 822 err_buf:
 823         mlx5_buf_free(dev->mdev, &qp->buf);
 824
 825 err_uuar:
 826         free_uuar(&dev->mdev->priv.uuari, uuarn);
 827         return err;
 828 }
 829
 830 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 831 {
 832         mlx5_db_free(dev->mdev, &qp->db);
 833         kfree(qp->sq.wqe_head);
 834         kfree(qp->sq.w_list);
 835         kfree(qp->sq.wrid);
 836         kfree(qp->sq.wr_data);
 837         kfree(qp->rq.wrid);
 838         mlx5_buf_free(dev->mdev, &qp->buf);
 839         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 840 }
 841
 842 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 843 {
 844         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 845             (attr->qp_type == IB_QPT_XRC_INI))
 846                 return cpu_to_be32(MLX5_SRQ_RQ);
 847         else if (!qp->has_rq)
 848                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 849         else
 850                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 851 }
 852
 853 static int is_connected(enum ib_qp_type qp_type)
 854 {
 855         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 856                 return 1;
 857
 858         return 0;
 859 }
 860
 861 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 862                             struct ib_qp_init_attr *init_attr,
 863                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
 864 {
 865         struct mlx5_ib_resources *devr = &dev->devr;
 866         struct mlx5_core_dev *mdev = dev->mdev;
 867         struct mlx5_ib_create_qp_resp resp;
 868         struct mlx5_create_qp_mbox_in *in;
 869         struct mlx5_ib_create_qp ucmd;
 870         int inlen = sizeof(*in);
 871         int err;
 872
 873         mlx5_ib_odp_create_qp(qp);
 874
 875         mutex_init(&qp->mutex);
 876         spin_lock_init(&qp->sq.lock);
 877         spin_lock_init(&qp->rq.lock);
 878
 879         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
 880                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
 881                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
 882                         return -EINVAL;
 883                 } else {
 884                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 885                 }
 886         }
 887
 888         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 889                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
 890
 891         if (pd && pd->uobject) {
 892                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
 893                         mlx5_ib_dbg(dev, "copy failed\n");
 894                         return -EFAULT;
 895                 }
 896
 897                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
 898                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
 899         } else {
 900                 qp->wq_sig = !!wq_signature;
 901         }
 902
 903         qp->has_rq = qp_has_rq(init_attr);
 904         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
 905                           qp, (pd && pd->uobject) ? &ucmd : NULL);
 906         if (err) {
 907                 mlx5_ib_dbg(dev, "err %d\n", err);
 908                 return err;
 909         }
 910
 911         if (pd) {
 912                 if (pd->uobject) {
 913                         __u32 max_wqes =
 914                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 915                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
 916                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
 917                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
 918                                 mlx5_ib_dbg(dev, "invalid rq params\n");
 919                                 return -EINVAL;
 920                         }
 921                         if (ucmd.sq_wqe_count > max_wqes) {
 922                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
 923                                             ucmd.sq_wqe_count, max_wqes);
 924                                 return -EINVAL;
 925                         }
 926                         err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
 927                         if (err)
 928                                 mlx5_ib_dbg(dev, "err %d\n", err);
 929                 } else {
 930                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
 931                         if (err)
 932                                 mlx5_ib_dbg(dev, "err %d\n", err);
 933                         else
 934                                 qp->pa_lkey = to_mpd(pd)->pa_lkey;
 935                 }
 936
 937                 if (err)
 938                         return err;
 939         } else {
 940                 in = mlx5_vzalloc(sizeof(*in));
 941                 if (!in)
 942                         return -ENOMEM;
 943
 944                 qp->create_type = MLX5_QP_EMPTY;
 945         }
 946
 947         if (is_sqp(init_attr->qp_type))
 948                 qp->port = init_attr->port_num;
 949
 950         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
 951                                     MLX5_QP_PM_MIGRATED << 11);
 952
 953         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
 954                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
 955         else
 956                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
 957
 958         if (qp->wq_sig)
 959                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
 960
 961         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
 962                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
 963
 964         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
 965                 int rcqe_sz;
 966                 int scqe_sz;
 967
 968                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
 969                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
 970
 971                 if (rcqe_sz == 128)
 972                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
 973                 else
 974                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
 975
 976                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
 977                         if (scqe_sz == 128)
 978                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
 979                         else
 980                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
 981                 }
 982         }
 983
 984         if (qp->rq.wqe_cnt) {
 985                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
 986                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
 987         }
 988
 989         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
 990
 991         if (qp->sq.wqe_cnt)
 992                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
 993         else
 994                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
 995
 996         /* Set default resources */
 997         switch (init_attr->qp_type) {
 998         case IB_QPT_XRC_TGT:
 999                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1000                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1001                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1002                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1003                 break;
1004         case IB_QPT_XRC_INI:
1005                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1006                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1007                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1008                 break;
1009         default:
1010                 if (init_attr->srq) {
1011                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1012                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1013                 } else {
1014                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1015                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1016                 }
1017         }
1018
1019         if (init_attr->send_cq)
1020                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1021
1022         if (init_attr->recv_cq)
1023                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1024
1025         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1026
1027         err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen);
1028         if (err) {
1029                 mlx5_ib_dbg(dev, "create qp failed\n");
1030                 goto err_create;
1031         }
1032
1033         kvfree(in);
1034         /* Hardware wants QPN written in big-endian order (after
1035          * shifting) for send doorbell.  Precompute this value to save
1036          * a little bit when posting sends.
1037          */
1038         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1039
1040         qp->mqp.event = mlx5_ib_qp_event;
1041
1042         return 0;
1043
1044 err_create:
1045         if (qp->create_type == MLX5_QP_USER)
1046                 destroy_qp_user(pd, qp);
1047         else if (qp->create_type == MLX5_QP_KERNEL)
1048                 destroy_qp_kernel(dev, qp);
1049
1050         kvfree(in);
1051         return err;
1052 }
1053
1054 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1055         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1056 {
1057         if (send_cq) {
1058                 if (recv_cq) {
1059                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1060                                 spin_lock_irq(&send_cq->lock);
1061                                 spin_lock_nested(&recv_cq->lock,
1062                                                  SINGLE_DEPTH_NESTING);
1063                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1064                                 spin_lock_irq(&send_cq->lock);
1065                                 __acquire(&recv_cq->lock);
1066                         } else {
1067                                 spin_lock_irq(&recv_cq->lock);
1068                                 spin_lock_nested(&send_cq->lock,
1069                                                  SINGLE_DEPTH_NESTING);
1070                         }
1071                 } else {
1072                         spin_lock_irq(&send_cq->lock);
1073                         __acquire(&recv_cq->lock);
1074                 }
1075         } else if (recv_cq) {
1076                 spin_lock_irq(&recv_cq->lock);
1077                 __acquire(&send_cq->lock);
1078         } else {
1079                 __acquire(&send_cq->lock);
1080                 __acquire(&recv_cq->lock);
1081         }
1082 }
1083
1084 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1085         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1086 {
1087         if (send_cq) {
1088                 if (recv_cq) {
1089                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1090                                 spin_unlock(&recv_cq->lock);
1091                                 spin_unlock_irq(&send_cq->lock);
1092                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1093                                 __release(&recv_cq->lock);
1094                                 spin_unlock_irq(&send_cq->lock);
1095                         } else {
1096                                 spin_unlock(&send_cq->lock);
1097                                 spin_unlock_irq(&recv_cq->lock);
1098                         }
1099                 } else {
1100                         __release(&recv_cq->lock);
1101                         spin_unlock_irq(&send_cq->lock);
1102                 }
1103         } else if (recv_cq) {
1104                 __release(&send_cq->lock);
1105                 spin_unlock_irq(&recv_cq->lock);
1106         } else {
1107                 __release(&recv_cq->lock);
1108                 __release(&send_cq->lock);
1109         }
1110 }
1111
1112 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1113 {
1114         return to_mpd(qp->ibqp.pd);
1115 }
1116
1117 static void get_cqs(struct mlx5_ib_qp *qp,
1118                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1119 {
1120         switch (qp->ibqp.qp_type) {
1121         case IB_QPT_XRC_TGT:
1122                 *send_cq = NULL;
1123                 *recv_cq = NULL;
1124                 break;
1125         case MLX5_IB_QPT_REG_UMR:
1126         case IB_QPT_XRC_INI:
1127                 *send_cq = to_mcq(qp->ibqp.send_cq);
1128                 *recv_cq = NULL;
1129                 break;
1130
1131         case IB_QPT_SMI:
1132         case IB_QPT_GSI:
1133         case IB_QPT_RC:
1134         case IB_QPT_UC:
1135         case IB_QPT_UD:
1136         case IB_QPT_RAW_IPV6:
1137         case IB_QPT_RAW_ETHERTYPE:
1138                 *send_cq = to_mcq(qp->ibqp.send_cq);
1139                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1140                 break;
1141
1142         case IB_QPT_RAW_PACKET:
1143         case IB_QPT_MAX:
1144         default:
1145                 *send_cq = NULL;
1146                 *recv_cq = NULL;
1147                 break;
1148         }
1149 }
1150
1151 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1152 {
1153         struct mlx5_ib_cq *send_cq, *recv_cq;
1154         struct mlx5_modify_qp_mbox_in *in;
1155         int err;
1156
1157         in = kzalloc(sizeof(*in), GFP_KERNEL);
1158         if (!in)
1159                 return;
1160
1161         if (qp->state != IB_QPS_RESET) {
1162                 mlx5_ib_qp_disable_pagefaults(qp);
1163                 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state),
1164                                         MLX5_QP_STATE_RST, in, 0, &qp->mqp))
1165                         mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1166                                      qp->mqp.qpn);
1167         }
1168
1169         get_cqs(qp, &send_cq, &recv_cq);
1170
1171         if (qp->create_type == MLX5_QP_KERNEL) {
1172                 mlx5_ib_lock_cqs(send_cq, recv_cq);
1173                 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1174                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1175                 if (send_cq != recv_cq)
1176                         __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1177                 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1178         }
1179
1180         err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp);
1181         if (err)
1182                 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1183         kfree(in);
1184
1185
1186         if (qp->create_type == MLX5_QP_KERNEL)
1187                 destroy_qp_kernel(dev, qp);
1188         else if (qp->create_type == MLX5_QP_USER)
1189                 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1190 }
1191
1192 static const char *ib_qp_type_str(enum ib_qp_type type)
1193 {
1194         switch (type) {
1195         case IB_QPT_SMI:
1196                 return "IB_QPT_SMI";
1197         case IB_QPT_GSI:
1198                 return "IB_QPT_GSI";
1199         case IB_QPT_RC:
1200                 return "IB_QPT_RC";
1201         case IB_QPT_UC:
1202                 return "IB_QPT_UC";
1203         case IB_QPT_UD:
1204                 return "IB_QPT_UD";
1205         case IB_QPT_RAW_IPV6:
1206                 return "IB_QPT_RAW_IPV6";
1207         case IB_QPT_RAW_ETHERTYPE:
1208                 return "IB_QPT_RAW_ETHERTYPE";
1209         case IB_QPT_XRC_INI:
1210                 return "IB_QPT_XRC_INI";
1211         case IB_QPT_XRC_TGT:
1212                 return "IB_QPT_XRC_TGT";
1213         case IB_QPT_RAW_PACKET:
1214                 return "IB_QPT_RAW_PACKET";
1215         case MLX5_IB_QPT_REG_UMR:
1216                 return "MLX5_IB_QPT_REG_UMR";
1217         case IB_QPT_MAX:
1218         default:
1219                 return "Invalid QP type";
1220         }
1221 }
1222
1223 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1224                                 struct ib_qp_init_attr *init_attr,
1225                                 struct ib_udata *udata)
1226 {
1227         struct mlx5_ib_dev *dev;
1228         struct mlx5_ib_qp *qp;
1229         u16 xrcdn = 0;
1230         int err;
1231
1232         if (pd) {
1233                 dev = to_mdev(pd->device);
1234         } else {
1235                 /* being cautious here */
1236                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1237                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1238                         pr_warn("%s: no PD for transport %s\n", __func__,
1239                                 ib_qp_type_str(init_attr->qp_type));
1240                         return ERR_PTR(-EINVAL);
1241                 }
1242                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1243         }
1244
1245         switch (init_attr->qp_type) {
1246         case IB_QPT_XRC_TGT:
1247         case IB_QPT_XRC_INI:
1248                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
1249                         mlx5_ib_dbg(dev, "XRC not supported\n");
1250                         return ERR_PTR(-ENOSYS);
1251                 }
1252                 init_attr->recv_cq = NULL;
1253                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1254                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1255                         init_attr->send_cq = NULL;
1256                 }
1257
1258                 /* fall through */
1259         case IB_QPT_RC:
1260         case IB_QPT_UC:
1261         case IB_QPT_UD:
1262         case IB_QPT_SMI:
1263         case IB_QPT_GSI:
1264         case MLX5_IB_QPT_REG_UMR:
1265                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1266                 if (!qp)
1267                         return ERR_PTR(-ENOMEM);
1268
1269                 err = create_qp_common(dev, pd, init_attr, udata, qp);
1270                 if (err) {
1271                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
1272                         kfree(qp);
1273                         return ERR_PTR(err);
1274                 }
1275
1276                 if (is_qp0(init_attr->qp_type))
1277                         qp->ibqp.qp_num = 0;
1278                 else if (is_qp1(init_attr->qp_type))
1279                         qp->ibqp.qp_num = 1;
1280                 else
1281                         qp->ibqp.qp_num = qp->mqp.qpn;
1282
1283                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1284                             qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1285                             to_mcq(init_attr->send_cq)->mcq.cqn);
1286
1287                 qp->xrcdn = xrcdn;
1288
1289                 break;
1290
1291         case IB_QPT_RAW_IPV6:
1292         case IB_QPT_RAW_ETHERTYPE:
1293         case IB_QPT_RAW_PACKET:
1294         case IB_QPT_MAX:
1295         default:
1296                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1297                             init_attr->qp_type);
1298                 /* Don't support raw QPs */
1299                 return ERR_PTR(-EINVAL);
1300         }
1301
1302         return &qp->ibqp;
1303 }
1304
1305 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1306 {
1307         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1308         struct mlx5_ib_qp *mqp = to_mqp(qp);
1309
1310         destroy_qp_common(dev, mqp);
1311
1312         kfree(mqp);
1313
1314         return 0;
1315 }
1316
1317 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1318                                    int attr_mask)
1319 {
1320         u32 hw_access_flags = 0;
1321         u8 dest_rd_atomic;
1322         u32 access_flags;
1323
1324         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1325                 dest_rd_atomic = attr->max_dest_rd_atomic;
1326         else
1327                 dest_rd_atomic = qp->resp_depth;
1328
1329         if (attr_mask & IB_QP_ACCESS_FLAGS)
1330                 access_flags = attr->qp_access_flags;
1331         else
1332                 access_flags = qp->atomic_rd_en;
1333
1334         if (!dest_rd_atomic)
1335                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1336
1337         if (access_flags & IB_ACCESS_REMOTE_READ)
1338                 hw_access_flags |= MLX5_QP_BIT_RRE;
1339         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1340                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1341         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1342                 hw_access_flags |= MLX5_QP_BIT_RWE;
1343
1344         return cpu_to_be32(hw_access_flags);
1345 }
1346
1347 enum {
1348         MLX5_PATH_FLAG_FL       = 1 << 0,
1349         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
1350         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
1351 };
1352
1353 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1354 {
1355         if (rate == IB_RATE_PORT_CURRENT) {
1356                 return 0;
1357         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1358                 return -EINVAL;
1359         } else {
1360                 while (rate != IB_RATE_2_5_GBPS &&
1361                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1362                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
1363                         --rate;
1364         }
1365
1366         return rate + MLX5_STAT_RATE_OFFSET;
1367 }
1368
1369 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1370                          struct mlx5_qp_path *path, u8 port, int attr_mask,
1371                          u32 path_flags, const struct ib_qp_attr *attr)
1372 {
1373         int err;
1374
1375         path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1376         path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1377
1378         if (attr_mask & IB_QP_PKEY_INDEX)
1379                 path->pkey_index = attr->pkey_index;
1380
1381         path->grh_mlid  = ah->src_path_bits & 0x7f;
1382         path->rlid      = cpu_to_be16(ah->dlid);
1383
1384         if (ah->ah_flags & IB_AH_GRH) {
1385                 if (ah->grh.sgid_index >=
1386                     dev->mdev->port_caps[port - 1].gid_table_len) {
1387                         pr_err("sgid_index (%u) too large. max is %d\n",
1388                                ah->grh.sgid_index,
1389                                dev->mdev->port_caps[port - 1].gid_table_len);
1390                         return -EINVAL;
1391                 }
1392                 path->grh_mlid |= 1 << 7;
1393                 path->mgid_index = ah->grh.sgid_index;
1394                 path->hop_limit  = ah->grh.hop_limit;
1395                 path->tclass_flowlabel =
1396                         cpu_to_be32((ah->grh.traffic_class << 20) |
1397                                     (ah->grh.flow_label));
1398                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1399         }
1400
1401         err = ib_rate_to_mlx5(dev, ah->static_rate);
1402         if (err < 0)
1403                 return err;
1404         path->static_rate = err;
1405         path->port = port;
1406
1407         if (attr_mask & IB_QP_TIMEOUT)
1408                 path->ackto_lt = attr->timeout << 3;
1409
1410         path->sl = ah->sl & 0xf;
1411
1412         return 0;
1413 }
1414
1415 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1416         [MLX5_QP_STATE_INIT] = {
1417                 [MLX5_QP_STATE_INIT] = {
1418                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1419                                           MLX5_QP_OPTPAR_RAE            |
1420                                           MLX5_QP_OPTPAR_RWE            |
1421                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1422                                           MLX5_QP_OPTPAR_PRI_PORT,
1423                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1424                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1425                                           MLX5_QP_OPTPAR_PRI_PORT,
1426                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1427                                           MLX5_QP_OPTPAR_Q_KEY          |
1428                                           MLX5_QP_OPTPAR_PRI_PORT,
1429                 },
1430                 [MLX5_QP_STATE_RTR] = {
1431                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1432                                           MLX5_QP_OPTPAR_RRE            |
1433                                           MLX5_QP_OPTPAR_RAE            |
1434                                           MLX5_QP_OPTPAR_RWE            |
1435                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1436                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1437                                           MLX5_QP_OPTPAR_RWE            |
1438                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1439                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1440                                           MLX5_QP_OPTPAR_Q_KEY,
1441                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
1442                                            MLX5_QP_OPTPAR_Q_KEY,
1443                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1444                                           MLX5_QP_OPTPAR_RRE            |
1445                                           MLX5_QP_OPTPAR_RAE            |
1446                                           MLX5_QP_OPTPAR_RWE            |
1447                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1448                 },
1449         },
1450         [MLX5_QP_STATE_RTR] = {
1451                 [MLX5_QP_STATE_RTS] = {
1452                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1453                                           MLX5_QP_OPTPAR_RRE            |
1454                                           MLX5_QP_OPTPAR_RAE            |
1455                                           MLX5_QP_OPTPAR_RWE            |
1456                                           MLX5_QP_OPTPAR_PM_STATE       |
1457                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
1458                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1459                                           MLX5_QP_OPTPAR_RWE            |
1460                                           MLX5_QP_OPTPAR_PM_STATE,
1461                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1462                 },
1463         },
1464         [MLX5_QP_STATE_RTS] = {
1465                 [MLX5_QP_STATE_RTS] = {
1466                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1467                                           MLX5_QP_OPTPAR_RAE            |
1468                                           MLX5_QP_OPTPAR_RWE            |
1469                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
1470                                           MLX5_QP_OPTPAR_PM_STATE       |
1471                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1472                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1473                                           MLX5_QP_OPTPAR_PM_STATE       |
1474                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1475                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
1476                                           MLX5_QP_OPTPAR_SRQN           |
1477                                           MLX5_QP_OPTPAR_CQN_RCV,
1478                 },
1479         },
1480         [MLX5_QP_STATE_SQER] = {
1481                 [MLX5_QP_STATE_RTS] = {
1482                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
1483                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1484                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
1485                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
1486                                            MLX5_QP_OPTPAR_RWE           |
1487                                            MLX5_QP_OPTPAR_RAE           |
1488                                            MLX5_QP_OPTPAR_RRE,
1489                 },
1490         },
1491 };
1492
1493 static int ib_nr_to_mlx5_nr(int ib_mask)
1494 {
1495         switch (ib_mask) {
1496         case IB_QP_STATE:
1497                 return 0;
1498         case IB_QP_CUR_STATE:
1499                 return 0;
1500         case IB_QP_EN_SQD_ASYNC_NOTIFY:
1501                 return 0;
1502         case IB_QP_ACCESS_FLAGS:
1503                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1504                         MLX5_QP_OPTPAR_RAE;
1505         case IB_QP_PKEY_INDEX:
1506                 return MLX5_QP_OPTPAR_PKEY_INDEX;
1507         case IB_QP_PORT:
1508                 return MLX5_QP_OPTPAR_PRI_PORT;
1509         case IB_QP_QKEY:
1510                 return MLX5_QP_OPTPAR_Q_KEY;
1511         case IB_QP_AV:
1512                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1513                         MLX5_QP_OPTPAR_PRI_PORT;
1514         case IB_QP_PATH_MTU:
1515                 return 0;
1516         case IB_QP_TIMEOUT:
1517                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1518         case IB_QP_RETRY_CNT:
1519                 return MLX5_QP_OPTPAR_RETRY_COUNT;
1520         case IB_QP_RNR_RETRY:
1521                 return MLX5_QP_OPTPAR_RNR_RETRY;
1522         case IB_QP_RQ_PSN:
1523                 return 0;
1524         case IB_QP_MAX_QP_RD_ATOMIC:
1525                 return MLX5_QP_OPTPAR_SRA_MAX;
1526         case IB_QP_ALT_PATH:
1527                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1528         case IB_QP_MIN_RNR_TIMER:
1529                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1530         case IB_QP_SQ_PSN:
1531                 return 0;
1532         case IB_QP_MAX_DEST_RD_ATOMIC:
1533                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1534                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1535         case IB_QP_PATH_MIG_STATE:
1536                 return MLX5_QP_OPTPAR_PM_STATE;
1537         case IB_QP_CAP:
1538                 return 0;
1539         case IB_QP_DEST_QPN:
1540                 return 0;
1541         }
1542         return 0;
1543 }
1544
1545 static int ib_mask_to_mlx5_opt(int ib_mask)
1546 {
1547         int result = 0;
1548         int i;
1549
1550         for (i = 0; i < 8 * sizeof(int); i++) {
1551                 if ((1 << i) & ib_mask)
1552                         result |= ib_nr_to_mlx5_nr(1 << i);
1553         }
1554
1555         return result;
1556 }
1557
1558 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1559                                const struct ib_qp_attr *attr, int attr_mask,
1560                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1561 {
1562         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1563         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1564         struct mlx5_ib_cq *send_cq, *recv_cq;
1565         struct mlx5_qp_context *context;
1566         struct mlx5_modify_qp_mbox_in *in;
1567         struct mlx5_ib_pd *pd;
1568         enum mlx5_qp_state mlx5_cur, mlx5_new;
1569         enum mlx5_qp_optpar optpar;
1570         int sqd_event;
1571         int mlx5_st;
1572         int err;
1573
1574         in = kzalloc(sizeof(*in), GFP_KERNEL);
1575         if (!in)
1576                 return -ENOMEM;
1577
1578         context = &in->ctx;
1579         err = to_mlx5_st(ibqp->qp_type);
1580         if (err < 0)
1581                 goto out;
1582
1583         context->flags = cpu_to_be32(err << 16);
1584
1585         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1586                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1587         } else {
1588                 switch (attr->path_mig_state) {
1589                 case IB_MIG_MIGRATED:
1590                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1591                         break;
1592                 case IB_MIG_REARM:
1593                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1594                         break;
1595                 case IB_MIG_ARMED:
1596                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1597                         break;
1598                 }
1599         }
1600
1601         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1602                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1603         } else if (ibqp->qp_type == IB_QPT_UD ||
1604                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1605                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1606         } else if (attr_mask & IB_QP_PATH_MTU) {
1607                 if (attr->path_mtu < IB_MTU_256 ||
1608                     attr->path_mtu > IB_MTU_4096) {
1609                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1610                         err = -EINVAL;
1611                         goto out;
1612                 }
1613                 context->mtu_msgmax = (attr->path_mtu << 5) |
1614                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
1615         }
1616
1617         if (attr_mask & IB_QP_DEST_QPN)
1618                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1619
1620         if (attr_mask & IB_QP_PKEY_INDEX)
1621                 context->pri_path.pkey_index = attr->pkey_index;
1622
1623         /* todo implement counter_index functionality */
1624
1625         if (is_sqp(ibqp->qp_type))
1626                 context->pri_path.port = qp->port;
1627
1628         if (attr_mask & IB_QP_PORT)
1629                 context->pri_path.port = attr->port_num;
1630
1631         if (attr_mask & IB_QP_AV) {
1632                 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1633                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1634                                     attr_mask, 0, attr);
1635                 if (err)
1636                         goto out;
1637         }
1638
1639         if (attr_mask & IB_QP_TIMEOUT)
1640                 context->pri_path.ackto_lt |= attr->timeout << 3;
1641
1642         if (attr_mask & IB_QP_ALT_PATH) {
1643                 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1644                                     attr->alt_port_num, attr_mask, 0, attr);
1645                 if (err)
1646                         goto out;
1647         }
1648
1649         pd = get_pd(qp);
1650         get_cqs(qp, &send_cq, &recv_cq);
1651
1652         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1653         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1654         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1655         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1656
1657         if (attr_mask & IB_QP_RNR_RETRY)
1658                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1659
1660         if (attr_mask & IB_QP_RETRY_CNT)
1661                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1662
1663         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1664                 if (attr->max_rd_atomic)
1665                         context->params1 |=
1666                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1667         }
1668
1669         if (attr_mask & IB_QP_SQ_PSN)
1670                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1671
1672         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1673                 if (attr->max_dest_rd_atomic)
1674                         context->params2 |=
1675                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1676         }
1677
1678         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1679                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1680
1681         if (attr_mask & IB_QP_MIN_RNR_TIMER)
1682                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1683
1684         if (attr_mask & IB_QP_RQ_PSN)
1685                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1686
1687         if (attr_mask & IB_QP_QKEY)
1688                 context->qkey = cpu_to_be32(attr->qkey);
1689
1690         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1691                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1692
1693         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1694             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1695                 sqd_event = 1;
1696         else
1697                 sqd_event = 0;
1698
1699         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1700                 context->sq_crq_size |= cpu_to_be16(1 << 4);
1701
1702
1703         mlx5_cur = to_mlx5_state(cur_state);
1704         mlx5_new = to_mlx5_state(new_state);
1705         mlx5_st = to_mlx5_st(ibqp->qp_type);
1706         if (mlx5_st < 0)
1707                 goto out;
1708
1709         /* If moving to a reset or error state, we must disable page faults on
1710          * this QP and flush all current page faults. Otherwise a stale page
1711          * fault may attempt to work on this QP after it is reset and moved
1712          * again to RTS, and may cause the driver and the device to get out of
1713          * sync. */
1714         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1715             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1716                 mlx5_ib_qp_disable_pagefaults(qp);
1717
1718         optpar = ib_mask_to_mlx5_opt(attr_mask);
1719         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1720         in->optparam = cpu_to_be32(optpar);
1721         err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state),
1722                                   to_mlx5_state(new_state), in, sqd_event,
1723                                   &qp->mqp);
1724         if (err)
1725                 goto out;
1726
1727         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1728                 mlx5_ib_qp_enable_pagefaults(qp);
1729
1730         qp->state = new_state;
1731
1732         if (attr_mask & IB_QP_ACCESS_FLAGS)
1733                 qp->atomic_rd_en = attr->qp_access_flags;
1734         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1735                 qp->resp_depth = attr->max_dest_rd_atomic;
1736         if (attr_mask & IB_QP_PORT)
1737                 qp->port = attr->port_num;
1738         if (attr_mask & IB_QP_ALT_PATH)
1739                 qp->alt_port = attr->alt_port_num;
1740
1741         /*
1742          * If we moved a kernel QP to RESET, clean up all old CQ
1743          * entries and reinitialize the QP.
1744          */
1745         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1746                 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1747                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1748                 if (send_cq != recv_cq)
1749                         mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1750
1751                 qp->rq.head = 0;
1752                 qp->rq.tail = 0;
1753                 qp->sq.head = 0;
1754                 qp->sq.tail = 0;
1755                 qp->sq.cur_post = 0;
1756                 qp->sq.last_poll = 0;
1757                 qp->db.db[MLX5_RCV_DBR] = 0;
1758                 qp->db.db[MLX5_SND_DBR] = 0;
1759         }
1760
1761 out:
1762         kfree(in);
1763         return err;
1764 }
1765
1766 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1767                       int attr_mask, struct ib_udata *udata)
1768 {
1769         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1770         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1771         enum ib_qp_state cur_state, new_state;
1772         int err = -EINVAL;
1773         int port;
1774
1775         mutex_lock(&qp->mutex);
1776
1777         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1778         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1779
1780         if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1781             !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1782                                 IB_LINK_LAYER_UNSPECIFIED))
1783                 goto out;
1784
1785         if ((attr_mask & IB_QP_PORT) &&
1786             (attr->port_num == 0 ||
1787              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)))
1788                 goto out;
1789
1790         if (attr_mask & IB_QP_PKEY_INDEX) {
1791                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1792                 if (attr->pkey_index >=
1793                     dev->mdev->port_caps[port - 1].pkey_table_len)
1794                         goto out;
1795         }
1796
1797         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1798             attr->max_rd_atomic >
1799             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp)))
1800                 goto out;
1801
1802         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1803             attr->max_dest_rd_atomic >
1804             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp)))
1805                 goto out;
1806
1807         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1808                 err = 0;
1809                 goto out;
1810         }
1811
1812         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1813
1814 out:
1815         mutex_unlock(&qp->mutex);
1816         return err;
1817 }
1818
1819 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1820 {
1821         struct mlx5_ib_cq *cq;
1822         unsigned cur;
1823
1824         cur = wq->head - wq->tail;
1825         if (likely(cur + nreq < wq->max_post))
1826                 return 0;
1827
1828         cq = to_mcq(ib_cq);
1829         spin_lock(&cq->lock);
1830         cur = wq->head - wq->tail;
1831         spin_unlock(&cq->lock);
1832
1833         return cur + nreq >= wq->max_post;
1834 }
1835
1836 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1837                                           u64 remote_addr, u32 rkey)
1838 {
1839         rseg->raddr    = cpu_to_be64(remote_addr);
1840         rseg->rkey     = cpu_to_be32(rkey);
1841         rseg->reserved = 0;
1842 }
1843
1844 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1845                              struct ib_send_wr *wr)
1846 {
1847         memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1848         dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1849         dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1850 }
1851
1852 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1853 {
1854         dseg->byte_count = cpu_to_be32(sg->length);
1855         dseg->lkey       = cpu_to_be32(sg->lkey);
1856         dseg->addr       = cpu_to_be64(sg->addr);
1857 }
1858
1859 static __be16 get_klm_octo(int npages)
1860 {
1861         return cpu_to_be16(ALIGN(npages, 8) / 2);
1862 }
1863
1864 static __be64 frwr_mkey_mask(void)
1865 {
1866         u64 result;
1867
1868         result = MLX5_MKEY_MASK_LEN             |
1869                 MLX5_MKEY_MASK_PAGE_SIZE        |
1870                 MLX5_MKEY_MASK_START_ADDR       |
1871                 MLX5_MKEY_MASK_EN_RINVAL        |
1872                 MLX5_MKEY_MASK_KEY              |
1873                 MLX5_MKEY_MASK_LR               |
1874                 MLX5_MKEY_MASK_LW               |
1875                 MLX5_MKEY_MASK_RR               |
1876                 MLX5_MKEY_MASK_RW               |
1877                 MLX5_MKEY_MASK_A                |
1878                 MLX5_MKEY_MASK_SMALL_FENCE      |
1879                 MLX5_MKEY_MASK_FREE;
1880
1881         return cpu_to_be64(result);
1882 }
1883
1884 static __be64 sig_mkey_mask(void)
1885 {
1886         u64 result;
1887
1888         result = MLX5_MKEY_MASK_LEN             |
1889                 MLX5_MKEY_MASK_PAGE_SIZE        |
1890                 MLX5_MKEY_MASK_START_ADDR       |
1891                 MLX5_MKEY_MASK_EN_SIGERR        |
1892                 MLX5_MKEY_MASK_EN_RINVAL        |
1893                 MLX5_MKEY_MASK_KEY              |
1894                 MLX5_MKEY_MASK_LR               |
1895                 MLX5_MKEY_MASK_LW               |
1896                 MLX5_MKEY_MASK_RR               |
1897                 MLX5_MKEY_MASK_RW               |
1898                 MLX5_MKEY_MASK_SMALL_FENCE      |
1899                 MLX5_MKEY_MASK_FREE             |
1900                 MLX5_MKEY_MASK_BSF_EN;
1901
1902         return cpu_to_be64(result);
1903 }
1904
1905 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1906                                  struct ib_send_wr *wr, int li)
1907 {
1908         memset(umr, 0, sizeof(*umr));
1909
1910         if (li) {
1911                 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1912                 umr->flags = 1 << 7;
1913                 return;
1914         }
1915
1916         umr->flags = (1 << 5); /* fail if not free */
1917         umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1918         umr->mkey_mask = frwr_mkey_mask();
1919 }
1920
1921 static __be64 get_umr_reg_mr_mask(void)
1922 {
1923         u64 result;
1924
1925         result = MLX5_MKEY_MASK_LEN             |
1926                  MLX5_MKEY_MASK_PAGE_SIZE       |
1927                  MLX5_MKEY_MASK_START_ADDR      |
1928                  MLX5_MKEY_MASK_PD              |
1929                  MLX5_MKEY_MASK_LR              |
1930                  MLX5_MKEY_MASK_LW              |
1931                  MLX5_MKEY_MASK_KEY             |
1932                  MLX5_MKEY_MASK_RR              |
1933                  MLX5_MKEY_MASK_RW              |
1934                  MLX5_MKEY_MASK_A               |
1935                  MLX5_MKEY_MASK_FREE;
1936
1937         return cpu_to_be64(result);
1938 }
1939
1940 static __be64 get_umr_unreg_mr_mask(void)
1941 {
1942         u64 result;
1943
1944         result = MLX5_MKEY_MASK_FREE;
1945
1946         return cpu_to_be64(result);
1947 }
1948
1949 static __be64 get_umr_update_mtt_mask(void)
1950 {
1951         u64 result;
1952
1953         result = MLX5_MKEY_MASK_FREE;
1954
1955         return cpu_to_be64(result);
1956 }
1957
1958 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1959                                 struct ib_send_wr *wr)
1960 {
1961         struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg;
1962
1963         memset(umr, 0, sizeof(*umr));
1964
1965         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
1966                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
1967         else
1968                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
1969
1970         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1971                 umr->klm_octowords = get_klm_octo(umrwr->npages);
1972                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
1973                         umr->mkey_mask = get_umr_update_mtt_mask();
1974                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
1975                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
1976                 } else {
1977                         umr->mkey_mask = get_umr_reg_mr_mask();
1978                 }
1979         } else {
1980                 umr->mkey_mask = get_umr_unreg_mr_mask();
1981         }
1982
1983         if (!wr->num_sge)
1984                 umr->flags |= MLX5_UMR_INLINE;
1985 }
1986
1987 static u8 get_umr_flags(int acc)
1988 {
1989         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
1990                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
1991                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
1992                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
1993                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
1994 }
1995
1996 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1997                              int li, int *writ)
1998 {
1999         memset(seg, 0, sizeof(*seg));
2000         if (li) {
2001                 seg->status = MLX5_MKEY_STATUS_FREE;
2002                 return;
2003         }
2004
2005         seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags) |
2006                      MLX5_ACCESS_MODE_MTT;
2007         *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
2008         seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
2009         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2010         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
2011         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
2012         seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
2013         seg->log2_page_size = wr->wr.fast_reg.page_shift;
2014 }
2015
2016 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2017 {
2018         struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg;
2019
2020         memset(seg, 0, sizeof(*seg));
2021         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
2022                 seg->status = MLX5_MKEY_STATUS_FREE;
2023                 return;
2024         }
2025
2026         seg->flags = convert_access(umrwr->access_flags);
2027         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
2028                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
2029                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2030         }
2031         seg->len = cpu_to_be64(umrwr->length);
2032         seg->log2_page_size = umrwr->page_shift;
2033         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
2034                                        mlx5_mkey_variant(umrwr->mkey));
2035 }
2036
2037 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
2038                            struct ib_send_wr *wr,
2039                            struct mlx5_core_dev *mdev,
2040                            struct mlx5_ib_pd *pd,
2041                            int writ)
2042 {
2043         struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2044         u64 *page_list = wr->wr.fast_reg.page_list->page_list;
2045         u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
2046         int i;
2047
2048         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
2049                 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
2050         dseg->addr = cpu_to_be64(mfrpl->map);
2051         dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
2052         dseg->lkey = cpu_to_be32(pd->pa_lkey);
2053 }
2054
2055 static __be32 send_ieth(struct ib_send_wr *wr)
2056 {
2057         switch (wr->opcode) {
2058         case IB_WR_SEND_WITH_IMM:
2059         case IB_WR_RDMA_WRITE_WITH_IMM:
2060                 return wr->ex.imm_data;
2061
2062         case IB_WR_SEND_WITH_INV:
2063                 return cpu_to_be32(wr->ex.invalidate_rkey);
2064
2065         default:
2066                 return 0;
2067         }
2068 }
2069
2070 static u8 calc_sig(void *wqe, int size)
2071 {
2072         u8 *p = wqe;
2073         u8 res = 0;
2074         int i;
2075
2076         for (i = 0; i < size; i++)
2077                 res ^= p[i];
2078
2079         return ~res;
2080 }
2081
2082 static u8 wq_sig(void *wqe)
2083 {
2084         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2085 }
2086
2087 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2088                             void *wqe, int *sz)
2089 {
2090         struct mlx5_wqe_inline_seg *seg;
2091         void *qend = qp->sq.qend;
2092         void *addr;
2093         int inl = 0;
2094         int copy;
2095         int len;
2096         int i;
2097
2098         seg = wqe;
2099         wqe += sizeof(*seg);
2100         for (i = 0; i < wr->num_sge; i++) {
2101                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2102                 len  = wr->sg_list[i].length;
2103                 inl += len;
2104
2105                 if (unlikely(inl > qp->max_inline_data))
2106                         return -ENOMEM;
2107
2108                 if (unlikely(wqe + len > qend)) {
2109                         copy = qend - wqe;
2110                         memcpy(wqe, addr, copy);
2111                         addr += copy;
2112                         len -= copy;
2113                         wqe = mlx5_get_send_wqe(qp, 0);
2114                 }
2115                 memcpy(wqe, addr, len);
2116                 wqe += len;
2117         }
2118
2119         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2120
2121         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2122
2123         return 0;
2124 }
2125
2126 static u16 prot_field_size(enum ib_signature_type type)
2127 {
2128         switch (type) {
2129         case IB_SIG_TYPE_T10_DIF:
2130                 return MLX5_DIF_SIZE;
2131         default:
2132                 return 0;
2133         }
2134 }
2135
2136 static u8 bs_selector(int block_size)
2137 {
2138         switch (block_size) {
2139         case 512:           return 0x1;
2140         case 520:           return 0x2;
2141         case 4096:          return 0x3;
2142         case 4160:          return 0x4;
2143         case 1073741824:    return 0x5;
2144         default:            return 0;
2145         }
2146 }
2147
2148 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2149                               struct mlx5_bsf_inl *inl)
2150 {
2151         /* Valid inline section and allow BSF refresh */
2152         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2153                                        MLX5_BSF_REFRESH_DIF);
2154         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2155         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
2156         /* repeating block */
2157         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2158         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2159                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
2160
2161         if (domain->sig.dif.ref_remap)
2162                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
2163
2164         if (domain->sig.dif.app_escape) {
2165                 if (domain->sig.dif.ref_escape)
2166                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2167                 else
2168                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
2169         }
2170
2171         inl->dif_app_bitmask_check =
2172                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
2173 }
2174
2175 static int mlx5_set_bsf(struct ib_mr *sig_mr,
2176                         struct ib_sig_attrs *sig_attrs,
2177                         struct mlx5_bsf *bsf, u32 data_size)
2178 {
2179         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2180         struct mlx5_bsf_basic *basic = &bsf->basic;
2181         struct ib_sig_domain *mem = &sig_attrs->mem;
2182         struct ib_sig_domain *wire = &sig_attrs->wire;
2183
2184         memset(bsf, 0, sizeof(*bsf));
2185
2186         /* Basic + Extended + Inline */
2187         basic->bsf_size_sbs = 1 << 7;
2188         /* Input domain check byte mask */
2189         basic->check_byte_mask = sig_attrs->check_mask;
2190         basic->raw_data_size = cpu_to_be32(data_size);
2191
2192         /* Memory domain */
2193         switch (sig_attrs->mem.sig_type) {
2194         case IB_SIG_TYPE_NONE:
2195                 break;
2196         case IB_SIG_TYPE_T10_DIF:
2197                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2198                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2199                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2200                 break;
2201         default:
2202                 return -EINVAL;
2203         }
2204
2205         /* Wire domain */
2206         switch (sig_attrs->wire.sig_type) {
2207         case IB_SIG_TYPE_NONE:
2208                 break;
2209         case IB_SIG_TYPE_T10_DIF:
2210                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2211                     mem->sig_type == wire->sig_type) {
2212                         /* Same block structure */
2213                         basic->bsf_size_sbs |= 1 << 4;
2214                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2215                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
2216                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
2217                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
2218                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
2219                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
2220                 } else
2221                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2222
2223                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
2224                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
2225                 break;
2226         default:
2227                 return -EINVAL;
2228         }
2229
2230         return 0;
2231 }
2232
2233 static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
2234                                 void **seg, int *size)
2235 {
2236         struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs;
2237         struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
2238         struct mlx5_bsf *bsf;
2239         u32 data_len = wr->sg_list->length;
2240         u32 data_key = wr->sg_list->lkey;
2241         u64 data_va = wr->sg_list->addr;
2242         int ret;
2243         int wqe_size;
2244
2245         if (!wr->wr.sig_handover.prot ||
2246             (data_key == wr->wr.sig_handover.prot->lkey &&
2247              data_va == wr->wr.sig_handover.prot->addr &&
2248              data_len == wr->wr.sig_handover.prot->length)) {
2249                 /**
2250                  * Source domain doesn't contain signature information
2251                  * or data and protection are interleaved in memory.
2252                  * So need construct:
2253                  *                  ------------------
2254                  *                 |     data_klm     |
2255                  *                  ------------------
2256                  *                 |       BSF        |
2257                  *                  ------------------
2258                  **/
2259                 struct mlx5_klm *data_klm = *seg;
2260
2261                 data_klm->bcount = cpu_to_be32(data_len);
2262                 data_klm->key = cpu_to_be32(data_key);
2263                 data_klm->va = cpu_to_be64(data_va);
2264                 wqe_size = ALIGN(sizeof(*data_klm), 64);
2265         } else {
2266                 /**
2267                  * Source domain contains signature information
2268                  * So need construct a strided block format:
2269                  *               ---------------------------
2270                  *              |     stride_block_ctrl     |
2271                  *               ---------------------------
2272                  *              |          data_klm         |
2273                  *               ---------------------------
2274                  *              |          prot_klm         |
2275                  *               ---------------------------
2276                  *              |             BSF           |
2277                  *               ---------------------------
2278                  **/
2279                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2280                 struct mlx5_stride_block_entry *data_sentry;
2281                 struct mlx5_stride_block_entry *prot_sentry;
2282                 u32 prot_key = wr->wr.sig_handover.prot->lkey;
2283                 u64 prot_va = wr->wr.sig_handover.prot->addr;
2284                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2285                 int prot_size;
2286
2287                 sblock_ctrl = *seg;
2288                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2289                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2290
2291                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2292                 if (!prot_size) {
2293                         pr_err("Bad block size given: %u\n", block_size);
2294                         return -EINVAL;
2295                 }
2296                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2297                                                             prot_size);
2298                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2299                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2300                 sblock_ctrl->num_entries = cpu_to_be16(2);
2301
2302                 data_sentry->bcount = cpu_to_be16(block_size);
2303                 data_sentry->key = cpu_to_be32(data_key);
2304                 data_sentry->va = cpu_to_be64(data_va);
2305                 data_sentry->stride = cpu_to_be16(block_size);
2306
2307                 prot_sentry->bcount = cpu_to_be16(prot_size);
2308                 prot_sentry->key = cpu_to_be32(prot_key);
2309                 prot_sentry->va = cpu_to_be64(prot_va);
2310                 prot_sentry->stride = cpu_to_be16(prot_size);
2311
2312                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2313                                  sizeof(*prot_sentry), 64);
2314         }
2315
2316         *seg += wqe_size;
2317         *size += wqe_size / 16;
2318         if (unlikely((*seg == qp->sq.qend)))
2319                 *seg = mlx5_get_send_wqe(qp, 0);
2320
2321         bsf = *seg;
2322         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2323         if (ret)
2324                 return -EINVAL;
2325
2326         *seg += sizeof(*bsf);
2327         *size += sizeof(*bsf) / 16;
2328         if (unlikely((*seg == qp->sq.qend)))
2329                 *seg = mlx5_get_send_wqe(qp, 0);
2330
2331         return 0;
2332 }
2333
2334 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
2335                                  struct ib_send_wr *wr, u32 nelements,
2336                                  u32 length, u32 pdn)
2337 {
2338         struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
2339         u32 sig_key = sig_mr->rkey;
2340         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
2341
2342         memset(seg, 0, sizeof(*seg));
2343
2344         seg->flags = get_umr_flags(wr->wr.sig_handover.access_flags) |
2345                                    MLX5_ACCESS_MODE_KLM;
2346         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
2347         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
2348                                     MLX5_MKEY_BSF_EN | pdn);
2349         seg->len = cpu_to_be64(length);
2350         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2351         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2352 }
2353
2354 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2355                                 struct ib_send_wr *wr, u32 nelements)
2356 {
2357         memset(umr, 0, sizeof(*umr));
2358
2359         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2360         umr->klm_octowords = get_klm_octo(nelements);
2361         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2362         umr->mkey_mask = sig_mkey_mask();
2363 }
2364
2365
2366 static int set_sig_umr_wr(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
2367                           void **seg, int *size)
2368 {
2369         struct mlx5_ib_mr *sig_mr = to_mmr(wr->wr.sig_handover.sig_mr);
2370         u32 pdn = get_pd(qp)->pdn;
2371         u32 klm_oct_size;
2372         int region_len, ret;
2373
2374         if (unlikely(wr->num_sge != 1) ||
2375             unlikely(wr->wr.sig_handover.access_flags &
2376                      IB_ACCESS_REMOTE_ATOMIC) ||
2377             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2378             unlikely(!sig_mr->sig->sig_status_checked))
2379                 return -EINVAL;
2380
2381         /* length of the protected region, data + protection */
2382         region_len = wr->sg_list->length;
2383         if (wr->wr.sig_handover.prot &&
2384             (wr->wr.sig_handover.prot->lkey != wr->sg_list->lkey  ||
2385              wr->wr.sig_handover.prot->addr != wr->sg_list->addr  ||
2386              wr->wr.sig_handover.prot->length != wr->sg_list->length))
2387                 region_len += wr->wr.sig_handover.prot->length;
2388
2389         /**
2390          * KLM octoword size - if protection was provided
2391          * then we use strided block format (3 octowords),
2392          * else we use single KLM (1 octoword)
2393          **/
2394         klm_oct_size = wr->wr.sig_handover.prot ? 3 : 1;
2395
2396         set_sig_umr_segment(*seg, wr, klm_oct_size);
2397         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2398         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2399         if (unlikely((*seg == qp->sq.qend)))
2400                 *seg = mlx5_get_send_wqe(qp, 0);
2401
2402         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
2403         *seg += sizeof(struct mlx5_mkey_seg);
2404         *size += sizeof(struct mlx5_mkey_seg) / 16;
2405         if (unlikely((*seg == qp->sq.qend)))
2406                 *seg = mlx5_get_send_wqe(qp, 0);
2407
2408         ret = set_sig_data_segment(wr, qp, seg, size);
2409         if (ret)
2410                 return ret;
2411
2412         sig_mr->sig->sig_status_checked = false;
2413         return 0;
2414 }
2415
2416 static int set_psv_wr(struct ib_sig_domain *domain,
2417                       u32 psv_idx, void **seg, int *size)
2418 {
2419         struct mlx5_seg_set_psv *psv_seg = *seg;
2420
2421         memset(psv_seg, 0, sizeof(*psv_seg));
2422         psv_seg->psv_num = cpu_to_be32(psv_idx);
2423         switch (domain->sig_type) {
2424         case IB_SIG_TYPE_NONE:
2425                 break;
2426         case IB_SIG_TYPE_T10_DIF:
2427                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
2428                                                      domain->sig.dif.app_tag);
2429                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
2430                 break;
2431         default:
2432                 pr_err("Bad signature type given.\n");
2433                 return 1;
2434         }
2435
2436         *seg += sizeof(*psv_seg);
2437         *size += sizeof(*psv_seg) / 16;
2438
2439         return 0;
2440 }
2441
2442 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
2443                           struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
2444 {
2445         int writ = 0;
2446         int li;
2447
2448         li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
2449         if (unlikely(wr->send_flags & IB_SEND_INLINE))
2450                 return -EINVAL;
2451
2452         set_frwr_umr_segment(*seg, wr, li);
2453         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2454         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2455         if (unlikely((*seg == qp->sq.qend)))
2456                 *seg = mlx5_get_send_wqe(qp, 0);
2457         set_mkey_segment(*seg, wr, li, &writ);
2458         *seg += sizeof(struct mlx5_mkey_seg);
2459         *size += sizeof(struct mlx5_mkey_seg) / 16;
2460         if (unlikely((*seg == qp->sq.qend)))
2461                 *seg = mlx5_get_send_wqe(qp, 0);
2462         if (!li) {
2463                 if (unlikely(wr->wr.fast_reg.page_list_len >
2464                              wr->wr.fast_reg.page_list->max_page_list_len))
2465                         return  -ENOMEM;
2466
2467                 set_frwr_pages(*seg, wr, mdev, pd, writ);
2468                 *seg += sizeof(struct mlx5_wqe_data_seg);
2469                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2470         }
2471         return 0;
2472 }
2473
2474 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
2475 {
2476         __be32 *p = NULL;
2477         int tidx = idx;
2478         int i, j;
2479
2480         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2481         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2482                 if ((i & 0xf) == 0) {
2483                         void *buf = mlx5_get_send_wqe(qp, tidx);
2484                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2485                         p = buf;
2486                         j = 0;
2487                 }
2488                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2489                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2490                          be32_to_cpu(p[j + 3]));
2491         }
2492 }
2493
2494 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2495                          unsigned bytecnt, struct mlx5_ib_qp *qp)
2496 {
2497         while (bytecnt > 0) {
2498                 __iowrite64_copy(dst++, src++, 8);
2499                 __iowrite64_copy(dst++, src++, 8);
2500                 __iowrite64_copy(dst++, src++, 8);
2501                 __iowrite64_copy(dst++, src++, 8);
2502                 __iowrite64_copy(dst++, src++, 8);
2503                 __iowrite64_copy(dst++, src++, 8);
2504                 __iowrite64_copy(dst++, src++, 8);
2505                 __iowrite64_copy(dst++, src++, 8);
2506                 bytecnt -= 64;
2507                 if (unlikely(src == qp->sq.qend))
2508                         src = mlx5_get_send_wqe(qp, 0);
2509         }
2510 }
2511
2512 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2513 {
2514         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2515                      wr->send_flags & IB_SEND_FENCE))
2516                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2517
2518         if (unlikely(fence)) {
2519                 if (wr->send_flags & IB_SEND_FENCE)
2520                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2521                 else
2522                         return fence;
2523
2524         } else {
2525                 return 0;
2526         }
2527 }
2528
2529 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
2530                      struct mlx5_wqe_ctrl_seg **ctrl,
2531                      struct ib_send_wr *wr, unsigned *idx,
2532                      int *size, int nreq)
2533 {
2534         int err = 0;
2535
2536         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2537                 err = -ENOMEM;
2538                 return err;
2539         }
2540
2541         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2542         *seg = mlx5_get_send_wqe(qp, *idx);
2543         *ctrl = *seg;
2544         *(uint32_t *)(*seg + 8) = 0;
2545         (*ctrl)->imm = send_ieth(wr);
2546         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
2547                 (wr->send_flags & IB_SEND_SIGNALED ?
2548                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2549                 (wr->send_flags & IB_SEND_SOLICITED ?
2550                  MLX5_WQE_CTRL_SOLICITED : 0);
2551
2552         *seg += sizeof(**ctrl);
2553         *size = sizeof(**ctrl) / 16;
2554
2555         return err;
2556 }
2557
2558 static void finish_wqe(struct mlx5_ib_qp *qp,
2559                        struct mlx5_wqe_ctrl_seg *ctrl,
2560                        u8 size, unsigned idx, u64 wr_id,
2561                        int nreq, u8 fence, u8 next_fence,
2562                        u32 mlx5_opcode)
2563 {
2564         u8 opmod = 0;
2565
2566         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2567                                              mlx5_opcode | ((u32)opmod << 24));
2568         ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2569         ctrl->fm_ce_se |= fence;
2570         qp->fm_cache = next_fence;
2571         if (unlikely(qp->wq_sig))
2572                 ctrl->signature = wq_sig(ctrl);
2573
2574         qp->sq.wrid[idx] = wr_id;
2575         qp->sq.w_list[idx].opcode = mlx5_opcode;
2576         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2577         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2578         qp->sq.w_list[idx].next = qp->sq.cur_post;
2579 }
2580
2581
2582 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2583                       struct ib_send_wr **bad_wr)
2584 {
2585         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
2586         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2587         struct mlx5_core_dev *mdev = dev->mdev;
2588         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2589         struct mlx5_ib_mr *mr;
2590         struct mlx5_wqe_data_seg *dpseg;
2591         struct mlx5_wqe_xrc_seg *xrc;
2592         struct mlx5_bf *bf = qp->bf;
2593         int uninitialized_var(size);
2594         void *qend = qp->sq.qend;
2595         unsigned long flags;
2596         unsigned idx;
2597         int err = 0;
2598         int inl = 0;
2599         int num_sge;
2600         void *seg;
2601         int nreq;
2602         int i;
2603         u8 next_fence = 0;
2604         u8 fence;
2605
2606         spin_lock_irqsave(&qp->sq.lock, flags);
2607
2608         for (nreq = 0; wr; nreq++, wr = wr->next) {
2609                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
2610                         mlx5_ib_warn(dev, "\n");
2611                         err = -EINVAL;
2612                         *bad_wr = wr;
2613                         goto out;
2614                 }
2615
2616                 fence = qp->fm_cache;
2617                 num_sge = wr->num_sge;
2618                 if (unlikely(num_sge > qp->sq.max_gs)) {
2619                         mlx5_ib_warn(dev, "\n");
2620                         err = -ENOMEM;
2621                         *bad_wr = wr;
2622                         goto out;
2623                 }
2624
2625                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
2626                 if (err) {
2627                         mlx5_ib_warn(dev, "\n");
2628                         err = -ENOMEM;
2629                         *bad_wr = wr;
2630                         goto out;
2631                 }
2632
2633                 switch (ibqp->qp_type) {
2634                 case IB_QPT_XRC_INI:
2635                         xrc = seg;
2636                         xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2637                         seg += sizeof(*xrc);
2638                         size += sizeof(*xrc) / 16;
2639                         /* fall through */
2640                 case IB_QPT_RC:
2641                         switch (wr->opcode) {
2642                         case IB_WR_RDMA_READ:
2643                         case IB_WR_RDMA_WRITE:
2644                         case IB_WR_RDMA_WRITE_WITH_IMM:
2645                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2646                                               wr->wr.rdma.rkey);
2647                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
2648                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2649                                 break;
2650
2651                         case IB_WR_ATOMIC_CMP_AND_SWP:
2652                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2653                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2654                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2655                                 err = -ENOSYS;
2656                                 *bad_wr = wr;
2657                                 goto out;
2658
2659                         case IB_WR_LOCAL_INV:
2660                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2661                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2662                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2663                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2664                                 if (err) {
2665                                         mlx5_ib_warn(dev, "\n");
2666                                         *bad_wr = wr;
2667                                         goto out;
2668                                 }
2669                                 num_sge = 0;
2670                                 break;
2671
2672                         case IB_WR_FAST_REG_MR:
2673                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2674                                 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2675                                 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2676                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2677                                 if (err) {
2678                                         mlx5_ib_warn(dev, "\n");
2679                                         *bad_wr = wr;
2680                                         goto out;
2681                                 }
2682                                 num_sge = 0;
2683                                 break;
2684
2685                         case IB_WR_REG_SIG_MR:
2686                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
2687                                 mr = to_mmr(wr->wr.sig_handover.sig_mr);
2688
2689                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
2690                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
2691                                 if (err) {
2692                                         mlx5_ib_warn(dev, "\n");
2693                                         *bad_wr = wr;
2694                                         goto out;
2695                                 }
2696
2697                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2698                                            nreq, get_fence(fence, wr),
2699                                            next_fence, MLX5_OPCODE_UMR);
2700                                 /*
2701                                  * SET_PSV WQEs are not signaled and solicited
2702                                  * on error
2703                                  */
2704                                 wr->send_flags &= ~IB_SEND_SIGNALED;
2705                                 wr->send_flags |= IB_SEND_SOLICITED;
2706                                 err = begin_wqe(qp, &seg, &ctrl, wr,
2707                                                 &idx, &size, nreq);
2708                                 if (err) {
2709                                         mlx5_ib_warn(dev, "\n");
2710                                         err = -ENOMEM;
2711                                         *bad_wr = wr;
2712                                         goto out;
2713                                 }
2714
2715                                 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->mem,
2716                                                  mr->sig->psv_memory.psv_idx, &seg,
2717                                                  &size);
2718                                 if (err) {
2719                                         mlx5_ib_warn(dev, "\n");
2720                                         *bad_wr = wr;
2721                                         goto out;
2722                                 }
2723
2724                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2725                                            nreq, get_fence(fence, wr),
2726                                            next_fence, MLX5_OPCODE_SET_PSV);
2727                                 err = begin_wqe(qp, &seg, &ctrl, wr,
2728                                                 &idx, &size, nreq);
2729                                 if (err) {
2730                                         mlx5_ib_warn(dev, "\n");
2731                                         err = -ENOMEM;
2732                                         *bad_wr = wr;
2733                                         goto out;
2734                                 }
2735
2736                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2737                                 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->wire,
2738                                                  mr->sig->psv_wire.psv_idx, &seg,
2739                                                  &size);
2740                                 if (err) {
2741                                         mlx5_ib_warn(dev, "\n");
2742                                         *bad_wr = wr;
2743                                         goto out;
2744                                 }
2745
2746                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2747                                            nreq, get_fence(fence, wr),
2748                                            next_fence, MLX5_OPCODE_SET_PSV);
2749                                 num_sge = 0;
2750                                 goto skip_psv;
2751
2752                         default:
2753                                 break;
2754                         }
2755                         break;
2756
2757                 case IB_QPT_UC:
2758                         switch (wr->opcode) {
2759                         case IB_WR_RDMA_WRITE:
2760                         case IB_WR_RDMA_WRITE_WITH_IMM:
2761                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2762                                               wr->wr.rdma.rkey);
2763                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2764                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2765                                 break;
2766
2767                         default:
2768                                 break;
2769                         }
2770                         break;
2771
2772                 case IB_QPT_UD:
2773                 case IB_QPT_SMI:
2774                 case IB_QPT_GSI:
2775                         set_datagram_seg(seg, wr);
2776                         seg += sizeof(struct mlx5_wqe_datagram_seg);
2777                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2778                         if (unlikely((seg == qend)))
2779                                 seg = mlx5_get_send_wqe(qp, 0);
2780                         break;
2781
2782                 case MLX5_IB_QPT_REG_UMR:
2783                         if (wr->opcode != MLX5_IB_WR_UMR) {
2784                                 err = -EINVAL;
2785                                 mlx5_ib_warn(dev, "bad opcode\n");
2786                                 goto out;
2787                         }
2788                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2789                         ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2790                         set_reg_umr_segment(seg, wr);
2791                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2792                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2793                         if (unlikely((seg == qend)))
2794                                 seg = mlx5_get_send_wqe(qp, 0);
2795                         set_reg_mkey_segment(seg, wr);
2796                         seg += sizeof(struct mlx5_mkey_seg);
2797                         size += sizeof(struct mlx5_mkey_seg) / 16;
2798                         if (unlikely((seg == qend)))
2799                                 seg = mlx5_get_send_wqe(qp, 0);
2800                         break;
2801
2802                 default:
2803                         break;
2804                 }
2805
2806                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2807                         int uninitialized_var(sz);
2808
2809                         err = set_data_inl_seg(qp, wr, seg, &sz);
2810                         if (unlikely(err)) {
2811                                 mlx5_ib_warn(dev, "\n");
2812                                 *bad_wr = wr;
2813                                 goto out;
2814                         }
2815                         inl = 1;
2816                         size += sz;
2817                 } else {
2818                         dpseg = seg;
2819                         for (i = 0; i < num_sge; i++) {
2820                                 if (unlikely(dpseg == qend)) {
2821                                         seg = mlx5_get_send_wqe(qp, 0);
2822                                         dpseg = seg;
2823                                 }
2824                                 if (likely(wr->sg_list[i].length)) {
2825                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
2826                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
2827                                         dpseg++;
2828                                 }
2829                         }
2830                 }
2831
2832                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
2833                            get_fence(fence, wr), next_fence,
2834                            mlx5_ib_opcode[wr->opcode]);
2835 skip_psv:
2836                 if (0)
2837                         dump_wqe(qp, idx, size);
2838         }
2839
2840 out:
2841         if (likely(nreq)) {
2842                 qp->sq.head += nreq;
2843
2844                 /* Make sure that descriptors are written before
2845                  * updating doorbell record and ringing the doorbell
2846                  */
2847                 wmb();
2848
2849                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2850
2851                 /* Make sure doorbell record is visible to the HCA before
2852                  * we hit doorbell */
2853                 wmb();
2854
2855                 if (bf->need_lock)
2856                         spin_lock(&bf->lock);
2857                 else
2858                         __acquire(&bf->lock);
2859
2860                 /* TBD enable WC */
2861                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2862                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2863                         /* wc_wmb(); */
2864                 } else {
2865                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2866                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2867                         /* Make sure doorbells don't leak out of SQ spinlock
2868                          * and reach the HCA out of order.
2869                          */
2870                         mmiowb();
2871                 }
2872                 bf->offset ^= bf->buf_size;
2873                 if (bf->need_lock)
2874                         spin_unlock(&bf->lock);
2875                 else
2876                         __release(&bf->lock);
2877         }
2878
2879         spin_unlock_irqrestore(&qp->sq.lock, flags);
2880
2881         return err;
2882 }
2883
2884 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2885 {
2886         sig->signature = calc_sig(sig, size);
2887 }
2888
2889 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2890                       struct ib_recv_wr **bad_wr)
2891 {
2892         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2893         struct mlx5_wqe_data_seg *scat;
2894         struct mlx5_rwqe_sig *sig;
2895         unsigned long flags;
2896         int err = 0;
2897         int nreq;
2898         int ind;
2899         int i;
2900
2901         spin_lock_irqsave(&qp->rq.lock, flags);
2902
2903         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2904
2905         for (nreq = 0; wr; nreq++, wr = wr->next) {
2906                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2907                         err = -ENOMEM;
2908                         *bad_wr = wr;
2909                         goto out;
2910                 }
2911
2912                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2913                         err = -EINVAL;
2914                         *bad_wr = wr;
2915                         goto out;
2916                 }
2917
2918                 scat = get_recv_wqe(qp, ind);
2919                 if (qp->wq_sig)
2920                         scat++;
2921
2922                 for (i = 0; i < wr->num_sge; i++)
2923                         set_data_ptr_seg(scat + i, wr->sg_list + i);
2924
2925                 if (i < qp->rq.max_gs) {
2926                         scat[i].byte_count = 0;
2927                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
2928                         scat[i].addr       = 0;
2929                 }
2930
2931                 if (qp->wq_sig) {
2932                         sig = (struct mlx5_rwqe_sig *)scat;
2933                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2934                 }
2935
2936                 qp->rq.wrid[ind] = wr->wr_id;
2937
2938                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2939         }
2940
2941 out:
2942         if (likely(nreq)) {
2943                 qp->rq.head += nreq;
2944
2945                 /* Make sure that descriptors are written before
2946                  * doorbell record.
2947                  */
2948                 wmb();
2949
2950                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2951         }
2952
2953         spin_unlock_irqrestore(&qp->rq.lock, flags);
2954
2955         return err;
2956 }
2957
2958 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2959 {
2960         switch (mlx5_state) {
2961         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
2962         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
2963         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
2964         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
2965         case MLX5_QP_STATE_SQ_DRAINING:
2966         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
2967         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
2968         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
2969         default:                     return -1;
2970         }
2971 }
2972
2973 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2974 {
2975         switch (mlx5_mig_state) {
2976         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
2977         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
2978         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2979         default: return -1;
2980         }
2981 }
2982
2983 static int to_ib_qp_access_flags(int mlx5_flags)
2984 {
2985         int ib_flags = 0;
2986
2987         if (mlx5_flags & MLX5_QP_BIT_RRE)
2988                 ib_flags |= IB_ACCESS_REMOTE_READ;
2989         if (mlx5_flags & MLX5_QP_BIT_RWE)
2990                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2991         if (mlx5_flags & MLX5_QP_BIT_RAE)
2992                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2993
2994         return ib_flags;
2995 }
2996
2997 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2998                                 struct mlx5_qp_path *path)
2999 {
3000         struct mlx5_core_dev *dev = ibdev->mdev;
3001
3002         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3003         ib_ah_attr->port_num      = path->port;
3004
3005         if (ib_ah_attr->port_num == 0 ||
3006             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
3007                 return;
3008
3009         ib_ah_attr->sl = path->sl & 0xf;
3010
3011         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3012         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3013         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3014         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3015         if (ib_ah_attr->ah_flags) {
3016                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3017                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3018                 ib_ah_attr->grh.traffic_class =
3019                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3020                 ib_ah_attr->grh.flow_label =
3021                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3022                 memcpy(ib_ah_attr->grh.dgid.raw,
3023                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3024         }
3025 }
3026
3027 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3028                      struct ib_qp_init_attr *qp_init_attr)
3029 {
3030         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3031         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3032         struct mlx5_query_qp_mbox_out *outb;
3033         struct mlx5_qp_context *context;
3034         int mlx5_state;
3035         int err = 0;
3036
3037 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3038         /*
3039          * Wait for any outstanding page faults, in case the user frees memory
3040          * based upon this query's result.
3041          */
3042         flush_workqueue(mlx5_ib_page_fault_wq);
3043 #endif
3044
3045         mutex_lock(&qp->mutex);
3046         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
3047         if (!outb) {
3048                 err = -ENOMEM;
3049                 goto out;
3050         }
3051         context = &outb->ctx;
3052         err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb));
3053         if (err)
3054                 goto out_free;
3055
3056         mlx5_state = be32_to_cpu(context->flags) >> 28;
3057
3058         qp->state                    = to_ib_qp_state(mlx5_state);
3059         qp_attr->qp_state            = qp->state;
3060         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
3061         qp_attr->path_mig_state      =
3062                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
3063         qp_attr->qkey                = be32_to_cpu(context->qkey);
3064         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
3065         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
3066         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
3067         qp_attr->qp_access_flags     =
3068                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
3069
3070         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3071                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
3072                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
3073                 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
3074                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3075         }
3076
3077         qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
3078         qp_attr->port_num = context->pri_path.port;
3079
3080         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3081         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
3082
3083         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
3084
3085         qp_attr->max_dest_rd_atomic =
3086                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
3087         qp_attr->min_rnr_timer      =
3088                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
3089         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
3090         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
3091         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
3092         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
3093         qp_attr->cur_qp_state        = qp_attr->qp_state;
3094         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3095         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3096
3097         if (!ibqp->uobject) {
3098                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3099                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3100         } else {
3101                 qp_attr->cap.max_send_wr  = 0;
3102                 qp_attr->cap.max_send_sge = 0;
3103         }
3104
3105         /* We don't support inline sends for kernel QPs (yet), and we
3106          * don't know what userspace's value should be.
3107          */
3108         qp_attr->cap.max_inline_data = 0;
3109
3110         qp_init_attr->cap            = qp_attr->cap;
3111
3112         qp_init_attr->create_flags = 0;
3113         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3114                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3115
3116         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
3117                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3118
3119 out_free:
3120         kfree(outb);
3121
3122 out:
3123         mutex_unlock(&qp->mutex);
3124         return err;
3125 }
3126
3127 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
3128                                           struct ib_ucontext *context,
3129                                           struct ib_udata *udata)
3130 {
3131         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3132         struct mlx5_ib_xrcd *xrcd;
3133         int err;
3134
3135         if (!MLX5_CAP_GEN(dev->mdev, xrc))
3136                 return ERR_PTR(-ENOSYS);
3137
3138         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3139         if (!xrcd)
3140                 return ERR_PTR(-ENOMEM);
3141
3142         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
3143         if (err) {
3144                 kfree(xrcd);
3145                 return ERR_PTR(-ENOMEM);
3146         }
3147
3148         return &xrcd->ibxrcd;
3149 }
3150
3151 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3152 {
3153         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3154         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3155         int err;
3156
3157         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
3158         if (err) {
3159                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3160                 return err;
3161         }
3162
3163         kfree(xrcd);
3164
3165         return 0;
3166 }