drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29 #include <linux/module.h>
  30 #include <linux/reset.h>
  31
  32 #include <asm/unaligned.h>
  33
  34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35 #define BYTES_PER_FIFO_WORD 4
  36
  37 #define I2C_CNFG                                0x000
  38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41 #define I2C_STATUS                              0x01C
  42 #define I2C_SL_CNFG                             0x020
  43 #define I2C_SL_CNFG_NACK                        (1<<1)
  44 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  45 #define I2C_SL_ADDR1                            0x02c
  46 #define I2C_SL_ADDR2                            0x030
  47 #define I2C_TX_FIFO                             0x050
  48 #define I2C_RX_FIFO                             0x054
  49 #define I2C_PACKET_TRANSFER_STATUS              0x058
  50 #define I2C_FIFO_CONTROL                        0x05c
  51 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  52 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  53 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  54 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  55 #define I2C_FIFO_STATUS                         0x060
  56 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  57 #define I2C_FIFO_STATUS_TX_SHIFT                4
  58 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  59 #define I2C_FIFO_STATUS_RX_SHIFT                0
  60 #define I2C_INT_MASK                            0x064
  61 #define I2C_INT_STATUS                          0x068
  62 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  63 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  64 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  65 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  66 #define I2C_INT_NO_ACK                          (1<<3)
  67 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  68 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  69 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  70 #define I2C_CLK_DIVISOR                         0x06c
  71 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  72 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  73
  74 #define DVC_CTRL_REG1                           0x000
  75 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  76 #define DVC_CTRL_REG2                           0x004
  77 #define DVC_CTRL_REG3                           0x008
  78 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  80 #define DVC_STATUS                              0x00c
  81 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  82
  83 #define I2C_ERR_NONE                            0x00
  84 #define I2C_ERR_NO_ACK                          0x01
  85 #define I2C_ERR_ARBITRATION_LOST                0x02
  86 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  87
  88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  89 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  90 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  91 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  92
  93 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  94 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  95 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  96 #define I2C_HEADER_READ                         (1<<19)
  97 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  98 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  99 #define I2C_HEADER_REPEAT_START                 (1<<16)
 100 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 101 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 102 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 103
 104 #define I2C_CONFIG_LOAD                         0x08C
 105 #define I2C_MSTR_CONFIG_LOAD                    (1 << 0)
 106 #define I2C_SLV_CONFIG_LOAD                     (1 << 1)
 107 #define I2C_TIMEOUT_CONFIG_LOAD                 (1 << 2)
 108
 109 /*
 110  * msg_end_type: The bus control which need to be send at end of transfer.
 111  * @MSG_END_STOP: Send stop pulse at end of transfer.
 112  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 113  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 114  *              stop or repeat start.
 115  */
 116 enum msg_end_type {
 117         MSG_END_STOP,
 118         MSG_END_REPEAT_START,
 119         MSG_END_CONTINUE,
 120 };
 121
 122 /**
 123  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 124  * @has_continue_xfer_support: Continue transfer supports.
 125  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 126  *              complete interrupt per packet basis.
 127  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 128  *              and earlier Socs has two clock sources i.e. div-clk and
 129  *              fast-clk.
 130  * @has_config_load_reg: Has the config load register to load the new
 131  *              configuration.
 132  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 133  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 134  *              applicable if there is no fast clock source i.e. single clock
 135  *              source.
 136  */
 137
 138 struct tegra_i2c_hw_feature {
 139         bool has_continue_xfer_support;
 140         bool has_per_pkt_xfer_complete_irq;
 141         bool has_single_clk_source;
 142         bool has_config_load_reg;
 143         int clk_divisor_hs_mode;
 144         int clk_divisor_std_fast_mode;
 145 };
 146
 147 /**
 148  * struct tegra_i2c_dev - per device i2c context
 149  * @dev: device reference for power management
 150  * @hw: Tegra i2c hw feature.
 151  * @adapter: core i2c layer adapter information
 152  * @div_clk: clock reference for div clock of i2c controller.
 153  * @fast_clk: clock reference for fast clock of i2c controller.
 154  * @base: ioremapped registers cookie
 155  * @cont_id: i2c controller id, used for for packet header
 156  * @irq: irq number of transfer complete interrupt
 157  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 158  * @msg_complete: transfer completion notifier
 159  * @msg_err: error code for completed message
 160  * @msg_buf: pointer to current message data
 161  * @msg_buf_remaining: size of unsent data in the message buffer
 162  * @msg_read: identifies read transfers
 163  * @bus_clk_rate: current i2c bus clock rate
 164  * @is_suspended: prevents i2c controller accesses after suspend is called
 165  */
 166 struct tegra_i2c_dev {
 167         struct device *dev;
 168         const struct tegra_i2c_hw_feature *hw;
 169         struct i2c_adapter adapter;
 170         struct clk *div_clk;
 171         struct clk *fast_clk;
 172         struct reset_control *rst;
 173         void __iomem *base;
 174         int cont_id;
 175         int irq;
 176         bool irq_disabled;
 177         int is_dvc;
 178         struct completion msg_complete;
 179         int msg_err;
 180         u8 *msg_buf;
 181         size_t msg_buf_remaining;
 182         int msg_read;
 183         u32 bus_clk_rate;
 184         bool is_suspended;
 185 };
 186
 187 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 188 {
 189         writel(val, i2c_dev->base + reg);
 190 }
 191
 192 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 193 {
 194         return readl(i2c_dev->base + reg);
 195 }
 196
 197 /*
 198  * i2c_writel and i2c_readl will offset the register if necessary to talk
 199  * to the I2C block inside the DVC block
 200  */
 201 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 202         unsigned long reg)
 203 {
 204         if (i2c_dev->is_dvc)
 205                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 206         return reg;
 207 }
 208
 209 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 210         unsigned long reg)
 211 {
 212         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 213
 214         /* Read back register to make sure that register writes completed */
 215         if (reg != I2C_TX_FIFO)
 216                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 217 }
 218
 219 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 220 {
 221         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 222 }
 223
 224 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 225         unsigned long reg, int len)
 226 {
 227         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 228 }
 229
 230 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 231         unsigned long reg, int len)
 232 {
 233         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 234 }
 235
 236 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 237 {
 238         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 239         int_mask &= ~mask;
 240         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 241 }
 242
 243 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 244 {
 245         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 246         int_mask |= mask;
 247         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 248 }
 249
 250 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 251 {
 252         unsigned long timeout = jiffies + HZ;
 253         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 254         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 255         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 256
 257         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 258                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 259                 if (time_after(jiffies, timeout)) {
 260                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 261                         return -ETIMEDOUT;
 262                 }
 263                 msleep(1);
 264         }
 265         return 0;
 266 }
 267
 268 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 269 {
 270         u32 val;
 271         int rx_fifo_avail;
 272         u8 *buf = i2c_dev->msg_buf;
 273         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 274         int words_to_transfer;
 275
 276         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 277         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 278                 I2C_FIFO_STATUS_RX_SHIFT;
 279
 280         /* Rounds down to not include partial word at the end of buf */
 281         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 282         if (words_to_transfer > rx_fifo_avail)
 283                 words_to_transfer = rx_fifo_avail;
 284
 285         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 286
 287         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 288         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 289         rx_fifo_avail -= words_to_transfer;
 290
 291         /*
 292          * If there is a partial word at the end of buf, handle it manually to
 293          * prevent overwriting past the end of buf
 294          */
 295         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 296                 BUG_ON(buf_remaining > 3);
 297                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 298                 val = cpu_to_le32(val);
 299                 memcpy(buf, &val, buf_remaining);
 300                 buf_remaining = 0;
 301                 rx_fifo_avail--;
 302         }
 303
 304         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 305         i2c_dev->msg_buf_remaining = buf_remaining;
 306         i2c_dev->msg_buf = buf;
 307         return 0;
 308 }
 309
 310 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 311 {
 312         u32 val;
 313         int tx_fifo_avail;
 314         u8 *buf = i2c_dev->msg_buf;
 315         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 316         int words_to_transfer;
 317
 318         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 319         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 320                 I2C_FIFO_STATUS_TX_SHIFT;
 321
 322         /* Rounds down to not include partial word at the end of buf */
 323         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 324
 325         /* It's very common to have < 4 bytes, so optimize that case. */
 326         if (words_to_transfer) {
 327                 if (words_to_transfer > tx_fifo_avail)
 328                         words_to_transfer = tx_fifo_avail;
 329
 330                 /*
 331                  * Update state before writing to FIFO.  If this casues us
 332                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 333                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 334                  * not maskable).  We need to make sure that the isr sees
 335                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 336                  */
 337                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 338                 tx_fifo_avail -= words_to_transfer;
 339                 i2c_dev->msg_buf_remaining = buf_remaining;
 340                 i2c_dev->msg_buf = buf +
 341                         words_to_transfer * BYTES_PER_FIFO_WORD;
 342                 barrier();
 343
 344                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 345
 346                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 347         }
 348
 349         /*
 350          * If there is a partial word at the end of buf, handle it manually to
 351          * prevent reading past the end of buf, which could cross a page
 352          * boundary and fault.
 353          */
 354         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 355                 BUG_ON(buf_remaining > 3);
 356                 memcpy(&val, buf, buf_remaining);
 357                 val = le32_to_cpu(val);
 358
 359                 /* Again update before writing to FIFO to make sure isr sees. */
 360                 i2c_dev->msg_buf_remaining = 0;
 361                 i2c_dev->msg_buf = NULL;
 362                 barrier();
 363
 364                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 365         }
 366
 367         return 0;
 368 }
 369
 370 /*
 371  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 372  * block.  This block is identical to the rest of the I2C blocks, except that
 373  * it only supports master mode, it has registers moved around, and it needs
 374  * some extra init to get it into I2C mode.  The register moves are handled
 375  * by i2c_readl and i2c_writel
 376  */
 377 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 378 {
 379         u32 val = 0;
 380         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 381         val |= DVC_CTRL_REG3_SW_PROG;
 382         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 383         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 384
 385         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 386         val |= DVC_CTRL_REG1_INTR_EN;
 387         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 388 }
 389
 390 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 391 {
 392         int ret;
 393         if (!i2c_dev->hw->has_single_clk_source) {
 394                 ret = clk_enable(i2c_dev->fast_clk);
 395                 if (ret < 0) {
 396                         dev_err(i2c_dev->dev,
 397                                 "Enabling fast clk failed, err %d\n", ret);
 398                         return ret;
 399                 }
 400         }
 401         ret = clk_enable(i2c_dev->div_clk);
 402         if (ret < 0) {
 403                 dev_err(i2c_dev->dev,
 404                         "Enabling div clk failed, err %d\n", ret);
 405                 clk_disable(i2c_dev->fast_clk);
 406         }
 407         return ret;
 408 }
 409
 410 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 411 {
 412         clk_disable(i2c_dev->div_clk);
 413         if (!i2c_dev->hw->has_single_clk_source)
 414                 clk_disable(i2c_dev->fast_clk);
 415 }
 416
 417 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 418 {
 419         u32 val;
 420         int err = 0;
 421         u32 clk_divisor;
 422         unsigned long timeout = jiffies + HZ;
 423
 424         err = tegra_i2c_clock_enable(i2c_dev);
 425         if (err < 0) {
 426                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
 427                 return err;
 428         }
 429
 430         reset_control_assert(i2c_dev->rst);
 431         udelay(2);
 432         reset_control_deassert(i2c_dev->rst);
 433
 434         if (i2c_dev->is_dvc)
 435                 tegra_dvc_init(i2c_dev);
 436
 437         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 438                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 439         i2c_writel(i2c_dev, val, I2C_CNFG);
 440         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 441
 442         /* Make sure clock divisor programmed correctly */
 443         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 444         clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
 445                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 446         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 447
 448         if (!i2c_dev->is_dvc) {
 449                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 450                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 451                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 452                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 453                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 454
 455         }
 456
 457         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 458                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 459         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 460
 461         if (tegra_i2c_flush_fifos(i2c_dev))
 462                 err = -ETIMEDOUT;
 463
 464         if (i2c_dev->hw->has_config_load_reg) {
 465                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 466                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
 467                         if (time_after(jiffies, timeout)) {
 468                                 dev_warn(i2c_dev->dev,
 469                                         "timeout waiting for config load\n");
 470                                 return -ETIMEDOUT;
 471                         }
 472                         msleep(1);
 473                 }
 474         }
 475
 476         tegra_i2c_clock_disable(i2c_dev);
 477
 478         if (i2c_dev->irq_disabled) {
 479                 i2c_dev->irq_disabled = 0;
 480                 enable_irq(i2c_dev->irq);
 481         }
 482
 483         return err;
 484 }
 485
 486 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 487 {
 488         u32 status;
 489         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 490         struct tegra_i2c_dev *i2c_dev = dev_id;
 491
 492         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 493
 494         if (status == 0) {
 495                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 496                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 497                          i2c_readl(i2c_dev, I2C_STATUS),
 498                          i2c_readl(i2c_dev, I2C_CNFG));
 499                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 500
 501                 if (!i2c_dev->irq_disabled) {
 502                         disable_irq_nosync(i2c_dev->irq);
 503                         i2c_dev->irq_disabled = 1;
 504                 }
 505                 goto err;
 506         }
 507
 508         if (unlikely(status & status_err)) {
 509                 if (status & I2C_INT_NO_ACK)
 510                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 511                 if (status & I2C_INT_ARBITRATION_LOST)
 512                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 513                 goto err;
 514         }
 515
 516         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 517                 if (i2c_dev->msg_buf_remaining)
 518                         tegra_i2c_empty_rx_fifo(i2c_dev);
 519                 else
 520                         BUG();
 521         }
 522
 523         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 524                 if (i2c_dev->msg_buf_remaining)
 525                         tegra_i2c_fill_tx_fifo(i2c_dev);
 526                 else
 527                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 528         }
 529
 530         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 531         if (i2c_dev->is_dvc)
 532                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 533
 534         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 535                 BUG_ON(i2c_dev->msg_buf_remaining);
 536                 complete(&i2c_dev->msg_complete);
 537         }
 538         return IRQ_HANDLED;
 539 err:
 540         /* An error occurred, mask all interrupts */
 541         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 542                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 543                 I2C_INT_RX_FIFO_DATA_REQ);
 544         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 545         if (i2c_dev->is_dvc)
 546                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 547
 548         complete(&i2c_dev->msg_complete);
 549         return IRQ_HANDLED;
 550 }
 551
 552 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 553         struct i2c_msg *msg, enum msg_end_type end_state)
 554 {
 555         u32 packet_header;
 556         u32 int_mask;
 557         unsigned long time_left;
 558
 559         tegra_i2c_flush_fifos(i2c_dev);
 560
 561         if (msg->len == 0)
 562                 return -EINVAL;
 563
 564         i2c_dev->msg_buf = msg->buf;
 565         i2c_dev->msg_buf_remaining = msg->len;
 566         i2c_dev->msg_err = I2C_ERR_NONE;
 567         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 568         reinit_completion(&i2c_dev->msg_complete);
 569
 570         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 571                         PACKET_HEADER0_PROTOCOL_I2C |
 572                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 573                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 574         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 575
 576         packet_header = msg->len - 1;
 577         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 578
 579         packet_header = I2C_HEADER_IE_ENABLE;
 580         if (end_state == MSG_END_CONTINUE)
 581                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 582         else if (end_state == MSG_END_REPEAT_START)
 583                 packet_header |= I2C_HEADER_REPEAT_START;
 584         if (msg->flags & I2C_M_TEN) {
 585                 packet_header |= msg->addr;
 586                 packet_header |= I2C_HEADER_10BIT_ADDR;
 587         } else {
 588                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 589         }
 590         if (msg->flags & I2C_M_IGNORE_NAK)
 591                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 592         if (msg->flags & I2C_M_RD)
 593                 packet_header |= I2C_HEADER_READ;
 594         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 595
 596         if (!(msg->flags & I2C_M_RD))
 597                 tegra_i2c_fill_tx_fifo(i2c_dev);
 598
 599         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 600         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 601                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 602         if (msg->flags & I2C_M_RD)
 603                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 604         else if (i2c_dev->msg_buf_remaining)
 605                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 606         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 607         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 608                 i2c_readl(i2c_dev, I2C_INT_MASK));
 609
 610         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 611                                                 TEGRA_I2C_TIMEOUT);
 612         tegra_i2c_mask_irq(i2c_dev, int_mask);
 613
 614         if (time_left == 0) {
 615                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 616
 617                 tegra_i2c_init(i2c_dev);
 618                 return -ETIMEDOUT;
 619         }
 620
 621         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
 622                 time_left, completion_done(&i2c_dev->msg_complete),
 623                 i2c_dev->msg_err);
 624
 625         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 626                 return 0;
 627
 628         /*
 629          * NACK interrupt is generated before the I2C controller generates the
 630          * STOP condition on the bus. So wait for 2 clock periods before resetting
 631          * the controller so that STOP condition has been delivered properly.
 632          */
 633         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 634                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 635
 636         tegra_i2c_init(i2c_dev);
 637         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 638                 if (msg->flags & I2C_M_IGNORE_NAK)
 639                         return 0;
 640                 return -EREMOTEIO;
 641         }
 642
 643         return -EIO;
 644 }
 645
 646 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 647         int num)
 648 {
 649         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 650         int i;
 651         int ret = 0;
 652
 653         if (i2c_dev->is_suspended)
 654                 return -EBUSY;
 655
 656         ret = tegra_i2c_clock_enable(i2c_dev);
 657         if (ret < 0) {
 658                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
 659                 return ret;
 660         }
 661
 662         for (i = 0; i < num; i++) {
 663                 enum msg_end_type end_type = MSG_END_STOP;
 664                 if (i < (num - 1)) {
 665                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 666                                 end_type = MSG_END_CONTINUE;
 667                         else
 668                                 end_type = MSG_END_REPEAT_START;
 669                 }
 670                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 671                 if (ret)
 672                         break;
 673         }
 674         tegra_i2c_clock_disable(i2c_dev);
 675         return ret ?: i;
 676 }
 677
 678 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 679 {
 680         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 681         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 682                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
 683
 684         if (i2c_dev->hw->has_continue_xfer_support)
 685                 ret |= I2C_FUNC_NOSTART;
 686         return ret;
 687 }
 688
 689 static const struct i2c_algorithm tegra_i2c_algo = {
 690         .master_xfer    = tegra_i2c_xfer,
 691         .functionality  = tegra_i2c_func,
 692 };
 693
 694 /* payload size is only 12 bit */
 695 static struct i2c_adapter_quirks tegra_i2c_quirks = {
 696         .max_read_len = 4096,
 697         .max_write_len = 4096,
 698 };
 699
 700 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 701         .has_continue_xfer_support = false,
 702         .has_per_pkt_xfer_complete_irq = false,
 703         .has_single_clk_source = false,
 704         .clk_divisor_hs_mode = 3,
 705         .clk_divisor_std_fast_mode = 0,
 706         .has_config_load_reg = false,
 707 };
 708
 709 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 710         .has_continue_xfer_support = true,
 711         .has_per_pkt_xfer_complete_irq = false,
 712         .has_single_clk_source = false,
 713         .clk_divisor_hs_mode = 3,
 714         .clk_divisor_std_fast_mode = 0,
 715         .has_config_load_reg = false,
 716 };
 717
 718 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 719         .has_continue_xfer_support = true,
 720         .has_per_pkt_xfer_complete_irq = true,
 721         .has_single_clk_source = true,
 722         .clk_divisor_hs_mode = 1,
 723         .clk_divisor_std_fast_mode = 0x19,
 724         .has_config_load_reg = false,
 725 };
 726
 727 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
 728         .has_continue_xfer_support = true,
 729         .has_per_pkt_xfer_complete_irq = true,
 730         .has_single_clk_source = true,
 731         .clk_divisor_hs_mode = 1,
 732         .clk_divisor_std_fast_mode = 0x19,
 733         .has_config_load_reg = true,
 734 };
 735
 736 /* Match table for of_platform binding */
 737 static const struct of_device_id tegra_i2c_of_match[] = {
 738         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 739         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 740         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 741         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 742         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 743         {},
 744 };
 745 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 746
 747 static int tegra_i2c_probe(struct platform_device *pdev)
 748 {
 749         struct tegra_i2c_dev *i2c_dev;
 750         struct resource *res;
 751         struct clk *div_clk;
 752         struct clk *fast_clk;
 753         void __iomem *base;
 754         int irq;
 755         int ret = 0;
 756         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 757
 758         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 759         base = devm_ioremap_resource(&pdev->dev, res);
 760         if (IS_ERR(base))
 761                 return PTR_ERR(base);
 762
 763         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 764         if (!res) {
 765                 dev_err(&pdev->dev, "no irq resource\n");
 766                 return -EINVAL;
 767         }
 768         irq = res->start;
 769
 770         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 771         if (IS_ERR(div_clk)) {
 772                 dev_err(&pdev->dev, "missing controller clock");
 773                 return PTR_ERR(div_clk);
 774         }
 775
 776         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 777         if (!i2c_dev)
 778                 return -ENOMEM;
 779
 780         i2c_dev->base = base;
 781         i2c_dev->div_clk = div_clk;
 782         i2c_dev->adapter.algo = &tegra_i2c_algo;
 783         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
 784         i2c_dev->irq = irq;
 785         i2c_dev->cont_id = pdev->id;
 786         i2c_dev->dev = &pdev->dev;
 787
 788         i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
 789         if (IS_ERR(i2c_dev->rst)) {
 790                 dev_err(&pdev->dev, "missing controller reset");
 791                 return PTR_ERR(i2c_dev->rst);
 792         }
 793
 794         ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
 795                                         &i2c_dev->bus_clk_rate);
 796         if (ret)
 797                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 798
 799         i2c_dev->hw = &tegra20_i2c_hw;
 800
 801         if (pdev->dev.of_node) {
 802                 const struct of_device_id *match;
 803                 match = of_match_device(tegra_i2c_of_match, &pdev->dev);
 804                 i2c_dev->hw = match->data;
 805                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 806                                                 "nvidia,tegra20-i2c-dvc");
 807         } else if (pdev->id == 3) {
 808                 i2c_dev->is_dvc = 1;
 809         }
 810         init_completion(&i2c_dev->msg_complete);
 811
 812         if (!i2c_dev->hw->has_single_clk_source) {
 813                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 814                 if (IS_ERR(fast_clk)) {
 815                         dev_err(&pdev->dev, "missing fast clock");
 816                         return PTR_ERR(fast_clk);
 817                 }
 818                 i2c_dev->fast_clk = fast_clk;
 819         }
 820
 821         platform_set_drvdata(pdev, i2c_dev);
 822
 823         if (!i2c_dev->hw->has_single_clk_source) {
 824                 ret = clk_prepare(i2c_dev->fast_clk);
 825                 if (ret < 0) {
 826                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 827                         return ret;
 828                 }
 829         }
 830
 831         clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
 832         ret = clk_set_rate(i2c_dev->div_clk,
 833                            i2c_dev->bus_clk_rate * clk_multiplier);
 834         if (ret) {
 835                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
 836                 goto unprepare_fast_clk;
 837         }
 838
 839         ret = clk_prepare(i2c_dev->div_clk);
 840         if (ret < 0) {
 841                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 842                 goto unprepare_fast_clk;
 843         }
 844
 845         ret = tegra_i2c_init(i2c_dev);
 846         if (ret) {
 847                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 848                 goto unprepare_div_clk;
 849         }
 850
 851         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 852                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 853         if (ret) {
 854                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 855                 goto unprepare_div_clk;
 856         }
 857
 858         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 859         i2c_dev->adapter.owner = THIS_MODULE;
 860         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
 861         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 862                 sizeof(i2c_dev->adapter.name));
 863         i2c_dev->adapter.algo = &tegra_i2c_algo;
 864         i2c_dev->adapter.dev.parent = &pdev->dev;
 865         i2c_dev->adapter.nr = pdev->id;
 866         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 867
 868         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 869         if (ret) {
 870                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 871                 goto unprepare_div_clk;
 872         }
 873
 874         return 0;
 875
 876 unprepare_div_clk:
 877         clk_unprepare(i2c_dev->div_clk);
 878
 879 unprepare_fast_clk:
 880         if (!i2c_dev->hw->has_single_clk_source)
 881                 clk_unprepare(i2c_dev->fast_clk);
 882
 883         return ret;
 884 }
 885
 886 static int tegra_i2c_remove(struct platform_device *pdev)
 887 {
 888         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 889         i2c_del_adapter(&i2c_dev->adapter);
 890
 891         clk_unprepare(i2c_dev->div_clk);
 892         if (!i2c_dev->hw->has_single_clk_source)
 893                 clk_unprepare(i2c_dev->fast_clk);
 894
 895         return 0;
 896 }
 897
 898 #ifdef CONFIG_PM_SLEEP
 899 static int tegra_i2c_suspend(struct device *dev)
 900 {
 901         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 902
 903         i2c_lock_adapter(&i2c_dev->adapter);
 904         i2c_dev->is_suspended = true;
 905         i2c_unlock_adapter(&i2c_dev->adapter);
 906
 907         return 0;
 908 }
 909
 910 static int tegra_i2c_resume(struct device *dev)
 911 {
 912         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 913         int ret;
 914
 915         i2c_lock_adapter(&i2c_dev->adapter);
 916
 917         ret = tegra_i2c_init(i2c_dev);
 918
 919         if (ret) {
 920                 i2c_unlock_adapter(&i2c_dev->adapter);
 921                 return ret;
 922         }
 923
 924         i2c_dev->is_suspended = false;
 925
 926         i2c_unlock_adapter(&i2c_dev->adapter);
 927
 928         return 0;
 929 }
 930
 931 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
 932 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
 933 #else
 934 #define TEGRA_I2C_PM    NULL
 935 #endif
 936
 937 static struct platform_driver tegra_i2c_driver = {
 938         .probe   = tegra_i2c_probe,
 939         .remove  = tegra_i2c_remove,
 940         .driver  = {
 941                 .name  = "tegra-i2c",
 942                 .of_match_table = tegra_i2c_of_match,
 943                 .pm    = TEGRA_I2C_PM,
 944         },
 945 };
 946
 947 static int __init tegra_i2c_init_driver(void)
 948 {
 949         return platform_driver_register(&tegra_i2c_driver);
 950 }
 951
 952 static void __exit tegra_i2c_exit_driver(void)
 953 {
 954         platform_driver_unregister(&tegra_i2c_driver);
 955 }
 956
 957 subsys_initcall(tegra_i2c_init_driver);
 958 module_exit(tegra_i2c_exit_driver);
 959
 960 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 961 MODULE_AUTHOR("Colin Cross");
 962 MODULE_LICENSE("GPL v2");