drivers/i2c/busses/i2c-rk3x.c

   1 /*
   2  * Driver for I2C adapter in Rockchip RK3xxx SoC
   3  *
   4  * Max Schwarz <max.schwarz@online.de>
   5  * based on the patches by Rockchip Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/i2c.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/io.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/clk.h>
  24 #include <linux/wait.h>
  25 #include <linux/mfd/syscon.h>
  26 #include <linux/regmap.h>
  27 #include <linux/math64.h>
  28 #include <linux/property.h>
  29
  30
  31 /* Register Map */
  32 #define REG_CON        0x00 /* control register */
  33 #define REG_CLKDIV     0x04 /* clock divisor register */
  34 #define REG_MRXADDR    0x08 /* slave address for REGISTER_TX */
  35 #define REG_MRXRADDR   0x0c /* slave register address for REGISTER_TX */
  36 #define REG_MTXCNT     0x10 /* number of bytes to be transmitted */
  37 #define REG_MRXCNT     0x14 /* number of bytes to be received */
  38 #define REG_IEN        0x18 /* interrupt enable */
  39 #define REG_IPD        0x1c /* interrupt pending */
  40 #define REG_FCNT       0x20 /* finished count */
  41
  42 /* Data buffer offsets */
  43 #define TXBUFFER_BASE 0x100
  44 #define RXBUFFER_BASE 0x200
  45
  46 /* REG_CON bits */
  47 #define REG_CON_EN        BIT(0)
  48 enum {
  49         REG_CON_MOD_TX = 0,      /* transmit data */
  50         REG_CON_MOD_REGISTER_TX, /* select register and restart */
  51         REG_CON_MOD_RX,          /* receive data */
  52         REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
  53                                   * register addr */
  54 };
  55 #define REG_CON_MOD(mod)  ((mod) << 1)
  56 #define REG_CON_MOD_MASK  (BIT(1) | BIT(2))
  57 #define REG_CON_START     BIT(3)
  58 #define REG_CON_STOP      BIT(4)
  59 #define REG_CON_LASTACK   BIT(5) /* 1: send NACK after last received byte */
  60 #define REG_CON_ACTACK    BIT(6) /* 1: stop if NACK is received */
  61
  62 #define REG_CON_SDA_CNT(cnt)  ((cnt) << 8)
  63 #define REG_CON_STA_CNT(cnt)  ((cnt) << 12)
  64 #define REG_CON_STO_CNT(cnt)  ((cnt) << 14)
  65
  66 /* REG_MRXADDR bits */
  67 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
  68
  69 /* REG_IEN/REG_IPD bits */
  70 #define REG_INT_BTF       BIT(0) /* a byte was transmitted */
  71 #define REG_INT_BRF       BIT(1) /* a byte was received */
  72 #define REG_INT_MBTF      BIT(2) /* master data transmit finished */
  73 #define REG_INT_MBRF      BIT(3) /* master data receive finished */
  74 #define REG_INT_START     BIT(4) /* START condition generated */
  75 #define REG_INT_STOP      BIT(5) /* STOP condition generated */
  76 #define REG_INT_NAKRCV    BIT(6) /* NACK received */
  77 #define REG_INT_ALL       0x7f
  78
  79 /* Constants */
  80 #define WAIT_TIMEOUT      1000 /* ms */
  81 #define DEFAULT_SCL_RATE  (100 * 1000) /* Hz */
  82
  83 enum rk3x_i2c_state {
  84         STATE_IDLE,
  85         STATE_START,
  86         STATE_READ,
  87         STATE_WRITE,
  88         STATE_STOP
  89 };
  90
  91 struct rk3x_i2c;
  92
  93 /**
  94  * struct rk3x_i2c_calced_timings:
  95  * @div_low: Divider output for low
  96  * @div_high: Divider output for high
  97  * @sda_update_cfg: Used to config sda change state when scl is low,
  98  * used to adjust setup/hold time
  99  * @stp_sta_cfg: Start setup config for setup start time and hold start time
 100  * @stp_sto_cfg: Stop setup config for setup stop time
 101  */
 102 struct rk3x_i2c_calced_timings {
 103         unsigned long div_low;
 104         unsigned long div_high;
 105         unsigned int sda_update_cfg;
 106         unsigned int stp_sta_cfg;
 107         unsigned int stp_sto_cfg;
 108 };
 109
 110 /**
 111  * @grf_offset: offset inside the grf regmap for setting the i2c type
 112  */
 113 struct rk3x_i2c_soc_data {
 114         int grf_offset;
 115
 116         int (*clk_init)(struct rk3x_i2c *, unsigned long *);
 117         int (*calc_timings)(unsigned long, struct i2c_timings *,
 118                             struct rk3x_i2c_calced_timings *);
 119 };
 120
 121 struct rk3x_i2c {
 122         struct i2c_adapter adap;
 123         struct device *dev;
 124         struct rk3x_i2c_soc_data *soc_data;
 125
 126         /* Hardware resources */
 127         void __iomem *regs;
 128         struct clk *pclk; /* APB clock */
 129         struct clk *clk; /* Func clk for rk3399 or Func & APB clks for others */
 130         struct notifier_block clk_rate_nb;
 131
 132         /* Settings */
 133         struct i2c_timings t;
 134         struct rk3x_i2c_calced_timings t_calc;
 135
 136         /* Synchronization & notification */
 137         spinlock_t lock;
 138         wait_queue_head_t wait;
 139         bool busy;
 140
 141         /* Current message */
 142         struct i2c_msg *msg;
 143         u8 addr;
 144         unsigned int mode;
 145         bool is_last_msg;
 146
 147         /* I2C state machine */
 148         enum rk3x_i2c_state state;
 149         unsigned int processed; /* sent/received bytes */
 150         int error;
 151 };
 152
 153 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
 154                               unsigned int offset)
 155 {
 156         writel(value, i2c->regs + offset);
 157 }
 158
 159 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
 160 {
 161         return readl(i2c->regs + offset);
 162 }
 163
 164 static inline u32 rk3x_i2c_get_con_count(struct rk3x_i2c *i2c)
 165 {
 166         return REG_CON_SDA_CNT(i2c->t_calc.sda_update_cfg) |
 167                REG_CON_STA_CNT(i2c->t_calc.stp_sta_cfg) |
 168                REG_CON_STO_CNT(i2c->t_calc.stp_sto_cfg);
 169 }
 170
 171 /* Reset all interrupt pending bits */
 172 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
 173 {
 174         i2c_writel(i2c, REG_INT_ALL, REG_IPD);
 175 }
 176
 177 /**
 178  * Generate a START condition, which triggers a REG_INT_START interrupt.
 179  */
 180 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
 181 {
 182         u32 val = rk3x_i2c_get_con_count(i2c);
 183
 184         rk3x_i2c_clean_ipd(i2c);
 185         i2c_writel(i2c, REG_INT_START, REG_IEN);
 186
 187         /* enable adapter with correct mode, send START condition */
 188         val = val | REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
 189
 190         /* if we want to react to NACK, set ACTACK bit */
 191         if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
 192                 val |= REG_CON_ACTACK;
 193
 194         i2c_writel(i2c, val, REG_CON);
 195 }
 196
 197 /**
 198  * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
 199  *
 200  * @error: Error code to return in rk3x_i2c_xfer
 201  */
 202 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
 203 {
 204         unsigned int ctrl;
 205
 206         i2c->processed = 0;
 207         i2c->msg = NULL;
 208         i2c->error = error;
 209
 210         if (i2c->is_last_msg) {
 211                 /* Enable stop interrupt */
 212                 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
 213
 214                 i2c->state = STATE_STOP;
 215
 216                 ctrl = i2c_readl(i2c, REG_CON);
 217                 ctrl |= REG_CON_STOP;
 218                 i2c_writel(i2c, ctrl, REG_CON);
 219         } else {
 220                 /* Signal rk3x_i2c_xfer to start the next message. */
 221                 i2c->busy = false;
 222                 i2c->state = STATE_IDLE;
 223
 224                 /*
 225                  * The HW is actually not capable of REPEATED START. But we can
 226                  * get the intended effect by resetting its internal state
 227                  * and issuing an ordinary START.
 228                  */
 229                 i2c_writel(i2c, rk3x_i2c_get_con_count(i2c), REG_CON);
 230
 231                 /* signal that we are finished with the current msg */
 232                 wake_up(&i2c->wait);
 233         }
 234 }
 235
 236 /**
 237  * Setup a read according to i2c->msg
 238  */
 239 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
 240 {
 241         unsigned int len = i2c->msg->len - i2c->processed;
 242         u32 con;
 243
 244         con = i2c_readl(i2c, REG_CON);
 245
 246         /*
 247          * The hw can read up to 32 bytes at a time. If we need more than one
 248          * chunk, send an ACK after the last byte of the current chunk.
 249          */
 250         if (len > 32) {
 251                 len = 32;
 252                 con &= ~REG_CON_LASTACK;
 253         } else {
 254                 con |= REG_CON_LASTACK;
 255         }
 256
 257         /* make sure we are in plain RX mode if we read a second chunk */
 258         if (i2c->processed != 0) {
 259                 con &= ~REG_CON_MOD_MASK;
 260                 con |= REG_CON_MOD(REG_CON_MOD_RX);
 261         }
 262
 263         i2c_writel(i2c, con, REG_CON);
 264         i2c_writel(i2c, len, REG_MRXCNT);
 265 }
 266
 267 /**
 268  * Fill the transmit buffer with data from i2c->msg
 269  */
 270 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
 271 {
 272         unsigned int i, j;
 273         u32 cnt = 0;
 274         u32 val;
 275         u8 byte;
 276
 277         for (i = 0; i < 8; ++i) {
 278                 val = 0;
 279                 for (j = 0; j < 4; ++j) {
 280                         if ((i2c->processed == i2c->msg->len) && (cnt != 0))
 281                                 break;
 282
 283                         if (i2c->processed == 0 && cnt == 0)
 284                                 byte = (i2c->addr & 0x7f) << 1;
 285                         else
 286                                 byte = i2c->msg->buf[i2c->processed++];
 287
 288                         val |= byte << (j * 8);
 289                         cnt++;
 290                 }
 291
 292                 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
 293
 294                 if (i2c->processed == i2c->msg->len)
 295                         break;
 296         }
 297
 298         i2c_writel(i2c, cnt, REG_MTXCNT);
 299 }
 300
 301
 302 /* IRQ handlers for individual states */
 303
 304 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
 305 {
 306         if (!(ipd & REG_INT_START)) {
 307                 rk3x_i2c_stop(i2c, -EIO);
 308                 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
 309                 rk3x_i2c_clean_ipd(i2c);
 310                 return;
 311         }
 312
 313         /* ack interrupt */
 314         i2c_writel(i2c, REG_INT_START, REG_IPD);
 315
 316         /* disable start bit */
 317         i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
 318
 319         /* enable appropriate interrupts and transition */
 320         if (i2c->mode == REG_CON_MOD_TX) {
 321                 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
 322                 i2c->state = STATE_WRITE;
 323                 rk3x_i2c_fill_transmit_buf(i2c);
 324         } else {
 325                 /* in any other case, we are going to be reading. */
 326                 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
 327                 i2c->state = STATE_READ;
 328                 rk3x_i2c_prepare_read(i2c);
 329         }
 330 }
 331
 332 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
 333 {
 334         if (!(ipd & REG_INT_MBTF)) {
 335                 rk3x_i2c_stop(i2c, -EIO);
 336                 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
 337                 rk3x_i2c_clean_ipd(i2c);
 338                 return;
 339         }
 340
 341         /* ack interrupt */
 342         i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
 343
 344         /* are we finished? */
 345         if (i2c->processed == i2c->msg->len)
 346                 rk3x_i2c_stop(i2c, i2c->error);
 347         else
 348                 rk3x_i2c_fill_transmit_buf(i2c);
 349 }
 350
 351 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
 352 {
 353         unsigned int i;
 354         unsigned int len = i2c->msg->len - i2c->processed;
 355         u32 uninitialized_var(val);
 356         u8 byte;
 357
 358         /* we only care for MBRF here. */
 359         if (!(ipd & REG_INT_MBRF))
 360                 return;
 361
 362         /* ack interrupt */
 363         i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
 364
 365         /* Can only handle a maximum of 32 bytes at a time */
 366         if (len > 32)
 367                 len = 32;
 368
 369         /* read the data from receive buffer */
 370         for (i = 0; i < len; ++i) {
 371                 if (i % 4 == 0)
 372                         val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
 373
 374                 byte = (val >> ((i % 4) * 8)) & 0xff;
 375                 i2c->msg->buf[i2c->processed++] = byte;
 376         }
 377
 378         /* are we finished? */
 379         if (i2c->processed == i2c->msg->len)
 380                 rk3x_i2c_stop(i2c, i2c->error);
 381         else
 382                 rk3x_i2c_prepare_read(i2c);
 383 }
 384
 385 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
 386 {
 387         unsigned int con;
 388
 389         if (!(ipd & REG_INT_STOP)) {
 390                 rk3x_i2c_stop(i2c, -EIO);
 391                 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
 392                 rk3x_i2c_clean_ipd(i2c);
 393                 return;
 394         }
 395
 396         /* ack interrupt */
 397         i2c_writel(i2c, REG_INT_STOP, REG_IPD);
 398
 399         /* disable STOP bit */
 400         con = i2c_readl(i2c, REG_CON);
 401         con &= ~REG_CON_STOP;
 402         i2c_writel(i2c, con, REG_CON);
 403
 404         i2c->busy = false;
 405         i2c->state = STATE_IDLE;
 406
 407         /* signal rk3x_i2c_xfer that we are finished */
 408         wake_up(&i2c->wait);
 409 }
 410
 411 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
 412 {
 413         struct rk3x_i2c *i2c = dev_id;
 414         unsigned int ipd;
 415
 416         spin_lock(&i2c->lock);
 417
 418         ipd = i2c_readl(i2c, REG_IPD);
 419         if (i2c->state == STATE_IDLE) {
 420                 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
 421                 rk3x_i2c_clean_ipd(i2c);
 422                 goto out;
 423         }
 424
 425         dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
 426
 427         /* Clean interrupt bits we don't care about */
 428         ipd &= ~(REG_INT_BRF | REG_INT_BTF);
 429
 430         if (ipd & REG_INT_NAKRCV) {
 431                 /*
 432                  * We got a NACK in the last operation. Depending on whether
 433                  * IGNORE_NAK is set, we have to stop the operation and report
 434                  * an error.
 435                  */
 436                 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
 437
 438                 ipd &= ~REG_INT_NAKRCV;
 439
 440                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
 441                         rk3x_i2c_stop(i2c, -ENXIO);
 442         }
 443
 444         /* is there anything left to handle? */
 445         if ((ipd & REG_INT_ALL) == 0)
 446                 goto out;
 447
 448         switch (i2c->state) {
 449         case STATE_START:
 450                 rk3x_i2c_handle_start(i2c, ipd);
 451                 break;
 452         case STATE_WRITE:
 453                 rk3x_i2c_handle_write(i2c, ipd);
 454                 break;
 455         case STATE_READ:
 456                 rk3x_i2c_handle_read(i2c, ipd);
 457                 break;
 458         case STATE_STOP:
 459                 rk3x_i2c_handle_stop(i2c, ipd);
 460                 break;
 461         case STATE_IDLE:
 462                 break;
 463         }
 464
 465 out:
 466         spin_unlock(&i2c->lock);
 467         return IRQ_HANDLED;
 468 }
 469
 470 /**
 471  * Calculate timing values for desired SCL frequency
 472  *
 473  * @clk_rate: I2C input clock rate
 474  * @t: Known I2C timing information.
 475  * @div_low: Divider output for low
 476  * @div_high: Divider output for high
 477  * @t_calc: Caculated rk3x private timings  that would
 478  * be written into regs
 479  *
 480  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
 481  * a best-effort divider value is returned in divs. If the target rate is
 482  * too high, we silently use the highest possible rate.
 483  */
 484 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
 485                                     struct i2c_timings *t,
 486                                     struct rk3x_i2c_calced_timings *t_calc)
 487 {
 488         unsigned long spec_min_low_ns, spec_min_high_ns;
 489         unsigned long spec_setup_start, spec_max_data_hold_ns;
 490         unsigned long data_hold_buffer_ns;
 491
 492         unsigned long min_low_ns, min_high_ns;
 493         unsigned long max_low_ns, min_total_ns;
 494
 495         unsigned long clk_rate_khz, scl_rate_khz;
 496
 497         unsigned long min_low_div, min_high_div;
 498         unsigned long max_low_div;
 499
 500         unsigned long min_div_for_hold, min_total_div;
 501         unsigned long extra_div, extra_low_div, ideal_low_div;
 502
 503         int ret = 0;
 504
 505         /* Only support standard-mode and fast-mode */
 506         if (WARN_ON(t->bus_freq_hz > 400000))
 507                 t->bus_freq_hz = 400000;
 508
 509         /* prevent scl_rate_khz from becoming 0 */
 510         if (WARN_ON(t->bus_freq_hz < 1000))
 511                 t->bus_freq_hz = 1000;
 512
 513         /*
 514          * min_low_ns:  The minimum number of ns we need to hold low to
 515          *              meet I2C specification, should include fall time.
 516          * min_high_ns: The minimum number of ns we need to hold high to
 517          *              meet I2C specification, should include rise time.
 518          * max_low_ns:  The maximum number of ns we can hold low to meet
 519          *              I2C specification.
 520          *
 521          * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
 522          *       This is because the i2c host on Rockchip holds the data line
 523          *       for half the low time.
 524          */
 525         if (t->bus_freq_hz <= 100000) {
 526                 /* Standard-mode */
 527                 spec_min_low_ns = 4700;
 528                 spec_setup_start = 4700;
 529                 spec_min_high_ns = 4000;
 530                 spec_max_data_hold_ns = 3450;
 531                 data_hold_buffer_ns = 50;
 532         } else {
 533                 /* Fast-mode */
 534                 spec_min_low_ns = 1300;
 535                 spec_setup_start = 600;
 536                 spec_min_high_ns = 600;
 537                 spec_max_data_hold_ns = 900;
 538                 data_hold_buffer_ns = 50;
 539         }
 540         min_high_ns = t->scl_rise_ns + spec_min_high_ns;
 541
 542         /*
 543          * Timings for repeated start:
 544          * - controller appears to drop SDA at .875x (7/8) programmed clk high.
 545          * - controller appears to keep SCL high for 2x programmed clk high.
 546          *
 547          * We need to account for those rules in picking our "high" time so
 548          * we meet tSU;STA and tHD;STA times.
 549          */
 550         min_high_ns = max(min_high_ns,
 551                 DIV_ROUND_UP((t->scl_rise_ns + spec_setup_start) * 1000, 875));
 552         min_high_ns = max(min_high_ns,
 553                 DIV_ROUND_UP((t->scl_rise_ns + spec_setup_start +
 554                               t->sda_fall_ns + spec_min_high_ns), 2));
 555
 556         min_low_ns = t->scl_fall_ns + spec_min_low_ns;
 557         max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns;
 558         min_total_ns = min_low_ns + min_high_ns;
 559
 560         /* Adjust to avoid overflow */
 561         clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
 562         scl_rate_khz = t->bus_freq_hz / 1000;
 563
 564         /*
 565          * We need the total div to be >= this number
 566          * so we don't clock too fast.
 567          */
 568         min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
 569
 570         /* These are the min dividers needed for min hold times. */
 571         min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
 572         min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
 573         min_div_for_hold = (min_low_div + min_high_div);
 574
 575         /*
 576          * This is the maximum divider so we don't go over the maximum.
 577          * We don't round up here (we round down) since this is a maximum.
 578          */
 579         max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
 580
 581         if (min_low_div > max_low_div) {
 582                 WARN_ONCE(true,
 583                           "Conflicting, min_low_div %lu, max_low_div %lu\n",
 584                           min_low_div, max_low_div);
 585                 max_low_div = min_low_div;
 586         }
 587
 588         if (min_div_for_hold > min_total_div) {
 589                 /*
 590                  * Time needed to meet hold requirements is important.
 591                  * Just use that.
 592                  */
 593                 t_calc->div_low = min_low_div;
 594                 t_calc->div_high = min_high_div;
 595         } else {
 596                 /*
 597                  * We've got to distribute some time among the low and high
 598                  * so we don't run too fast.
 599                  */
 600                 extra_div = min_total_div - min_div_for_hold;
 601
 602                 /*
 603                  * We'll try to split things up perfectly evenly,
 604                  * biasing slightly towards having a higher div
 605                  * for low (spend more time low).
 606                  */
 607                 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
 608                                              scl_rate_khz * 8 * min_total_ns);
 609
 610                 /* Don't allow it to go over the maximum */
 611                 if (ideal_low_div > max_low_div)
 612                         ideal_low_div = max_low_div;
 613
 614                 /*
 615                  * Handle when the ideal low div is going to take up
 616                  * more than we have.
 617                  */
 618                 if (ideal_low_div > min_low_div + extra_div)
 619                         ideal_low_div = min_low_div + extra_div;
 620
 621                 /* Give low the "ideal" and give high whatever extra is left */
 622                 extra_low_div = ideal_low_div - min_low_div;
 623                 t_calc->div_low = ideal_low_div;
 624                 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
 625         }
 626
 627         /*
 628          * Adjust to the fact that the hardware has an implicit "+1".
 629          * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
 630          */
 631         t_calc->div_low -= 1;
 632         t_calc->div_high -=  1;
 633
 634         /* Maximum divider supported by hw is 0xffff */
 635         if (t_calc->div_low > 0xffff) {
 636                 t_calc->div_low = 0xffff;
 637                 ret = -EINVAL;
 638         }
 639
 640         if (t_calc->div_high > 0xffff) {
 641                 t_calc->div_high = 0xffff;
 642                 ret = -EINVAL;
 643         }
 644
 645         return ret;
 646 }
 647
 648 /**
 649  * Calculate timing values for desired SCL frequency
 650  *
 651  * @clk_rate: I2C input clock rate
 652  * @t: Known I2C timing information
 653  * @t_calc: Caculated rk3x private timings that would
 654  * be written into regs
 655  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
 656  * a best-effort divider value is returned in divs. If the target rate is
 657  * too high, we silently use the highest possible rate.
 658  * The following formulas are v1's method to calculate timings.
 659  *
 660  * l = divl + 1;
 661  * h = divh + 1;
 662  * s = sda_update_config + 1;
 663  * u = start_setup_config + 1;
 664  * p = stop_setup_config + 1;
 665  * T = Tclk_i2c;
 666
 667  * tHigh = 8 * h * T;
 668  * tLow = 8 * l * T;
 669
 670  * tHD;sda = (l * s + 1) * T;
 671  * tSU;sda = [(8 - s) * l + 1] * T;
 672  * tI2C = 8 * (l + h) * T;
 673
 674  * tSU;sta = (8h * u + 1) * T;
 675  * tHD;sta = [8h * (u + 1) - 1] * T;
 676  * tSU;sto = (8h * p + 1) * T;
 677  */
 678 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
 679                                     struct i2c_timings *t,
 680                                     struct rk3x_i2c_calced_timings *t_calc)
 681 {
 682         unsigned long spec_min_low_ns, spec_min_high_ns;
 683         unsigned long spec_min_setup_start_ns, spec_min_stop_setup_ns;
 684         unsigned long spec_min_data_setup_ns, spec_max_data_hold_ns;
 685
 686         unsigned long min_low_ns, min_high_ns, min_total_ns;
 687         unsigned long min_setup_start_ns, min_setup_data_ns;
 688         unsigned long min_stop_setup_ns, max_hold_data_ns;
 689
 690         unsigned long clk_rate_khz, scl_rate_khz;
 691
 692         unsigned long min_low_div, min_high_div;
 693
 694         unsigned long min_div_for_hold, min_total_div;
 695         unsigned long extra_div, extra_low_div;
 696         unsigned long sda_update_cfg;
 697
 698         int ret = 0;
 699
 700         /* Support standard-mode, fast-mode and highspeed-mode */
 701         if (WARN_ON(t->bus_freq_hz > 3400000))
 702                 t->bus_freq_hz = 3400000;
 703
 704         /* prevent scl_rate_khz from becoming 0 */
 705         if (WARN_ON(t->bus_freq_hz < 1000))
 706                 t->bus_freq_hz = 1000;
 707
 708         /*
 709          * min_low_ns: The minimum number of ns we need to hold low to
 710          *             meet I2C specification, should include fall time.
 711          * min_high_ns: The minimum number of ns we need to hold high to
 712          *              meet I2C specification, should include rise time.
 713          */
 714         if (t->bus_freq_hz <= 100000) {
 715                 spec_min_low_ns = 4700;
 716                 spec_min_high_ns = 4000;
 717
 718                 spec_min_setup_start_ns = 4700;
 719                 spec_min_stop_setup_ns = 4000;
 720
 721                 spec_min_data_setup_ns = 250;
 722                 spec_max_data_hold_ns = 3450;
 723         } else if (t->bus_freq_hz <= 400000) {
 724                 spec_min_low_ns = 1300;
 725                 spec_min_high_ns = 600;
 726
 727                 spec_min_setup_start_ns = 600;
 728                 spec_min_stop_setup_ns = 600;
 729
 730                 spec_min_data_setup_ns = 100;
 731                 spec_max_data_hold_ns = 900;
 732         } else if (t->bus_freq_hz <= 1700000) {
 733                 spec_min_low_ns = 320;
 734                 spec_min_high_ns = 120;
 735
 736                 spec_min_setup_start_ns = 160;
 737                 spec_min_stop_setup_ns = 160;
 738
 739                 spec_min_data_setup_ns = 10;
 740                 spec_max_data_hold_ns = 150;
 741         } else {
 742                 spec_min_low_ns = 160;
 743                 spec_min_high_ns = 60;
 744
 745                 spec_min_setup_start_ns = 160;
 746                 spec_min_stop_setup_ns = 160;
 747
 748                 spec_min_data_setup_ns = 10;
 749                 spec_max_data_hold_ns = 70;
 750         }
 751
 752         /* caculate min-divh and min-divl */
 753         clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
 754         scl_rate_khz = t->bus_freq_hz / 1000;
 755         min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
 756
 757         min_high_ns = t->scl_rise_ns + spec_min_high_ns;
 758         min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
 759
 760         min_low_ns = t->scl_fall_ns + spec_min_low_ns;
 761         min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
 762
 763         /* Final divh and divl must be greater than 0, otherwise the
 764          * hardware would not output the i2c clk.
 765          */
 766         min_high_div = (min_high_div < 1) ? 2 : min_high_div;
 767         min_low_div = (min_low_div < 1) ? 2 : min_low_div;
 768
 769         /* These are the min dividers needed for min hold times. */
 770         min_div_for_hold = (min_low_div + min_high_div);
 771         min_total_ns = min_low_ns + min_high_ns;
 772
 773         /*
 774          * This is the maximum divider so we don't go over the maximum.
 775          * We don't round up here (we round down) since this is a maximum.
 776          */
 777          if (min_div_for_hold >= min_total_div) {
 778                 /*
 779                  * Time needed to meet hold requirements is important.
 780                  * Just use that.
 781                  */
 782                 t_calc->div_low = min_low_div;
 783                 t_calc->div_high = min_high_div;
 784         } else {
 785                 /*
 786                  * We've got to distribute some time among the low and high
 787                  * so we don't run too fast.
 788                  * We'll try to split things up by the scale of min_low_div and
 789                  * min_high_div, biasing slightly towards having a higher div
 790                  * for low (spend more time low).
 791                  */
 792                 extra_div = min_total_div - min_div_for_hold;
 793                 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
 794                                              min_div_for_hold);
 795
 796                 t_calc->div_low = min_low_div + extra_low_div;
 797                 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
 798         }
 799
 800         /*
 801          * calculate sda data hold count by the rules, data_upd_st:3
 802          * is a appropriate value to reduce calculated times.
 803          */
 804         for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
 805                 max_hold_data_ns =  DIV_ROUND_UP((sda_update_cfg
 806                                                  * (t_calc->div_low) + 1)
 807                                                  * 1000000, clk_rate_khz);
 808                 min_setup_data_ns =  DIV_ROUND_UP(((8 - sda_update_cfg)
 809                                                  * (t_calc->div_low) + 1)
 810                                                  * 1000000, clk_rate_khz);
 811                 if ((max_hold_data_ns < spec_max_data_hold_ns) &&
 812                     (min_setup_data_ns > spec_min_data_setup_ns)) {
 813                         t_calc->sda_update_cfg = sda_update_cfg;
 814                         break;
 815                 }
 816         }
 817
 818         /* caculate setup start config */
 819         min_setup_start_ns = t->scl_rise_ns + spec_min_setup_start_ns;
 820         t_calc->stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
 821                            - 1000000, 8 * 1000000 * (t_calc->div_high));
 822
 823         /* caculate setup stop config */
 824         min_stop_setup_ns = t->scl_rise_ns + spec_min_stop_setup_ns;
 825         t_calc->stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_stop_setup_ns
 826                            - 1000000, 8 * 1000000 * (t_calc->div_high));
 827
 828         t_calc->stp_sta_cfg -= 1;
 829         t_calc->stp_sto_cfg -= 1;
 830         t_calc->sda_update_cfg -= 1;
 831
 832         t_calc->div_low -= 1;
 833         t_calc->div_high -= 1;
 834
 835         /* Maximum divider supported by hw is 0xffff */
 836         if ((t_calc->div_low > 0xffff) || (t_calc->div_high > 0xffff)) {
 837                 t_calc->div_low = 0xffff;
 838                 t_calc->div_high = 0xffff;
 839                 ret = -EINVAL;
 840         }
 841
 842         return ret;
 843 }
 844
 845 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
 846 {
 847         struct i2c_timings *t = &i2c->t;
 848         struct rk3x_i2c_calced_timings *t_calc = &i2c->t_calc;
 849         u64 t_low_ns, t_high_ns;
 850         int ret = 0;
 851
 852         if (i2c->soc_data->calc_timings)
 853                 ret = i2c->soc_data->calc_timings(clk_rate, t, t_calc);
 854         WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
 855
 856         if (i2c->pclk)
 857                 clk_enable(i2c->pclk);
 858         else
 859                 clk_enable(i2c->clk);
 860
 861         i2c_writel(i2c, (t_calc->div_high << 16) |
 862                   (t_calc->div_low & 0xffff), REG_CLKDIV);
 863
 864         if (i2c->pclk)
 865                 clk_disable(i2c->pclk);
 866         else
 867                 clk_disable(i2c->clk);
 868
 869         t_low_ns = div_u64(((u64)t_calc->div_low + 1) * 8 * 1000000000,
 870                            clk_rate);
 871         t_high_ns = div_u64(((u64)t_calc->div_high + 1) * 8 * 1000000000,
 872                             clk_rate);
 873         dev_dbg(i2c->dev,
 874                 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
 875                 clk_rate / 1000,
 876                 1000000000 / t->bus_freq_hz,
 877                 t_low_ns, t_high_ns);
 878 }
 879
 880 /**
 881  * rk3x_i2c_clk_notifier_cb - Clock rate change callback
 882  * @nb:         Pointer to notifier block
 883  * @event:      Notification reason
 884  * @data:       Pointer to notification data object
 885  *
 886  * The callback checks whether a valid bus frequency can be generated after the
 887  * change. If so, the change is acknowledged, otherwise the change is aborted.
 888  * New dividers are written to the HW in the pre- or post change notification
 889  * depending on the scaling direction.
 890  *
 891  * Code adapted from i2c-cadence.c.
 892  *
 893  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
 894  *              to acknowedge the change, NOTIFY_DONE if the notification is
 895  *              considered irrelevant.
 896  */
 897 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
 898                                     event, void *data)
 899 {
 900         struct clk_notifier_data *ndata = data;
 901         struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
 902         struct i2c_timings *t = &i2c->t;
 903         struct rk3x_i2c_calced_timings *t_calc = &i2c->t_calc;
 904
 905         switch (event) {
 906         case PRE_RATE_CHANGE:
 907                 if (i2c->soc_data->calc_timings(ndata->new_rate,
 908                                                 t, t_calc) != 0)
 909                         return NOTIFY_STOP;
 910
 911                 /* scale up */
 912                 if (ndata->new_rate > ndata->old_rate)
 913                         rk3x_i2c_adapt_div(i2c, ndata->new_rate);
 914
 915                 return NOTIFY_OK;
 916         case POST_RATE_CHANGE:
 917                 /* scale down */
 918                 if (ndata->new_rate < ndata->old_rate)
 919                         rk3x_i2c_adapt_div(i2c, ndata->new_rate);
 920                 return NOTIFY_OK;
 921         case ABORT_RATE_CHANGE:
 922                 /* scale up */
 923                 if (ndata->new_rate > ndata->old_rate)
 924                         rk3x_i2c_adapt_div(i2c, ndata->old_rate);
 925                 return NOTIFY_OK;
 926         default:
 927                 return NOTIFY_DONE;
 928         }
 929 }
 930
 931 /**
 932  * Setup I2C registers for an I2C operation specified by msgs, num.
 933  *
 934  * Must be called with i2c->lock held.
 935  *
 936  * @msgs: I2C msgs to process
 937  * @num: Number of msgs
 938  *
 939  * returns: Number of I2C msgs processed or negative in case of error
 940  */
 941 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
 942 {
 943         u32 addr = (msgs[0].addr & 0x7f) << 1;
 944         int ret = 0;
 945
 946         /*
 947          * The I2C adapter can issue a small (len < 4) write packet before
 948          * reading. This speeds up SMBus-style register reads.
 949          * The MRXADDR/MRXRADDR hold the slave address and the slave register
 950          * address in this case.
 951          */
 952
 953         if (num >= 2 && msgs[0].len < 4 &&
 954             !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
 955                 u32 reg_addr = 0;
 956                 int i;
 957
 958                 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
 959                         addr >> 1);
 960
 961                 /* Fill MRXRADDR with the register address(es) */
 962                 for (i = 0; i < msgs[0].len; ++i) {
 963                         reg_addr |= msgs[0].buf[i] << (i * 8);
 964                         reg_addr |= REG_MRXADDR_VALID(i);
 965                 }
 966
 967                 /* msgs[0] is handled by hw. */
 968                 i2c->msg = &msgs[1];
 969
 970                 i2c->mode = REG_CON_MOD_REGISTER_TX;
 971
 972                 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
 973                 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
 974
 975                 ret = 2;
 976         } else {
 977                 /*
 978                  * We'll have to do it the boring way and process the msgs
 979                  * one-by-one.
 980                  */
 981
 982                 if (msgs[0].flags & I2C_M_RD) {
 983                         addr |= 1; /* set read bit */
 984
 985                         /*
 986                          * We have to transmit the slave addr first. Use
 987                          * MOD_REGISTER_TX for that purpose.
 988                          */
 989                         i2c->mode = REG_CON_MOD_REGISTER_TX;
 990                         i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
 991                                    REG_MRXADDR);
 992                         i2c_writel(i2c, 0, REG_MRXRADDR);
 993                 } else {
 994                         i2c->mode = REG_CON_MOD_TX;
 995                 }
 996
 997                 i2c->msg = &msgs[0];
 998
 999                 ret = 1;
1000         }
1001
1002         i2c->addr = msgs[0].addr;
1003         i2c->busy = true;
1004         i2c->state = STATE_START;
1005         i2c->processed = 0;
1006         i2c->error = 0;
1007
1008         rk3x_i2c_clean_ipd(i2c);
1009
1010         return ret;
1011 }
1012
1013 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1014                          struct i2c_msg *msgs, int num)
1015 {
1016         struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1017         unsigned long timeout, flags;
1018         int ret = 0;
1019         int i;
1020
1021         spin_lock_irqsave(&i2c->lock, flags);
1022
1023         if (i2c->pclk)
1024                 clk_enable(i2c->pclk);
1025         clk_enable(i2c->clk);
1026
1027         i2c->is_last_msg = false;
1028
1029         /*
1030          * Process msgs. We can handle more than one message at once (see
1031          * rk3x_i2c_setup()).
1032          */
1033         for (i = 0; i < num; i += ret) {
1034                 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1035
1036                 if (ret < 0) {
1037                         dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1038                         break;
1039                 }
1040
1041                 if (i + ret >= num)
1042                         i2c->is_last_msg = true;
1043
1044                 spin_unlock_irqrestore(&i2c->lock, flags);
1045
1046                 rk3x_i2c_start(i2c);
1047
1048                 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
1049                                              msecs_to_jiffies(WAIT_TIMEOUT));
1050
1051                 spin_lock_irqsave(&i2c->lock, flags);
1052
1053                 if (timeout == 0) {
1054                         dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
1055                                 i2c_readl(i2c, REG_IPD), i2c->state);
1056
1057                         /* Force a STOP condition without interrupt */
1058                         i2c_writel(i2c, 0, REG_IEN);
1059                         i2c_writel(i2c, rk3x_i2c_get_con_count(i2c) |
1060                                    REG_CON_EN | REG_CON_STOP, REG_CON);
1061
1062                         i2c->state = STATE_IDLE;
1063
1064                         ret = -ETIMEDOUT;
1065                         break;
1066                 }
1067
1068                 if (i2c->error) {
1069                         ret = i2c->error;
1070                         break;
1071                 }
1072         }
1073
1074         clk_disable(i2c->clk);
1075         if (i2c->pclk)
1076                 clk_disable(i2c->pclk);
1077         spin_unlock_irqrestore(&i2c->lock, flags);
1078
1079         return ret < 0 ? ret : num;
1080 }
1081
1082 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1083 {
1084         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1085 }
1086
1087 static const struct i2c_algorithm rk3x_i2c_algorithm = {
1088         .master_xfer            = rk3x_i2c_xfer,
1089         .functionality          = rk3x_i2c_func,
1090 };
1091
1092 static int rk3x_i2c_v0_clock_init(struct rk3x_i2c *i2c, unsigned long *clk_rate)
1093 {
1094         int ret = 0;
1095
1096         i2c->clk = devm_clk_get(i2c->dev, "i2c");
1097         if (IS_ERR(i2c->clk)) {
1098                 dev_err(i2c->dev, "Could not get i2c clk\n");
1099                 return PTR_ERR(i2c->clk);
1100         }
1101
1102         ret = clk_prepare(i2c->clk);
1103         if (ret < 0) {
1104                 dev_err(i2c->dev, "Could not prepare i2c clk\n");
1105                 return ret;
1106         }
1107
1108         *clk_rate = clk_get_rate(i2c->clk);
1109
1110         i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1111         ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1112         if (ret != 0) {
1113                 dev_err(i2c->dev, "Unable to register clk notifier\n");
1114                 clk_unprepare(i2c->clk);
1115         }
1116
1117         return ret;
1118 }
1119
1120 static int rk3x_i2c_v1_clock_init(struct rk3x_i2c *i2c, unsigned long *clk_rate)
1121 {
1122         int ret = 0;
1123         u32 rate = 0;
1124
1125         /* sclk and pclk need to do individually*/
1126         i2c->pclk = devm_clk_get(i2c->dev, "pclk");
1127         if (IS_ERR(i2c->pclk)) {
1128                 dev_err(i2c->dev, "Could not get i2c pclk\n");
1129                 return PTR_ERR(i2c->pclk);
1130         }
1131
1132         ret = clk_prepare(i2c->pclk);
1133         if (ret < 0) {
1134                 dev_err(i2c->dev, "Could not prepare pclk\n");
1135                 return ret;
1136         }
1137
1138         i2c->clk = devm_clk_get(i2c->dev, "i2c");
1139         if (IS_ERR(i2c->clk)) {
1140                 dev_err(i2c->dev, "cannot get i2c clk\n");
1141                 clk_unprepare(i2c->pclk);
1142                 return PTR_ERR(i2c->clk);
1143         }
1144         ret = clk_prepare(i2c->clk);
1145         if (ret) {
1146                 dev_err(i2c->dev, "Could not prepare i2c clk\n");
1147                 clk_unprepare(i2c->pclk);
1148                 return ret;
1149         }
1150
1151         if (!device_property_read_u32(i2c->dev, "input-clk-rate", &rate)) {
1152                 *clk_rate = rate;
1153                 ret = clk_set_rate(i2c->clk, *clk_rate);
1154                 if (ret) {
1155                         dev_err(i2c->dev, "i2c clk set rate failed\n");
1156                         clk_unprepare(i2c->clk);
1157                         clk_unprepare(i2c->pclk);
1158                         return ret;
1159                 }
1160         } else {
1161                 /* use default input clock rate */
1162                 *clk_rate = clk_get_rate(i2c->clk);
1163         }
1164
1165         return ret;
1166 }
1167
1168 static struct rk3x_i2c_soc_data soc_data[] = {
1169         {
1170                 .grf_offset = 0x154,
1171                 .clk_init = rk3x_i2c_v0_clock_init,
1172                 .calc_timings = rk3x_i2c_v0_calc_timings,
1173         },
1174         {
1175                 .grf_offset = 0x0a4,
1176                 .clk_init = rk3x_i2c_v0_clock_init,
1177                 .calc_timings = rk3x_i2c_v0_calc_timings,
1178         },
1179         {
1180                 .grf_offset = -1,
1181                 .clk_init = rk3x_i2c_v0_clock_init,
1182                 .calc_timings = rk3x_i2c_v0_calc_timings,
1183         },
1184         {
1185                 .grf_offset = -1,
1186                 .clk_init = rk3x_i2c_v1_clock_init,
1187                 .calc_timings = rk3x_i2c_v1_calc_timings,
1188         },
1189 };
1190
1191 static const struct of_device_id rk3x_i2c_match[] = {
1192         { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },
1193         { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },
1194         { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },
1195         { .compatible = "rockchip,rk3399-i2c", .data = (void *)&soc_data[3] },
1196         {},
1197 };
1198 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1199
1200 static int rk3x_i2c_probe(struct platform_device *pdev)
1201 {
1202         struct device_node *np = pdev->dev.of_node;
1203         const struct of_device_id *match;
1204         struct rk3x_i2c *i2c;
1205         struct resource *mem;
1206         int ret = 0;
1207         int bus_nr;
1208         u32 value;
1209         int irq;
1210         unsigned long clk_rate;
1211
1212         i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1213         if (!i2c)
1214                 return -ENOMEM;
1215
1216         match = of_match_node(rk3x_i2c_match, np);
1217         i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data;
1218
1219         /* use common interface to get I2C timing properties */
1220         i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1221
1222         strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1223         i2c->adap.owner = THIS_MODULE;
1224         i2c->adap.algo = &rk3x_i2c_algorithm;
1225         i2c->adap.retries = 3;
1226         i2c->adap.dev.of_node = np;
1227         i2c->adap.algo_data = i2c;
1228         i2c->adap.dev.parent = &pdev->dev;
1229         i2c->dev = &pdev->dev;
1230
1231         spin_lock_init(&i2c->lock);
1232         init_waitqueue_head(&i2c->wait);
1233
1234         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1235         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
1236         if (IS_ERR(i2c->regs))
1237                 return PTR_ERR(i2c->regs);
1238
1239         /* Try to set the I2C adapter number from dt */
1240         bus_nr = of_alias_get_id(np, "i2c");
1241
1242         /*
1243          * Switch to new interface if the SoC also offers the old one.
1244          * The control bit is located in the GRF register space.
1245          */
1246         if (i2c->soc_data->grf_offset >= 0) {
1247                 struct regmap *grf;
1248
1249                 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1250                 if (IS_ERR(grf)) {
1251                         dev_err(&pdev->dev,
1252                                 "rk3x-i2c needs 'rockchip,grf' property\n");
1253                         return PTR_ERR(grf);
1254                 }
1255
1256                 if (bus_nr < 0) {
1257                         dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1258                         return -EINVAL;
1259                 }
1260
1261                 /* 27+i: write mask, 11+i: value */
1262                 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1263
1264                 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
1265                 if (ret != 0) {
1266                         dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1267                         return ret;
1268                 }
1269         }
1270
1271         /* IRQ setup */
1272         irq = platform_get_irq(pdev, 0);
1273         if (irq < 0) {
1274                 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
1275                 return irq;
1276         }
1277
1278         ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1279                                0, dev_name(&pdev->dev), i2c);
1280         if (ret < 0) {
1281                 dev_err(&pdev->dev, "cannot request IRQ\n");
1282                 return ret;
1283         }
1284
1285         platform_set_drvdata(pdev, i2c);
1286
1287         if (i2c->soc_data->clk_init) {
1288                 ret = i2c->soc_data->clk_init(i2c, &clk_rate);
1289                 if (ret < 0) {
1290                         dev_err(&pdev->dev, "clock init failed\n");
1291                         return ret;
1292                 }
1293         }
1294
1295         rk3x_i2c_adapt_div(i2c, clk_rate);
1296         ret = i2c_add_adapter(&i2c->adap);
1297         if (ret < 0) {
1298                 dev_err(&pdev->dev, "Could not register adapter\n");
1299                 goto err_clk_notifier;
1300         }
1301
1302         dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
1303
1304         return 0;
1305
1306 err_clk_notifier:
1307         clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1308         clk_unprepare(i2c->clk);
1309         if (i2c->pclk)
1310                 clk_unprepare(i2c->pclk);
1311
1312         return ret;
1313 }
1314
1315 static int rk3x_i2c_remove(struct platform_device *pdev)
1316 {
1317         struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1318
1319         i2c_del_adapter(&i2c->adap);
1320
1321         clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1322         clk_unprepare(i2c->clk);
1323         if (i2c->pclk)
1324                 clk_unprepare(i2c->pclk);
1325
1326         return 0;
1327 }
1328
1329 static struct platform_driver rk3x_i2c_driver = {
1330         .probe   = rk3x_i2c_probe,
1331         .remove  = rk3x_i2c_remove,
1332         .driver  = {
1333                 .name  = "rk3x-i2c",
1334                 .of_match_table = rk3x_i2c_match,
1335         },
1336 };
1337
1338 module_platform_driver(rk3x_i2c_driver);
1339
1340 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1341 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1342 MODULE_LICENSE("GPL v2");