drivers/gpu/drm/tegra/hdmi.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/gpio.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/clk/tegra.h>
  18
  19 #include "hdmi.h"
  20 #include "drm.h"
  21 #include "dc.h"
  22
  23 struct tegra_hdmi {
  24         struct host1x_client client;
  25         struct tegra_output output;
  26         struct device *dev;
  27
  28         struct regulator *vdd;
  29         struct regulator *pll;
  30
  31         void __iomem *regs;
  32         unsigned int irq;
  33
  34         struct clk *clk_parent;
  35         struct clk *clk;
  36
  37         unsigned int audio_source;
  38         unsigned int audio_freq;
  39         bool stereo;
  40         bool dvi;
  41
  42         struct drm_info_list *debugfs_files;
  43         struct drm_minor *minor;
  44         struct dentry *debugfs;
  45 };
  46
  47 static inline struct tegra_hdmi *
  48 host1x_client_to_hdmi(struct host1x_client *client)
  49 {
  50         return container_of(client, struct tegra_hdmi, client);
  51 }
  52
  53 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
  54 {
  55         return container_of(output, struct tegra_hdmi, output);
  56 }
  57
  58 #define HDMI_AUDIOCLK_FREQ 216000000
  59 #define HDMI_REKEY_DEFAULT 56
  60
  61 enum {
  62         AUTO = 0,
  63         SPDIF,
  64         HDA,
  65 };
  66
  67 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
  68                                              unsigned long reg)
  69 {
  70         return readl(hdmi->regs + (reg << 2));
  71 }
  72
  73 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
  74                                      unsigned long reg)
  75 {
  76         writel(val, hdmi->regs + (reg << 2));
  77 }
  78
  79 struct tegra_hdmi_audio_config {
  80         unsigned int pclk;
  81         unsigned int n;
  82         unsigned int cts;
  83         unsigned int aval;
  84 };
  85
  86 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
  87         {  25200000, 4096,  25200, 24000 },
  88         {  27000000, 4096,  27000, 24000 },
  89         {  74250000, 4096,  74250, 24000 },
  90         { 148500000, 4096, 148500, 24000 },
  91         {         0,    0,      0,     0 },
  92 };
  93
  94 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
  95         {  25200000, 5880,  26250, 25000 },
  96         {  27000000, 5880,  28125, 25000 },
  97         {  74250000, 4704,  61875, 20000 },
  98         { 148500000, 4704, 123750, 20000 },
  99         {         0,    0,      0,     0 },
 100 };
 101
 102 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 103         {  25200000, 6144,  25200, 24000 },
 104         {  27000000, 6144,  27000, 24000 },
 105         {  74250000, 6144,  74250, 24000 },
 106         { 148500000, 6144, 148500, 24000 },
 107         {         0,    0,      0,     0 },
 108 };
 109
 110 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
 111         {  25200000, 11760,  26250, 25000 },
 112         {  27000000, 11760,  28125, 25000 },
 113         {  74250000,  9408,  61875, 20000 },
 114         { 148500000,  9408, 123750, 20000 },
 115         {         0,     0,      0,     0 },
 116 };
 117
 118 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
 119         {  25200000, 12288,  25200, 24000 },
 120         {  27000000, 12288,  27000, 24000 },
 121         {  74250000, 12288,  74250, 24000 },
 122         { 148500000, 12288, 148500, 24000 },
 123         {         0,     0,      0,     0 },
 124 };
 125
 126 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
 127         {  25200000, 23520,  26250, 25000 },
 128         {  27000000, 23520,  28125, 25000 },
 129         {  74250000, 18816,  61875, 20000 },
 130         { 148500000, 18816, 123750, 20000 },
 131         {         0,     0,      0,     0 },
 132 };
 133
 134 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
 135         {  25200000, 24576,  25200, 24000 },
 136         {  27000000, 24576,  27000, 24000 },
 137         {  74250000, 24576,  74250, 24000 },
 138         { 148500000, 24576, 148500, 24000 },
 139         {         0,     0,      0,     0 },
 140 };
 141
 142 struct tmds_config {
 143         unsigned int pclk;
 144         u32 pll0;
 145         u32 pll1;
 146         u32 pe_current;
 147         u32 drive_current;
 148 };
 149
 150 static const struct tmds_config tegra2_tmds_config[] = {
 151         { /* slow pixel clock modes */
 152                 .pclk = 27000000,
 153                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 154                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 155                         SOR_PLL_TX_REG_LOAD(3),
 156                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 157                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 158                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 159                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 160                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 161                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 162                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 163                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 164                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 165         },
 166         { /* high pixel clock modes */
 167                 .pclk = UINT_MAX,
 168                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 169                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 170                         SOR_PLL_TX_REG_LOAD(3),
 171                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 172                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
 173                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
 174                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
 175                         PE_CURRENT3(PE_CURRENT_6_0_mA),
 176                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 177                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 178                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 179                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 180         },
 181 };
 182
 183 static const struct tmds_config tegra3_tmds_config[] = {
 184         { /* 480p modes */
 185                 .pclk = 27000000,
 186                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 187                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 188                         SOR_PLL_TX_REG_LOAD(0),
 189                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 190                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 191                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 192                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 193                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 194                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 195                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 196                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 197                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 198         }, { /* 720p modes */
 199                 .pclk = 74250000,
 200                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 201                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 202                         SOR_PLL_TX_REG_LOAD(0),
 203                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 204                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 205                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 206                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 207                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 208                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 209                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 210                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 211                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 212         }, { /* 1080p modes */
 213                 .pclk = UINT_MAX,
 214                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 215                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
 216                         SOR_PLL_TX_REG_LOAD(0),
 217                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 218                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 219                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 220                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 221                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 222                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 223                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 224                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 225                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 226         },
 227 };
 228
 229 static const struct tegra_hdmi_audio_config *
 230 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
 231 {
 232         const struct tegra_hdmi_audio_config *table;
 233
 234         switch (audio_freq) {
 235         case 32000:
 236                 table = tegra_hdmi_audio_32k;
 237                 break;
 238
 239         case 44100:
 240                 table = tegra_hdmi_audio_44_1k;
 241                 break;
 242
 243         case 48000:
 244                 table = tegra_hdmi_audio_48k;
 245                 break;
 246
 247         case 88200:
 248                 table = tegra_hdmi_audio_88_2k;
 249                 break;
 250
 251         case 96000:
 252                 table = tegra_hdmi_audio_96k;
 253                 break;
 254
 255         case 176400:
 256                 table = tegra_hdmi_audio_176_4k;
 257                 break;
 258
 259         case 192000:
 260                 table = tegra_hdmi_audio_192k;
 261                 break;
 262
 263         default:
 264                 return NULL;
 265         }
 266
 267         while (table->pclk) {
 268                 if (table->pclk == pclk)
 269                         return table;
 270
 271                 table++;
 272         }
 273
 274         return NULL;
 275 }
 276
 277 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
 278 {
 279         const unsigned int freqs[] = {
 280                 32000, 44100, 48000, 88200, 96000, 176400, 192000
 281         };
 282         unsigned int i;
 283
 284         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 285                 unsigned int f = freqs[i];
 286                 unsigned int eight_half;
 287                 unsigned long value;
 288                 unsigned int delta;
 289
 290                 if (f > 96000)
 291                         delta = 2;
 292                 else if (f > 480000)
 293                         delta = 6;
 294                 else
 295                         delta = 9;
 296
 297                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 298                 value = AUDIO_FS_LOW(eight_half - delta) |
 299                         AUDIO_FS_HIGH(eight_half + delta);
 300                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
 301         }
 302 }
 303
 304 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
 305 {
 306         struct device_node *node = hdmi->dev->of_node;
 307         const struct tegra_hdmi_audio_config *config;
 308         unsigned int offset = 0;
 309         unsigned long value;
 310
 311         switch (hdmi->audio_source) {
 312         case HDA:
 313                 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
 314                 break;
 315
 316         case SPDIF:
 317                 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 318                 break;
 319
 320         default:
 321                 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 322                 break;
 323         }
 324
 325         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
 326                 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 327                          AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
 328                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 329         } else {
 330                 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
 331                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
 332
 333                 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 334                         AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
 335                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 336         }
 337
 338         config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
 339         if (!config) {
 340                 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
 341                         hdmi->audio_freq, pclk);
 342                 return -EINVAL;
 343         }
 344
 345         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 346
 347         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
 348                 AUDIO_N_VALUE(config->n - 1);
 349         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 350
 351         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
 352                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 353
 354         value = ACR_SUBPACK_CTS(config->cts);
 355         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 356
 357         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
 358         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
 359
 360         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
 361         value &= ~AUDIO_N_RESETF;
 362         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 363
 364         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
 365                 switch (hdmi->audio_freq) {
 366                 case 32000:
 367                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
 368                         break;
 369
 370                 case 44100:
 371                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
 372                         break;
 373
 374                 case 48000:
 375                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
 376                         break;
 377
 378                 case 88200:
 379                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
 380                         break;
 381
 382                 case 96000:
 383                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
 384                         break;
 385
 386                 case 176400:
 387                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
 388                         break;
 389
 390                 case 192000:
 391                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
 392                         break;
 393                 }
 394
 395                 tegra_hdmi_writel(hdmi, config->aval, offset);
 396         }
 397
 398         tegra_hdmi_setup_audio_fs_tables(hdmi);
 399
 400         return 0;
 401 }
 402
 403 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi,
 404                                       unsigned int offset, u8 type,
 405                                       u8 version, void *data, size_t size)
 406 {
 407         unsigned long value;
 408         u8 *ptr = data;
 409         u32 subpack[2];
 410         size_t i;
 411         u8 csum;
 412
 413         /* first byte of data is the checksum */
 414         csum = type + version + size - 1;
 415
 416         for (i = 1; i < size; i++)
 417                 csum += ptr[i];
 418
 419         ptr[0] = 0x100 - csum;
 420
 421         value = INFOFRAME_HEADER_TYPE(type) |
 422                 INFOFRAME_HEADER_VERSION(version) |
 423                 INFOFRAME_HEADER_LEN(size - 1);
 424         tegra_hdmi_writel(hdmi, value, offset);
 425
 426         /* The audio inforame only has one set of subpack registers.  The hdmi
 427          * block pads the rest of the data as per the spec so we have to fixup
 428          * the length before filling in the subpacks.
 429          */
 430         if (offset == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
 431                 size = 6;
 432
 433         /* each subpack 7 bytes devided into:
 434          *   subpack_low - bytes 0 - 3
 435          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
 436          */
 437         for (i = 0; i < size; i++) {
 438                 size_t index = i % 7;
 439
 440                 if (index == 0)
 441                         memset(subpack, 0x0, sizeof(subpack));
 442
 443                 ((u8 *)subpack)[index] = ptr[i];
 444
 445                 if (index == 6 || (i + 1 == size)) {
 446                         unsigned int reg = offset + 1 + (i / 7) * 2;
 447
 448                         tegra_hdmi_writel(hdmi, subpack[0], reg);
 449                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
 450                 }
 451         }
 452 }
 453
 454 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
 455                                            struct drm_display_mode *mode)
 456 {
 457         struct hdmi_avi_infoframe frame;
 458         unsigned int h_front_porch;
 459         unsigned int hsize = 16;
 460         unsigned int vsize = 9;
 461
 462         if (hdmi->dvi) {
 463                 tegra_hdmi_writel(hdmi, 0,
 464                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 465                 return;
 466         }
 467
 468         h_front_porch = mode->hsync_start - mode->hdisplay;
 469         memset(&frame, 0, sizeof(frame));
 470         frame.r = HDMI_AVI_R_SAME;
 471
 472         switch (mode->vdisplay) {
 473         case 480:
 474                 if (mode->hdisplay == 640) {
 475                         frame.m = HDMI_AVI_M_4_3;
 476                         frame.vic = 1;
 477                 } else {
 478                         frame.m = HDMI_AVI_M_16_9;
 479                         frame.vic = 3;
 480                 }
 481                 break;
 482
 483         case 576:
 484                 if (((hsize * 10) / vsize) > 14) {
 485                         frame.m = HDMI_AVI_M_16_9;
 486                         frame.vic = 18;
 487                 } else {
 488                         frame.m = HDMI_AVI_M_4_3;
 489                         frame.vic = 17;
 490                 }
 491                 break;
 492
 493         case 720:
 494         case 1470: /* stereo mode */
 495                 frame.m = HDMI_AVI_M_16_9;
 496
 497                 if (h_front_porch == 110)
 498                         frame.vic = 4;
 499                 else
 500                         frame.vic = 19;
 501                 break;
 502
 503         case 1080:
 504         case 2205: /* stereo mode */
 505                 frame.m = HDMI_AVI_M_16_9;
 506
 507                 switch (h_front_porch) {
 508                 case 88:
 509                         frame.vic = 16;
 510                         break;
 511
 512                 case 528:
 513                         frame.vic = 31;
 514                         break;
 515
 516                 default:
 517                         frame.vic = 32;
 518                         break;
 519                 }
 520                 break;
 521
 522         default:
 523                 frame.m = HDMI_AVI_M_16_9;
 524                 frame.vic = 0;
 525                 break;
 526         }
 527
 528         tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
 529                                   HDMI_INFOFRAME_TYPE_AVI, HDMI_AVI_VERSION,
 530                                   &frame, sizeof(frame));
 531
 532         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 533                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 534 }
 535
 536 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
 537 {
 538         struct hdmi_audio_infoframe frame;
 539
 540         if (hdmi->dvi) {
 541                 tegra_hdmi_writel(hdmi, 0,
 542                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 543                 return;
 544         }
 545
 546         memset(&frame, 0, sizeof(frame));
 547         frame.cc = HDMI_AUDIO_CC_2;
 548
 549         tegra_hdmi_write_infopack(hdmi,
 550                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
 551                                   HDMI_INFOFRAME_TYPE_AUDIO,
 552                                   HDMI_AUDIO_VERSION,
 553                                   &frame, sizeof(frame));
 554
 555         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 556                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 557 }
 558
 559 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
 560 {
 561         struct hdmi_stereo_infoframe frame;
 562         unsigned long value;
 563
 564         if (!hdmi->stereo) {
 565                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 566                 value &= ~GENERIC_CTRL_ENABLE;
 567                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 568                 return;
 569         }
 570
 571         memset(&frame, 0, sizeof(frame));
 572         frame.regid0 = 0x03;
 573         frame.regid1 = 0x0c;
 574         frame.regid2 = 0x00;
 575         frame.hdmi_video_format = 2;
 576
 577         /* TODO: 74 MHz limit? */
 578         if (1) {
 579                 frame._3d_structure = 0;
 580         } else {
 581                 frame._3d_structure = 8;
 582                 frame._3d_ext_data = 0;
 583         }
 584
 585         tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
 586                                   HDMI_INFOFRAME_TYPE_VENDOR,
 587                                   HDMI_VENDOR_VERSION, &frame, 6);
 588
 589         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 590         value |= GENERIC_CTRL_ENABLE;
 591         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 592 }
 593
 594 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 595                                   const struct tmds_config *tmds)
 596 {
 597         unsigned long value;
 598
 599         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
 600         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
 601         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
 602
 603         value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
 604         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 605 }
 606
 607 static int tegra_output_hdmi_enable(struct tegra_output *output)
 608 {
 609         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
 610         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
 611         struct drm_display_mode *mode = &dc->base.mode;
 612         struct tegra_hdmi *hdmi = to_hdmi(output);
 613         struct device_node *node = hdmi->dev->of_node;
 614         unsigned int pulse_start, div82, pclk;
 615         const struct tmds_config *tmds;
 616         unsigned int num_tmds;
 617         unsigned long value;
 618         int retries = 1000;
 619         int err;
 620
 621         pclk = mode->clock * 1000;
 622         h_sync_width = mode->hsync_end - mode->hsync_start;
 623         h_back_porch = mode->htotal - mode->hsync_end;
 624         h_front_porch = mode->hsync_start - mode->hdisplay;
 625
 626         err = regulator_enable(hdmi->vdd);
 627         if (err < 0) {
 628                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
 629                 return err;
 630         }
 631
 632         err = regulator_enable(hdmi->pll);
 633         if (err < 0) {
 634                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
 635                 return err;
 636         }
 637
 638         /*
 639          * This assumes that the display controller will divide its parent
 640          * clock by 2 to generate the pixel clock.
 641          */
 642         err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
 643         if (err < 0) {
 644                 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
 645                 return err;
 646         }
 647
 648         err = clk_set_rate(hdmi->clk, pclk);
 649         if (err < 0)
 650                 return err;
 651
 652         err = clk_enable(hdmi->clk);
 653         if (err < 0) {
 654                 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
 655                 return err;
 656         }
 657
 658         tegra_periph_reset_assert(hdmi->clk);
 659         usleep_range(1000, 2000);
 660         tegra_periph_reset_deassert(hdmi->clk);
 661
 662         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
 663                         DC_DISP_DISP_TIMING_OPTIONS);
 664         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
 665                         DC_DISP_DISP_COLOR_CONTROL);
 666
 667         /* video_preamble uses h_pulse2 */
 668         pulse_start = 1 + h_sync_width + h_back_porch - 10;
 669
 670         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
 671
 672         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
 673                 PULSE_LAST_END_A;
 674         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
 675
 676         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
 677         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
 678
 679         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
 680                 VSYNC_WINDOW_ENABLE;
 681         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 682
 683         if (dc->pipe)
 684                 value = HDMI_SRC_DISPLAYB;
 685         else
 686                 value = HDMI_SRC_DISPLAYA;
 687
 688         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
 689                                         (mode->vdisplay == 576)))
 690                 tegra_hdmi_writel(hdmi,
 691                                   value | ARM_VIDEO_RANGE_FULL,
 692                                   HDMI_NV_PDISP_INPUT_CONTROL);
 693         else
 694                 tegra_hdmi_writel(hdmi,
 695                                   value | ARM_VIDEO_RANGE_LIMITED,
 696                                   HDMI_NV_PDISP_INPUT_CONTROL);
 697
 698         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
 699         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
 700         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
 701
 702         if (!hdmi->dvi) {
 703                 err = tegra_hdmi_setup_audio(hdmi, pclk);
 704                 if (err < 0)
 705                         hdmi->dvi = true;
 706         }
 707
 708         if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
 709                 /*
 710                  * TODO: add ELD support
 711                  */
 712         }
 713
 714         rekey = HDMI_REKEY_DEFAULT;
 715         value = HDMI_CTRL_REKEY(rekey);
 716         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
 717                                           h_front_porch - rekey - 18) / 32);
 718
 719         if (!hdmi->dvi)
 720                 value |= HDMI_CTRL_ENABLE;
 721
 722         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
 723
 724         if (hdmi->dvi)
 725                 tegra_hdmi_writel(hdmi, 0x0,
 726                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 727         else
 728                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
 729                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 730
 731         tegra_hdmi_setup_avi_infoframe(hdmi, mode);
 732         tegra_hdmi_setup_audio_infoframe(hdmi);
 733         tegra_hdmi_setup_stereo_infoframe(hdmi);
 734
 735         /* TMDS CONFIG */
 736         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
 737                 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
 738                 tmds = tegra3_tmds_config;
 739         } else {
 740                 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
 741                 tmds = tegra2_tmds_config;
 742         }
 743
 744         for (i = 0; i < num_tmds; i++) {
 745                 if (pclk <= tmds[i].pclk) {
 746                         tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
 747                         break;
 748                 }
 749         }
 750
 751         tegra_hdmi_writel(hdmi,
 752                           SOR_SEQ_CTL_PU_PC(0) |
 753                           SOR_SEQ_PU_PC_ALT(0) |
 754                           SOR_SEQ_PD_PC(8) |
 755                           SOR_SEQ_PD_PC_ALT(8),
 756                           HDMI_NV_PDISP_SOR_SEQ_CTL);
 757
 758         value = SOR_SEQ_INST_WAIT_TIME(1) |
 759                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
 760                 SOR_SEQ_INST_HALT |
 761                 SOR_SEQ_INST_PIN_A_LOW |
 762                 SOR_SEQ_INST_PIN_B_LOW |
 763                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
 764
 765         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
 766         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
 767
 768         value = 0x1c800;
 769         value &= ~SOR_CSTM_ROTCLK(~0);
 770         value |= SOR_CSTM_ROTCLK(2);
 771         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
 772
 773         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
 774         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 775         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 776
 777         /* start SOR */
 778         tegra_hdmi_writel(hdmi,
 779                           SOR_PWR_NORMAL_STATE_PU |
 780                           SOR_PWR_NORMAL_START_NORMAL |
 781                           SOR_PWR_SAFE_STATE_PD |
 782                           SOR_PWR_SETTING_NEW_TRIGGER,
 783                           HDMI_NV_PDISP_SOR_PWR);
 784         tegra_hdmi_writel(hdmi,
 785                           SOR_PWR_NORMAL_STATE_PU |
 786                           SOR_PWR_NORMAL_START_NORMAL |
 787                           SOR_PWR_SAFE_STATE_PD |
 788                           SOR_PWR_SETTING_NEW_DONE,
 789                           HDMI_NV_PDISP_SOR_PWR);
 790
 791         do {
 792                 BUG_ON(--retries < 0);
 793                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
 794         } while (value & SOR_PWR_SETTING_NEW_PENDING);
 795
 796         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
 797                 SOR_STATE_ASY_OWNER_HEAD0 |
 798                 SOR_STATE_ASY_SUBOWNER_BOTH |
 799                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
 800                 SOR_STATE_ASY_DEPOL_POS;
 801
 802         /* setup sync polarities */
 803         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 804                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
 805
 806         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 807                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
 808
 809         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 810                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
 811
 812         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 813                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
 814
 815         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
 816
 817         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
 818         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
 819
 820         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
 821         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
 822         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
 823                           HDMI_NV_PDISP_SOR_STATE1);
 824         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
 825
 826         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
 827
 828         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 829                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 830         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 831
 832         value = DISP_CTRL_MODE_C_DISPLAY;
 833         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
 834
 835         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 836         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 837
 838         /* TODO: add HDCP support */
 839
 840         return 0;
 841 }
 842
 843 static int tegra_output_hdmi_disable(struct tegra_output *output)
 844 {
 845         struct tegra_hdmi *hdmi = to_hdmi(output);
 846
 847         tegra_periph_reset_assert(hdmi->clk);
 848         clk_disable(hdmi->clk);
 849         regulator_disable(hdmi->pll);
 850         regulator_disable(hdmi->vdd);
 851
 852         return 0;
 853 }
 854
 855 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
 856                                          struct clk *clk, unsigned long pclk)
 857 {
 858         struct tegra_hdmi *hdmi = to_hdmi(output);
 859         struct clk *base;
 860         int err;
 861
 862         err = clk_set_parent(clk, hdmi->clk_parent);
 863         if (err < 0) {
 864                 dev_err(output->dev, "failed to set parent: %d\n", err);
 865                 return err;
 866         }
 867
 868         base = clk_get_parent(hdmi->clk_parent);
 869
 870         /*
 871          * This assumes that the parent clock is pll_d_out0 or pll_d2_out
 872          * respectively, each of which divides the base pll_d by 2.
 873          */
 874         err = clk_set_rate(base, pclk * 2);
 875         if (err < 0)
 876                 dev_err(output->dev,
 877                         "failed to set base clock rate to %lu Hz\n",
 878                         pclk * 2);
 879
 880         return 0;
 881 }
 882
 883 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
 884                                         struct drm_display_mode *mode,
 885                                         enum drm_mode_status *status)
 886 {
 887         struct tegra_hdmi *hdmi = to_hdmi(output);
 888         unsigned long pclk = mode->clock * 1000;
 889         struct clk *parent;
 890         long err;
 891
 892         parent = clk_get_parent(hdmi->clk_parent);
 893
 894         err = clk_round_rate(parent, pclk * 4);
 895         if (err < 0)
 896                 *status = MODE_NOCLOCK;
 897         else
 898                 *status = MODE_OK;
 899
 900         return 0;
 901 }
 902
 903 static const struct tegra_output_ops hdmi_ops = {
 904         .enable = tegra_output_hdmi_enable,
 905         .disable = tegra_output_hdmi_disable,
 906         .setup_clock = tegra_output_hdmi_setup_clock,
 907         .check_mode = tegra_output_hdmi_check_mode,
 908 };
 909
 910 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
 911 {
 912         struct drm_info_node *node = s->private;
 913         struct tegra_hdmi *hdmi = node->info_ent->data;
 914
 915 #define DUMP_REG(name)                                          \
 916         seq_printf(s, "%-56s %#05x %08lx\n", #name, name,       \
 917                 tegra_hdmi_readl(hdmi, name))
 918
 919         DUMP_REG(HDMI_CTXSW);
 920         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 921         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 922         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 923         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 924         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 925         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 926         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 927         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 928         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 929         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 930         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 931         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 932         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 933         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 934         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 935         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 936         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 937         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 938         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 939         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 940         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 941         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 942         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 943         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 944         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 945         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 946         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 947         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 948         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 949         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 950         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 951         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 952         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 953         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 954         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 955         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 956         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 957         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 958         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 959         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 960         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 961         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 962         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 963         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 964         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 965         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 966         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 967         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 968         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 969         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 970         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 971         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 972         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 973         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 974         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 975         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 976         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 977         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 978         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 979         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 980         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 981         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 982         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 983         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 984         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 985         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 986         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 987         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 988         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 989         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 990         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 991         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 992         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 993         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 994         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 995         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 996         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 997         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 998         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 999         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1000         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1001         DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1002         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1003         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1004         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1005         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1006         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1007         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1008         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1009         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1010         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1011         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1012         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1013         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1014         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1015         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1016         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1017         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1018         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1019         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1020         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1021         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1022         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1023         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1024         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1025         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1026         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1027         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1028         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1029         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1030         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1031         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1032         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1033         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1034         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1035         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1036         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1037         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1038         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1039         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1040         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1041         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1042         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1043         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1044         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1045         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1046         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1047         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1048         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1049         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1050         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1051         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1052         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1053         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1054         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1055         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1056         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1057         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1058         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1059         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1060         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1061         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1062         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1063         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1064         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1065         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1066         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1067         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1068         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1069         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1070         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1071         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1072         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1073         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1074         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1075         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1076
1077 #undef DUMP_REG
1078
1079         return 0;
1080 }
1081
1082 static struct drm_info_list debugfs_files[] = {
1083         { "regs", tegra_hdmi_show_regs, 0, NULL },
1084 };
1085
1086 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1087                                    struct drm_minor *minor)
1088 {
1089         unsigned int i;
1090         int err;
1091
1092         hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1093         if (!hdmi->debugfs)
1094                 return -ENOMEM;
1095
1096         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1097                                       GFP_KERNEL);
1098         if (!hdmi->debugfs_files) {
1099                 err = -ENOMEM;
1100                 goto remove;
1101         }
1102
1103         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1104                 hdmi->debugfs_files[i].data = hdmi;
1105
1106         err = drm_debugfs_create_files(hdmi->debugfs_files,
1107                                        ARRAY_SIZE(debugfs_files),
1108                                        hdmi->debugfs, minor);
1109         if (err < 0)
1110                 goto free;
1111
1112         hdmi->minor = minor;
1113
1114         return 0;
1115
1116 free:
1117         kfree(hdmi->debugfs_files);
1118         hdmi->debugfs_files = NULL;
1119 remove:
1120         debugfs_remove(hdmi->debugfs);
1121         hdmi->debugfs = NULL;
1122
1123         return err;
1124 }
1125
1126 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1127 {
1128         drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1129                                  hdmi->minor);
1130         hdmi->minor = NULL;
1131
1132         kfree(hdmi->debugfs_files);
1133         hdmi->debugfs_files = NULL;
1134
1135         debugfs_remove(hdmi->debugfs);
1136         hdmi->debugfs = NULL;
1137
1138         return 0;
1139 }
1140
1141 static int tegra_hdmi_drm_init(struct host1x_client *client,
1142                                struct drm_device *drm)
1143 {
1144         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1145         int err;
1146
1147         hdmi->output.type = TEGRA_OUTPUT_HDMI;
1148         hdmi->output.dev = client->dev;
1149         hdmi->output.ops = &hdmi_ops;
1150
1151         err = tegra_output_init(drm, &hdmi->output);
1152         if (err < 0) {
1153                 dev_err(client->dev, "output setup failed: %d\n", err);
1154                 return err;
1155         }
1156
1157         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1158                 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1159                 if (err < 0)
1160                         dev_err(client->dev, "debugfs setup failed: %d\n", err);
1161         }
1162
1163         return 0;
1164 }
1165
1166 static int tegra_hdmi_drm_exit(struct host1x_client *client)
1167 {
1168         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1169         int err;
1170
1171         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1172                 err = tegra_hdmi_debugfs_exit(hdmi);
1173                 if (err < 0)
1174                         dev_err(client->dev, "debugfs cleanup failed: %d\n",
1175                                 err);
1176         }
1177
1178         err = tegra_output_disable(&hdmi->output);
1179         if (err < 0) {
1180                 dev_err(client->dev, "output failed to disable: %d\n", err);
1181                 return err;
1182         }
1183
1184         err = tegra_output_exit(&hdmi->output);
1185         if (err < 0) {
1186                 dev_err(client->dev, "output cleanup failed: %d\n", err);
1187                 return err;
1188         }
1189
1190         return 0;
1191 }
1192
1193 static const struct host1x_client_ops hdmi_client_ops = {
1194         .drm_init = tegra_hdmi_drm_init,
1195         .drm_exit = tegra_hdmi_drm_exit,
1196 };
1197
1198 static int tegra_hdmi_probe(struct platform_device *pdev)
1199 {
1200         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1201         struct tegra_hdmi *hdmi;
1202         struct resource *regs;
1203         int err;
1204
1205         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1206         if (!hdmi)
1207                 return -ENOMEM;
1208
1209         hdmi->dev = &pdev->dev;
1210         hdmi->audio_source = AUTO;
1211         hdmi->audio_freq = 44100;
1212         hdmi->stereo = false;
1213         hdmi->dvi = false;
1214
1215         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1216         if (IS_ERR(hdmi->clk)) {
1217                 dev_err(&pdev->dev, "failed to get clock\n");
1218                 return PTR_ERR(hdmi->clk);
1219         }
1220
1221         err = clk_prepare(hdmi->clk);
1222         if (err < 0)
1223                 return err;
1224
1225         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1226         if (IS_ERR(hdmi->clk_parent))
1227                 return PTR_ERR(hdmi->clk_parent);
1228
1229         err = clk_prepare(hdmi->clk_parent);
1230         if (err < 0)
1231                 return err;
1232
1233         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1234         if (err < 0) {
1235                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1236                 return err;
1237         }
1238
1239         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1240         if (IS_ERR(hdmi->vdd)) {
1241                 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1242                 return PTR_ERR(hdmi->vdd);
1243         }
1244
1245         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1246         if (IS_ERR(hdmi->pll)) {
1247                 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1248                 return PTR_ERR(hdmi->pll);
1249         }
1250
1251         hdmi->output.dev = &pdev->dev;
1252
1253         err = tegra_output_parse_dt(&hdmi->output);
1254         if (err < 0)
1255                 return err;
1256
1257         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1258         if (!regs)
1259                 return -ENXIO;
1260
1261         hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1262         if (IS_ERR(hdmi->regs))
1263                 return PTR_ERR(hdmi->regs);
1264
1265         err = platform_get_irq(pdev, 0);
1266         if (err < 0)
1267                 return err;
1268
1269         hdmi->irq = err;
1270
1271         hdmi->client.ops = &hdmi_client_ops;
1272         INIT_LIST_HEAD(&hdmi->client.list);
1273         hdmi->client.dev = &pdev->dev;
1274
1275         err = host1x_register_client(host1x, &hdmi->client);
1276         if (err < 0) {
1277                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1278                         err);
1279                 return err;
1280         }
1281
1282         platform_set_drvdata(pdev, hdmi);
1283
1284         return 0;
1285 }
1286
1287 static int tegra_hdmi_remove(struct platform_device *pdev)
1288 {
1289         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1290         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1291         int err;
1292
1293         err = host1x_unregister_client(host1x, &hdmi->client);
1294         if (err < 0) {
1295                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1296                         err);
1297                 return err;
1298         }
1299
1300         clk_unprepare(hdmi->clk_parent);
1301         clk_unprepare(hdmi->clk);
1302
1303         return 0;
1304 }
1305
1306 static struct of_device_id tegra_hdmi_of_match[] = {
1307         { .compatible = "nvidia,tegra30-hdmi", },
1308         { .compatible = "nvidia,tegra20-hdmi", },
1309         { },
1310 };
1311
1312 struct platform_driver tegra_hdmi_driver = {
1313         .driver = {
1314                 .name = "tegra-hdmi",
1315                 .owner = THIS_MODULE,
1316                 .of_match_table = tegra_hdmi_of_match,
1317         },
1318         .probe = tegra_hdmi_probe,
1319         .remove = tegra_hdmi_remove,
1320 };