drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/reset.h>
  14
  15 #include <soc/tegra/pmc.h>
  16
  17 #include "dc.h"
  18 #include "drm.h"
  19 #include "gem.h"
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_plane_helper.h>
  24
  25 struct tegra_dc_soc_info {
  26         bool supports_border_color;
  27         bool supports_interlacing;
  28         bool supports_cursor;
  29         bool supports_block_linear;
  30         unsigned int pitch_align;
  31         bool has_powergate;
  32 };
  33
  34 struct tegra_plane {
  35         struct drm_plane base;
  36         unsigned int index;
  37 };
  38
  39 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  40 {
  41         return container_of(plane, struct tegra_plane, base);
  42 }
  43
  44 struct tegra_dc_state {
  45         struct drm_crtc_state base;
  46
  47         struct clk *clk;
  48         unsigned long pclk;
  49         unsigned int div;
  50
  51         u32 planes;
  52 };
  53
  54 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  55 {
  56         if (state)
  57                 return container_of(state, struct tegra_dc_state, base);
  58
  59         return NULL;
  60 }
  61
  62 struct tegra_plane_state {
  63         struct drm_plane_state base;
  64
  65         struct tegra_bo_tiling tiling;
  66         u32 format;
  67         u32 swap;
  68 };
  69
  70 static inline struct tegra_plane_state *
  71 to_tegra_plane_state(struct drm_plane_state *state)
  72 {
  73         if (state)
  74                 return container_of(state, struct tegra_plane_state, base);
  75
  76         return NULL;
  77 }
  78
  79 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  80 {
  81         stats->frames = 0;
  82         stats->vblank = 0;
  83         stats->underflow = 0;
  84         stats->overflow = 0;
  85 }
  86
  87 /*
  88  * Reads the active copy of a register. This takes the dc->lock spinlock to
  89  * prevent races with the VBLANK processing which also needs access to the
  90  * active copy of some registers.
  91  */
  92 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  93 {
  94         unsigned long flags;
  95         u32 value;
  96
  97         spin_lock_irqsave(&dc->lock, flags);
  98
  99         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 100         value = tegra_dc_readl(dc, offset);
 101         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 102
 103         spin_unlock_irqrestore(&dc->lock, flags);
 104         return value;
 105 }
 106
 107 /*
 108  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 109  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 110  * Latching happens mmediately if the display controller is in STOP mode or
 111  * on the next frame boundary otherwise.
 112  *
 113  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 114  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 115  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 116  * into the ACTIVE copy, either immediately if the display controller is in
 117  * STOP mode, or at the next frame boundary otherwise.
 118  */
 119 void tegra_dc_commit(struct tegra_dc *dc)
 120 {
 121         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 122         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 123 }
 124
 125 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
 126 {
 127         /* assume no swapping of fetched data */
 128         if (swap)
 129                 *swap = BYTE_SWAP_NOSWAP;
 130
 131         switch (fourcc) {
 132         case DRM_FORMAT_XBGR8888:
 133                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
 134                 break;
 135
 136         case DRM_FORMAT_XRGB8888:
 137                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
 138                 break;
 139
 140         case DRM_FORMAT_RGB565:
 141                 *format = WIN_COLOR_DEPTH_B5G6R5;
 142                 break;
 143
 144         case DRM_FORMAT_UYVY:
 145                 *format = WIN_COLOR_DEPTH_YCbCr422;
 146                 break;
 147
 148         case DRM_FORMAT_YUYV:
 149                 if (swap)
 150                         *swap = BYTE_SWAP_SWAP2;
 151
 152                 *format = WIN_COLOR_DEPTH_YCbCr422;
 153                 break;
 154
 155         case DRM_FORMAT_YUV420:
 156                 *format = WIN_COLOR_DEPTH_YCbCr420P;
 157                 break;
 158
 159         case DRM_FORMAT_YUV422:
 160                 *format = WIN_COLOR_DEPTH_YCbCr422P;
 161                 break;
 162
 163         default:
 164                 return -EINVAL;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 171 {
 172         switch (format) {
 173         case WIN_COLOR_DEPTH_YCbCr422:
 174         case WIN_COLOR_DEPTH_YUV422:
 175                 if (planar)
 176                         *planar = false;
 177
 178                 return true;
 179
 180         case WIN_COLOR_DEPTH_YCbCr420P:
 181         case WIN_COLOR_DEPTH_YUV420P:
 182         case WIN_COLOR_DEPTH_YCbCr422P:
 183         case WIN_COLOR_DEPTH_YUV422P:
 184         case WIN_COLOR_DEPTH_YCbCr422R:
 185         case WIN_COLOR_DEPTH_YUV422R:
 186         case WIN_COLOR_DEPTH_YCbCr422RA:
 187         case WIN_COLOR_DEPTH_YUV422RA:
 188                 if (planar)
 189                         *planar = true;
 190
 191                 return true;
 192         }
 193
 194         if (planar)
 195                 *planar = false;
 196
 197         return false;
 198 }
 199
 200 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 201                                   unsigned int bpp)
 202 {
 203         fixed20_12 outf = dfixed_init(out);
 204         fixed20_12 inf = dfixed_init(in);
 205         u32 dda_inc;
 206         int max;
 207
 208         if (v)
 209                 max = 15;
 210         else {
 211                 switch (bpp) {
 212                 case 2:
 213                         max = 8;
 214                         break;
 215
 216                 default:
 217                         WARN_ON_ONCE(1);
 218                         /* fallthrough */
 219                 case 4:
 220                         max = 4;
 221                         break;
 222                 }
 223         }
 224
 225         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 226         inf.full -= dfixed_const(1);
 227
 228         dda_inc = dfixed_div(inf, outf);
 229         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 230
 231         return dda_inc;
 232 }
 233
 234 static inline u32 compute_initial_dda(unsigned int in)
 235 {
 236         fixed20_12 inf = dfixed_init(in);
 237         return dfixed_frac(inf);
 238 }
 239
 240 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 241                                   const struct tegra_dc_window *window)
 242 {
 243         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 244         unsigned long value, flags;
 245         bool yuv, planar;
 246
 247         /*
 248          * For YUV planar modes, the number of bytes per pixel takes into
 249          * account only the luma component and therefore is 1.
 250          */
 251         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 252         if (!yuv)
 253                 bpp = window->bits_per_pixel / 8;
 254         else
 255                 bpp = planar ? 1 : 2;
 256
 257         spin_lock_irqsave(&dc->lock, flags);
 258
 259         value = WINDOW_A_SELECT << index;
 260         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 261
 262         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 263         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 264
 265         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 266         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 267
 268         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 269         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 270
 271         h_offset = window->src.x * bpp;
 272         v_offset = window->src.y;
 273         h_size = window->src.w * bpp;
 274         v_size = window->src.h;
 275
 276         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 277         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 278
 279         /*
 280          * For DDA computations the number of bytes per pixel for YUV planar
 281          * modes needs to take into account all Y, U and V components.
 282          */
 283         if (yuv && planar)
 284                 bpp = 2;
 285
 286         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 287         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 288
 289         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 290         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 291
 292         h_dda = compute_initial_dda(window->src.x);
 293         v_dda = compute_initial_dda(window->src.y);
 294
 295         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 296         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 297
 298         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 299         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 300
 301         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 302
 303         if (yuv && planar) {
 304                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 305                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 306                 value = window->stride[1] << 16 | window->stride[0];
 307                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 308         } else {
 309                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 310         }
 311
 312         if (window->bottom_up)
 313                 v_offset += window->src.h - 1;
 314
 315         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 316         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 317
 318         if (dc->soc->supports_block_linear) {
 319                 unsigned long height = window->tiling.value;
 320
 321                 switch (window->tiling.mode) {
 322                 case TEGRA_BO_TILING_MODE_PITCH:
 323                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 324                         break;
 325
 326                 case TEGRA_BO_TILING_MODE_TILED:
 327                         value = DC_WINBUF_SURFACE_KIND_TILED;
 328                         break;
 329
 330                 case TEGRA_BO_TILING_MODE_BLOCK:
 331                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 332                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 333                         break;
 334                 }
 335
 336                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 337         } else {
 338                 switch (window->tiling.mode) {
 339                 case TEGRA_BO_TILING_MODE_PITCH:
 340                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 341                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 342                         break;
 343
 344                 case TEGRA_BO_TILING_MODE_TILED:
 345                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 346                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 347                         break;
 348
 349                 case TEGRA_BO_TILING_MODE_BLOCK:
 350                         /*
 351                          * No need to handle this here because ->atomic_check
 352                          * will already have filtered it out.
 353                          */
 354                         break;
 355                 }
 356
 357                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 358         }
 359
 360         value = WIN_ENABLE;
 361
 362         if (yuv) {
 363                 /* setup default colorspace conversion coefficients */
 364                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 365                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 366                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 367                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 368                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 369                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 370                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 371                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 372
 373                 value |= CSC_ENABLE;
 374         } else if (window->bits_per_pixel < 24) {
 375                 value |= COLOR_EXPAND;
 376         }
 377
 378         if (window->bottom_up)
 379                 value |= V_DIRECTION;
 380
 381         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 382
 383         /*
 384          * Disable blending and assume Window A is the bottom-most window,
 385          * Window C is the top-most window and Window B is in the middle.
 386          */
 387         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 388         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 389
 390         switch (index) {
 391         case 0:
 392                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 393                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 394                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 395                 break;
 396
 397         case 1:
 398                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 399                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 400                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 401                 break;
 402
 403         case 2:
 404                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 405                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 406                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 407                 break;
 408         }
 409
 410         spin_unlock_irqrestore(&dc->lock, flags);
 411 }
 412
 413 static void tegra_plane_destroy(struct drm_plane *plane)
 414 {
 415         struct tegra_plane *p = to_tegra_plane(plane);
 416
 417         drm_plane_cleanup(plane);
 418         kfree(p);
 419 }
 420
 421 static const u32 tegra_primary_plane_formats[] = {
 422         DRM_FORMAT_XBGR8888,
 423         DRM_FORMAT_XRGB8888,
 424         DRM_FORMAT_RGB565,
 425 };
 426
 427 static void tegra_primary_plane_destroy(struct drm_plane *plane)
 428 {
 429         tegra_plane_destroy(plane);
 430 }
 431
 432 static void tegra_plane_reset(struct drm_plane *plane)
 433 {
 434         struct tegra_plane_state *state;
 435
 436         if (plane->state)
 437                 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
 438
 439         kfree(plane->state);
 440         plane->state = NULL;
 441
 442         state = kzalloc(sizeof(*state), GFP_KERNEL);
 443         if (state) {
 444                 plane->state = &state->base;
 445                 plane->state->plane = plane;
 446         }
 447 }
 448
 449 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
 450 {
 451         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 452         struct tegra_plane_state *copy;
 453
 454         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
 455         if (!copy)
 456                 return NULL;
 457
 458         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
 459         copy->tiling = state->tiling;
 460         copy->format = state->format;
 461         copy->swap = state->swap;
 462
 463         return &copy->base;
 464 }
 465
 466 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
 467                                              struct drm_plane_state *state)
 468 {
 469         __drm_atomic_helper_plane_destroy_state(plane, state);
 470         kfree(state);
 471 }
 472
 473 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 474         .update_plane = drm_atomic_helper_update_plane,
 475         .disable_plane = drm_atomic_helper_disable_plane,
 476         .destroy = tegra_primary_plane_destroy,
 477         .reset = tegra_plane_reset,
 478         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 479         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 480 };
 481
 482 static int tegra_plane_prepare_fb(struct drm_plane *plane,
 483                                   struct drm_framebuffer *fb,
 484                                   const struct drm_plane_state *new_state)
 485 {
 486         return 0;
 487 }
 488
 489 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
 490                                    struct drm_framebuffer *fb,
 491                                    const struct drm_plane_state *old_fb)
 492 {
 493 }
 494
 495 static int tegra_plane_state_add(struct tegra_plane *plane,
 496                                  struct drm_plane_state *state)
 497 {
 498         struct drm_crtc_state *crtc_state;
 499         struct tegra_dc_state *tegra;
 500
 501         /* Propagate errors from allocation or locking failures. */
 502         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 503         if (IS_ERR(crtc_state))
 504                 return PTR_ERR(crtc_state);
 505
 506         tegra = to_dc_state(crtc_state);
 507
 508         tegra->planes |= WIN_A_ACT_REQ << plane->index;
 509
 510         return 0;
 511 }
 512
 513 static int tegra_plane_atomic_check(struct drm_plane *plane,
 514                                     struct drm_plane_state *state)
 515 {
 516         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 517         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 518         struct tegra_plane *tegra = to_tegra_plane(plane);
 519         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 520         int err;
 521
 522         /* no need for further checks if the plane is being disabled */
 523         if (!state->crtc)
 524                 return 0;
 525
 526         err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
 527                               &plane_state->swap);
 528         if (err < 0)
 529                 return err;
 530
 531         err = tegra_fb_get_tiling(state->fb, tiling);
 532         if (err < 0)
 533                 return err;
 534
 535         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 536             !dc->soc->supports_block_linear) {
 537                 DRM_ERROR("hardware doesn't support block linear mode\n");
 538                 return -EINVAL;
 539         }
 540
 541         /*
 542          * Tegra doesn't support different strides for U and V planes so we
 543          * error out if the user tries to display a framebuffer with such a
 544          * configuration.
 545          */
 546         if (drm_format_num_planes(state->fb->pixel_format) > 2) {
 547                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 548                         DRM_ERROR("unsupported UV-plane configuration\n");
 549                         return -EINVAL;
 550                 }
 551         }
 552
 553         err = tegra_plane_state_add(tegra, state);
 554         if (err < 0)
 555                 return err;
 556
 557         return 0;
 558 }
 559
 560 static void tegra_plane_atomic_update(struct drm_plane *plane,
 561                                       struct drm_plane_state *old_state)
 562 {
 563         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 564         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 565         struct drm_framebuffer *fb = plane->state->fb;
 566         struct tegra_plane *p = to_tegra_plane(plane);
 567         struct tegra_dc_window window;
 568         unsigned int i;
 569
 570         /* rien ne va plus */
 571         if (!plane->state->crtc || !plane->state->fb)
 572                 return;
 573
 574         memset(&window, 0, sizeof(window));
 575         window.src.x = plane->state->src_x >> 16;
 576         window.src.y = plane->state->src_y >> 16;
 577         window.src.w = plane->state->src_w >> 16;
 578         window.src.h = plane->state->src_h >> 16;
 579         window.dst.x = plane->state->crtc_x;
 580         window.dst.y = plane->state->crtc_y;
 581         window.dst.w = plane->state->crtc_w;
 582         window.dst.h = plane->state->crtc_h;
 583         window.bits_per_pixel = fb->bits_per_pixel;
 584         window.bottom_up = tegra_fb_is_bottom_up(fb);
 585
 586         /* copy from state */
 587         window.tiling = state->tiling;
 588         window.format = state->format;
 589         window.swap = state->swap;
 590
 591         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
 592                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 593
 594                 window.base[i] = bo->paddr + fb->offsets[i];
 595                 window.stride[i] = fb->pitches[i];
 596         }
 597
 598         tegra_dc_setup_window(dc, p->index, &window);
 599 }
 600
 601 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 602                                        struct drm_plane_state *old_state)
 603 {
 604         struct tegra_plane *p = to_tegra_plane(plane);
 605         struct tegra_dc *dc;
 606         unsigned long flags;
 607         u32 value;
 608
 609         /* rien ne va plus */
 610         if (!old_state || !old_state->crtc)
 611                 return;
 612
 613         dc = to_tegra_dc(old_state->crtc);
 614
 615         spin_lock_irqsave(&dc->lock, flags);
 616
 617         value = WINDOW_A_SELECT << p->index;
 618         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 619
 620         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 621         value &= ~WIN_ENABLE;
 622         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 623
 624         spin_unlock_irqrestore(&dc->lock, flags);
 625 }
 626
 627 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
 628         .prepare_fb = tegra_plane_prepare_fb,
 629         .cleanup_fb = tegra_plane_cleanup_fb,
 630         .atomic_check = tegra_plane_atomic_check,
 631         .atomic_update = tegra_plane_atomic_update,
 632         .atomic_disable = tegra_plane_atomic_disable,
 633 };
 634
 635 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
 636                                                        struct tegra_dc *dc)
 637 {
 638         /*
 639          * Ideally this would use drm_crtc_mask(), but that would require the
 640          * CRTC to already be in the mode_config's list of CRTCs. However, it
 641          * will only be added to that list in the drm_crtc_init_with_planes()
 642          * (in tegra_dc_init()), which in turn requires registration of these
 643          * planes. So we have ourselves a nice little chicken and egg problem
 644          * here.
 645          *
 646          * We work around this by manually creating the mask from the number
 647          * of CRTCs that have been registered, and should therefore always be
 648          * the same as drm_crtc_index() after registration.
 649          */
 650         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
 651         struct tegra_plane *plane;
 652         unsigned int num_formats;
 653         const u32 *formats;
 654         int err;
 655
 656         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 657         if (!plane)
 658                 return ERR_PTR(-ENOMEM);
 659
 660         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
 661         formats = tegra_primary_plane_formats;
 662
 663         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 664                                        &tegra_primary_plane_funcs, formats,
 665                                        num_formats, DRM_PLANE_TYPE_PRIMARY);
 666         if (err < 0) {
 667                 kfree(plane);
 668                 return ERR_PTR(err);
 669         }
 670
 671         drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
 672
 673         return &plane->base;
 674 }
 675
 676 static const u32 tegra_cursor_plane_formats[] = {
 677         DRM_FORMAT_RGBA8888,
 678 };
 679
 680 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 681                                      struct drm_plane_state *state)
 682 {
 683         struct tegra_plane *tegra = to_tegra_plane(plane);
 684         int err;
 685
 686         /* no need for further checks if the plane is being disabled */
 687         if (!state->crtc)
 688                 return 0;
 689
 690         /* scaling not supported for cursor */
 691         if ((state->src_w >> 16 != state->crtc_w) ||
 692             (state->src_h >> 16 != state->crtc_h))
 693                 return -EINVAL;
 694
 695         /* only square cursors supported */
 696         if (state->src_w != state->src_h)
 697                 return -EINVAL;
 698
 699         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 700             state->crtc_w != 128 && state->crtc_w != 256)
 701                 return -EINVAL;
 702
 703         err = tegra_plane_state_add(tegra, state);
 704         if (err < 0)
 705                 return err;
 706
 707         return 0;
 708 }
 709
 710 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 711                                        struct drm_plane_state *old_state)
 712 {
 713         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 714         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 715         struct drm_plane_state *state = plane->state;
 716         u32 value = CURSOR_CLIP_DISPLAY;
 717
 718         /* rien ne va plus */
 719         if (!plane->state->crtc || !plane->state->fb)
 720                 return;
 721
 722         switch (state->crtc_w) {
 723         case 32:
 724                 value |= CURSOR_SIZE_32x32;
 725                 break;
 726
 727         case 64:
 728                 value |= CURSOR_SIZE_64x64;
 729                 break;
 730
 731         case 128:
 732                 value |= CURSOR_SIZE_128x128;
 733                 break;
 734
 735         case 256:
 736                 value |= CURSOR_SIZE_256x256;
 737                 break;
 738
 739         default:
 740                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 741                      state->crtc_h);
 742                 return;
 743         }
 744
 745         value |= (bo->paddr >> 10) & 0x3fffff;
 746         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 747
 748 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 749         value = (bo->paddr >> 32) & 0x3;
 750         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 751 #endif
 752
 753         /* enable cursor and set blend mode */
 754         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 755         value |= CURSOR_ENABLE;
 756         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 757
 758         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 759         value &= ~CURSOR_DST_BLEND_MASK;
 760         value &= ~CURSOR_SRC_BLEND_MASK;
 761         value |= CURSOR_MODE_NORMAL;
 762         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 763         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 764         value |= CURSOR_ALPHA;
 765         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 766
 767         /* position the cursor */
 768         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 769         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 770 }
 771
 772 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 773                                         struct drm_plane_state *old_state)
 774 {
 775         struct tegra_dc *dc;
 776         u32 value;
 777
 778         /* rien ne va plus */
 779         if (!old_state || !old_state->crtc)
 780                 return;
 781
 782         dc = to_tegra_dc(old_state->crtc);
 783
 784         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 785         value &= ~CURSOR_ENABLE;
 786         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 787 }
 788
 789 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
 790         .update_plane = drm_atomic_helper_update_plane,
 791         .disable_plane = drm_atomic_helper_disable_plane,
 792         .destroy = tegra_plane_destroy,
 793         .reset = tegra_plane_reset,
 794         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 795         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 796 };
 797
 798 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 799         .prepare_fb = tegra_plane_prepare_fb,
 800         .cleanup_fb = tegra_plane_cleanup_fb,
 801         .atomic_check = tegra_cursor_atomic_check,
 802         .atomic_update = tegra_cursor_atomic_update,
 803         .atomic_disable = tegra_cursor_atomic_disable,
 804 };
 805
 806 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 807                                                       struct tegra_dc *dc)
 808 {
 809         struct tegra_plane *plane;
 810         unsigned int num_formats;
 811         const u32 *formats;
 812         int err;
 813
 814         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 815         if (!plane)
 816                 return ERR_PTR(-ENOMEM);
 817
 818         /*
 819          * This index is kind of fake. The cursor isn't a regular plane, but
 820          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 821          * use the same programming. Setting this fake index here allows the
 822          * code in tegra_add_plane_state() to do the right thing without the
 823          * need to special-casing the cursor plane.
 824          */
 825         plane->index = 6;
 826
 827         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 828         formats = tegra_cursor_plane_formats;
 829
 830         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 831                                        &tegra_cursor_plane_funcs, formats,
 832                                        num_formats, DRM_PLANE_TYPE_CURSOR);
 833         if (err < 0) {
 834                 kfree(plane);
 835                 return ERR_PTR(err);
 836         }
 837
 838         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 839
 840         return &plane->base;
 841 }
 842
 843 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
 844 {
 845         tegra_plane_destroy(plane);
 846 }
 847
 848 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
 849         .update_plane = drm_atomic_helper_update_plane,
 850         .disable_plane = drm_atomic_helper_disable_plane,
 851         .destroy = tegra_overlay_plane_destroy,
 852         .reset = tegra_plane_reset,
 853         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 854         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 855 };
 856
 857 static const uint32_t tegra_overlay_plane_formats[] = {
 858         DRM_FORMAT_XBGR8888,
 859         DRM_FORMAT_XRGB8888,
 860         DRM_FORMAT_RGB565,
 861         DRM_FORMAT_UYVY,
 862         DRM_FORMAT_YUYV,
 863         DRM_FORMAT_YUV420,
 864         DRM_FORMAT_YUV422,
 865 };
 866
 867 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
 868         .prepare_fb = tegra_plane_prepare_fb,
 869         .cleanup_fb = tegra_plane_cleanup_fb,
 870         .atomic_check = tegra_plane_atomic_check,
 871         .atomic_update = tegra_plane_atomic_update,
 872         .atomic_disable = tegra_plane_atomic_disable,
 873 };
 874
 875 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
 876                                                        struct tegra_dc *dc,
 877                                                        unsigned int index)
 878 {
 879         struct tegra_plane *plane;
 880         unsigned int num_formats;
 881         const u32 *formats;
 882         int err;
 883
 884         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 885         if (!plane)
 886                 return ERR_PTR(-ENOMEM);
 887
 888         plane->index = index;
 889
 890         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
 891         formats = tegra_overlay_plane_formats;
 892
 893         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 894                                        &tegra_overlay_plane_funcs, formats,
 895                                        num_formats, DRM_PLANE_TYPE_OVERLAY);
 896         if (err < 0) {
 897                 kfree(plane);
 898                 return ERR_PTR(err);
 899         }
 900
 901         drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
 902
 903         return &plane->base;
 904 }
 905
 906 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 907 {
 908         struct drm_plane *plane;
 909         unsigned int i;
 910
 911         for (i = 0; i < 2; i++) {
 912                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
 913                 if (IS_ERR(plane))
 914                         return PTR_ERR(plane);
 915         }
 916
 917         return 0;
 918 }
 919
 920 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
 921 {
 922         if (dc->syncpt)
 923                 return host1x_syncpt_read(dc->syncpt);
 924
 925         /* fallback to software emulated VBLANK counter */
 926         return drm_crtc_vblank_count(&dc->base);
 927 }
 928
 929 void tegra_dc_enable_vblank(struct tegra_dc *dc)
 930 {
 931         unsigned long value, flags;
 932
 933         spin_lock_irqsave(&dc->lock, flags);
 934
 935         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 936         value |= VBLANK_INT;
 937         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 938
 939         spin_unlock_irqrestore(&dc->lock, flags);
 940 }
 941
 942 void tegra_dc_disable_vblank(struct tegra_dc *dc)
 943 {
 944         unsigned long value, flags;
 945
 946         spin_lock_irqsave(&dc->lock, flags);
 947
 948         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 949         value &= ~VBLANK_INT;
 950         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 951
 952         spin_unlock_irqrestore(&dc->lock, flags);
 953 }
 954
 955 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 956 {
 957         struct drm_device *drm = dc->base.dev;
 958         struct drm_crtc *crtc = &dc->base;
 959         unsigned long flags, base;
 960         struct tegra_bo *bo;
 961
 962         spin_lock_irqsave(&drm->event_lock, flags);
 963
 964         if (!dc->event) {
 965                 spin_unlock_irqrestore(&drm->event_lock, flags);
 966                 return;
 967         }
 968
 969         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 970
 971         spin_lock(&dc->lock);
 972
 973         /* check if new start address has been latched */
 974         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 975         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 976         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 977         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 978
 979         spin_unlock(&dc->lock);
 980
 981         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
 982                 drm_crtc_send_vblank_event(crtc, dc->event);
 983                 drm_crtc_vblank_put(crtc);
 984                 dc->event = NULL;
 985         }
 986
 987         spin_unlock_irqrestore(&drm->event_lock, flags);
 988 }
 989
 990 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 991 {
 992         struct tegra_dc *dc = to_tegra_dc(crtc);
 993         struct drm_device *drm = crtc->dev;
 994         unsigned long flags;
 995
 996         spin_lock_irqsave(&drm->event_lock, flags);
 997
 998         if (dc->event && dc->event->base.file_priv == file) {
 999                 dc->event->base.destroy(&dc->event->base);
1000                 drm_crtc_vblank_put(crtc);
1001                 dc->event = NULL;
1002         }
1003
1004         spin_unlock_irqrestore(&drm->event_lock, flags);
1005 }
1006
1007 static void tegra_dc_destroy(struct drm_crtc *crtc)
1008 {
1009         drm_crtc_cleanup(crtc);
1010 }
1011
1012 static void tegra_crtc_reset(struct drm_crtc *crtc)
1013 {
1014         struct tegra_dc_state *state;
1015
1016         if (crtc->state)
1017                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1018
1019         kfree(crtc->state);
1020         crtc->state = NULL;
1021
1022         state = kzalloc(sizeof(*state), GFP_KERNEL);
1023         if (state) {
1024                 crtc->state = &state->base;
1025                 crtc->state->crtc = crtc;
1026         }
1027
1028         drm_crtc_vblank_reset(crtc);
1029 }
1030
1031 static struct drm_crtc_state *
1032 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1033 {
1034         struct tegra_dc_state *state = to_dc_state(crtc->state);
1035         struct tegra_dc_state *copy;
1036
1037         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1038         if (!copy)
1039                 return NULL;
1040
1041         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1042         copy->clk = state->clk;
1043         copy->pclk = state->pclk;
1044         copy->div = state->div;
1045         copy->planes = state->planes;
1046
1047         return &copy->base;
1048 }
1049
1050 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1051                                             struct drm_crtc_state *state)
1052 {
1053         __drm_atomic_helper_crtc_destroy_state(crtc, state);
1054         kfree(state);
1055 }
1056
1057 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1058         .page_flip = drm_atomic_helper_page_flip,
1059         .set_config = drm_atomic_helper_set_config,
1060         .destroy = tegra_dc_destroy,
1061         .reset = tegra_crtc_reset,
1062         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1063         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1064 };
1065
1066 static void tegra_dc_stop(struct tegra_dc *dc)
1067 {
1068         u32 value;
1069
1070         /* stop the display controller */
1071         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1072         value &= ~DISP_CTRL_MODE_MASK;
1073         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1074
1075         tegra_dc_commit(dc);
1076 }
1077
1078 static bool tegra_dc_idle(struct tegra_dc *dc)
1079 {
1080         u32 value;
1081
1082         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1083
1084         return (value & DISP_CTRL_MODE_MASK) == 0;
1085 }
1086
1087 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1088 {
1089         timeout = jiffies + msecs_to_jiffies(timeout);
1090
1091         while (time_before(jiffies, timeout)) {
1092                 if (tegra_dc_idle(dc))
1093                         return 0;
1094
1095                 usleep_range(1000, 2000);
1096         }
1097
1098         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1099         return -ETIMEDOUT;
1100 }
1101
1102 static void tegra_crtc_disable(struct drm_crtc *crtc)
1103 {
1104         struct tegra_dc *dc = to_tegra_dc(crtc);
1105         u32 value;
1106
1107         if (!tegra_dc_idle(dc)) {
1108                 tegra_dc_stop(dc);
1109
1110                 /*
1111                  * Ignore the return value, there isn't anything useful to do
1112                  * in case this fails.
1113                  */
1114                 tegra_dc_wait_idle(dc, 100);
1115         }
1116
1117         /*
1118          * This should really be part of the RGB encoder driver, but clearing
1119          * these bits has the side-effect of stopping the display controller.
1120          * When that happens no VBLANK interrupts will be raised. At the same
1121          * time the encoder is disabled before the display controller, so the
1122          * above code is always going to timeout waiting for the controller
1123          * to go idle.
1124          *
1125          * Given the close coupling between the RGB encoder and the display
1126          * controller doing it here is still kind of okay. None of the other
1127          * encoder drivers require these bits to be cleared.
1128          *
1129          * XXX: Perhaps given that the display controller is switched off at
1130          * this point anyway maybe clearing these bits isn't even useful for
1131          * the RGB encoder?
1132          */
1133         if (dc->rgb) {
1134                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1135                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1136                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1137                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1138         }
1139
1140         tegra_dc_stats_reset(&dc->stats);
1141         drm_crtc_vblank_off(crtc);
1142 }
1143
1144 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
1145                                   const struct drm_display_mode *mode,
1146                                   struct drm_display_mode *adjusted)
1147 {
1148         return true;
1149 }
1150
1151 static int tegra_dc_set_timings(struct tegra_dc *dc,
1152                                 struct drm_display_mode *mode)
1153 {
1154         unsigned int h_ref_to_sync = 1;
1155         unsigned int v_ref_to_sync = 1;
1156         unsigned long value;
1157
1158         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1159
1160         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1161         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1162
1163         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1164                 ((mode->hsync_end - mode->hsync_start) <<  0);
1165         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1166
1167         value = ((mode->vtotal - mode->vsync_end) << 16) |
1168                 ((mode->htotal - mode->hsync_end) <<  0);
1169         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1170
1171         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1172                 ((mode->hsync_start - mode->hdisplay) <<  0);
1173         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1174
1175         value = (mode->vdisplay << 16) | mode->hdisplay;
1176         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1177
1178         return 0;
1179 }
1180
1181 /**
1182  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1183  *     state
1184  * @dc: display controller
1185  * @crtc_state: CRTC atomic state
1186  * @clk: parent clock for display controller
1187  * @pclk: pixel clock
1188  * @div: shift clock divider
1189  *
1190  * Returns:
1191  * 0 on success or a negative error-code on failure.
1192  */
1193 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1194                                struct drm_crtc_state *crtc_state,
1195                                struct clk *clk, unsigned long pclk,
1196                                unsigned int div)
1197 {
1198         struct tegra_dc_state *state = to_dc_state(crtc_state);
1199
1200         if (!clk_has_parent(dc->clk, clk))
1201                 return -EINVAL;
1202
1203         state->clk = clk;
1204         state->pclk = pclk;
1205         state->div = div;
1206
1207         return 0;
1208 }
1209
1210 static void tegra_dc_commit_state(struct tegra_dc *dc,
1211                                   struct tegra_dc_state *state)
1212 {
1213         u32 value;
1214         int err;
1215
1216         err = clk_set_parent(dc->clk, state->clk);
1217         if (err < 0)
1218                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1219
1220         /*
1221          * Outputs may not want to change the parent clock rate. This is only
1222          * relevant to Tegra20 where only a single display PLL is available.
1223          * Since that PLL would typically be used for HDMI, an internal LVDS
1224          * panel would need to be driven by some other clock such as PLL_P
1225          * which is shared with other peripherals. Changing the clock rate
1226          * should therefore be avoided.
1227          */
1228         if (state->pclk > 0) {
1229                 err = clk_set_rate(state->clk, state->pclk);
1230                 if (err < 0)
1231                         dev_err(dc->dev,
1232                                 "failed to set clock rate to %lu Hz\n",
1233                                 state->pclk);
1234         }
1235
1236         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1237                       state->div);
1238         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1239
1240         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1241         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1242 }
1243
1244 static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
1245 {
1246         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1247         struct tegra_dc_state *state = to_dc_state(crtc->state);
1248         struct tegra_dc *dc = to_tegra_dc(crtc);
1249         u32 value;
1250
1251         tegra_dc_commit_state(dc, state);
1252
1253         /* program display mode */
1254         tegra_dc_set_timings(dc, mode);
1255
1256         /* interlacing isn't supported yet, so disable it */
1257         if (dc->soc->supports_interlacing) {
1258                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1259                 value &= ~INTERLACE_ENABLE;
1260                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1261         }
1262
1263         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1264         value &= ~DISP_CTRL_MODE_MASK;
1265         value |= DISP_CTRL_MODE_C_DISPLAY;
1266         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1267
1268         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1269         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1270                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1271         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1272
1273         tegra_dc_commit(dc);
1274 }
1275
1276 static void tegra_crtc_prepare(struct drm_crtc *crtc)
1277 {
1278         drm_crtc_vblank_off(crtc);
1279 }
1280
1281 static void tegra_crtc_commit(struct drm_crtc *crtc)
1282 {
1283         drm_crtc_vblank_on(crtc);
1284 }
1285
1286 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1287                                    struct drm_crtc_state *state)
1288 {
1289         return 0;
1290 }
1291
1292 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc)
1293 {
1294         struct tegra_dc *dc = to_tegra_dc(crtc);
1295
1296         if (crtc->state->event) {
1297                 crtc->state->event->pipe = drm_crtc_index(crtc);
1298
1299                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1300
1301                 dc->event = crtc->state->event;
1302                 crtc->state->event = NULL;
1303         }
1304 }
1305
1306 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc)
1307 {
1308         struct tegra_dc_state *state = to_dc_state(crtc->state);
1309         struct tegra_dc *dc = to_tegra_dc(crtc);
1310
1311         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1312         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1313 }
1314
1315 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1316         .disable = tegra_crtc_disable,
1317         .mode_fixup = tegra_crtc_mode_fixup,
1318         .mode_set_nofb = tegra_crtc_mode_set_nofb,
1319         .prepare = tegra_crtc_prepare,
1320         .commit = tegra_crtc_commit,
1321         .atomic_check = tegra_crtc_atomic_check,
1322         .atomic_begin = tegra_crtc_atomic_begin,
1323         .atomic_flush = tegra_crtc_atomic_flush,
1324 };
1325
1326 static irqreturn_t tegra_dc_irq(int irq, void *data)
1327 {
1328         struct tegra_dc *dc = data;
1329         unsigned long status;
1330
1331         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1332         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1333
1334         if (status & FRAME_END_INT) {
1335                 /*
1336                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1337                 */
1338                 dc->stats.frames++;
1339         }
1340
1341         if (status & VBLANK_INT) {
1342                 /*
1343                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1344                 */
1345                 drm_crtc_handle_vblank(&dc->base);
1346                 tegra_dc_finish_page_flip(dc);
1347                 dc->stats.vblank++;
1348         }
1349
1350         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1351                 /*
1352                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1353                 */
1354                 dc->stats.underflow++;
1355         }
1356
1357         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1358                 /*
1359                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1360                 */
1361                 dc->stats.overflow++;
1362         }
1363
1364         return IRQ_HANDLED;
1365 }
1366
1367 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1368 {
1369         struct drm_info_node *node = s->private;
1370         struct tegra_dc *dc = node->info_ent->data;
1371
1372 #define DUMP_REG(name)                                          \
1373         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1374                    tegra_dc_readl(dc, name))
1375
1376         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1377         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1378         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1379         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1380         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1381         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1382         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1383         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1384         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1385         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1386         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1387         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1388         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1389         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1390         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1391         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1392         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1393         DUMP_REG(DC_CMD_INT_STATUS);
1394         DUMP_REG(DC_CMD_INT_MASK);
1395         DUMP_REG(DC_CMD_INT_ENABLE);
1396         DUMP_REG(DC_CMD_INT_TYPE);
1397         DUMP_REG(DC_CMD_INT_POLARITY);
1398         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1399         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1400         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1401         DUMP_REG(DC_CMD_STATE_ACCESS);
1402         DUMP_REG(DC_CMD_STATE_CONTROL);
1403         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1404         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1405         DUMP_REG(DC_COM_CRC_CONTROL);
1406         DUMP_REG(DC_COM_CRC_CHECKSUM);
1407         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1408         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1409         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1410         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1411         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1412         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1413         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1414         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1415         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1416         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1417         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1418         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1419         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1420         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1421         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1422         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1423         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1424         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1425         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1426         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1427         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1428         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1429         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1430         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1431         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1432         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1433         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1434         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1435         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1436         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1437         DUMP_REG(DC_COM_SPI_CONTROL);
1438         DUMP_REG(DC_COM_SPI_START_BYTE);
1439         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1440         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1441         DUMP_REG(DC_COM_HSPI_CS_DC);
1442         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1443         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1444         DUMP_REG(DC_COM_GPIO_CTRL);
1445         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1446         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1447         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1448         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1449         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1450         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1451         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1452         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1453         DUMP_REG(DC_DISP_REF_TO_SYNC);
1454         DUMP_REG(DC_DISP_SYNC_WIDTH);
1455         DUMP_REG(DC_DISP_BACK_PORCH);
1456         DUMP_REG(DC_DISP_ACTIVE);
1457         DUMP_REG(DC_DISP_FRONT_PORCH);
1458         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1459         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1460         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1461         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1462         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1463         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1464         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1465         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1466         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1467         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1468         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1469         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1470         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1471         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1472         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1473         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1474         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1475         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1476         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1477         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1478         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1479         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1480         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1481         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1482         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1483         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1484         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1485         DUMP_REG(DC_DISP_M0_CONTROL);
1486         DUMP_REG(DC_DISP_M1_CONTROL);
1487         DUMP_REG(DC_DISP_DI_CONTROL);
1488         DUMP_REG(DC_DISP_PP_CONTROL);
1489         DUMP_REG(DC_DISP_PP_SELECT_A);
1490         DUMP_REG(DC_DISP_PP_SELECT_B);
1491         DUMP_REG(DC_DISP_PP_SELECT_C);
1492         DUMP_REG(DC_DISP_PP_SELECT_D);
1493         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1494         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1495         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1496         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1497         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1498         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1499         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1500         DUMP_REG(DC_DISP_BORDER_COLOR);
1501         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1502         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1503         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1504         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1505         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1506         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1507         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1508         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1509         DUMP_REG(DC_DISP_CURSOR_POSITION);
1510         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1511         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1512         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1513         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1514         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1515         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1516         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1517         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1518         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1519         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1520         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1521         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1522         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1523         DUMP_REG(DC_DISP_SD_CONTROL);
1524         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1525         DUMP_REG(DC_DISP_SD_LUT(0));
1526         DUMP_REG(DC_DISP_SD_LUT(1));
1527         DUMP_REG(DC_DISP_SD_LUT(2));
1528         DUMP_REG(DC_DISP_SD_LUT(3));
1529         DUMP_REG(DC_DISP_SD_LUT(4));
1530         DUMP_REG(DC_DISP_SD_LUT(5));
1531         DUMP_REG(DC_DISP_SD_LUT(6));
1532         DUMP_REG(DC_DISP_SD_LUT(7));
1533         DUMP_REG(DC_DISP_SD_LUT(8));
1534         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1535         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1536         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1537         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1538         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1539         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1540         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1541         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1542         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1543         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1544         DUMP_REG(DC_DISP_SD_BL_TF(0));
1545         DUMP_REG(DC_DISP_SD_BL_TF(1));
1546         DUMP_REG(DC_DISP_SD_BL_TF(2));
1547         DUMP_REG(DC_DISP_SD_BL_TF(3));
1548         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1549         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1550         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1551         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1552         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1553         DUMP_REG(DC_WIN_WIN_OPTIONS);
1554         DUMP_REG(DC_WIN_BYTE_SWAP);
1555         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1556         DUMP_REG(DC_WIN_COLOR_DEPTH);
1557         DUMP_REG(DC_WIN_POSITION);
1558         DUMP_REG(DC_WIN_SIZE);
1559         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1560         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1561         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1562         DUMP_REG(DC_WIN_DDA_INC);
1563         DUMP_REG(DC_WIN_LINE_STRIDE);
1564         DUMP_REG(DC_WIN_BUF_STRIDE);
1565         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1566         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1567         DUMP_REG(DC_WIN_DV_CONTROL);
1568         DUMP_REG(DC_WIN_BLEND_NOKEY);
1569         DUMP_REG(DC_WIN_BLEND_1WIN);
1570         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1571         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1572         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1573         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1574         DUMP_REG(DC_WINBUF_START_ADDR);
1575         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1576         DUMP_REG(DC_WINBUF_START_ADDR_U);
1577         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1578         DUMP_REG(DC_WINBUF_START_ADDR_V);
1579         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1580         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1581         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1582         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1583         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1584         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1585         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1586         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1587         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1588
1589 #undef DUMP_REG
1590
1591         return 0;
1592 }
1593
1594 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1595 {
1596         struct drm_info_node *node = s->private;
1597         struct tegra_dc *dc = node->info_ent->data;
1598         u32 value;
1599
1600         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1601         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1602         tegra_dc_commit(dc);
1603
1604         drm_crtc_wait_one_vblank(&dc->base);
1605         drm_crtc_wait_one_vblank(&dc->base);
1606
1607         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1608         seq_printf(s, "%08x\n", value);
1609
1610         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1611
1612         return 0;
1613 }
1614
1615 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1616 {
1617         struct drm_info_node *node = s->private;
1618         struct tegra_dc *dc = node->info_ent->data;
1619
1620         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1621         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1622         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1623         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1624
1625         return 0;
1626 }
1627
1628 static struct drm_info_list debugfs_files[] = {
1629         { "regs", tegra_dc_show_regs, 0, NULL },
1630         { "crc", tegra_dc_show_crc, 0, NULL },
1631         { "stats", tegra_dc_show_stats, 0, NULL },
1632 };
1633
1634 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1635 {
1636         unsigned int i;
1637         char *name;
1638         int err;
1639
1640         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1641         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1642         kfree(name);
1643
1644         if (!dc->debugfs)
1645                 return -ENOMEM;
1646
1647         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1648                                     GFP_KERNEL);
1649         if (!dc->debugfs_files) {
1650                 err = -ENOMEM;
1651                 goto remove;
1652         }
1653
1654         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1655                 dc->debugfs_files[i].data = dc;
1656
1657         err = drm_debugfs_create_files(dc->debugfs_files,
1658                                        ARRAY_SIZE(debugfs_files),
1659                                        dc->debugfs, minor);
1660         if (err < 0)
1661                 goto free;
1662
1663         dc->minor = minor;
1664
1665         return 0;
1666
1667 free:
1668         kfree(dc->debugfs_files);
1669         dc->debugfs_files = NULL;
1670 remove:
1671         debugfs_remove(dc->debugfs);
1672         dc->debugfs = NULL;
1673
1674         return err;
1675 }
1676
1677 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1678 {
1679         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1680                                  dc->minor);
1681         dc->minor = NULL;
1682
1683         kfree(dc->debugfs_files);
1684         dc->debugfs_files = NULL;
1685
1686         debugfs_remove(dc->debugfs);
1687         dc->debugfs = NULL;
1688
1689         return 0;
1690 }
1691
1692 static int tegra_dc_init(struct host1x_client *client)
1693 {
1694         struct drm_device *drm = dev_get_drvdata(client->parent);
1695         struct tegra_dc *dc = host1x_client_to_dc(client);
1696         struct tegra_drm *tegra = drm->dev_private;
1697         struct drm_plane *primary = NULL;
1698         struct drm_plane *cursor = NULL;
1699         u32 value;
1700         int err;
1701
1702         if (tegra->domain) {
1703                 err = iommu_attach_device(tegra->domain, dc->dev);
1704                 if (err < 0) {
1705                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1706                                 err);
1707                         return err;
1708                 }
1709
1710                 dc->domain = tegra->domain;
1711         }
1712
1713         primary = tegra_dc_primary_plane_create(drm, dc);
1714         if (IS_ERR(primary)) {
1715                 err = PTR_ERR(primary);
1716                 goto cleanup;
1717         }
1718
1719         if (dc->soc->supports_cursor) {
1720                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1721                 if (IS_ERR(cursor)) {
1722                         err = PTR_ERR(cursor);
1723                         goto cleanup;
1724                 }
1725         }
1726
1727         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1728                                         &tegra_crtc_funcs);
1729         if (err < 0)
1730                 goto cleanup;
1731
1732         drm_mode_crtc_set_gamma_size(&dc->base, 256);
1733         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1734
1735         /*
1736          * Keep track of the minimum pitch alignment across all display
1737          * controllers.
1738          */
1739         if (dc->soc->pitch_align > tegra->pitch_align)
1740                 tegra->pitch_align = dc->soc->pitch_align;
1741
1742         err = tegra_dc_rgb_init(drm, dc);
1743         if (err < 0 && err != -ENODEV) {
1744                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1745                 goto cleanup;
1746         }
1747
1748         err = tegra_dc_add_planes(drm, dc);
1749         if (err < 0)
1750                 goto cleanup;
1751
1752         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1753                 err = tegra_dc_debugfs_init(dc, drm->primary);
1754                 if (err < 0)
1755                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1756         }
1757
1758         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1759                                dev_name(dc->dev), dc);
1760         if (err < 0) {
1761                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1762                         err);
1763                 goto cleanup;
1764         }
1765
1766         /* initialize display controller */
1767         if (dc->syncpt) {
1768                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1769
1770                 value = SYNCPT_CNTRL_NO_STALL;
1771                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1772
1773                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1774                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1775         }
1776
1777         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1778                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1779         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1780
1781         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1782                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1783         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1784
1785         /* initialize timer */
1786         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1787                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1788         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1789
1790         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1791                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1792         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1793
1794         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1795                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1796         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1797
1798         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1799                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1800         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1801
1802         if (dc->soc->supports_border_color)
1803                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1804
1805         tegra_dc_stats_reset(&dc->stats);
1806
1807         return 0;
1808
1809 cleanup:
1810         if (cursor)
1811                 drm_plane_cleanup(cursor);
1812
1813         if (primary)
1814                 drm_plane_cleanup(primary);
1815
1816         if (tegra->domain) {
1817                 iommu_detach_device(tegra->domain, dc->dev);
1818                 dc->domain = NULL;
1819         }
1820
1821         return err;
1822 }
1823
1824 static int tegra_dc_exit(struct host1x_client *client)
1825 {
1826         struct tegra_dc *dc = host1x_client_to_dc(client);
1827         int err;
1828
1829         devm_free_irq(dc->dev, dc->irq, dc);
1830
1831         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1832                 err = tegra_dc_debugfs_exit(dc);
1833                 if (err < 0)
1834                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1835         }
1836
1837         err = tegra_dc_rgb_exit(dc);
1838         if (err) {
1839                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1840                 return err;
1841         }
1842
1843         if (dc->domain) {
1844                 iommu_detach_device(dc->domain, dc->dev);
1845                 dc->domain = NULL;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static const struct host1x_client_ops dc_client_ops = {
1852         .init = tegra_dc_init,
1853         .exit = tegra_dc_exit,
1854 };
1855
1856 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1857         .supports_border_color = true,
1858         .supports_interlacing = false,
1859         .supports_cursor = false,
1860         .supports_block_linear = false,
1861         .pitch_align = 8,
1862         .has_powergate = false,
1863 };
1864
1865 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1866         .supports_border_color = true,
1867         .supports_interlacing = false,
1868         .supports_cursor = false,
1869         .supports_block_linear = false,
1870         .pitch_align = 8,
1871         .has_powergate = false,
1872 };
1873
1874 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1875         .supports_border_color = true,
1876         .supports_interlacing = false,
1877         .supports_cursor = false,
1878         .supports_block_linear = false,
1879         .pitch_align = 64,
1880         .has_powergate = true,
1881 };
1882
1883 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1884         .supports_border_color = false,
1885         .supports_interlacing = true,
1886         .supports_cursor = true,
1887         .supports_block_linear = true,
1888         .pitch_align = 64,
1889         .has_powergate = true,
1890 };
1891
1892 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1893         .supports_border_color = false,
1894         .supports_interlacing = true,
1895         .supports_cursor = true,
1896         .supports_block_linear = true,
1897         .pitch_align = 64,
1898         .has_powergate = true,
1899 };
1900
1901 static const struct of_device_id tegra_dc_of_match[] = {
1902         {
1903                 .compatible = "nvidia,tegra210-dc",
1904                 .data = &tegra210_dc_soc_info,
1905         }, {
1906                 .compatible = "nvidia,tegra124-dc",
1907                 .data = &tegra124_dc_soc_info,
1908         }, {
1909                 .compatible = "nvidia,tegra114-dc",
1910                 .data = &tegra114_dc_soc_info,
1911         }, {
1912                 .compatible = "nvidia,tegra30-dc",
1913                 .data = &tegra30_dc_soc_info,
1914         }, {
1915                 .compatible = "nvidia,tegra20-dc",
1916                 .data = &tegra20_dc_soc_info,
1917         }, {
1918                 /* sentinel */
1919         }
1920 };
1921 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1922
1923 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1924 {
1925         struct device_node *np;
1926         u32 value = 0;
1927         int err;
1928
1929         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1930         if (err < 0) {
1931                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1932
1933                 /*
1934                  * If the nvidia,head property isn't present, try to find the
1935                  * correct head number by looking up the position of this
1936                  * display controller's node within the device tree. Assuming
1937                  * that the nodes are ordered properly in the DTS file and
1938                  * that the translation into a flattened device tree blob
1939                  * preserves that ordering this will actually yield the right
1940                  * head number.
1941                  *
1942                  * If those assumptions don't hold, this will still work for
1943                  * cases where only a single display controller is used.
1944                  */
1945                 for_each_matching_node(np, tegra_dc_of_match) {
1946                         if (np == dc->dev->of_node)
1947                                 break;
1948
1949                         value++;
1950                 }
1951         }
1952
1953         dc->pipe = value;
1954
1955         return 0;
1956 }
1957
1958 static int tegra_dc_probe(struct platform_device *pdev)
1959 {
1960         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1961         const struct of_device_id *id;
1962         struct resource *regs;
1963         struct tegra_dc *dc;
1964         int err;
1965
1966         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1967         if (!dc)
1968                 return -ENOMEM;
1969
1970         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1971         if (!id)
1972                 return -ENODEV;
1973
1974         spin_lock_init(&dc->lock);
1975         INIT_LIST_HEAD(&dc->list);
1976         dc->dev = &pdev->dev;
1977         dc->soc = id->data;
1978
1979         err = tegra_dc_parse_dt(dc);
1980         if (err < 0)
1981                 return err;
1982
1983         dc->clk = devm_clk_get(&pdev->dev, NULL);
1984         if (IS_ERR(dc->clk)) {
1985                 dev_err(&pdev->dev, "failed to get clock\n");
1986                 return PTR_ERR(dc->clk);
1987         }
1988
1989         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1990         if (IS_ERR(dc->rst)) {
1991                 dev_err(&pdev->dev, "failed to get reset\n");
1992                 return PTR_ERR(dc->rst);
1993         }
1994
1995         if (dc->soc->has_powergate) {
1996                 if (dc->pipe == 0)
1997                         dc->powergate = TEGRA_POWERGATE_DIS;
1998                 else
1999                         dc->powergate = TEGRA_POWERGATE_DISB;
2000
2001                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2002                                                         dc->rst);
2003                 if (err < 0) {
2004                         dev_err(&pdev->dev, "failed to power partition: %d\n",
2005                                 err);
2006                         return err;
2007                 }
2008         } else {
2009                 err = clk_prepare_enable(dc->clk);
2010                 if (err < 0) {
2011                         dev_err(&pdev->dev, "failed to enable clock: %d\n",
2012                                 err);
2013                         return err;
2014                 }
2015
2016                 err = reset_control_deassert(dc->rst);
2017                 if (err < 0) {
2018                         dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2019                                 err);
2020                         return err;
2021                 }
2022         }
2023
2024         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2025         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2026         if (IS_ERR(dc->regs))
2027                 return PTR_ERR(dc->regs);
2028
2029         dc->irq = platform_get_irq(pdev, 0);
2030         if (dc->irq < 0) {
2031                 dev_err(&pdev->dev, "failed to get IRQ\n");
2032                 return -ENXIO;
2033         }
2034
2035         dc->syncpt = host1x_syncpt_request(&pdev->dev, flags);
2036         if (!dc->syncpt)
2037                 dev_warn(&pdev->dev, "failed to allocate syncpoint\n");
2038
2039         INIT_LIST_HEAD(&dc->client.list);
2040         dc->client.ops = &dc_client_ops;
2041         dc->client.dev = &pdev->dev;
2042
2043         err = tegra_dc_rgb_probe(dc);
2044         if (err < 0 && err != -ENODEV) {
2045                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2046                 return err;
2047         }
2048
2049         err = host1x_client_register(&dc->client);
2050         if (err < 0) {
2051                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2052                         err);
2053                 return err;
2054         }
2055
2056         platform_set_drvdata(pdev, dc);
2057
2058         return 0;
2059 }
2060
2061 static int tegra_dc_remove(struct platform_device *pdev)
2062 {
2063         struct tegra_dc *dc = platform_get_drvdata(pdev);
2064         int err;
2065
2066         host1x_syncpt_free(dc->syncpt);
2067
2068         err = host1x_client_unregister(&dc->client);
2069         if (err < 0) {
2070                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2071                         err);
2072                 return err;
2073         }
2074
2075         err = tegra_dc_rgb_remove(dc);
2076         if (err < 0) {
2077                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2078                 return err;
2079         }
2080
2081         reset_control_assert(dc->rst);
2082
2083         if (dc->soc->has_powergate)
2084                 tegra_powergate_power_off(dc->powergate);
2085
2086         clk_disable_unprepare(dc->clk);
2087
2088         return 0;
2089 }
2090
2091 struct platform_driver tegra_dc_driver = {
2092         .driver = {
2093                 .name = "tegra-dc",
2094                 .of_match_table = tegra_dc_of_match,
2095         },
2096         .probe = tegra_dc_probe,
2097         .remove = tegra_dc_remove,
2098 };