drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG(off, _mask, s) \
  24                 {.offset = off, \
  25                  .mask = _mask, \
  26                  .shift = s, \
  27                  .write_mask = false,}
  28
  29 #define VOP_REG_MASK(off, _mask, s) \
  30                 {.offset = off, \
  31                  .mask = _mask, \
  32                  .shift = s, \
  33                  .write_mask = true,}
  34
  35 static const uint32_t formats_win_full[] = {
  36         DRM_FORMAT_XRGB8888,
  37         DRM_FORMAT_ARGB8888,
  38         DRM_FORMAT_XBGR8888,
  39         DRM_FORMAT_ABGR8888,
  40         DRM_FORMAT_RGB888,
  41         DRM_FORMAT_BGR888,
  42         DRM_FORMAT_RGB565,
  43         DRM_FORMAT_BGR565,
  44         DRM_FORMAT_NV12,
  45         DRM_FORMAT_NV16,
  46         DRM_FORMAT_NV24,
  47 };
  48
  49 static const uint32_t formats_win_lite[] = {
  50         DRM_FORMAT_XRGB8888,
  51         DRM_FORMAT_ARGB8888,
  52         DRM_FORMAT_XBGR8888,
  53         DRM_FORMAT_ABGR8888,
  54         DRM_FORMAT_RGB888,
  55         DRM_FORMAT_BGR888,
  56         DRM_FORMAT_RGB565,
  57         DRM_FORMAT_BGR565,
  58 };
  59
  60 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  61         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  62         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  63         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  64         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  65         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  66         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  67         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  68         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  69         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  70         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  71         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  72         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  73         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  74         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  75         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  76         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  77         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  78         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  79         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  80         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  81         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  82 };
  83
  84 static const struct vop_scl_regs rk3288_win_full_scl = {
  85         .ext = &rk3288_win_full_scl_ext,
  86         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  87         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
  88         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
  89         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
  90 };
  91
  92 static const struct vop_win_phy rk3288_win01_data = {
  93         .scl = &rk3288_win_full_scl,
  94         .data_formats = formats_win_full,
  95         .nformats = ARRAY_SIZE(formats_win_full),
  96         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
  97         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
  98         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
  99         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 100         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 101         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 102         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 103         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 104         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 105         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 106         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 107         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
 108 };
 109
 110 static const struct vop_win_phy rk3288_win23_data = {
 111         .data_formats = formats_win_lite,
 112         .nformats = ARRAY_SIZE(formats_win_lite),
 113         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 114         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 115         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 116         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 117         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 118         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 120         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 121         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 122 };
 123
 124 static const struct vop_win_phy rk3288_area1_data = {
 125         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 126         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 127         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 128         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 129         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 130 };
 131
 132 static const struct vop_win_phy rk3288_area2_data = {
 133         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 134         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 135         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 136         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 137         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 138 };
 139
 140 static const struct vop_win_phy rk3288_area3_data = {
 141         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 142         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 143         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 144         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 145         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 146 };
 147
 148 static const struct vop_win_phy *rk3288_area_data[] = {
 149         &rk3288_area1_data,
 150         &rk3288_area2_data,
 151         &rk3288_area3_data
 152 };
 153
 154 static const struct vop_ctrl rk3288_ctrl_data = {
 155         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 156         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 157         .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 158         .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
 159         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 160         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 161         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 162         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 163         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 164         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 165         .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
 166         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 167         .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
 168         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 169         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 170         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 171         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 172         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 173         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 174         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 175 };
 176
 177 static const struct vop_reg_data rk3288_init_reg_table[] = {
 178         {RK3288_SYS_CTRL, 0x00c00000},
 179         {RK3288_DSP_CTRL0, 0x00000000},
 180         {RK3288_WIN0_CTRL0, 0x00000080},
 181         {RK3288_WIN1_CTRL0, 0x00000080},
 182         /*
 183          * Bit[0] is win2/3 gate en bit, there is no power consume with this
 184          * bit enable. the bit's function similar with area plane enable bit,
 185          * So default enable this bit, then We can control win2/3 area plane
 186          * with its enable bit.
 187          */
 188         {RK3288_WIN2_CTRL0, 0x00000001},
 189         {RK3288_WIN3_CTRL0, 0x00000001},
 190 };
 191
 192 /*
 193  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 194  * special support to get alpha blending working.  For now, just use overlay
 195  * window 3 for the drm cursor.
 196  *
 197  */
 198 static const struct vop_win_data rk3288_vop_win_data[] = {
 199         { .base = 0x00, .phy = &rk3288_win01_data,
 200           .type = DRM_PLANE_TYPE_PRIMARY },
 201         { .base = 0x40, .phy = &rk3288_win01_data,
 202           .type = DRM_PLANE_TYPE_OVERLAY },
 203         { .base = 0x00, .phy = &rk3288_win23_data,
 204           .type = DRM_PLANE_TYPE_OVERLAY,
 205           .area = rk3288_area_data,
 206           .area_size = ARRAY_SIZE(rk3288_area_data), },
 207         { .base = 0x50, .phy = &rk3288_win23_data,
 208           .type = DRM_PLANE_TYPE_CURSOR,
 209           .area = rk3288_area_data,
 210           .area_size = ARRAY_SIZE(rk3288_area_data), },
 211 };
 212
 213 static const int rk3288_vop_intrs[] = {
 214         DSP_HOLD_VALID_INTR,
 215         FS_INTR,
 216         LINE_FLAG_INTR,
 217         BUS_ERROR_INTR,
 218 };
 219
 220 static const struct vop_intr rk3288_vop_intr = {
 221         .intrs = rk3288_vop_intrs,
 222         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 223         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 224         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 225         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 226 };
 227
 228 static const struct vop_data rk3288_vop = {
 229         .init_table = rk3288_init_reg_table,
 230         .table_size = ARRAY_SIZE(rk3288_init_reg_table),
 231         .intr = &rk3288_vop_intr,
 232         .ctrl = &rk3288_ctrl_data,
 233         .win = rk3288_vop_win_data,
 234         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 235 };
 236
 237 static const struct vop_ctrl rk3399_ctrl_data = {
 238         .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
 239         .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
 240         .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
 241         .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
 242         .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
 243         .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
 244         .dsp_layer_sel = VOP_REG(RK3399_DSP_CTRL1, 0xff, 8),
 245         .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
 246         .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
 247         .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
 248         .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
 249         .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
 250         .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
 251         .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
 252         .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
 253         .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 254         .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
 255         .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 256         .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
 257         .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 258         .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 259         .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
 260 };
 261
 262 static const int rk3399_vop_intrs[] = {
 263         FS_INTR,
 264         0, 0,
 265         LINE_FLAG_INTR,
 266         0,
 267         BUS_ERROR_INTR,
 268         0, 0, 0, 0, 0, 0, 0,
 269         DSP_HOLD_VALID_INTR,
 270 };
 271
 272 static const struct vop_intr rk3399_vop_intr = {
 273         .intrs = rk3399_vop_intrs,
 274         .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
 275         .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
 276         .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
 277         .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
 278 };
 279
 280 static const struct vop_reg_data rk3399_init_reg_table[] = {
 281         {RK3399_SYS_CTRL, 0x2000f800},
 282         {RK3399_DSP_CTRL0, 0x00000000},
 283         {RK3399_WIN0_CTRL0, 0x00000080},
 284         {RK3399_WIN1_CTRL0, 0x00000080},
 285         /*
 286          * Bit[0] is win2/3 gate en bit, there is no power consume with this
 287          * bit enable. the bit's function similar with area plane enable bit,
 288          * So default enable this bit, then We can control win2/3 area plane
 289          * with its enable bit.
 290          */
 291         {RK3399_WIN2_CTRL0, 0x00000001},
 292         {RK3399_WIN3_CTRL0, 0x00000001},
 293 };
 294
 295 static const struct vop_win_phy rk3399_win23_data = {
 296         .data_formats = formats_win_lite,
 297         .nformats = ARRAY_SIZE(formats_win_lite),
 298         .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 4),
 299         .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 5),
 300         .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 20),
 301         .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 302         .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST0, 0x1fff1fff, 0),
 303         .yrgb_mst = VOP_REG(RK3399_WIN2_MST0, 0xffffffff, 0),
 304         .yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 0),
 305         .src_alpha_ctl = VOP_REG(RK3399_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 306         .dst_alpha_ctl = VOP_REG(RK3399_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 307 };
 308
 309 static const struct vop_win_phy rk3399_area1_data = {
 310         .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 8),
 311         .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 9),
 312         .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 23),
 313         .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 314         .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST1, 0x1fff1fff, 0),
 315         .yrgb_mst = VOP_REG(RK3399_WIN2_MST1, 0xffffffff, 0),
 316         .yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 16),
 317 };
 318
 319 static const struct vop_win_phy rk3399_area2_data = {
 320         .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 12),
 321         .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 13),
 322         .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 26),
 323         .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 324         .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST2, 0x1fff1fff, 0),
 325         .yrgb_mst = VOP_REG(RK3399_WIN2_MST2, 0xffffffff, 0),
 326         .yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 0),
 327 };
 328
 329 static const struct vop_win_phy rk3399_area3_data = {
 330         .enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 16),
 331         .format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 17),
 332         .rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 29),
 333         .dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 334         .dsp_st = VOP_REG(RK3399_WIN2_DSP_ST3, 0x1fff1fff, 0),
 335         .yrgb_mst = VOP_REG(RK3399_WIN2_MST3, 0xffffffff, 0),
 336         .yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 16),
 337 };
 338
 339 static const struct vop_win_phy *rk3399_area_data[] = {
 340         &rk3399_area1_data,
 341         &rk3399_area2_data,
 342         &rk3399_area3_data
 343 };
 344
 345 static const struct vop_win_data rk3399_vop_win_data[] = {
 346         { .base = 0x00, .phy = &rk3288_win01_data,
 347           .type = DRM_PLANE_TYPE_PRIMARY },
 348         { .base = 0x40, .phy = &rk3288_win01_data,
 349           .type = DRM_PLANE_TYPE_OVERLAY },
 350         { .base = 0x00, .phy = &rk3399_win23_data,
 351           .type = DRM_PLANE_TYPE_OVERLAY,
 352           .area = rk3399_area_data,
 353           .area_size = ARRAY_SIZE(rk3399_area_data), },
 354         { .base = 0x50, .phy = &rk3399_win23_data,
 355           .type = DRM_PLANE_TYPE_CURSOR,
 356           .area = rk3399_area_data,
 357           .area_size = ARRAY_SIZE(rk3399_area_data), },
 358 };
 359
 360 static const struct vop_data rk3399_vop_big = {
 361         .init_table = rk3399_init_reg_table,
 362         .table_size = ARRAY_SIZE(rk3399_init_reg_table),
 363         .intr = &rk3399_vop_intr,
 364         .ctrl = &rk3399_ctrl_data,
 365         /*
 366          * rk3399 vop big windows register layout is same as rk3288.
 367          */
 368         .win = rk3399_vop_win_data,
 369         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 370 };
 371
 372 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 373         { .base = 0x00, .phy = &rk3288_win01_data,
 374           .type = DRM_PLANE_TYPE_PRIMARY },
 375         { .base = 0x00, .phy = &rk3288_win23_data,
 376           .type = DRM_PLANE_TYPE_CURSOR},
 377 };
 378
 379
 380 static const struct vop_data rk3399_vop_lit = {
 381         .init_table = rk3399_init_reg_table,
 382         .table_size = ARRAY_SIZE(rk3399_init_reg_table),
 383         .intr = &rk3399_vop_intr,
 384         .ctrl = &rk3399_ctrl_data,
 385         /*
 386          * rk3399 vop lit windows register layout is same as rk3288,
 387          * but cut off the win1 and win3 windows.
 388          */
 389         .win = rk3399_vop_lit_win_data,
 390         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 391 };
 392
 393 static const struct vop_scl_regs rk3066_win_scl = {
 394         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 395         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 396         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 397         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 398 };
 399
 400 static const struct vop_win_phy rk3036_win0_data = {
 401         .scl = &rk3066_win_scl,
 402         .data_formats = formats_win_full,
 403         .nformats = ARRAY_SIZE(formats_win_full),
 404         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 405         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 406         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 407         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 408         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 409         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 410         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 411         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 412         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 413 };
 414
 415 static const struct vop_win_phy rk3036_win1_data = {
 416         .data_formats = formats_win_lite,
 417         .nformats = ARRAY_SIZE(formats_win_lite),
 418         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 419         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 420         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 421         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 422         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 423         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 424         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 425         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 426 };
 427
 428 static const struct vop_win_data rk3036_vop_win_data[] = {
 429         { .base = 0x00, .phy = &rk3036_win0_data,
 430           .type = DRM_PLANE_TYPE_PRIMARY },
 431         { .base = 0x00, .phy = &rk3036_win1_data,
 432           .type = DRM_PLANE_TYPE_CURSOR },
 433 };
 434
 435 static const int rk3036_vop_intrs[] = {
 436         DSP_HOLD_VALID_INTR,
 437         FS_INTR,
 438         LINE_FLAG_INTR,
 439         BUS_ERROR_INTR,
 440 };
 441
 442 static const struct vop_intr rk3036_intr = {
 443         .intrs = rk3036_vop_intrs,
 444         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 445         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 446         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 447         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 448 };
 449
 450 static const struct vop_ctrl rk3036_ctrl_data = {
 451         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 452         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 453         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 454         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 455         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 456         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 457         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 458         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 459         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 460 };
 461
 462 static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
 463         {RK3036_DSP_CTRL1, 0x00000000},
 464 };
 465
 466 static const struct vop_data rk3036_vop = {
 467         .init_table = rk3036_vop_init_reg_table,
 468         .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
 469         .ctrl = &rk3036_ctrl_data,
 470         .intr = &rk3036_intr,
 471         .win = rk3036_vop_win_data,
 472         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 473 };
 474
 475 static const struct of_device_id vop_driver_dt_match[] = {
 476         { .compatible = "rockchip,rk3288-vop",
 477           .data = &rk3288_vop },
 478         { .compatible = "rockchip,rk3036-vop",
 479           .data = &rk3036_vop },
 480         { .compatible = "rockchip,rk3399-vop-big",
 481           .data = &rk3399_vop_big },
 482         { .compatible = "rockchip,rk3399-vop-lit",
 483           .data = &rk3399_vop_lit },
 484         {},
 485 };
 486 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 487
 488 static int vop_probe(struct platform_device *pdev)
 489 {
 490         struct device *dev = &pdev->dev;
 491
 492         if (!dev->of_node) {
 493                 dev_err(dev, "can't find vop devices\n");
 494                 return -ENODEV;
 495         }
 496
 497         return component_add(dev, &vop_component_ops);
 498 }
 499
 500 static int vop_remove(struct platform_device *pdev)
 501 {
 502         component_del(&pdev->dev, &vop_component_ops);
 503
 504         return 0;
 505 }
 506
 507 struct platform_driver vop_platform_driver = {
 508         .probe = vop_probe,
 509         .remove = vop_remove,
 510         .driver = {
 511                 .name = "rockchip-vop",
 512                 .owner = THIS_MODULE,
 513                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 514         },
 515 };
 516
 517 module_platform_driver(vop_platform_driver);
 518
 519 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 520 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 521 MODULE_LICENSE("GPL v2");