drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
  24                          _begin_minor, _end_minor) \
  25                 {.offset = off, \
  26                  .mask = _mask, \
  27                  .shift = s, \
  28                  .write_mask = _write_mask, \
  29                  .major = _major, \
  30                  .begin_minor = _begin_minor, \
  31                  .end_minor = _end_minor,}
  32
  33 #define VOP_REG(off, _mask, s) \
  34                 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
  35
  36 #define VOP_REG_MASK(off, _mask, s) \
  37                 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
  38
  39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
  40                 VOP_REG_VER_MASK(off, _mask, s, false, \
  41                                  _major, _begin_minor, _end_minor)
  42
  43
  44 static const uint32_t formats_win_full[] = {
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_XBGR8888,
  48         DRM_FORMAT_ABGR8888,
  49         DRM_FORMAT_RGB888,
  50         DRM_FORMAT_BGR888,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53         DRM_FORMAT_NV12,
  54         DRM_FORMAT_NV16,
  55         DRM_FORMAT_NV24,
  56 };
  57
  58 static const uint32_t formats_win_lite[] = {
  59         DRM_FORMAT_XRGB8888,
  60         DRM_FORMAT_ARGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_ABGR8888,
  63         DRM_FORMAT_RGB888,
  64         DRM_FORMAT_BGR888,
  65         DRM_FORMAT_RGB565,
  66         DRM_FORMAT_BGR565,
  67 };
  68
  69 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  70         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  71         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  72         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  73         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  74         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  75         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  76         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  77         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  78         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  79         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  80         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  81         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  82         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  83         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  84         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  85         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  86         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  87         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  88         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  89         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  90         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  91 };
  92
  93 static const struct vop_scl_regs rk3288_win_full_scl = {
  94         .ext = &rk3288_win_full_scl_ext,
  95         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  96         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
  97         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
  98         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
  99 };
 100
 101 static const struct vop_win_phy rk3288_win01_data = {
 102         .scl = &rk3288_win_full_scl,
 103         .data_formats = formats_win_full,
 104         .nformats = ARRAY_SIZE(formats_win_full),
 105         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 106         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 107         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 108         .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
 109         .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
 110         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 111         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 112         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 113         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 114         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 115         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 116         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 117         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
 118         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
 119 };
 120
 121 static const struct vop_win_phy rk3288_win23_data = {
 122         .data_formats = formats_win_lite,
 123         .nformats = ARRAY_SIZE(formats_win_lite),
 124         .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 125         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 126         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 127         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 128         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 129         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 130         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 131         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 132         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 133         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 134 };
 135
 136 static const struct vop_win_phy rk3288_area1_data = {
 137         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 138         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 139         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 140         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 141         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 142 };
 143
 144 static const struct vop_win_phy rk3288_area2_data = {
 145         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 146         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 147         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 148         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 149         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 150 };
 151
 152 static const struct vop_win_phy rk3288_area3_data = {
 153         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 154         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 155         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 156         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 157         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 158 };
 159
 160 static const struct vop_win_phy *rk3288_area_data[] = {
 161         &rk3288_area1_data,
 162         &rk3288_area2_data,
 163         &rk3288_area3_data
 164 };
 165
 166 static const struct vop_ctrl rk3288_ctrl_data = {
 167         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 168         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 169         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 170         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 171         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 172         .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 173         .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 174         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 175         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 176         .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 177         .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
 178         .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 179         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 180         .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
 181         .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 182         .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
 183         .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
 184         .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
 185         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 186         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 187         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 188         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 189         .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
 190         .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 191         .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
 192         .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
 193         .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
 194
 195         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 196         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 197
 198         .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
 199         .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
 200         .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 201         .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
 202         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 203
 204         .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
 205         .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
 206         .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
 207         .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
 208         .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
 209         .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
 210         .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
 211
 212         .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
 213         .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 214
 215         .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
 216
 217         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 218 };
 219
 220 /*
 221  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 222  * special support to get alpha blending working.  For now, just use overlay
 223  * window 3 for the drm cursor.
 224  *
 225  */
 226 static const struct vop_win_data rk3288_vop_win_data[] = {
 227         { .base = 0x00, .phy = &rk3288_win01_data,
 228           .type = DRM_PLANE_TYPE_PRIMARY },
 229         { .base = 0x40, .phy = &rk3288_win01_data,
 230           .type = DRM_PLANE_TYPE_OVERLAY },
 231         { .base = 0x00, .phy = &rk3288_win23_data,
 232           .type = DRM_PLANE_TYPE_OVERLAY,
 233           .area = rk3288_area_data,
 234           .area_size = ARRAY_SIZE(rk3288_area_data), },
 235         { .base = 0x50, .phy = &rk3288_win23_data,
 236           .type = DRM_PLANE_TYPE_CURSOR,
 237           .area = rk3288_area_data,
 238           .area_size = ARRAY_SIZE(rk3288_area_data), },
 239 };
 240
 241 static const int rk3288_vop_intrs[] = {
 242         DSP_HOLD_VALID_INTR,
 243         FS_INTR,
 244         LINE_FLAG_INTR,
 245         BUS_ERROR_INTR,
 246 };
 247
 248 static const struct vop_intr rk3288_vop_intr = {
 249         .intrs = rk3288_vop_intrs,
 250         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 251         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 252         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 253         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 254 };
 255
 256 static const struct vop_data rk3288_vop = {
 257         .version = VOP_VERSION(3, 1),
 258         .feature = VOP_FEATURE_OUTPUT_10BIT,
 259         .intr = &rk3288_vop_intr,
 260         .ctrl = &rk3288_ctrl_data,
 261         .win = rk3288_vop_win_data,
 262         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 263 };
 264
 265 static const int rk3368_vop_intrs[] = {
 266         FS_INTR,
 267         FS_NEW_INTR,
 268         ADDR_SAME_INTR,
 269         LINE_FLAG_INTR,
 270         LINE_FLAG1_INTR,
 271         BUS_ERROR_INTR,
 272         WIN0_EMPTY_INTR,
 273         WIN1_EMPTY_INTR,
 274         WIN2_EMPTY_INTR,
 275         WIN3_EMPTY_INTR,
 276         HWC_EMPTY_INTR,
 277         POST_BUF_EMPTY_INTR,
 278         PWM_GEN_INTR,
 279         DSP_HOLD_VALID_INTR,
 280 };
 281
 282 static const struct vop_intr rk3368_vop_intr = {
 283         .intrs = rk3368_vop_intrs,
 284         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 285         .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
 286         .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
 287         .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
 288 };
 289
 290 static const struct vop_win_phy rk3368_win23_data = {
 291         .data_formats = formats_win_lite,
 292         .nformats = ARRAY_SIZE(formats_win_lite),
 293         .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
 294         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
 295         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
 296         .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
 297         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
 298         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 299         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
 300         .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
 301         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
 302         .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 303         .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 304 };
 305
 306 static const struct vop_win_phy rk3368_area1_data = {
 307         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
 308         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
 309         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
 310         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 311         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
 312         .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
 313         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
 314 };
 315
 316 static const struct vop_win_phy rk3368_area2_data = {
 317         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
 318         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
 319         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
 320         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 321         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
 322         .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
 323         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
 324 };
 325
 326 static const struct vop_win_phy rk3368_area3_data = {
 327         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
 328         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
 329         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
 330         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 331         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
 332         .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
 333         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
 334 };
 335
 336 static const struct vop_win_phy *rk3368_area_data[] = {
 337         &rk3368_area1_data,
 338         &rk3368_area2_data,
 339         &rk3368_area3_data
 340 };
 341
 342 static const struct vop_win_data rk3368_vop_win_data[] = {
 343         { .base = 0x00, .phy = &rk3288_win01_data,
 344           .type = DRM_PLANE_TYPE_PRIMARY },
 345         { .base = 0x40, .phy = &rk3288_win01_data,
 346           .type = DRM_PLANE_TYPE_OVERLAY },
 347         { .base = 0x00, .phy = &rk3368_win23_data,
 348           .type = DRM_PLANE_TYPE_OVERLAY,
 349           .area = rk3368_area_data,
 350           .area_size = ARRAY_SIZE(rk3368_area_data), },
 351         { .base = 0x50, .phy = &rk3368_win23_data,
 352           .type = DRM_PLANE_TYPE_CURSOR,
 353           .area = rk3368_area_data,
 354           .area_size = ARRAY_SIZE(rk3368_area_data), },
 355 };
 356
 357 static const struct vop_data rk3368_vop = {
 358         .version = VOP_VERSION(3, 2),
 359         .feature = VOP_FEATURE_OUTPUT_10BIT,
 360         .intr = &rk3368_vop_intr,
 361         .ctrl = &rk3288_ctrl_data,
 362         .win = rk3368_vop_win_data,
 363         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 364 };
 365
 366 static const struct vop_intr rk3366_vop_intr = {
 367         .intrs = rk3368_vop_intrs,
 368         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 369         .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
 370         .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
 371         .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
 372 };
 373
 374 static const struct vop_data rk3366_vop = {
 375         .version = VOP_VERSION(3, 4),
 376         .feature = VOP_FEATURE_OUTPUT_10BIT,
 377         .intr = &rk3366_vop_intr,
 378         .ctrl = &rk3288_ctrl_data,
 379         .win = rk3368_vop_win_data,
 380         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 381 };
 382
 383 static const uint32_t vop_csc_y2r_bt601[] = {
 384         0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
 385         0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
 386 };
 387
 388 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
 389         0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
 390         0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
 391 };
 392
 393 static const uint32_t vop_csc_r2y_bt601[] = {
 394         0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
 395         0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
 396 };
 397
 398 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
 399         0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
 400         0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
 401 };
 402
 403 static const uint32_t vop_csc_y2r_bt709[] = {
 404         0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
 405         0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
 406 };
 407
 408 static const uint32_t vop_csc_r2y_bt709[] = {
 409         0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
 410         0xffd7fe68, 0x00010200, 0x00080200, 0x00080200,
 411 };
 412
 413 static const uint32_t vop_csc_y2r_bt2020[] = {
 414         0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
 415         0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
 416 };
 417
 418 static const uint32_t vop_csc_r2y_bt2020[] = {
 419         0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
 420         0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
 421 };
 422
 423 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
 424         0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
 425         0x0000047a, 0x00000200, 0x00000200, 0x00000200,
 426 };
 427
 428 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
 429         0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
 430         0x00000394, 0x00000200, 0x00000200, 0x00000200,
 431 };
 432
 433 static const struct vop_csc_table rk3399_csc_table = {
 434         .y2r_bt601              = vop_csc_y2r_bt601,
 435         .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
 436         .r2y_bt601              = vop_csc_r2y_bt601,
 437         .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
 438
 439         .y2r_bt709              = vop_csc_y2r_bt709,
 440         .r2y_bt709              = vop_csc_r2y_bt709,
 441
 442         .y2r_bt2020             = vop_csc_y2r_bt2020,
 443         .r2y_bt2020             = vop_csc_r2y_bt2020,
 444
 445         .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
 446         .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
 447 };
 448
 449 static const struct vop_csc rk3399_win0_csc = {
 450         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
 451         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
 452         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
 453         .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
 454         .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
 455         .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
 456 };
 457
 458 static const struct vop_csc rk3399_win1_csc = {
 459         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
 460         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
 461         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
 462         .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
 463         .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
 464         .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
 465 };
 466
 467 static const struct vop_win_data rk3399_vop_win_data[] = {
 468         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 469           .type = DRM_PLANE_TYPE_PRIMARY },
 470         { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
 471           .type = DRM_PLANE_TYPE_OVERLAY },
 472         { .base = 0x00, .phy = &rk3368_win23_data,
 473           .type = DRM_PLANE_TYPE_OVERLAY,
 474           .area = rk3368_area_data,
 475           .area_size = ARRAY_SIZE(rk3368_area_data), },
 476         { .base = 0x50, .phy = &rk3368_win23_data,
 477           .type = DRM_PLANE_TYPE_CURSOR,
 478           .area = rk3368_area_data,
 479           .area_size = ARRAY_SIZE(rk3368_area_data), },
 480 };
 481
 482 static const struct vop_data rk3399_vop_big = {
 483         .version = VOP_VERSION(3, 5),
 484         .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
 485         .intr = &rk3366_vop_intr,
 486         .ctrl = &rk3288_ctrl_data,
 487         .win = rk3399_vop_win_data,
 488         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 489 };
 490
 491 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 492         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 493           .type = DRM_PLANE_TYPE_PRIMARY },
 494         { .phy = NULL },
 495         { .base = 0x00, .phy = &rk3368_win23_data,
 496           .type = DRM_PLANE_TYPE_CURSOR,
 497           .area = rk3368_area_data,
 498           .area_size = ARRAY_SIZE(rk3368_area_data), },
 499         { .phy = NULL },
 500 };
 501
 502
 503 static const struct vop_data rk3399_vop_lit = {
 504         .version = VOP_VERSION(3, 6),
 505         .csc_table = &rk3399_csc_table,
 506         .intr = &rk3366_vop_intr,
 507         .ctrl = &rk3288_ctrl_data,
 508         .win = rk3399_vop_lit_win_data,
 509         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 510 };
 511
 512 static const struct vop_data rk322x_vop = {
 513         .version = VOP_VERSION(3, 7),
 514         .feature = VOP_FEATURE_OUTPUT_10BIT,
 515         .intr = &rk3366_vop_intr,
 516         .ctrl = &rk3288_ctrl_data,
 517         .win = rk3368_vop_win_data,
 518         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 519 };
 520
 521 static const struct vop_scl_regs rk3066_win_scl = {
 522         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 523         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 524         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 525         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 526 };
 527
 528 static const struct vop_win_phy rk3036_win0_data = {
 529         .scl = &rk3066_win_scl,
 530         .data_formats = formats_win_full,
 531         .nformats = ARRAY_SIZE(formats_win_full),
 532         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 533         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 534         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 535         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 536         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 537         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 538         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 539         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 540         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 541         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
 542         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
 543         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
 544 };
 545
 546 static const struct vop_win_phy rk3036_win1_data = {
 547         .data_formats = formats_win_lite,
 548         .nformats = ARRAY_SIZE(formats_win_lite),
 549         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 550         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 551         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 552         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 553         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 554         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 555         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 556         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 557         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
 558         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
 559 };
 560
 561 static const struct vop_win_data rk3036_vop_win_data[] = {
 562         { .base = 0x00, .phy = &rk3036_win0_data,
 563           .type = DRM_PLANE_TYPE_PRIMARY },
 564         { .base = 0x00, .phy = &rk3036_win1_data,
 565           .type = DRM_PLANE_TYPE_CURSOR },
 566 };
 567
 568 static const int rk3036_vop_intrs[] = {
 569         DSP_HOLD_VALID_INTR,
 570         FS_INTR,
 571         LINE_FLAG_INTR,
 572         BUS_ERROR_INTR,
 573 };
 574
 575 static const struct vop_intr rk3036_intr = {
 576         .intrs = rk3036_vop_intrs,
 577         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 578         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 579         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 580         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 581 };
 582
 583 static const struct vop_ctrl rk3036_ctrl_data = {
 584         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 585         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 586         .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
 587         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 588         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 589         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 590         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 591         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 592         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 593         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 594 };
 595
 596 static const struct vop_data rk3036_vop = {
 597         .version = VOP_VERSION(2, 2),
 598         .ctrl = &rk3036_ctrl_data,
 599         .intr = &rk3036_intr,
 600         .win = rk3036_vop_win_data,
 601         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 602 };
 603
 604 static const struct of_device_id vop_driver_dt_match[] = {
 605         { .compatible = "rockchip,rk3036-vop",
 606           .data = &rk3036_vop },
 607         { .compatible = "rockchip,rk3288-vop",
 608           .data = &rk3288_vop },
 609         { .compatible = "rockchip,rk3368-vop",
 610           .data = &rk3368_vop },
 611         { .compatible = "rockchip,rk3366-vop",
 612           .data = &rk3366_vop },
 613         { .compatible = "rockchip,rk3399-vop-big",
 614           .data = &rk3399_vop_big },
 615         { .compatible = "rockchip,rk3399-vop-lit",
 616           .data = &rk3399_vop_lit },
 617         { .compatible = "rockchip,rk322x-vop",
 618           .data = &rk322x_vop },
 619         {},
 620 };
 621 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 622
 623 static int vop_probe(struct platform_device *pdev)
 624 {
 625         struct device *dev = &pdev->dev;
 626
 627         if (!dev->of_node) {
 628                 dev_err(dev, "can't find vop devices\n");
 629                 return -ENODEV;
 630         }
 631
 632         return component_add(dev, &vop_component_ops);
 633 }
 634
 635 static int vop_remove(struct platform_device *pdev)
 636 {
 637         component_del(&pdev->dev, &vop_component_ops);
 638
 639         return 0;
 640 }
 641
 642 struct platform_driver vop_platform_driver = {
 643         .probe = vop_probe,
 644         .remove = vop_remove,
 645         .driver = {
 646                 .name = "rockchip-vop",
 647                 .owner = THIS_MODULE,
 648                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 649         },
 650 };
 651
 652 module_platform_driver(vop_platform_driver);
 653
 654 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 655 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 656 MODULE_LICENSE("GPL v2");