drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, win, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, win, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  76                 REG_SET(x, name, win->offset, win->ext->name, v, true)
  77 #define VOP_SCL_SET(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  79 #define VOP_SCL_SET_EXT(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  81
  82 #define VOP_CTRL_SET(x, name, v) \
  83                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  84
  85 #define VOP_INTR_GET(vop, name) \
  86                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  87
  88 #define VOP_INTR_SET(vop, name, mask, v) \
  89                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  90                              mask, v, false)
  91
  92 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  93         do { \
  94                 int i, reg = 0, mask = 0; \
  95                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  96                         if (vop->data->intr->intrs[i] & type) { \
  97                                 reg |= (v) << i; \
  98                                 mask |= 1 << i; \
  99                         } \
 100                 } \
 101                 VOP_INTR_SET(vop, name, mask, reg); \
 102         } while (0)
 103 #define VOP_INTR_GET_TYPE(vop, name, type) \
 104                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 105
 106 #define VOP_CTRL_GET(x, name) \
 107                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 108
 109 #define VOP_WIN_GET(x, win, name) \
 110                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 111
 112 #define VOP_WIN_NAME(win, name) \
 113                 (vop_get_win_phy(win, &win->phy->name)->name)
 114
 115 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 116                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 117
 118 #define to_vop(x) container_of(x, struct vop, crtc)
 119 #define to_vop_win(x) container_of(x, struct vop_win, base)
 120 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 121
 122 struct vop_zpos {
 123         int win_id;
 124         int zpos;
 125 };
 126
 127 struct vop_plane_state {
 128         struct drm_plane_state base;
 129         int format;
 130         int zpos;
 131         struct drm_rect src;
 132         struct drm_rect dest;
 133         dma_addr_t yrgb_mst;
 134         dma_addr_t uv_mst;
 135         const uint32_t *y2r_table;
 136         const uint32_t *r2r_table;
 137         const uint32_t *r2y_table;
 138         bool enable;
 139 };
 140
 141 struct vop_win {
 142         struct vop_win *parent;
 143         struct drm_plane base;
 144
 145         int win_id;
 146         int area_id;
 147         uint32_t offset;
 148         enum drm_plane_type type;
 149         const struct vop_win_phy *phy;
 150         const struct vop_csc *csc;
 151         const uint32_t *data_formats;
 152         uint32_t nformats;
 153         struct vop *vop;
 154
 155         struct drm_property *rotation_prop;
 156         struct vop_plane_state state;
 157 };
 158
 159 struct vop {
 160         struct drm_crtc crtc;
 161         struct device *dev;
 162         struct drm_device *drm_dev;
 163         struct drm_property *plane_zpos_prop;
 164         struct drm_property *plane_feature_prop;
 165         bool is_iommu_enabled;
 166         bool is_iommu_needed;
 167         bool is_enabled;
 168
 169         /* mutex vsync_ work */
 170         struct mutex vsync_mutex;
 171         bool vsync_work_pending;
 172         struct completion dsp_hold_completion;
 173         struct completion wait_update_complete;
 174         struct drm_pending_vblank_event *event;
 175
 176         const struct vop_data *data;
 177         int num_wins;
 178
 179         uint32_t *regsbak;
 180         void __iomem *regs;
 181
 182         /* physical map length of vop register */
 183         uint32_t len;
 184
 185         /* one time only one process allowed to config the register */
 186         spinlock_t reg_lock;
 187         /* lock vop irq reg */
 188         spinlock_t irq_lock;
 189
 190         unsigned int irq;
 191
 192         /* vop AHP clk */
 193         struct clk *hclk;
 194         /* vop dclk */
 195         struct clk *dclk;
 196         /* vop share memory frequency */
 197         struct clk *aclk;
 198
 199         /* vop dclk reset */
 200         struct reset_control *dclk_rst;
 201
 202         struct vop_win win[];
 203 };
 204
 205 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 206 {
 207         writel(v, vop->regs + offset);
 208         vop->regsbak[offset >> 2] = v;
 209 }
 210
 211 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 212 {
 213         return readl(vop->regs + offset);
 214 }
 215
 216 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 217                                     const struct vop_reg *reg)
 218 {
 219         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 220 }
 221
 222 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 223                                   uint32_t mask, uint32_t shift, uint32_t v,
 224                                   bool write_mask, bool relaxed)
 225 {
 226         if (!mask)
 227                 return;
 228
 229         if (write_mask) {
 230                 v = ((v & mask) << shift) | (mask << (shift + 16));
 231         } else {
 232                 uint32_t cached_val = vop->regsbak[offset >> 2];
 233
 234                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 235                 vop->regsbak[offset >> 2] = v;
 236         }
 237
 238         if (relaxed)
 239                 writel_relaxed(v, vop->regs + offset);
 240         else
 241                 writel(v, vop->regs + offset);
 242 }
 243
 244 static inline const struct vop_win_phy *
 245 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 246 {
 247         if (!reg->mask && win->parent)
 248                 return win->parent->phy;
 249
 250         return win->phy;
 251 }
 252
 253 static inline uint32_t vop_get_intr_type(struct vop *vop,
 254                                          const struct vop_reg *reg, int type)
 255 {
 256         uint32_t i, ret = 0;
 257         uint32_t regs = vop_read_reg(vop, 0, reg);
 258
 259         for (i = 0; i < vop->data->intr->nintrs; i++) {
 260                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 261                         ret |= vop->data->intr->intrs[i];
 262         }
 263
 264         return ret;
 265 }
 266
 267 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 268 {
 269         int i;
 270
 271         if (!table)
 272                 return;
 273
 274         for (i = 0; i < 8; i++)
 275                 vop_writel(vop, offset + i * 4, table[i]);
 276 }
 277
 278 static inline void vop_cfg_done(struct vop *vop)
 279 {
 280         VOP_CTRL_SET(vop, cfg_done, 1);
 281 }
 282
 283 static bool vop_is_allwin_disabled(struct vop *vop)
 284 {
 285         int i;
 286
 287         for (i = 0; i < vop->num_wins; i++) {
 288                 struct vop_win *win = &vop->win[i];
 289
 290                 if (VOP_WIN_GET(vop, win, enable) != 0)
 291                         return false;
 292         }
 293
 294         return true;
 295 }
 296
 297 static bool vop_is_cfg_done_complete(struct vop *vop)
 298 {
 299         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 300 }
 301
 302 static bool has_rb_swapped(uint32_t format)
 303 {
 304         switch (format) {
 305         case DRM_FORMAT_XBGR8888:
 306         case DRM_FORMAT_ABGR8888:
 307         case DRM_FORMAT_BGR888:
 308         case DRM_FORMAT_BGR565:
 309                 return true;
 310         default:
 311                 return false;
 312         }
 313 }
 314
 315 static enum vop_data_format vop_convert_format(uint32_t format)
 316 {
 317         switch (format) {
 318         case DRM_FORMAT_XRGB8888:
 319         case DRM_FORMAT_ARGB8888:
 320         case DRM_FORMAT_XBGR8888:
 321         case DRM_FORMAT_ABGR8888:
 322                 return VOP_FMT_ARGB8888;
 323         case DRM_FORMAT_RGB888:
 324         case DRM_FORMAT_BGR888:
 325                 return VOP_FMT_RGB888;
 326         case DRM_FORMAT_RGB565:
 327         case DRM_FORMAT_BGR565:
 328                 return VOP_FMT_RGB565;
 329         case DRM_FORMAT_NV12:
 330                 return VOP_FMT_YUV420SP;
 331         case DRM_FORMAT_NV16:
 332                 return VOP_FMT_YUV422SP;
 333         case DRM_FORMAT_NV24:
 334                 return VOP_FMT_YUV444SP;
 335         default:
 336                 DRM_ERROR("unsupport format[%08x]\n", format);
 337                 return -EINVAL;
 338         }
 339 }
 340
 341 static bool is_yuv_support(uint32_t format)
 342 {
 343         switch (format) {
 344         case DRM_FORMAT_NV12:
 345         case DRM_FORMAT_NV16:
 346         case DRM_FORMAT_NV24:
 347                 return true;
 348         default:
 349                 return false;
 350         }
 351 }
 352
 353 static bool is_alpha_support(uint32_t format)
 354 {
 355         switch (format) {
 356         case DRM_FORMAT_ARGB8888:
 357         case DRM_FORMAT_ABGR8888:
 358                 return true;
 359         default:
 360                 return false;
 361         }
 362 }
 363
 364 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 365                                   uint32_t dst, bool is_horizontal,
 366                                   int vsu_mode, int *vskiplines)
 367 {
 368         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 369
 370         if (is_horizontal) {
 371                 if (mode == SCALE_UP)
 372                         val = GET_SCL_FT_BIC(src, dst);
 373                 else if (mode == SCALE_DOWN)
 374                         val = GET_SCL_FT_BILI_DN(src, dst);
 375         } else {
 376                 if (mode == SCALE_UP) {
 377                         if (vsu_mode == SCALE_UP_BIL)
 378                                 val = GET_SCL_FT_BILI_UP(src, dst);
 379                         else
 380                                 val = GET_SCL_FT_BIC(src, dst);
 381                 } else if (mode == SCALE_DOWN) {
 382                         if (vskiplines) {
 383                                 *vskiplines = scl_get_vskiplines(src, dst);
 384                                 val = scl_get_bili_dn_vskip(src, dst,
 385                                                             *vskiplines);
 386                         } else {
 387                                 val = GET_SCL_FT_BILI_DN(src, dst);
 388                         }
 389                 }
 390         }
 391
 392         return val;
 393 }
 394
 395 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 396                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 397                                 uint32_t dst_h, uint32_t pixel_format)
 398 {
 399         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 400         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 401         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 402         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 403         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 404         bool is_yuv = is_yuv_support(pixel_format);
 405         uint16_t cbcr_src_w = src_w / hsub;
 406         uint16_t cbcr_src_h = src_h / vsub;
 407         uint16_t vsu_mode;
 408         uint16_t lb_mode;
 409         uint32_t val;
 410         int vskiplines = 0;
 411
 412         if (!win->phy->scl)
 413                 return;
 414
 415         if (dst_w > 3840) {
 416                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 417                 return;
 418         }
 419
 420         if (!win->phy->scl->ext) {
 421                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 422                             scl_cal_scale2(src_w, dst_w));
 423                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 424                             scl_cal_scale2(src_h, dst_h));
 425                 if (is_yuv) {
 426                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 427                                     scl_cal_scale2(cbcr_src_w, dst_w));
 428                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 429                                     scl_cal_scale2(cbcr_src_h, dst_h));
 430                 }
 431                 return;
 432         }
 433
 434         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 435         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 436
 437         if (is_yuv) {
 438                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 439                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 440                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 441                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 442                 else
 443                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 444         } else {
 445                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 446                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 447                 else
 448                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 449         }
 450
 451         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 452         if (lb_mode == LB_RGB_3840X2) {
 453                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 454                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 455                         return;
 456                 }
 457                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 458                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 459                         return;
 460                 }
 461                 vsu_mode = SCALE_UP_BIL;
 462         } else if (lb_mode == LB_RGB_2560X4) {
 463                 vsu_mode = SCALE_UP_BIL;
 464         } else {
 465                 vsu_mode = SCALE_UP_BIC;
 466         }
 467
 468         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 469                                 true, 0, NULL);
 470         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 471         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 472                                 false, vsu_mode, &vskiplines);
 473         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 474
 475         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 476         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 477
 478         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 479         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 480         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 481         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 482         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 483         if (is_yuv) {
 484                 vskiplines = 0;
 485
 486                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 487                                         dst_w, true, 0, NULL);
 488                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 489                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 490                                         dst_h, false, vsu_mode, &vskiplines);
 491                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 492
 493                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 494                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 495                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 496                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 497                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 498                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 499                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 500         }
 501 }
 502
 503 /*
 504  * rk3399 colorspace path:
 505  *      Input        Win csc                     Output
 506  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 507  *    RGB        --> R2Y                  __/
 508  *
 509  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 510  *    RGB        --> 709To2020->R2Y       __/
 511  *
 512  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 513  *    RGB        --> R2Y                  __/
 514  *
 515  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 516  *    RGB        --> 709To2020->R2Y       __/
 517  *
 518  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 519  *    RGB        --> R2Y                  __/
 520  *
 521  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 522  *    RGB        --> R2Y(601)             __/
 523  *
 524  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 525  *    RGB        --> bypass               __/
 526  *
 527  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 528  *
 529  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 530  *
 531  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 532  *
 533  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 534  */
 535 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 536                          bool is_input_yuv, bool is_output_yuv,
 537                          int input_csc, int output_csc,
 538                          const uint32_t **y2r_table,
 539                          const uint32_t **r2r_table,
 540                          const uint32_t **r2y_table)
 541 {
 542         *y2r_table = NULL;
 543         *r2r_table = NULL;
 544         *r2y_table = NULL;
 545
 546         if (is_output_yuv) {
 547                 if (output_csc == CSC_BT2020) {
 548                         if (is_input_yuv) {
 549                                 if (input_csc == CSC_BT2020)
 550                                         return 0;
 551                                 *y2r_table = csc_table->y2r_bt709;
 552                         }
 553                         if (input_csc != CSC_BT2020)
 554                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 555                         *r2y_table = csc_table->r2y_bt2020;
 556                 } else {
 557                         if (is_input_yuv && input_csc == CSC_BT2020)
 558                                 *y2r_table = csc_table->y2r_bt2020;
 559                         if (input_csc == CSC_BT2020)
 560                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 561                         if (!is_input_yuv || y2r_table) {
 562                                 if (output_csc == CSC_BT709)
 563                                         *r2y_table = csc_table->r2y_bt709;
 564                                 else
 565                                         *r2y_table = csc_table->r2y_bt601;
 566                         }
 567                 }
 568
 569         } else {
 570                 if (!is_input_yuv)
 571                         return 0;
 572
 573                 /*
 574                  * is possible use bt2020 on rgb mode?
 575                  */
 576                 if (WARN_ON(output_csc == CSC_BT2020))
 577                         return -EINVAL;
 578
 579                 if (input_csc == CSC_BT2020)
 580                         *y2r_table = csc_table->y2r_bt2020;
 581                 else if (input_csc == CSC_BT709)
 582                         *y2r_table = csc_table->y2r_bt709;
 583                 else
 584                         *y2r_table = csc_table->y2r_bt601;
 585
 586                 if (input_csc == CSC_BT2020)
 587                         /*
 588                          * We don't have bt601 to bt709 table, force use bt709.
 589                          */
 590                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 591         }
 592
 593         return 0;
 594 }
 595
 596 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 597                                 struct drm_crtc_state *crtc_state)
 598 {
 599         struct vop *vop = to_vop(crtc);
 600         struct drm_atomic_state *state = crtc_state->state;
 601         const struct vop_csc_table *csc_table = vop->data->csc_table;
 602         struct drm_plane_state *pstate;
 603         struct drm_plane *plane;
 604         bool is_yuv;
 605         int ret;
 606
 607         if (!csc_table)
 608                 return 0;
 609
 610         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 611                 struct vop_plane_state *vop_plane_state;
 612
 613                 pstate = drm_atomic_get_plane_state(state, plane);
 614                 if (IS_ERR(pstate))
 615                         return PTR_ERR(pstate);
 616                 vop_plane_state = to_vop_plane_state(pstate);
 617
 618                 if (!pstate->fb)
 619                         continue;
 620                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 621
 622                 /*
 623                  * TODO: force set input and output csc mode.
 624                  */
 625                 ret = vop_csc_setup(csc_table, is_yuv, false,
 626                                     CSC_BT709, CSC_BT709,
 627                                     &vop_plane_state->y2r_table,
 628                                     &vop_plane_state->r2r_table,
 629                                     &vop_plane_state->r2y_table);
 630                 if (ret)
 631                         return ret;
 632         }
 633
 634         return 0;
 635 }
 636
 637 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 638 {
 639         unsigned long flags;
 640
 641         spin_lock_irqsave(&vop->irq_lock, flags);
 642
 643         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 644
 645         spin_unlock_irqrestore(&vop->irq_lock, flags);
 646 }
 647
 648 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 649 {
 650         unsigned long flags;
 651
 652         spin_lock_irqsave(&vop->irq_lock, flags);
 653
 654         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 655
 656         spin_unlock_irqrestore(&vop->irq_lock, flags);
 657 }
 658
 659 static void vop_enable(struct drm_crtc *crtc)
 660 {
 661         struct vop *vop = to_vop(crtc);
 662         int ret, i;
 663
 664         ret = clk_prepare_enable(vop->hclk);
 665         if (ret < 0) {
 666                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 667                 return;
 668         }
 669
 670         ret = clk_prepare_enable(vop->dclk);
 671         if (ret < 0) {
 672                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 673                 goto err_disable_hclk;
 674         }
 675
 676         ret = clk_prepare_enable(vop->aclk);
 677         if (ret < 0) {
 678                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 679                 goto err_disable_dclk;
 680         }
 681
 682         ret = pm_runtime_get_sync(vop->dev);
 683         if (ret < 0) {
 684                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 685                 return;
 686         }
 687
 688         memcpy(vop->regsbak, vop->regs, vop->len);
 689
 690         VOP_CTRL_SET(vop, global_regdone_en, 1);
 691         VOP_CTRL_SET(vop, dsp_blank, 0);
 692
 693         for (i = 0; i < vop->num_wins; i++) {
 694                 struct vop_win *win = &vop->win[i];
 695
 696                 VOP_WIN_SET(vop, win, gate, 1);
 697         }
 698         vop->is_enabled = true;
 699
 700         spin_lock(&vop->reg_lock);
 701
 702         VOP_CTRL_SET(vop, standby, 0);
 703
 704         spin_unlock(&vop->reg_lock);
 705
 706         enable_irq(vop->irq);
 707
 708         drm_crtc_vblank_on(crtc);
 709
 710         return;
 711
 712 err_disable_dclk:
 713         clk_disable_unprepare(vop->dclk);
 714 err_disable_hclk:
 715         clk_disable_unprepare(vop->hclk);
 716 }
 717
 718 static void vop_crtc_disable(struct drm_crtc *crtc)
 719 {
 720         struct vop *vop = to_vop(crtc);
 721         int i;
 722
 723         /*
 724          * We need to make sure that all windows are disabled before we
 725          * disable that crtc. Otherwise we might try to scan from a destroyed
 726          * buffer later.
 727          */
 728         for (i = 0; i < vop->num_wins; i++) {
 729                 struct vop_win *win = &vop->win[i];
 730
 731                 spin_lock(&vop->reg_lock);
 732                 VOP_WIN_SET(vop, win, enable, 0);
 733                 spin_unlock(&vop->reg_lock);
 734         }
 735         vop_cfg_done(vop);
 736
 737         drm_crtc_vblank_off(crtc);
 738
 739         /*
 740          * Vop standby will take effect at end of current frame,
 741          * if dsp hold valid irq happen, it means standby complete.
 742          *
 743          * we must wait standby complete when we want to disable aclk,
 744          * if not, memory bus maybe dead.
 745          */
 746         reinit_completion(&vop->dsp_hold_completion);
 747         vop_dsp_hold_valid_irq_enable(vop);
 748
 749         spin_lock(&vop->reg_lock);
 750
 751         VOP_CTRL_SET(vop, standby, 1);
 752
 753         spin_unlock(&vop->reg_lock);
 754
 755         wait_for_completion(&vop->dsp_hold_completion);
 756
 757         vop_dsp_hold_valid_irq_disable(vop);
 758
 759         disable_irq(vop->irq);
 760
 761         vop->is_enabled = false;
 762         if (vop->is_iommu_enabled) {
 763                 /*
 764                  * vop standby complete, so iommu detach is safe.
 765                  */
 766                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 767                 vop->is_iommu_enabled = false;
 768         }
 769
 770         pm_runtime_put(vop->dev);
 771         clk_disable_unprepare(vop->dclk);
 772         clk_disable_unprepare(vop->aclk);
 773         clk_disable_unprepare(vop->hclk);
 774 }
 775
 776 static void vop_plane_destroy(struct drm_plane *plane)
 777 {
 778         drm_plane_cleanup(plane);
 779 }
 780
 781 static int vop_plane_prepare_fb(struct drm_plane *plane,
 782                                 const struct drm_plane_state *new_state)
 783 {
 784         if (plane->state->fb)
 785                 drm_framebuffer_reference(plane->state->fb);
 786
 787         return 0;
 788 }
 789
 790 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 791                                  const struct drm_plane_state *old_state)
 792 {
 793         if (old_state->fb)
 794                 drm_framebuffer_unreference(old_state->fb);
 795 }
 796
 797 static int vop_plane_atomic_check(struct drm_plane *plane,
 798                            struct drm_plane_state *state)
 799 {
 800         struct drm_crtc *crtc = state->crtc;
 801         struct drm_framebuffer *fb = state->fb;
 802         struct vop_win *win = to_vop_win(plane);
 803         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 804         struct drm_crtc_state *crtc_state;
 805         bool visible;
 806         int ret;
 807         struct drm_rect *dest = &vop_plane_state->dest;
 808         struct drm_rect *src = &vop_plane_state->src;
 809         struct drm_rect clip;
 810         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 811                                         DRM_PLANE_HELPER_NO_SCALING;
 812         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 813                                         DRM_PLANE_HELPER_NO_SCALING;
 814         unsigned long offset;
 815         dma_addr_t dma_addr;
 816
 817         crtc = crtc ? crtc : plane->state->crtc;
 818         /*
 819          * Both crtc or plane->state->crtc can be null.
 820          */
 821         if (!crtc || !fb)
 822                 goto out_disable;
 823
 824         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 825         if (IS_ERR(crtc_state))
 826                 return PTR_ERR(crtc_state);
 827
 828         src->x1 = state->src_x;
 829         src->y1 = state->src_y;
 830         src->x2 = state->src_x + state->src_w;
 831         src->y2 = state->src_y + state->src_h;
 832         dest->x1 = state->crtc_x;
 833         dest->y1 = state->crtc_y;
 834         dest->x2 = state->crtc_x + state->crtc_w;
 835         dest->y2 = state->crtc_y + state->crtc_h;
 836
 837         clip.x1 = 0;
 838         clip.y1 = 0;
 839         clip.x2 = crtc_state->mode.hdisplay;
 840         clip.y2 = crtc_state->mode.vdisplay;
 841
 842         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 843                                             src, dest, &clip,
 844                                             min_scale,
 845                                             max_scale,
 846                                             true, true, &visible);
 847         if (ret)
 848                 return ret;
 849
 850         if (!visible)
 851                 goto out_disable;
 852
 853         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 854         if (vop_plane_state->format < 0)
 855                 return vop_plane_state->format;
 856
 857         /*
 858          * Src.x1 can be odd when do clip, but yuv plane start point
 859          * need align with 2 pixel.
 860          */
 861         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 862                 return -EINVAL;
 863
 864         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 865         if (state->rotation & BIT(DRM_REFLECT_Y))
 866                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 867         else
 868                 offset += (src->y1 >> 16) * fb->pitches[0];
 869
 870         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 871         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 872         if (is_yuv_support(fb->pixel_format)) {
 873                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 874                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 875                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 876
 877                 offset = (src->x1 >> 16) * bpp / hsub;
 878                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 879
 880                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 881                 dma_addr += offset + fb->offsets[1];
 882                 vop_plane_state->uv_mst = dma_addr;
 883         }
 884
 885         vop_plane_state->enable = true;
 886
 887         return 0;
 888
 889 out_disable:
 890         vop_plane_state->enable = false;
 891         return 0;
 892 }
 893
 894 static void vop_plane_atomic_disable(struct drm_plane *plane,
 895                                      struct drm_plane_state *old_state)
 896 {
 897         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 898         struct vop_win *win = to_vop_win(plane);
 899         struct vop *vop = to_vop(old_state->crtc);
 900
 901         if (!old_state->crtc)
 902                 return;
 903
 904         spin_lock(&vop->reg_lock);
 905
 906         VOP_WIN_SET(vop, win, enable, 0);
 907
 908         spin_unlock(&vop->reg_lock);
 909
 910         vop_plane_state->enable = false;
 911 }
 912
 913 static void vop_plane_atomic_update(struct drm_plane *plane,
 914                 struct drm_plane_state *old_state)
 915 {
 916         struct drm_plane_state *state = plane->state;
 917         struct drm_crtc *crtc = state->crtc;
 918         struct vop_win *win = to_vop_win(plane);
 919         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 920         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 921         struct vop *vop = to_vop(state->crtc);
 922         struct drm_framebuffer *fb = state->fb;
 923         unsigned int actual_w, actual_h;
 924         unsigned int dsp_stx, dsp_sty;
 925         uint32_t act_info, dsp_info, dsp_st;
 926         struct drm_rect *src = &vop_plane_state->src;
 927         struct drm_rect *dest = &vop_plane_state->dest;
 928         const uint32_t *y2r_table = vop_plane_state->y2r_table;
 929         const uint32_t *r2r_table = vop_plane_state->r2r_table;
 930         const uint32_t *r2y_table = vop_plane_state->r2y_table;
 931         int ymirror, xmirror;
 932         uint32_t val;
 933         bool rb_swap;
 934
 935         /*
 936          * can't update plane when vop is disabled.
 937          */
 938         if (!crtc)
 939                 return;
 940
 941         if (!vop_plane_state->enable) {
 942                 vop_plane_atomic_disable(plane, old_state);
 943                 return;
 944         }
 945
 946         actual_w = drm_rect_width(src) >> 16;
 947         actual_h = drm_rect_height(src) >> 16;
 948         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 949
 950         dsp_info = (drm_rect_height(dest) - 1) << 16;
 951         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 952
 953         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 954         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 955         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 956
 957         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 958         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 959
 960         spin_lock(&vop->reg_lock);
 961
 962         VOP_WIN_SET(vop, win, xmirror, xmirror);
 963         VOP_WIN_SET(vop, win, ymirror, ymirror);
 964         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 965         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 966         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 967         if (is_yuv_support(fb->pixel_format)) {
 968                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 969                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
 970         }
 971
 972         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 973                             drm_rect_width(dest), drm_rect_height(dest),
 974                             fb->pixel_format);
 975
 976         VOP_WIN_SET(vop, win, act_info, act_info);
 977         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 978         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 979
 980         rb_swap = has_rb_swapped(fb->pixel_format);
 981         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 982
 983         if (is_alpha_support(fb->pixel_format) &&
 984             (s->dsp_layer_sel & 0x3) != win->win_id) {
 985                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 986                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 987                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 988                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 989                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 990                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 991                         SRC_FACTOR_M0(ALPHA_ONE);
 992                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 993                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 994                 VOP_WIN_SET(vop, win, alpha_en, 1);
 995         } else {
 996                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 997                 VOP_WIN_SET(vop, win, alpha_en, 0);
 998         }
 999
1000         if (win->csc) {
1001                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1002                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1003                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1004                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1005                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1006                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1007         }
1008         VOP_WIN_SET(vop, win, enable, 1);
1009         spin_unlock(&vop->reg_lock);
1010         vop->is_iommu_needed = true;
1011 }
1012
1013 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1014         .prepare_fb = vop_plane_prepare_fb,
1015         .cleanup_fb = vop_plane_cleanup_fb,
1016         .atomic_check = vop_plane_atomic_check,
1017         .atomic_update = vop_plane_atomic_update,
1018         .atomic_disable = vop_plane_atomic_disable,
1019 };
1020
1021 void vop_atomic_plane_reset(struct drm_plane *plane)
1022 {
1023         struct vop_win *win = to_vop_win(plane);
1024         struct vop_plane_state *vop_plane_state =
1025                                         to_vop_plane_state(plane->state);
1026
1027         if (plane->state && plane->state->fb)
1028                 drm_framebuffer_unreference(plane->state->fb);
1029
1030         kfree(vop_plane_state);
1031         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1032         if (!vop_plane_state)
1033                 return;
1034
1035         vop_plane_state->zpos = win->win_id;
1036         plane->state = &vop_plane_state->base;
1037         plane->state->plane = plane;
1038 }
1039
1040 struct drm_plane_state *
1041 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1042 {
1043         struct vop_plane_state *old_vop_plane_state;
1044         struct vop_plane_state *vop_plane_state;
1045
1046         if (WARN_ON(!plane->state))
1047                 return NULL;
1048
1049         old_vop_plane_state = to_vop_plane_state(plane->state);
1050         vop_plane_state = kmemdup(old_vop_plane_state,
1051                                   sizeof(*vop_plane_state), GFP_KERNEL);
1052         if (!vop_plane_state)
1053                 return NULL;
1054
1055         __drm_atomic_helper_plane_duplicate_state(plane,
1056                                                   &vop_plane_state->base);
1057
1058         return &vop_plane_state->base;
1059 }
1060
1061 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1062                                            struct drm_plane_state *state)
1063 {
1064         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1065
1066         __drm_atomic_helper_plane_destroy_state(plane, state);
1067
1068         kfree(vop_state);
1069 }
1070
1071 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1072                                          struct drm_plane_state *state,
1073                                          struct drm_property *property,
1074                                          uint64_t val)
1075 {
1076         struct vop_win *win = to_vop_win(plane);
1077         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1078
1079         if (property == win->vop->plane_zpos_prop) {
1080                 plane_state->zpos = val;
1081                 return 0;
1082         }
1083
1084         if (property == win->rotation_prop) {
1085                 state->rotation = val;
1086                 return 0;
1087         }
1088
1089         DRM_ERROR("failed to set vop plane property\n");
1090         return -EINVAL;
1091 }
1092
1093 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1094                                          const struct drm_plane_state *state,
1095                                          struct drm_property *property,
1096                                          uint64_t *val)
1097 {
1098         struct vop_win *win = to_vop_win(plane);
1099         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1100
1101         if (property == win->vop->plane_zpos_prop) {
1102                 *val = plane_state->zpos;
1103                 return 0;
1104         }
1105
1106         if (property == win->rotation_prop) {
1107                 *val = state->rotation;
1108                 return 0;
1109         }
1110
1111         DRM_ERROR("failed to get vop plane property\n");
1112         return -EINVAL;
1113 }
1114
1115 static const struct drm_plane_funcs vop_plane_funcs = {
1116         .update_plane   = drm_atomic_helper_update_plane,
1117         .disable_plane  = drm_atomic_helper_disable_plane,
1118         .destroy = vop_plane_destroy,
1119         .reset = vop_atomic_plane_reset,
1120         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1121         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1122         .atomic_set_property = vop_atomic_plane_set_property,
1123         .atomic_get_property = vop_atomic_plane_get_property,
1124 };
1125
1126 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1127 {
1128         struct vop *vop = to_vop(crtc);
1129         unsigned long flags;
1130
1131         if (!vop->is_enabled)
1132                 return -EPERM;
1133
1134         spin_lock_irqsave(&vop->irq_lock, flags);
1135
1136         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1137
1138         spin_unlock_irqrestore(&vop->irq_lock, flags);
1139
1140         return 0;
1141 }
1142
1143 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1144 {
1145         struct vop *vop = to_vop(crtc);
1146         unsigned long flags;
1147
1148         if (!vop->is_enabled)
1149                 return;
1150
1151         spin_lock_irqsave(&vop->irq_lock, flags);
1152
1153         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1154
1155         spin_unlock_irqrestore(&vop->irq_lock, flags);
1156 }
1157
1158 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1159 {
1160         struct vop *vop = to_vop(crtc);
1161
1162         reinit_completion(&vop->wait_update_complete);
1163         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1164 }
1165
1166 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1167                                            struct drm_file *file_priv)
1168 {
1169         struct drm_device *drm = crtc->dev;
1170         struct vop *vop = to_vop(crtc);
1171         struct drm_pending_vblank_event *e;
1172         unsigned long flags;
1173
1174         spin_lock_irqsave(&drm->event_lock, flags);
1175         e = vop->event;
1176         if (e && e->base.file_priv == file_priv) {
1177                 vop->event = NULL;
1178
1179                 e->base.destroy(&e->base);
1180                 file_priv->event_space += sizeof(e->event);
1181         }
1182         spin_unlock_irqrestore(&drm->event_lock, flags);
1183 }
1184
1185 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1186         .enable_vblank = vop_crtc_enable_vblank,
1187         .disable_vblank = vop_crtc_disable_vblank,
1188         .wait_for_update = vop_crtc_wait_for_update,
1189         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1190 };
1191
1192 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1193                                 const struct drm_display_mode *mode,
1194                                 struct drm_display_mode *adjusted_mode)
1195 {
1196         struct vop *vop = to_vop(crtc);
1197
1198         adjusted_mode->clock =
1199                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1200
1201         return true;
1202 }
1203
1204 static void vop_crtc_enable(struct drm_crtc *crtc)
1205 {
1206         struct vop *vop = to_vop(crtc);
1207         const struct vop_data *vop_data = vop->data;
1208         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1209         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1210         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1211         u16 hdisplay = adjusted_mode->hdisplay;
1212         u16 htotal = adjusted_mode->htotal;
1213         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1214         u16 hact_end = hact_st + hdisplay;
1215         u16 vdisplay = adjusted_mode->vdisplay;
1216         u16 vtotal = adjusted_mode->vtotal;
1217         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1218         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1219         u16 vact_end = vact_st + vdisplay;
1220         uint32_t val;
1221
1222         vop_enable(crtc);
1223         /*
1224          * If dclk rate is zero, mean that scanout is stop,
1225          * we don't need wait any more.
1226          */
1227         if (clk_get_rate(vop->dclk)) {
1228                 /*
1229                  * Rk3288 vop timing register is immediately, when configure
1230                  * display timing on display time, may cause tearing.
1231                  *
1232                  * Vop standby will take effect at end of current frame,
1233                  * if dsp hold valid irq happen, it means standby complete.
1234                  *
1235                  * mode set:
1236                  *    standby and wait complete --> |----
1237                  *                                  | display time
1238                  *                                  |----
1239                  *                                  |---> dsp hold irq
1240                  *     configure display timing --> |
1241                  *         standby exit             |
1242                  *                                  | new frame start.
1243                  */
1244
1245                 reinit_completion(&vop->dsp_hold_completion);
1246                 vop_dsp_hold_valid_irq_enable(vop);
1247
1248                 spin_lock(&vop->reg_lock);
1249
1250                 VOP_CTRL_SET(vop, standby, 1);
1251
1252                 spin_unlock(&vop->reg_lock);
1253
1254                 wait_for_completion(&vop->dsp_hold_completion);
1255
1256                 vop_dsp_hold_valid_irq_disable(vop);
1257         }
1258
1259         val = 0x8;
1260         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1261         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1262         VOP_CTRL_SET(vop, pin_pol, val);
1263         switch (s->output_type) {
1264         case DRM_MODE_CONNECTOR_LVDS:
1265                 VOP_CTRL_SET(vop, rgb_en, 1);
1266                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1267                 break;
1268         case DRM_MODE_CONNECTOR_eDP:
1269                 VOP_CTRL_SET(vop, edp_en, 1);
1270                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1271                 break;
1272         case DRM_MODE_CONNECTOR_HDMIA:
1273                 VOP_CTRL_SET(vop, hdmi_en, 1);
1274                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1275                 break;
1276         case DRM_MODE_CONNECTOR_DSI:
1277                 VOP_CTRL_SET(vop, mipi_en, 1);
1278                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1279                 break;
1280         default:
1281                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1282         }
1283
1284         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1285             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1286                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1287
1288         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1289
1290         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1291         val = hact_st << 16;
1292         val |= hact_end;
1293         VOP_CTRL_SET(vop, hact_st_end, val);
1294         VOP_CTRL_SET(vop, hpost_st_end, val);
1295
1296         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1297         val = vact_st << 16;
1298         val |= vact_end;
1299         VOP_CTRL_SET(vop, vact_st_end, val);
1300         VOP_CTRL_SET(vop, vpost_st_end, val);
1301
1302         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1303
1304         VOP_CTRL_SET(vop, standby, 0);
1305 }
1306
1307 static int vop_zpos_cmp(const void *a, const void *b)
1308 {
1309         struct vop_zpos *pa = (struct vop_zpos *)a;
1310         struct vop_zpos *pb = (struct vop_zpos *)b;
1311
1312         return pa->zpos - pb->zpos;
1313 }
1314
1315 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1316                                  struct drm_crtc_state *crtc_state)
1317 {
1318         struct drm_atomic_state *state = crtc_state->state;
1319         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1320         struct vop *vop = to_vop(crtc);
1321         const struct vop_data *vop_data = vop->data;
1322         struct drm_plane *plane;
1323         struct drm_plane_state *pstate;
1324         struct vop_plane_state *plane_state;
1325         struct vop_zpos *pzpos;
1326         int dsp_layer_sel = 0;
1327         int i, j, cnt = 0, ret = 0;
1328
1329         ret = vop_csc_atomic_check(crtc, crtc_state);
1330         if (ret)
1331                 return ret;
1332
1333         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1334         if (!pzpos)
1335                 return -ENOMEM;
1336
1337         for (i = 0; i < vop_data->win_size; i++) {
1338                 const struct vop_win_data *win_data = &vop_data->win[i];
1339                 struct vop_win *win;
1340
1341                 if (!win_data->phy)
1342                         continue;
1343
1344                 for (j = 0; j < vop->num_wins; j++) {
1345                         win = &vop->win[j];
1346
1347                         if (win->win_id == i && !win->area_id)
1348                                 break;
1349                 }
1350                 if (WARN_ON(j >= vop->num_wins)) {
1351                         ret = -EINVAL;
1352                         goto err_free_pzpos;
1353                 }
1354
1355                 plane = &win->base;
1356                 pstate = state->plane_states[drm_plane_index(plane)];
1357                 /*
1358                  * plane might not have changed, in which case take
1359                  * current state:
1360                  */
1361                 if (!pstate)
1362                         pstate = plane->state;
1363                 plane_state = to_vop_plane_state(pstate);
1364                 pzpos[cnt].zpos = plane_state->zpos;
1365                 pzpos[cnt++].win_id = win->win_id;
1366         }
1367
1368         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1369
1370         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1371                 const struct vop_win_data *win_data = &vop_data->win[i];
1372                 int shift = i * 2;
1373
1374                 if (win_data->phy) {
1375                         struct vop_zpos *zpos = &pzpos[cnt++];
1376
1377                         dsp_layer_sel |= zpos->win_id << shift;
1378                 } else {
1379                         dsp_layer_sel |= i << shift;
1380                 }
1381         }
1382
1383         s->dsp_layer_sel = dsp_layer_sel;
1384
1385 err_free_pzpos:
1386         kfree(pzpos);
1387         return ret;
1388 }
1389
1390 static void vop_cfg_update(struct drm_crtc *crtc,
1391                            struct drm_crtc_state *old_crtc_state)
1392 {
1393         struct rockchip_crtc_state *s =
1394                         to_rockchip_crtc_state(crtc->state);
1395         struct vop *vop = to_vop(crtc);
1396
1397         spin_lock(&vop->reg_lock);
1398
1399         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1400         vop_cfg_done(vop);
1401
1402         spin_unlock(&vop->reg_lock);
1403 }
1404
1405 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1406                                   struct drm_crtc_state *old_crtc_state)
1407 {
1408         struct vop *vop = to_vop(crtc);
1409
1410         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1411                 int ret;
1412                 if (!vop_is_allwin_disabled(vop)) {
1413                         vop_cfg_update(crtc, old_crtc_state);
1414                         while(!vop_is_cfg_done_complete(vop));
1415                 }
1416                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1417                 if (ret) {
1418                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1419                 }
1420                 vop->is_iommu_enabled = true;
1421         }
1422
1423         vop_cfg_update(crtc, old_crtc_state);
1424 }
1425
1426 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1427                                   struct drm_crtc_state *old_crtc_state)
1428 {
1429         struct vop *vop = to_vop(crtc);
1430
1431         if (crtc->state->event) {
1432                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1433
1434                 vop->event = crtc->state->event;
1435                 crtc->state->event = NULL;
1436         }
1437 }
1438
1439 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1440         .enable = vop_crtc_enable,
1441         .disable = vop_crtc_disable,
1442         .mode_fixup = vop_crtc_mode_fixup,
1443         .atomic_check = vop_crtc_atomic_check,
1444         .atomic_flush = vop_crtc_atomic_flush,
1445         .atomic_begin = vop_crtc_atomic_begin,
1446 };
1447
1448 static void vop_crtc_destroy(struct drm_crtc *crtc)
1449 {
1450         drm_crtc_cleanup(crtc);
1451 }
1452
1453 static void vop_crtc_reset(struct drm_crtc *crtc)
1454 {
1455         if (crtc->state)
1456                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1457         kfree(crtc->state);
1458
1459         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1460         if (crtc->state)
1461                 crtc->state->crtc = crtc;
1462 }
1463
1464 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1465 {
1466         struct rockchip_crtc_state *rockchip_state;
1467
1468         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1469         if (!rockchip_state)
1470                 return NULL;
1471
1472         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1473         return &rockchip_state->base;
1474 }
1475
1476 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1477                                    struct drm_crtc_state *state)
1478 {
1479         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1480
1481         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1482         kfree(s);
1483 }
1484
1485 static const struct drm_crtc_funcs vop_crtc_funcs = {
1486         .set_config = drm_atomic_helper_set_config,
1487         .page_flip = drm_atomic_helper_page_flip,
1488         .destroy = vop_crtc_destroy,
1489         .reset = vop_crtc_reset,
1490         .atomic_duplicate_state = vop_crtc_duplicate_state,
1491         .atomic_destroy_state = vop_crtc_destroy_state,
1492 };
1493
1494 static void vop_handle_vblank(struct vop *vop)
1495 {
1496         struct drm_device *drm = vop->drm_dev;
1497         struct drm_crtc *crtc = &vop->crtc;
1498         unsigned long flags;
1499
1500         if (!vop_is_cfg_done_complete(vop))
1501                 return;
1502
1503         if (vop->event) {
1504                 spin_lock_irqsave(&drm->event_lock, flags);
1505
1506                 drm_crtc_send_vblank_event(crtc, vop->event);
1507                 drm_crtc_vblank_put(crtc);
1508                 vop->event = NULL;
1509
1510                 spin_unlock_irqrestore(&drm->event_lock, flags);
1511         }
1512         if (!completion_done(&vop->wait_update_complete))
1513                 complete(&vop->wait_update_complete);
1514 }
1515
1516 static irqreturn_t vop_isr(int irq, void *data)
1517 {
1518         struct vop *vop = data;
1519         struct drm_crtc *crtc = &vop->crtc;
1520         uint32_t active_irqs;
1521         unsigned long flags;
1522         int ret = IRQ_NONE;
1523
1524         /*
1525          * interrupt register has interrupt status, enable and clear bits, we
1526          * must hold irq_lock to avoid a race with enable/disable_vblank().
1527         */
1528         spin_lock_irqsave(&vop->irq_lock, flags);
1529
1530         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1531         /* Clear all active interrupt sources */
1532         if (active_irqs)
1533                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1534
1535         spin_unlock_irqrestore(&vop->irq_lock, flags);
1536
1537         /* This is expected for vop iommu irqs, since the irq is shared */
1538         if (!active_irqs)
1539                 return IRQ_NONE;
1540
1541         if (active_irqs & DSP_HOLD_VALID_INTR) {
1542                 complete(&vop->dsp_hold_completion);
1543                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1544                 ret = IRQ_HANDLED;
1545         }
1546
1547         if (active_irqs & FS_INTR) {
1548                 drm_crtc_handle_vblank(crtc);
1549                 vop_handle_vblank(vop);
1550                 active_irqs &= ~FS_INTR;
1551                 ret = IRQ_HANDLED;
1552         }
1553
1554         /* Unhandled irqs are spurious. */
1555         if (active_irqs)
1556                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1557
1558         return ret;
1559 }
1560
1561 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1562                           unsigned long possible_crtcs)
1563 {
1564         struct drm_plane *share = NULL;
1565         unsigned int rotations = 0;
1566         struct drm_property *prop;
1567         uint64_t feature = 0;
1568         int ret;
1569
1570         if (win->parent)
1571                 share = &win->parent->base;
1572
1573         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1574                                    possible_crtcs, &vop_plane_funcs,
1575                                    win->data_formats, win->nformats, win->type);
1576         if (ret) {
1577                 DRM_ERROR("failed to initialize plane\n");
1578                 return ret;
1579         }
1580         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1581         drm_object_attach_property(&win->base.base,
1582                                    vop->plane_zpos_prop, win->win_id);
1583
1584         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1585                 rotations |= BIT(DRM_REFLECT_X);
1586
1587         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1588                 rotations |= BIT(DRM_REFLECT_Y);
1589
1590         if (rotations) {
1591                 rotations |= BIT(DRM_ROTATE_0);
1592                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1593                                                          rotations);
1594                 if (!prop) {
1595                         DRM_ERROR("failed to create zpos property\n");
1596                         return -EINVAL;
1597                 }
1598                 drm_object_attach_property(&win->base.base, prop,
1599                                            BIT(DRM_ROTATE_0));
1600                 win->rotation_prop = prop;
1601         }
1602         if (win->phy->scl)
1603                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1604         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1605             VOP_WIN_SUPPORT(vop, win, alpha_en))
1606                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1607
1608         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1609                                    feature);
1610
1611         return 0;
1612 }
1613
1614 static int vop_create_crtc(struct vop *vop)
1615 {
1616         struct device *dev = vop->dev;
1617         struct drm_device *drm_dev = vop->drm_dev;
1618         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1619         struct drm_crtc *crtc = &vop->crtc;
1620         struct device_node *port;
1621         int ret;
1622         int i;
1623
1624         /*
1625          * Create drm_plane for primary and cursor planes first, since we need
1626          * to pass them to drm_crtc_init_with_planes, which sets the
1627          * "possible_crtcs" to the newly initialized crtc.
1628          */
1629         for (i = 0; i < vop->num_wins; i++) {
1630                 struct vop_win *win = &vop->win[i];
1631
1632                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1633                     win->type != DRM_PLANE_TYPE_CURSOR)
1634                         continue;
1635
1636                 ret = vop_plane_init(vop, win, 0);
1637                 if (ret)
1638                         goto err_cleanup_planes;
1639
1640                 plane = &win->base;
1641                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1642                         primary = plane;
1643                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1644                         cursor = plane;
1645
1646         }
1647
1648         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1649                                         &vop_crtc_funcs, NULL);
1650         if (ret)
1651                 goto err_cleanup_planes;
1652
1653         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1654
1655         /*
1656          * Create drm_planes for overlay windows with possible_crtcs restricted
1657          * to the newly created crtc.
1658          */
1659         for (i = 0; i < vop->num_wins; i++) {
1660                 struct vop_win *win = &vop->win[i];
1661                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1662
1663                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1664                         continue;
1665
1666                 ret = vop_plane_init(vop, win, possible_crtcs);
1667                 if (ret)
1668                         goto err_cleanup_crtc;
1669         }
1670
1671         port = of_get_child_by_name(dev->of_node, "port");
1672         if (!port) {
1673                 DRM_ERROR("no port node found in %s\n",
1674                           dev->of_node->full_name);
1675                 ret = -ENOENT;
1676                 goto err_cleanup_crtc;
1677         }
1678
1679         init_completion(&vop->dsp_hold_completion);
1680         init_completion(&vop->wait_update_complete);
1681         crtc->port = port;
1682         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1683
1684         return 0;
1685
1686 err_cleanup_crtc:
1687         drm_crtc_cleanup(crtc);
1688 err_cleanup_planes:
1689         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1690                                  head)
1691                 drm_plane_cleanup(plane);
1692         return ret;
1693 }
1694
1695 static void vop_destroy_crtc(struct vop *vop)
1696 {
1697         struct drm_crtc *crtc = &vop->crtc;
1698         struct drm_device *drm_dev = vop->drm_dev;
1699         struct drm_plane *plane, *tmp;
1700
1701         rockchip_unregister_crtc_funcs(crtc);
1702         of_node_put(crtc->port);
1703
1704         /*
1705          * We need to cleanup the planes now.  Why?
1706          *
1707          * The planes are "&vop->win[i].base".  That means the memory is
1708          * all part of the big "struct vop" chunk of memory.  That memory
1709          * was devm allocated and associated with this component.  We need to
1710          * free it ourselves before vop_unbind() finishes.
1711          */
1712         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1713                                  head)
1714                 vop_plane_destroy(plane);
1715
1716         /*
1717          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1718          * references the CRTC.
1719          */
1720         drm_crtc_cleanup(crtc);
1721 }
1722
1723 /*
1724  * Initialize the vop->win array elements.
1725  */
1726 static int vop_win_init(struct vop *vop)
1727 {
1728         const struct vop_data *vop_data = vop->data;
1729         unsigned int i, j;
1730         unsigned int num_wins = 0;
1731         struct drm_property *prop;
1732         static const struct drm_prop_enum_list props[] = {
1733                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1734                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1735         };
1736
1737         for (i = 0; i < vop_data->win_size; i++) {
1738                 struct vop_win *vop_win = &vop->win[num_wins];
1739                 const struct vop_win_data *win_data = &vop_data->win[i];
1740
1741                 if (!win_data->phy)
1742                         continue;
1743
1744                 vop_win->phy = win_data->phy;
1745                 vop_win->csc = win_data->csc;
1746                 vop_win->offset = win_data->base;
1747                 vop_win->type = win_data->type;
1748                 vop_win->data_formats = win_data->phy->data_formats;
1749                 vop_win->nformats = win_data->phy->nformats;
1750                 vop_win->vop = vop;
1751                 vop_win->win_id = i;
1752                 vop_win->area_id = 0;
1753                 num_wins++;
1754
1755                 for (j = 0; j < win_data->area_size; j++) {
1756                         struct vop_win *vop_area = &vop->win[num_wins];
1757                         const struct vop_win_phy *area = win_data->area[j];
1758
1759                         vop_area->parent = vop_win;
1760                         vop_area->offset = vop_win->offset;
1761                         vop_area->phy = area;
1762                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1763                         vop_area->data_formats = vop_win->data_formats;
1764                         vop_area->nformats = vop_win->nformats;
1765                         vop_area->vop = vop;
1766                         vop_area->win_id = i;
1767                         vop_area->area_id = j;
1768                         num_wins++;
1769                 }
1770         }
1771
1772         vop->num_wins = num_wins;
1773
1774         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1775                                          "ZPOS", 0, vop->data->win_size);
1776         if (!prop) {
1777                 DRM_ERROR("failed to create zpos property\n");
1778                 return -EINVAL;
1779         }
1780         vop->plane_zpos_prop = prop;
1781
1782         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1783                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1784                                 props, ARRAY_SIZE(props),
1785                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1786                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1787         if (!vop->plane_feature_prop) {
1788                 DRM_ERROR("failed to create feature property\n");
1789                 return -EINVAL;
1790         }
1791
1792         return 0;
1793 }
1794
1795 static int vop_bind(struct device *dev, struct device *master, void *data)
1796 {
1797         struct platform_device *pdev = to_platform_device(dev);
1798         const struct vop_data *vop_data;
1799         struct drm_device *drm_dev = data;
1800         struct vop *vop;
1801         struct resource *res;
1802         size_t alloc_size;
1803         int ret, irq, i;
1804         int num_wins = 0;
1805
1806         vop_data = of_device_get_match_data(dev);
1807         if (!vop_data)
1808                 return -ENODEV;
1809
1810         for (i = 0; i < vop_data->win_size; i++) {
1811                 const struct vop_win_data *win_data = &vop_data->win[i];
1812
1813                 num_wins += win_data->area_size + 1;
1814         }
1815
1816         /* Allocate vop struct and its vop_win array */
1817         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1818         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1819         if (!vop)
1820                 return -ENOMEM;
1821
1822         vop->dev = dev;
1823         vop->data = vop_data;
1824         vop->drm_dev = drm_dev;
1825         vop->num_wins = num_wins;
1826         dev_set_drvdata(dev, vop);
1827
1828         ret = vop_win_init(vop);
1829         if (ret)
1830                 return ret;
1831
1832         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1833         vop->len = resource_size(res);
1834         vop->regs = devm_ioremap_resource(dev, res);
1835         if (IS_ERR(vop->regs))
1836                 return PTR_ERR(vop->regs);
1837
1838         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1839         if (!vop->regsbak)
1840                 return -ENOMEM;
1841
1842         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1843         if (IS_ERR(vop->hclk)) {
1844                 dev_err(vop->dev, "failed to get hclk source\n");
1845                 return PTR_ERR(vop->hclk);
1846         }
1847         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1848         if (IS_ERR(vop->aclk)) {
1849                 dev_err(vop->dev, "failed to get aclk source\n");
1850                 return PTR_ERR(vop->aclk);
1851         }
1852         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1853         if (IS_ERR(vop->dclk)) {
1854                 dev_err(vop->dev, "failed to get dclk source\n");
1855                 return PTR_ERR(vop->dclk);
1856         }
1857
1858         irq = platform_get_irq(pdev, 0);
1859         if (irq < 0) {
1860                 dev_err(dev, "cannot find irq for vop\n");
1861                 return irq;
1862         }
1863         vop->irq = (unsigned int)irq;
1864
1865         spin_lock_init(&vop->reg_lock);
1866         spin_lock_init(&vop->irq_lock);
1867
1868         mutex_init(&vop->vsync_mutex);
1869
1870         ret = devm_request_irq(dev, vop->irq, vop_isr,
1871                                IRQF_SHARED, dev_name(dev), vop);
1872         if (ret)
1873                 return ret;
1874
1875         /* IRQ is initially disabled; it gets enabled in power_on */
1876         disable_irq(vop->irq);
1877
1878         ret = vop_create_crtc(vop);
1879         if (ret)
1880                 return ret;
1881
1882         pm_runtime_enable(&pdev->dev);
1883         return 0;
1884 }
1885
1886 static void vop_unbind(struct device *dev, struct device *master, void *data)
1887 {
1888         struct vop *vop = dev_get_drvdata(dev);
1889
1890         pm_runtime_disable(dev);
1891         vop_destroy_crtc(vop);
1892 }
1893
1894 const struct component_ops vop_component_ops = {
1895         .bind = vop_bind,
1896         .unbind = vop_unbind,
1897 };
1898 EXPORT_SYMBOL_GPL(vop_component_ops);