drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34
  35 #include "rockchip_drm_drv.h"
  36 #include "rockchip_drm_gem.h"
  37 #include "rockchip_drm_fb.h"
  38 #include "rockchip_drm_vop.h"
  39
  40 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
  41                 vop_mask_write(x, off, mask, shift, v, write_mask, true)
  42
  43 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
  44                 vop_mask_write(x, off, mask, shift, v, write_mask, false)
  45
  46 #define REG_SET(x, off, reg, v, mode) \
  47                 __REG_SET_##mode(x, off + reg.offset, \
  48                                  reg.mask, reg.shift, v, reg.write_mask)
  49 #define REG_SET_MASK(x, off, reg, mask, v, mode) \
  50                 __REG_SET_##mode(x, off + reg.offset, \
  51                                  mask, reg.shift, v, reg.write_mask)
  52
  53 #define VOP_WIN_SET(x, win, name, v) \
  54                 REG_SET(x, win->offset, VOP_WIN_NAME(win, name), v, RELAXED)
  55 #define VOP_SCL_SET(x, win, name, v) \
  56                 REG_SET(x, win->offset, win->phy->scl->name, v, RELAXED)
  57 #define VOP_SCL_SET_EXT(x, win, name, v) \
  58                 REG_SET(x, win->offset, win->phy->scl->ext->name, v, RELAXED)
  59
  60 #define VOP_CTRL_SET(x, name, v) \
  61                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  62
  63 #define VOP_INTR_GET(vop, name) \
  64                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  65
  66 #define VOP_INTR_SET(vop, name, mask, v) \
  67                 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
  68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  69         do { \
  70                 int i, reg = 0, mask = 0; \
  71                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  72                         if (vop->data->intr->intrs[i] & type) { \
  73                                 reg |= (v) << i; \
  74                                 mask |= 1 << i; \
  75                         } \
  76                 } \
  77                 VOP_INTR_SET(vop, name, mask, reg); \
  78         } while (0)
  79 #define VOP_INTR_GET_TYPE(vop, name, type) \
  80                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  81
  82 #define VOP_WIN_GET(x, win, name) \
  83                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
  84
  85 #define VOP_WIN_NAME(win, name) \
  86                 (vop_get_win_phy(win, &win->phy->name)->name)
  87
  88 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  89                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
  90
  91 #define to_vop(x) container_of(x, struct vop, crtc)
  92 #define to_vop_win(x) container_of(x, struct vop_win, base)
  93 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  94
  95 struct vop_zpos {
  96         int win_id;
  97         int zpos;
  98 };
  99
 100 struct vop_plane_state {
 101         struct drm_plane_state base;
 102         int format;
 103         int zpos;
 104         struct drm_rect src;
 105         struct drm_rect dest;
 106         dma_addr_t yrgb_mst;
 107         bool enable;
 108 };
 109
 110 struct vop_win {
 111         struct vop_win *parent;
 112         struct drm_plane base;
 113
 114         int win_id;
 115         int area_id;
 116         uint32_t offset;
 117         enum drm_plane_type type;
 118         const struct vop_win_phy *phy;
 119         const uint32_t *data_formats;
 120         uint32_t nformats;
 121         struct vop *vop;
 122
 123         struct vop_plane_state state;
 124 };
 125
 126 struct vop {
 127         struct drm_crtc crtc;
 128         struct device *dev;
 129         struct drm_device *drm_dev;
 130         struct drm_property *plane_zpos_prop;
 131         bool is_enabled;
 132
 133         /* mutex vsync_ work */
 134         struct mutex vsync_mutex;
 135         bool vsync_work_pending;
 136         struct completion dsp_hold_completion;
 137         struct completion wait_update_complete;
 138         struct drm_pending_vblank_event *event;
 139
 140         const struct vop_data *data;
 141         int num_wins;
 142
 143         uint32_t *regsbak;
 144         void __iomem *regs;
 145
 146         /* physical map length of vop register */
 147         uint32_t len;
 148
 149         /* one time only one process allowed to config the register */
 150         spinlock_t reg_lock;
 151         /* lock vop irq reg */
 152         spinlock_t irq_lock;
 153
 154         unsigned int irq;
 155
 156         /* vop AHP clk */
 157         struct clk *hclk;
 158         /* vop dclk */
 159         struct clk *dclk;
 160         /* vop share memory frequency */
 161         struct clk *aclk;
 162
 163         /* vop dclk reset */
 164         struct reset_control *dclk_rst;
 165
 166         struct vop_win win[];
 167 };
 168
 169 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 170 {
 171         writel(v, vop->regs + offset);
 172         vop->regsbak[offset >> 2] = v;
 173 }
 174
 175 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 176 {
 177         return readl(vop->regs + offset);
 178 }
 179
 180 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 181                                     const struct vop_reg *reg)
 182 {
 183         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 184 }
 185
 186 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 187                                   uint32_t mask, uint32_t shift, uint32_t v,
 188                                   bool write_mask, bool relaxed)
 189 {
 190         if (!mask)
 191                 return;
 192
 193         if (write_mask) {
 194                 v = (v << shift) | (mask << (shift + 16));
 195         } else {
 196                 uint32_t cached_val = vop->regsbak[offset >> 2];
 197
 198                 v = (cached_val & ~(mask << shift)) | (v << shift);
 199                 vop->regsbak[offset >> 2] = v;
 200         }
 201
 202         if (relaxed)
 203                 writel_relaxed(v, vop->regs + offset);
 204         else
 205                 writel(v, vop->regs + offset);
 206 }
 207
 208 static inline const struct vop_win_phy *
 209 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 210 {
 211         if (!reg->mask && win->parent)
 212                 return win->parent->phy;
 213
 214         return win->phy;
 215 }
 216
 217 static inline uint32_t vop_get_intr_type(struct vop *vop,
 218                                          const struct vop_reg *reg, int type)
 219 {
 220         uint32_t i, ret = 0;
 221         uint32_t regs = vop_read_reg(vop, 0, reg);
 222
 223         for (i = 0; i < vop->data->intr->nintrs; i++) {
 224                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 225                         ret |= vop->data->intr->intrs[i];
 226         }
 227
 228         return ret;
 229 }
 230
 231 static inline void vop_cfg_done(struct vop *vop)
 232 {
 233         VOP_CTRL_SET(vop, cfg_done, 1);
 234 }
 235
 236 static bool has_rb_swapped(uint32_t format)
 237 {
 238         switch (format) {
 239         case DRM_FORMAT_XBGR8888:
 240         case DRM_FORMAT_ABGR8888:
 241         case DRM_FORMAT_BGR888:
 242         case DRM_FORMAT_BGR565:
 243                 return true;
 244         default:
 245                 return false;
 246         }
 247 }
 248
 249 static enum vop_data_format vop_convert_format(uint32_t format)
 250 {
 251         switch (format) {
 252         case DRM_FORMAT_XRGB8888:
 253         case DRM_FORMAT_ARGB8888:
 254         case DRM_FORMAT_XBGR8888:
 255         case DRM_FORMAT_ABGR8888:
 256                 return VOP_FMT_ARGB8888;
 257         case DRM_FORMAT_RGB888:
 258         case DRM_FORMAT_BGR888:
 259                 return VOP_FMT_RGB888;
 260         case DRM_FORMAT_RGB565:
 261         case DRM_FORMAT_BGR565:
 262                 return VOP_FMT_RGB565;
 263         case DRM_FORMAT_NV12:
 264                 return VOP_FMT_YUV420SP;
 265         case DRM_FORMAT_NV16:
 266                 return VOP_FMT_YUV422SP;
 267         case DRM_FORMAT_NV24:
 268                 return VOP_FMT_YUV444SP;
 269         default:
 270                 DRM_ERROR("unsupport format[%08x]\n", format);
 271                 return -EINVAL;
 272         }
 273 }
 274
 275 static bool is_yuv_support(uint32_t format)
 276 {
 277         switch (format) {
 278         case DRM_FORMAT_NV12:
 279         case DRM_FORMAT_NV16:
 280         case DRM_FORMAT_NV24:
 281                 return true;
 282         default:
 283                 return false;
 284         }
 285 }
 286
 287 static bool is_alpha_support(uint32_t format)
 288 {
 289         switch (format) {
 290         case DRM_FORMAT_ARGB8888:
 291         case DRM_FORMAT_ABGR8888:
 292                 return true;
 293         default:
 294                 return false;
 295         }
 296 }
 297
 298 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 299                                   uint32_t dst, bool is_horizontal,
 300                                   int vsu_mode, int *vskiplines)
 301 {
 302         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 303
 304         if (is_horizontal) {
 305                 if (mode == SCALE_UP)
 306                         val = GET_SCL_FT_BIC(src, dst);
 307                 else if (mode == SCALE_DOWN)
 308                         val = GET_SCL_FT_BILI_DN(src, dst);
 309         } else {
 310                 if (mode == SCALE_UP) {
 311                         if (vsu_mode == SCALE_UP_BIL)
 312                                 val = GET_SCL_FT_BILI_UP(src, dst);
 313                         else
 314                                 val = GET_SCL_FT_BIC(src, dst);
 315                 } else if (mode == SCALE_DOWN) {
 316                         if (vskiplines) {
 317                                 *vskiplines = scl_get_vskiplines(src, dst);
 318                                 val = scl_get_bili_dn_vskip(src, dst,
 319                                                             *vskiplines);
 320                         } else {
 321                                 val = GET_SCL_FT_BILI_DN(src, dst);
 322                         }
 323                 }
 324         }
 325
 326         return val;
 327 }
 328
 329 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 330                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 331                                 uint32_t dst_h, uint32_t pixel_format)
 332 {
 333         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 334         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 335         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 336         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 337         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 338         bool is_yuv = is_yuv_support(pixel_format);
 339         uint16_t cbcr_src_w = src_w / hsub;
 340         uint16_t cbcr_src_h = src_h / vsub;
 341         uint16_t vsu_mode;
 342         uint16_t lb_mode;
 343         uint32_t val;
 344         int vskiplines = 0;
 345
 346         if (!win->phy->scl)
 347                 return;
 348
 349         if (dst_w > 3840) {
 350                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 351                 return;
 352         }
 353
 354         if (!win->phy->scl->ext) {
 355                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 356                             scl_cal_scale2(src_w, dst_w));
 357                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 358                             scl_cal_scale2(src_h, dst_h));
 359                 if (is_yuv) {
 360                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 361                                     scl_cal_scale2(src_w, dst_w));
 362                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 363                                     scl_cal_scale2(src_h, dst_h));
 364                 }
 365                 return;
 366         }
 367
 368         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 369         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 370
 371         if (is_yuv) {
 372                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 373                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 374                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 375                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 376                 else
 377                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 378         } else {
 379                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 380                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 381                 else
 382                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 383         }
 384
 385         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 386         if (lb_mode == LB_RGB_3840X2) {
 387                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 388                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 389                         return;
 390                 }
 391                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 392                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 393                         return;
 394                 }
 395                 vsu_mode = SCALE_UP_BIL;
 396         } else if (lb_mode == LB_RGB_2560X4) {
 397                 vsu_mode = SCALE_UP_BIL;
 398         } else {
 399                 vsu_mode = SCALE_UP_BIC;
 400         }
 401
 402         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 403                                 true, 0, NULL);
 404         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 405         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 406                                 false, vsu_mode, &vskiplines);
 407         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 408
 409         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 410         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 411
 412         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 413         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 414         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 415         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 416         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 417         if (is_yuv) {
 418                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 419                                         dst_w, true, 0, NULL);
 420                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 421                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 422                                         dst_h, false, vsu_mode, &vskiplines);
 423                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 424
 425                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 426                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 427                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 428                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 429                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 430                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 431                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 432         }
 433 }
 434
 435 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 436 {
 437         unsigned long flags;
 438
 439         if (WARN_ON(!vop->is_enabled))
 440                 return;
 441
 442         spin_lock_irqsave(&vop->irq_lock, flags);
 443
 444         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 445
 446         spin_unlock_irqrestore(&vop->irq_lock, flags);
 447 }
 448
 449 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 450 {
 451         unsigned long flags;
 452
 453         if (WARN_ON(!vop->is_enabled))
 454                 return;
 455
 456         spin_lock_irqsave(&vop->irq_lock, flags);
 457
 458         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 459
 460         spin_unlock_irqrestore(&vop->irq_lock, flags);
 461 }
 462
 463 static void vop_enable(struct drm_crtc *crtc)
 464 {
 465         struct vop *vop = to_vop(crtc);
 466         int ret;
 467
 468         if (vop->is_enabled)
 469                 return;
 470
 471         ret = pm_runtime_get_sync(vop->dev);
 472         if (ret < 0) {
 473                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 474                 return;
 475         }
 476
 477         ret = clk_enable(vop->hclk);
 478         if (ret < 0) {
 479                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 480                 return;
 481         }
 482
 483         ret = clk_enable(vop->dclk);
 484         if (ret < 0) {
 485                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 486                 goto err_disable_hclk;
 487         }
 488
 489         ret = clk_enable(vop->aclk);
 490         if (ret < 0) {
 491                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 492                 goto err_disable_dclk;
 493         }
 494
 495         /*
 496          * Slave iommu shares power, irq and clock with vop.  It was associated
 497          * automatically with this master device via common driver code.
 498          * Now that we have enabled the clock we attach it to the shared drm
 499          * mapping.
 500          */
 501         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 502         if (ret) {
 503                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 504                 goto err_disable_aclk;
 505         }
 506
 507         memcpy(vop->regs, vop->regsbak, vop->len);
 508         /*
 509          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 510          */
 511         vop->is_enabled = true;
 512
 513         spin_lock(&vop->reg_lock);
 514
 515         VOP_CTRL_SET(vop, standby, 0);
 516
 517         spin_unlock(&vop->reg_lock);
 518
 519         enable_irq(vop->irq);
 520
 521         drm_crtc_vblank_on(crtc);
 522
 523         return;
 524
 525 err_disable_aclk:
 526         clk_disable(vop->aclk);
 527 err_disable_dclk:
 528         clk_disable(vop->dclk);
 529 err_disable_hclk:
 530         clk_disable(vop->hclk);
 531 }
 532
 533 static void vop_crtc_disable(struct drm_crtc *crtc)
 534 {
 535         struct vop *vop = to_vop(crtc);
 536         int i;
 537
 538         if (!vop->is_enabled)
 539                 return;
 540
 541         /*
 542          * We need to make sure that all windows are disabled before we
 543          * disable that crtc. Otherwise we might try to scan from a destroyed
 544          * buffer later.
 545          */
 546         for (i = 0; i < vop->num_wins; i++) {
 547                 struct vop_win *win = &vop->win[i];
 548
 549                 spin_lock(&vop->reg_lock);
 550                 VOP_WIN_SET(vop, win, enable, 0);
 551                 spin_unlock(&vop->reg_lock);
 552         }
 553
 554         drm_crtc_vblank_off(crtc);
 555
 556         /*
 557          * Vop standby will take effect at end of current frame,
 558          * if dsp hold valid irq happen, it means standby complete.
 559          *
 560          * we must wait standby complete when we want to disable aclk,
 561          * if not, memory bus maybe dead.
 562          */
 563         reinit_completion(&vop->dsp_hold_completion);
 564         vop_dsp_hold_valid_irq_enable(vop);
 565
 566         spin_lock(&vop->reg_lock);
 567
 568         VOP_CTRL_SET(vop, standby, 1);
 569
 570         spin_unlock(&vop->reg_lock);
 571
 572         wait_for_completion(&vop->dsp_hold_completion);
 573
 574         vop_dsp_hold_valid_irq_disable(vop);
 575
 576         disable_irq(vop->irq);
 577
 578         vop->is_enabled = false;
 579
 580         /*
 581          * vop standby complete, so iommu detach is safe.
 582          */
 583         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 584
 585         clk_disable(vop->dclk);
 586         clk_disable(vop->aclk);
 587         clk_disable(vop->hclk);
 588         pm_runtime_put(vop->dev);
 589 }
 590
 591 static void vop_plane_destroy(struct drm_plane *plane)
 592 {
 593         drm_plane_cleanup(plane);
 594 }
 595
 596 static int vop_plane_prepare_fb(struct drm_plane *plane,
 597                                 const struct drm_plane_state *new_state)
 598 {
 599         if (plane->state->fb)
 600                 drm_framebuffer_reference(plane->state->fb);
 601
 602         return 0;
 603 }
 604
 605 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 606                                  const struct drm_plane_state *old_state)
 607 {
 608         if (old_state->fb)
 609                 drm_framebuffer_unreference(old_state->fb);
 610 }
 611
 612 static int vop_plane_atomic_check(struct drm_plane *plane,
 613                            struct drm_plane_state *state)
 614 {
 615         struct drm_crtc *crtc = state->crtc;
 616         struct drm_framebuffer *fb = state->fb;
 617         struct vop_win *win = to_vop_win(plane);
 618         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 619         bool visible;
 620         int ret;
 621         struct drm_rect *dest = &vop_plane_state->dest;
 622         struct drm_rect *src = &vop_plane_state->src;
 623         struct drm_rect clip;
 624         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 625                                         DRM_PLANE_HELPER_NO_SCALING;
 626         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 627                                         DRM_PLANE_HELPER_NO_SCALING;
 628
 629         crtc = crtc ? crtc : plane->state->crtc;
 630         /*
 631          * Both crtc or plane->state->crtc can be null.
 632          */
 633         if (!crtc || !fb)
 634                 goto out_disable;
 635         src->x1 = state->src_x;
 636         src->y1 = state->src_y;
 637         src->x2 = state->src_x + state->src_w;
 638         src->y2 = state->src_y + state->src_h;
 639         dest->x1 = state->crtc_x;
 640         dest->y1 = state->crtc_y;
 641         dest->x2 = state->crtc_x + state->crtc_w;
 642         dest->y2 = state->crtc_y + state->crtc_h;
 643
 644         clip.x1 = 0;
 645         clip.y1 = 0;
 646         clip.x2 = crtc->mode.hdisplay;
 647         clip.y2 = crtc->mode.vdisplay;
 648
 649         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 650                                             src, dest, &clip,
 651                                             min_scale,
 652                                             max_scale,
 653                                             true, true, &visible);
 654         if (ret)
 655                 return ret;
 656
 657         if (!visible)
 658                 goto out_disable;
 659
 660         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 661         if (vop_plane_state->format < 0)
 662                 return vop_plane_state->format;
 663
 664         /*
 665          * Src.x1 can be odd when do clip, but yuv plane start point
 666          * need align with 2 pixel.
 667          */
 668         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 669                 return -EINVAL;
 670
 671         vop_plane_state->enable = true;
 672
 673         return 0;
 674
 675 out_disable:
 676         vop_plane_state->enable = false;
 677         return 0;
 678 }
 679
 680 static void vop_plane_atomic_disable(struct drm_plane *plane,
 681                                      struct drm_plane_state *old_state)
 682 {
 683         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 684         struct vop_win *win = to_vop_win(plane);
 685         struct vop *vop = to_vop(old_state->crtc);
 686
 687         if (!old_state->crtc)
 688                 return;
 689
 690         spin_lock(&vop->reg_lock);
 691
 692         VOP_WIN_SET(vop, win, enable, 0);
 693
 694         spin_unlock(&vop->reg_lock);
 695
 696         vop_plane_state->enable = false;
 697 }
 698
 699 static void vop_plane_atomic_update(struct drm_plane *plane,
 700                 struct drm_plane_state *old_state)
 701 {
 702         struct drm_plane_state *state = plane->state;
 703         struct drm_crtc *crtc = state->crtc;
 704         struct vop_win *win = to_vop_win(plane);
 705         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 706         struct vop *vop = to_vop(state->crtc);
 707         struct drm_framebuffer *fb = state->fb;
 708         unsigned int actual_w, actual_h;
 709         unsigned int dsp_stx, dsp_sty;
 710         uint32_t act_info, dsp_info, dsp_st;
 711         struct drm_rect *src = &vop_plane_state->src;
 712         struct drm_rect *dest = &vop_plane_state->dest;
 713         struct drm_gem_object *obj, *uv_obj;
 714         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 715         unsigned long offset;
 716         dma_addr_t dma_addr;
 717         uint32_t val;
 718         bool rb_swap;
 719
 720         /*
 721          * can't update plane when vop is disabled.
 722          */
 723         if (!crtc)
 724                 return;
 725
 726         if (WARN_ON(!vop->is_enabled))
 727                 return;
 728
 729         if (!vop_plane_state->enable) {
 730                 vop_plane_atomic_disable(plane, old_state);
 731                 return;
 732         }
 733
 734         obj = rockchip_fb_get_gem_obj(fb, 0);
 735         rk_obj = to_rockchip_obj(obj);
 736
 737         actual_w = drm_rect_width(src) >> 16;
 738         actual_h = drm_rect_height(src) >> 16;
 739         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 740
 741         dsp_info = (drm_rect_height(dest) - 1) << 16;
 742         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 743
 744         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 745         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 746         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 747
 748         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 749         offset += (src->y1 >> 16) * fb->pitches[0];
 750         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 751
 752         spin_lock(&vop->reg_lock);
 753
 754         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 755         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 756         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 757         if (is_yuv_support(fb->pixel_format)) {
 758                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 759                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 760                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 761
 762                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 763                 rk_uv_obj = to_rockchip_obj(uv_obj);
 764
 765                 offset = (src->x1 >> 16) * bpp / hsub;
 766                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 767
 768                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 769                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 770                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 771         }
 772
 773         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 774                             drm_rect_width(dest), drm_rect_height(dest),
 775                             fb->pixel_format);
 776
 777         VOP_WIN_SET(vop, win, act_info, act_info);
 778         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 779         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 780
 781         rb_swap = has_rb_swapped(fb->pixel_format);
 782         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 783
 784         if (is_alpha_support(fb->pixel_format)) {
 785                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 786                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 787                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 788                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 789                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 790                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 791                         SRC_FACTOR_M0(ALPHA_ONE);
 792                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 793         } else {
 794                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 795         }
 796
 797         VOP_WIN_SET(vop, win, enable, 1);
 798         spin_unlock(&vop->reg_lock);
 799 }
 800
 801 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 802         .prepare_fb = vop_plane_prepare_fb,
 803         .cleanup_fb = vop_plane_cleanup_fb,
 804         .atomic_check = vop_plane_atomic_check,
 805         .atomic_update = vop_plane_atomic_update,
 806         .atomic_disable = vop_plane_atomic_disable,
 807 };
 808
 809 void vop_atomic_plane_reset(struct drm_plane *plane)
 810 {
 811         struct vop_win *win = to_vop_win(plane);
 812         struct vop_plane_state *vop_plane_state =
 813                                         to_vop_plane_state(plane->state);
 814
 815         if (plane->state && plane->state->fb)
 816                 drm_framebuffer_unreference(plane->state->fb);
 817
 818         kfree(vop_plane_state);
 819         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 820         if (!vop_plane_state)
 821                 return;
 822
 823         vop_plane_state->zpos = win->win_id;
 824         plane->state = &vop_plane_state->base;
 825         plane->state->plane = plane;
 826 }
 827
 828 struct drm_plane_state *
 829 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 830 {
 831         struct vop_plane_state *old_vop_plane_state;
 832         struct vop_plane_state *vop_plane_state;
 833
 834         if (WARN_ON(!plane->state))
 835                 return NULL;
 836
 837         old_vop_plane_state = to_vop_plane_state(plane->state);
 838         vop_plane_state = kmemdup(old_vop_plane_state,
 839                                   sizeof(*vop_plane_state), GFP_KERNEL);
 840         if (!vop_plane_state)
 841                 return NULL;
 842
 843         __drm_atomic_helper_plane_duplicate_state(plane,
 844                                                   &vop_plane_state->base);
 845
 846         return &vop_plane_state->base;
 847 }
 848
 849 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 850                                            struct drm_plane_state *state)
 851 {
 852         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 853
 854         __drm_atomic_helper_plane_destroy_state(plane, state);
 855
 856         kfree(vop_state);
 857 }
 858
 859 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 860                                          struct drm_plane_state *state,
 861                                          struct drm_property *property,
 862                                          uint64_t val)
 863 {
 864         struct vop_win *win = to_vop_win(plane);
 865         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 866
 867         if (property == win->vop->plane_zpos_prop) {
 868                 plane_state->zpos = val;
 869                 return 0;
 870         }
 871
 872         DRM_ERROR("failed to set vop plane property\n");
 873         return -EINVAL;
 874 }
 875
 876 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 877                                          const struct drm_plane_state *state,
 878                                          struct drm_property *property,
 879                                          uint64_t *val)
 880 {
 881         struct vop_win *win = to_vop_win(plane);
 882         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 883
 884         if (property == win->vop->plane_zpos_prop) {
 885                 *val = plane_state->zpos;
 886                 return 0;
 887         }
 888
 889         DRM_ERROR("failed to get vop plane property\n");
 890         return -EINVAL;
 891 }
 892
 893 static const struct drm_plane_funcs vop_plane_funcs = {
 894         .update_plane   = drm_atomic_helper_update_plane,
 895         .disable_plane  = drm_atomic_helper_disable_plane,
 896         .destroy = vop_plane_destroy,
 897         .reset = vop_atomic_plane_reset,
 898         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 899         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 900         .atomic_set_property = vop_atomic_plane_set_property,
 901         .atomic_get_property = vop_atomic_plane_get_property,
 902 };
 903
 904 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 905 {
 906         struct vop *vop = to_vop(crtc);
 907         unsigned long flags;
 908
 909         if (WARN_ON(!vop->is_enabled))
 910                 return -EPERM;
 911
 912         spin_lock_irqsave(&vop->irq_lock, flags);
 913
 914         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 915
 916         spin_unlock_irqrestore(&vop->irq_lock, flags);
 917
 918         return 0;
 919 }
 920
 921 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 922 {
 923         struct vop *vop = to_vop(crtc);
 924         unsigned long flags;
 925
 926         if (WARN_ON(!vop->is_enabled))
 927                 return;
 928
 929         spin_lock_irqsave(&vop->irq_lock, flags);
 930
 931         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 932
 933         spin_unlock_irqrestore(&vop->irq_lock, flags);
 934 }
 935
 936 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 937 {
 938         struct vop *vop = to_vop(crtc);
 939
 940         reinit_completion(&vop->wait_update_complete);
 941         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
 942 }
 943
 944 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
 945                                            struct drm_file *file_priv)
 946 {
 947         struct drm_device *drm = crtc->dev;
 948         struct vop *vop = to_vop(crtc);
 949         struct drm_pending_vblank_event *e;
 950         unsigned long flags;
 951
 952         spin_lock_irqsave(&drm->event_lock, flags);
 953         e = vop->event;
 954         if (e && e->base.file_priv == file_priv) {
 955                 vop->event = NULL;
 956
 957                 e->base.destroy(&e->base);
 958                 file_priv->event_space += sizeof(e->event);
 959         }
 960         spin_unlock_irqrestore(&drm->event_lock, flags);
 961 }
 962
 963 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 964         .enable_vblank = vop_crtc_enable_vblank,
 965         .disable_vblank = vop_crtc_disable_vblank,
 966         .wait_for_update = vop_crtc_wait_for_update,
 967         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
 968 };
 969
 970 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 971                                 const struct drm_display_mode *mode,
 972                                 struct drm_display_mode *adjusted_mode)
 973 {
 974         struct vop *vop = to_vop(crtc);
 975
 976         adjusted_mode->clock =
 977                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
 978
 979         return true;
 980 }
 981
 982 static void vop_crtc_enable(struct drm_crtc *crtc)
 983 {
 984         struct vop *vop = to_vop(crtc);
 985         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 986         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 987         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 988         u16 hdisplay = adjusted_mode->hdisplay;
 989         u16 htotal = adjusted_mode->htotal;
 990         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 991         u16 hact_end = hact_st + hdisplay;
 992         u16 vdisplay = adjusted_mode->vdisplay;
 993         u16 vtotal = adjusted_mode->vtotal;
 994         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 995         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 996         u16 vact_end = vact_st + vdisplay;
 997         uint32_t val;
 998
 999         vop_enable(crtc);
1000         /*
1001          * If dclk rate is zero, mean that scanout is stop,
1002          * we don't need wait any more.
1003          */
1004         if (clk_get_rate(vop->dclk)) {
1005                 /*
1006                  * Rk3288 vop timing register is immediately, when configure
1007                  * display timing on display time, may cause tearing.
1008                  *
1009                  * Vop standby will take effect at end of current frame,
1010                  * if dsp hold valid irq happen, it means standby complete.
1011                  *
1012                  * mode set:
1013                  *    standby and wait complete --> |----
1014                  *                                  | display time
1015                  *                                  |----
1016                  *                                  |---> dsp hold irq
1017                  *     configure display timing --> |
1018                  *         standby exit             |
1019                  *                                  | new frame start.
1020                  */
1021
1022                 reinit_completion(&vop->dsp_hold_completion);
1023                 vop_dsp_hold_valid_irq_enable(vop);
1024
1025                 spin_lock(&vop->reg_lock);
1026
1027                 VOP_CTRL_SET(vop, standby, 1);
1028
1029                 spin_unlock(&vop->reg_lock);
1030
1031                 wait_for_completion(&vop->dsp_hold_completion);
1032
1033                 vop_dsp_hold_valid_irq_disable(vop);
1034         }
1035
1036         val = 0x8;
1037         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1038         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1039         VOP_CTRL_SET(vop, pin_pol, val);
1040         switch (s->output_type) {
1041         case DRM_MODE_CONNECTOR_LVDS:
1042                 VOP_CTRL_SET(vop, rgb_en, 1);
1043                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1044                 break;
1045         case DRM_MODE_CONNECTOR_eDP:
1046                 VOP_CTRL_SET(vop, edp_en, 1);
1047                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1048                 break;
1049         case DRM_MODE_CONNECTOR_HDMIA:
1050                 VOP_CTRL_SET(vop, hdmi_en, 1);
1051                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1052                 break;
1053         case DRM_MODE_CONNECTOR_DSI:
1054                 VOP_CTRL_SET(vop, mipi_en, 1);
1055                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1056                 break;
1057         default:
1058                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1059         }
1060         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1061
1062         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1063         val = hact_st << 16;
1064         val |= hact_end;
1065         VOP_CTRL_SET(vop, hact_st_end, val);
1066         VOP_CTRL_SET(vop, hpost_st_end, val);
1067
1068         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1069         val = vact_st << 16;
1070         val |= vact_end;
1071         VOP_CTRL_SET(vop, vact_st_end, val);
1072         VOP_CTRL_SET(vop, vpost_st_end, val);
1073
1074         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1075
1076         VOP_CTRL_SET(vop, standby, 0);
1077 }
1078
1079 static int vop_zpos_cmp(const void *a, const void *b)
1080 {
1081         struct vop_zpos *pa = (struct vop_zpos *)a;
1082         struct vop_zpos *pb = (struct vop_zpos *)b;
1083
1084         return pb->zpos - pa->zpos;
1085 }
1086
1087 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1088                                  struct drm_crtc_state *state)
1089 {
1090         struct drm_device *dev = crtc->dev;
1091         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1092         struct vop *vop = to_vop(crtc);
1093         struct drm_plane *plane;
1094         struct vop_zpos *pzpos;
1095         int dsp_layer_sel = 0;
1096         int i, cnt = 0, ret = 0;
1097
1098         pzpos = kmalloc_array(vop->num_wins, sizeof(*pzpos), GFP_KERNEL);
1099         if (!pzpos)
1100                 return -ENOMEM;
1101
1102         drm_atomic_crtc_state_for_each_plane(plane, state) {
1103                 struct drm_plane_state *pstate;
1104                 struct vop_plane_state *plane_state;
1105                 struct vop_win *win = to_vop_win(plane);
1106
1107                 if (plane->parent)
1108                         continue;
1109                 if (cnt >= vop->num_wins) {
1110                         dev_err(dev->dev, "too many planes!\n");
1111                         ret = -EINVAL;
1112                         goto err_free_pzpos;
1113                 }
1114                 pstate = state->state->plane_states[drm_plane_index(plane)];
1115
1116                 /*
1117                  * plane might not have changed, in which case take
1118                  * current state:
1119                  */
1120                 if (!pstate)
1121                         pstate = plane->state;
1122                 plane_state = to_vop_plane_state(pstate);
1123                 pzpos[cnt].zpos = plane_state->zpos;
1124                 pzpos[cnt].win_id = win->win_id;
1125
1126                 cnt++;
1127         }
1128
1129         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1130
1131         for (i = 0; i < cnt; i++) {
1132                 struct vop_zpos *zpos = &pzpos[i];
1133
1134                 dsp_layer_sel <<= 2;
1135                 dsp_layer_sel |= zpos->win_id;
1136         }
1137
1138         s->dsp_layer_sel = dsp_layer_sel;
1139
1140 err_free_pzpos:
1141         kfree(pzpos);
1142         return ret;
1143 }
1144
1145 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1146                                   struct drm_crtc_state *old_crtc_state)
1147 {
1148         struct rockchip_crtc_state *s =
1149                         to_rockchip_crtc_state(crtc->state);
1150         struct vop *vop = to_vop(crtc);
1151
1152         if (WARN_ON(!vop->is_enabled))
1153                 return;
1154
1155         spin_lock(&vop->reg_lock);
1156
1157         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1158         vop_cfg_done(vop);
1159
1160         spin_unlock(&vop->reg_lock);
1161 }
1162
1163 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1164                                   struct drm_crtc_state *old_crtc_state)
1165 {
1166         struct vop *vop = to_vop(crtc);
1167
1168         if (crtc->state->event) {
1169                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1170
1171                 vop->event = crtc->state->event;
1172                 crtc->state->event = NULL;
1173         }
1174 }
1175
1176 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1177         .enable = vop_crtc_enable,
1178         .disable = vop_crtc_disable,
1179         .mode_fixup = vop_crtc_mode_fixup,
1180         .atomic_check = vop_crtc_atomic_check,
1181         .atomic_flush = vop_crtc_atomic_flush,
1182         .atomic_begin = vop_crtc_atomic_begin,
1183 };
1184
1185 static void vop_crtc_destroy(struct drm_crtc *crtc)
1186 {
1187         drm_crtc_cleanup(crtc);
1188 }
1189
1190 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1191 {
1192         struct rockchip_crtc_state *rockchip_state;
1193
1194         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1195         if (!rockchip_state)
1196                 return NULL;
1197
1198         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1199         return &rockchip_state->base;
1200 }
1201
1202 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1203                                    struct drm_crtc_state *state)
1204 {
1205         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1206
1207         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1208         kfree(s);
1209 }
1210
1211 static const struct drm_crtc_funcs vop_crtc_funcs = {
1212         .set_config = drm_atomic_helper_set_config,
1213         .page_flip = drm_atomic_helper_page_flip,
1214         .destroy = vop_crtc_destroy,
1215         .reset = drm_atomic_helper_crtc_reset,
1216         .atomic_duplicate_state = vop_crtc_duplicate_state,
1217         .atomic_destroy_state = vop_crtc_destroy_state,
1218 };
1219
1220 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1221 {
1222         struct drm_plane *plane = &vop_win->base;
1223         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1224         dma_addr_t yrgb_mst;
1225
1226         if (!state->enable)
1227                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1228
1229         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1230
1231         return yrgb_mst == state->yrgb_mst;
1232 }
1233
1234 static void vop_handle_vblank(struct vop *vop)
1235 {
1236         struct drm_device *drm = vop->drm_dev;
1237         struct drm_crtc *crtc = &vop->crtc;
1238         unsigned long flags;
1239         int i;
1240
1241         for (i = 0; i < vop->num_wins; i++) {
1242                 if (!vop_win_pending_is_complete(&vop->win[i]))
1243                         return;
1244         }
1245
1246         if (vop->event) {
1247                 spin_lock_irqsave(&drm->event_lock, flags);
1248
1249                 drm_crtc_send_vblank_event(crtc, vop->event);
1250                 drm_crtc_vblank_put(crtc);
1251                 vop->event = NULL;
1252
1253                 spin_unlock_irqrestore(&drm->event_lock, flags);
1254         }
1255         if (!completion_done(&vop->wait_update_complete))
1256                 complete(&vop->wait_update_complete);
1257 }
1258
1259 static irqreturn_t vop_isr(int irq, void *data)
1260 {
1261         struct vop *vop = data;
1262         struct drm_crtc *crtc = &vop->crtc;
1263         uint32_t active_irqs;
1264         unsigned long flags;
1265         int ret = IRQ_NONE;
1266
1267         /*
1268          * interrupt register has interrupt status, enable and clear bits, we
1269          * must hold irq_lock to avoid a race with enable/disable_vblank().
1270         */
1271         spin_lock_irqsave(&vop->irq_lock, flags);
1272
1273         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1274         /* Clear all active interrupt sources */
1275         if (active_irqs)
1276                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1277
1278         spin_unlock_irqrestore(&vop->irq_lock, flags);
1279
1280         /* This is expected for vop iommu irqs, since the irq is shared */
1281         if (!active_irqs)
1282                 return IRQ_NONE;
1283
1284         if (active_irqs & DSP_HOLD_VALID_INTR) {
1285                 complete(&vop->dsp_hold_completion);
1286                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1287                 ret = IRQ_HANDLED;
1288         }
1289
1290         if (active_irqs & FS_INTR) {
1291                 drm_crtc_handle_vblank(crtc);
1292                 vop_handle_vblank(vop);
1293                 active_irqs &= ~FS_INTR;
1294                 ret = IRQ_HANDLED;
1295         }
1296
1297         /* Unhandled irqs are spurious. */
1298         if (active_irqs)
1299                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1300
1301         return ret;
1302 }
1303
1304 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1305                           unsigned long possible_crtcs)
1306 {
1307         struct drm_plane *share = NULL;
1308         int ret;
1309
1310         if (win->parent)
1311                 share = &win->parent->base;
1312
1313         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1314                                    possible_crtcs, &vop_plane_funcs,
1315                                    win->data_formats, win->nformats, win->type);
1316         if (ret) {
1317                 DRM_ERROR("failed to initialize plane\n");
1318                 return ret;
1319         }
1320         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1321         drm_object_attach_property(&win->base.base,
1322                                    vop->plane_zpos_prop, win->win_id);
1323         return 0;
1324 }
1325
1326 static int vop_create_crtc(struct vop *vop)
1327 {
1328         struct device *dev = vop->dev;
1329         struct drm_device *drm_dev = vop->drm_dev;
1330         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1331         struct drm_crtc *crtc = &vop->crtc;
1332         struct device_node *port;
1333         int ret;
1334         int i;
1335
1336         /*
1337          * Create drm_plane for primary and cursor planes first, since we need
1338          * to pass them to drm_crtc_init_with_planes, which sets the
1339          * "possible_crtcs" to the newly initialized crtc.
1340          */
1341         for (i = 0; i < vop->num_wins; i++) {
1342                 struct vop_win *win = &vop->win[i];
1343
1344                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1345                     win->type != DRM_PLANE_TYPE_CURSOR)
1346                         continue;
1347
1348                 if (vop_plane_init(vop, win, 0))
1349                         goto err_cleanup_planes;
1350
1351                 plane = &win->base;
1352                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1353                         primary = plane;
1354                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1355                         cursor = plane;
1356
1357         }
1358
1359         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1360                                         &vop_crtc_funcs, NULL);
1361         if (ret)
1362                 goto err_cleanup_planes;
1363
1364         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1365
1366         /*
1367          * Create drm_planes for overlay windows with possible_crtcs restricted
1368          * to the newly created crtc.
1369          */
1370         for (i = 0; i < vop->num_wins; i++) {
1371                 struct vop_win *win = &vop->win[i];
1372                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1373
1374                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1375                         continue;
1376
1377                 if (vop_plane_init(vop, win, possible_crtcs))
1378                         goto err_cleanup_crtc;
1379         }
1380
1381         port = of_get_child_by_name(dev->of_node, "port");
1382         if (!port) {
1383                 DRM_ERROR("no port node found in %s\n",
1384                           dev->of_node->full_name);
1385                 ret = -ENOENT;
1386                 goto err_cleanup_crtc;
1387         }
1388
1389         init_completion(&vop->dsp_hold_completion);
1390         init_completion(&vop->wait_update_complete);
1391         crtc->port = port;
1392         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1393
1394         return 0;
1395
1396 err_cleanup_crtc:
1397         drm_crtc_cleanup(crtc);
1398 err_cleanup_planes:
1399         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1400                                  head)
1401                 drm_plane_cleanup(plane);
1402         return ret;
1403 }
1404
1405 static void vop_destroy_crtc(struct vop *vop)
1406 {
1407         struct drm_crtc *crtc = &vop->crtc;
1408         struct drm_device *drm_dev = vop->drm_dev;
1409         struct drm_plane *plane, *tmp;
1410
1411         rockchip_unregister_crtc_funcs(crtc);
1412         of_node_put(crtc->port);
1413
1414         /*
1415          * We need to cleanup the planes now.  Why?
1416          *
1417          * The planes are "&vop->win[i].base".  That means the memory is
1418          * all part of the big "struct vop" chunk of memory.  That memory
1419          * was devm allocated and associated with this component.  We need to
1420          * free it ourselves before vop_unbind() finishes.
1421          */
1422         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1423                                  head)
1424                 vop_plane_destroy(plane);
1425
1426         /*
1427          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1428          * references the CRTC.
1429          */
1430         drm_crtc_cleanup(crtc);
1431 }
1432
1433 static int vop_initial(struct vop *vop)
1434 {
1435         const struct vop_data *vop_data = vop->data;
1436         const struct vop_reg_data *init_table = vop_data->init_table;
1437         struct reset_control *ahb_rst;
1438         int i, ret;
1439
1440         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1441         if (IS_ERR(vop->hclk)) {
1442                 dev_err(vop->dev, "failed to get hclk source\n");
1443                 return PTR_ERR(vop->hclk);
1444         }
1445         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1446         if (IS_ERR(vop->aclk)) {
1447                 dev_err(vop->dev, "failed to get aclk source\n");
1448                 return PTR_ERR(vop->aclk);
1449         }
1450         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1451         if (IS_ERR(vop->dclk)) {
1452                 dev_err(vop->dev, "failed to get dclk source\n");
1453                 return PTR_ERR(vop->dclk);
1454         }
1455
1456         ret = clk_prepare(vop->dclk);
1457         if (ret < 0) {
1458                 dev_err(vop->dev, "failed to prepare dclk\n");
1459                 return ret;
1460         }
1461
1462         /* Enable both the hclk and aclk to setup the vop */
1463         ret = clk_prepare_enable(vop->hclk);
1464         if (ret < 0) {
1465                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1466                 goto err_unprepare_dclk;
1467         }
1468
1469         ret = clk_prepare_enable(vop->aclk);
1470         if (ret < 0) {
1471                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1472                 goto err_disable_hclk;
1473         }
1474
1475         /*
1476          * do hclk_reset, reset all vop registers.
1477          */
1478         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1479         if (IS_ERR(ahb_rst)) {
1480                 dev_err(vop->dev, "failed to get ahb reset\n");
1481                 ret = PTR_ERR(ahb_rst);
1482                 goto err_disable_aclk;
1483         }
1484         reset_control_assert(ahb_rst);
1485         usleep_range(10, 20);
1486         reset_control_deassert(ahb_rst);
1487
1488         memcpy(vop->regsbak, vop->regs, vop->len);
1489
1490         for (i = 0; i < vop_data->table_size; i++)
1491                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1492
1493         for (i = 0; i < vop->num_wins; i++) {
1494                 struct vop_win *win = &vop->win[i];
1495
1496                 VOP_WIN_SET(vop, win, enable, 0);
1497         }
1498
1499         vop_cfg_done(vop);
1500
1501         /*
1502          * do dclk_reset, let all config take affect.
1503          */
1504         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1505         if (IS_ERR(vop->dclk_rst)) {
1506                 dev_err(vop->dev, "failed to get dclk reset\n");
1507                 ret = PTR_ERR(vop->dclk_rst);
1508                 goto err_disable_aclk;
1509         }
1510         reset_control_assert(vop->dclk_rst);
1511         usleep_range(10, 20);
1512         reset_control_deassert(vop->dclk_rst);
1513
1514         clk_disable(vop->hclk);
1515         clk_disable(vop->aclk);
1516
1517         vop->is_enabled = false;
1518
1519         return 0;
1520
1521 err_disable_aclk:
1522         clk_disable_unprepare(vop->aclk);
1523 err_disable_hclk:
1524         clk_disable_unprepare(vop->hclk);
1525 err_unprepare_dclk:
1526         clk_unprepare(vop->dclk);
1527         return ret;
1528 }
1529
1530 /*
1531  * Initialize the vop->win array elements.
1532  */
1533 static int vop_win_init(struct vop *vop)
1534 {
1535         const struct vop_data *vop_data = vop->data;
1536         unsigned int i, j;
1537         unsigned int num_wins = 0;
1538         struct drm_property *prop;
1539
1540         for (i = 0; i < vop_data->win_size; i++) {
1541                 struct vop_win *vop_win = &vop->win[num_wins];
1542                 const struct vop_win_data *win_data = &vop_data->win[i];
1543
1544                 vop_win->phy = win_data->phy;
1545                 vop_win->offset = win_data->base;
1546                 vop_win->type = win_data->type;
1547                 vop_win->data_formats = win_data->phy->data_formats;
1548                 vop_win->nformats = win_data->phy->nformats;
1549                 vop_win->vop = vop;
1550                 vop_win->win_id = i;
1551                 vop_win->area_id = 0;
1552                 num_wins++;
1553
1554                 for (j = 0; j < win_data->area_size; j++) {
1555                         struct vop_win *vop_area = &vop->win[num_wins];
1556                         const struct vop_win_phy *area = win_data->area[j];
1557
1558                         vop_area->parent = vop_win;
1559                         vop_area->offset = vop_win->offset;
1560                         vop_area->phy = area;
1561                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1562                         vop_area->data_formats = vop_win->data_formats;
1563                         vop_area->nformats = vop_win->nformats;
1564                         vop_area->vop = vop;
1565                         vop_area->win_id = i;
1566                         vop_area->area_id = j;
1567                         num_wins++;
1568                 }
1569         }
1570         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1571                                          "ZPOS", 0, vop->data->win_size);
1572         if (!prop) {
1573                 DRM_ERROR("failed to create zpos property\n");
1574                 return -EINVAL;
1575         }
1576         vop->plane_zpos_prop = prop;
1577
1578         return 0;
1579 }
1580
1581 static int vop_bind(struct device *dev, struct device *master, void *data)
1582 {
1583         struct platform_device *pdev = to_platform_device(dev);
1584         const struct vop_data *vop_data;
1585         struct drm_device *drm_dev = data;
1586         struct vop *vop;
1587         struct resource *res;
1588         size_t alloc_size;
1589         int ret, irq, i;
1590         int num_wins = 0;
1591
1592         vop_data = of_device_get_match_data(dev);
1593         if (!vop_data)
1594                 return -ENODEV;
1595
1596         for (i = 0; i < vop_data->win_size; i++) {
1597                 const struct vop_win_data *win_data = &vop_data->win[i];
1598
1599                 num_wins += win_data->area_size + 1;
1600         }
1601
1602         /* Allocate vop struct and its vop_win array */
1603         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1604         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1605         if (!vop)
1606                 return -ENOMEM;
1607
1608         vop->dev = dev;
1609         vop->data = vop_data;
1610         vop->drm_dev = drm_dev;
1611         vop->num_wins = num_wins;
1612         dev_set_drvdata(dev, vop);
1613
1614         ret = vop_win_init(vop);
1615         if (ret)
1616                 return ret;
1617
1618         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1619         vop->len = resource_size(res);
1620         vop->regs = devm_ioremap_resource(dev, res);
1621         if (IS_ERR(vop->regs))
1622                 return PTR_ERR(vop->regs);
1623
1624         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1625         if (!vop->regsbak)
1626                 return -ENOMEM;
1627
1628         ret = vop_initial(vop);
1629         if (ret < 0) {
1630                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1631                 return ret;
1632         }
1633
1634         irq = platform_get_irq(pdev, 0);
1635         if (irq < 0) {
1636                 dev_err(dev, "cannot find irq for vop\n");
1637                 return irq;
1638         }
1639         vop->irq = (unsigned int)irq;
1640
1641         spin_lock_init(&vop->reg_lock);
1642         spin_lock_init(&vop->irq_lock);
1643
1644         mutex_init(&vop->vsync_mutex);
1645
1646         ret = devm_request_irq(dev, vop->irq, vop_isr,
1647                                IRQF_SHARED, dev_name(dev), vop);
1648         if (ret)
1649                 return ret;
1650
1651         /* IRQ is initially disabled; it gets enabled in power_on */
1652         disable_irq(vop->irq);
1653
1654         ret = vop_create_crtc(vop);
1655         if (ret)
1656                 return ret;
1657
1658         pm_runtime_enable(&pdev->dev);
1659         return 0;
1660 }
1661
1662 static void vop_unbind(struct device *dev, struct device *master, void *data)
1663 {
1664         struct vop *vop = dev_get_drvdata(dev);
1665
1666         pm_runtime_disable(dev);
1667         vop_destroy_crtc(vop);
1668 }
1669
1670 const struct component_ops vop_component_ops = {
1671         .bind = vop_bind,
1672         .unbind = vop_unbind,
1673 };
1674 EXPORT_SYMBOL_GPL(vop_component_ops);