drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  76                 REG_SET(x, name, win->offset, win->ext->name, v, true)
  77 #define VOP_SCL_SET(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  79 #define VOP_SCL_SET_EXT(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  81
  82 #define VOP_CTRL_SET(x, name, v) \
  83                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  84
  85 #define VOP_INTR_GET(vop, name) \
  86                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  87
  88 #define VOP_INTR_SET(vop, name, mask, v) \
  89                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  90                              mask, v, false)
  91
  92 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  93         do { \
  94                 int i, reg = 0, mask = 0; \
  95                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  96                         if (vop->data->intr->intrs[i] & type) { \
  97                                 reg |= (v) << i; \
  98                                 mask |= 1 << i; \
  99                         } \
 100                 } \
 101                 VOP_INTR_SET(vop, name, mask, reg); \
 102         } while (0)
 103 #define VOP_INTR_GET_TYPE(vop, name, type) \
 104                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 105
 106 #define VOP_CTRL_GET(x, name) \
 107                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 108
 109 #define VOP_WIN_GET(x, win, name) \
 110                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 111
 112 #define VOP_WIN_NAME(win, name) \
 113                 (vop_get_win_phy(win, &win->phy->name)->name)
 114
 115 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 116                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 117
 118 #define to_vop(x) container_of(x, struct vop, crtc)
 119 #define to_vop_win(x) container_of(x, struct vop_win, base)
 120 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 121
 122 struct vop_zpos {
 123         int win_id;
 124         int zpos;
 125 };
 126
 127 struct vop_plane_state {
 128         struct drm_plane_state base;
 129         int format;
 130         int zpos;
 131         struct drm_rect src;
 132         struct drm_rect dest;
 133         dma_addr_t yrgb_mst;
 134         dma_addr_t uv_mst;
 135         const uint32_t *y2r_table;
 136         const uint32_t *r2r_table;
 137         const uint32_t *r2y_table;
 138         bool enable;
 139 };
 140
 141 struct vop_win {
 142         struct vop_win *parent;
 143         struct drm_plane base;
 144
 145         int win_id;
 146         int area_id;
 147         uint32_t offset;
 148         enum drm_plane_type type;
 149         const struct vop_win_phy *phy;
 150         const struct vop_csc *csc;
 151         const uint32_t *data_formats;
 152         uint32_t nformats;
 153         struct vop *vop;
 154
 155         struct drm_property *rotation_prop;
 156         struct vop_plane_state state;
 157 };
 158
 159 struct vop {
 160         struct drm_crtc crtc;
 161         struct device *dev;
 162         struct drm_device *drm_dev;
 163         struct drm_property *plane_zpos_prop;
 164         struct drm_property *plane_feature_prop;
 165         struct drm_property *feature_prop;
 166         bool is_iommu_enabled;
 167         bool is_iommu_needed;
 168         bool is_enabled;
 169
 170         /* mutex vsync_ work */
 171         struct mutex vsync_mutex;
 172         bool vsync_work_pending;
 173         struct completion dsp_hold_completion;
 174         struct completion wait_update_complete;
 175         struct drm_pending_vblank_event *event;
 176
 177         const struct vop_data *data;
 178         int num_wins;
 179
 180         uint32_t *regsbak;
 181         void __iomem *regs;
 182
 183         /* physical map length of vop register */
 184         uint32_t len;
 185
 186         /* one time only one process allowed to config the register */
 187         spinlock_t reg_lock;
 188         /* lock vop irq reg */
 189         spinlock_t irq_lock;
 190
 191         unsigned int irq;
 192
 193         /* vop AHP clk */
 194         struct clk *hclk;
 195         /* vop dclk */
 196         struct clk *dclk;
 197         /* vop share memory frequency */
 198         struct clk *aclk;
 199
 200         /* vop dclk reset */
 201         struct reset_control *dclk_rst;
 202
 203         struct vop_win win[];
 204 };
 205
 206 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 207 {
 208         writel(v, vop->regs + offset);
 209         vop->regsbak[offset >> 2] = v;
 210 }
 211
 212 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 213 {
 214         return readl(vop->regs + offset);
 215 }
 216
 217 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 218                                     const struct vop_reg *reg)
 219 {
 220         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 221 }
 222
 223 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 224                                   uint32_t mask, uint32_t shift, uint32_t v,
 225                                   bool write_mask, bool relaxed)
 226 {
 227         if (!mask)
 228                 return;
 229
 230         if (write_mask) {
 231                 v = ((v & mask) << shift) | (mask << (shift + 16));
 232         } else {
 233                 uint32_t cached_val = vop->regsbak[offset >> 2];
 234
 235                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 236                 vop->regsbak[offset >> 2] = v;
 237         }
 238
 239         if (relaxed)
 240                 writel_relaxed(v, vop->regs + offset);
 241         else
 242                 writel(v, vop->regs + offset);
 243 }
 244
 245 static inline const struct vop_win_phy *
 246 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 247 {
 248         if (!reg->mask && win->parent)
 249                 return win->parent->phy;
 250
 251         return win->phy;
 252 }
 253
 254 static inline uint32_t vop_get_intr_type(struct vop *vop,
 255                                          const struct vop_reg *reg, int type)
 256 {
 257         uint32_t i, ret = 0;
 258         uint32_t regs = vop_read_reg(vop, 0, reg);
 259
 260         for (i = 0; i < vop->data->intr->nintrs; i++) {
 261                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 262                         ret |= vop->data->intr->intrs[i];
 263         }
 264
 265         return ret;
 266 }
 267
 268 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 269 {
 270         int i;
 271
 272         if (!table)
 273                 return;
 274
 275         for (i = 0; i < 8; i++)
 276                 vop_writel(vop, offset + i * 4, table[i]);
 277 }
 278
 279 static inline void vop_cfg_done(struct vop *vop)
 280 {
 281         VOP_CTRL_SET(vop, cfg_done, 1);
 282 }
 283
 284 static bool vop_is_allwin_disabled(struct vop *vop)
 285 {
 286         int i;
 287
 288         for (i = 0; i < vop->num_wins; i++) {
 289                 struct vop_win *win = &vop->win[i];
 290
 291                 if (VOP_WIN_GET(vop, win, enable) != 0)
 292                         return false;
 293         }
 294
 295         return true;
 296 }
 297
 298 static bool vop_is_cfg_done_complete(struct vop *vop)
 299 {
 300         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 301 }
 302
 303 static bool has_rb_swapped(uint32_t format)
 304 {
 305         switch (format) {
 306         case DRM_FORMAT_XBGR8888:
 307         case DRM_FORMAT_ABGR8888:
 308         case DRM_FORMAT_BGR888:
 309         case DRM_FORMAT_BGR565:
 310                 return true;
 311         default:
 312                 return false;
 313         }
 314 }
 315
 316 static enum vop_data_format vop_convert_format(uint32_t format)
 317 {
 318         switch (format) {
 319         case DRM_FORMAT_XRGB8888:
 320         case DRM_FORMAT_ARGB8888:
 321         case DRM_FORMAT_XBGR8888:
 322         case DRM_FORMAT_ABGR8888:
 323                 return VOP_FMT_ARGB8888;
 324         case DRM_FORMAT_RGB888:
 325         case DRM_FORMAT_BGR888:
 326                 return VOP_FMT_RGB888;
 327         case DRM_FORMAT_RGB565:
 328         case DRM_FORMAT_BGR565:
 329                 return VOP_FMT_RGB565;
 330         case DRM_FORMAT_NV12:
 331                 return VOP_FMT_YUV420SP;
 332         case DRM_FORMAT_NV16:
 333                 return VOP_FMT_YUV422SP;
 334         case DRM_FORMAT_NV24:
 335                 return VOP_FMT_YUV444SP;
 336         default:
 337                 DRM_ERROR("unsupport format[%08x]\n", format);
 338                 return -EINVAL;
 339         }
 340 }
 341
 342 static bool is_yuv_support(uint32_t format)
 343 {
 344         switch (format) {
 345         case DRM_FORMAT_NV12:
 346         case DRM_FORMAT_NV16:
 347         case DRM_FORMAT_NV24:
 348                 return true;
 349         default:
 350                 return false;
 351         }
 352 }
 353
 354 static bool is_alpha_support(uint32_t format)
 355 {
 356         switch (format) {
 357         case DRM_FORMAT_ARGB8888:
 358         case DRM_FORMAT_ABGR8888:
 359                 return true;
 360         default:
 361                 return false;
 362         }
 363 }
 364
 365 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 366                                   uint32_t dst, bool is_horizontal,
 367                                   int vsu_mode, int *vskiplines)
 368 {
 369         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 370
 371         if (is_horizontal) {
 372                 if (mode == SCALE_UP)
 373                         val = GET_SCL_FT_BIC(src, dst);
 374                 else if (mode == SCALE_DOWN)
 375                         val = GET_SCL_FT_BILI_DN(src, dst);
 376         } else {
 377                 if (mode == SCALE_UP) {
 378                         if (vsu_mode == SCALE_UP_BIL)
 379                                 val = GET_SCL_FT_BILI_UP(src, dst);
 380                         else
 381                                 val = GET_SCL_FT_BIC(src, dst);
 382                 } else if (mode == SCALE_DOWN) {
 383                         if (vskiplines) {
 384                                 *vskiplines = scl_get_vskiplines(src, dst);
 385                                 val = scl_get_bili_dn_vskip(src, dst,
 386                                                             *vskiplines);
 387                         } else {
 388                                 val = GET_SCL_FT_BILI_DN(src, dst);
 389                         }
 390                 }
 391         }
 392
 393         return val;
 394 }
 395
 396 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 397                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 398                                 uint32_t dst_h, uint32_t pixel_format)
 399 {
 400         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 401         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 402         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 403         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 404         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 405         bool is_yuv = is_yuv_support(pixel_format);
 406         uint16_t cbcr_src_w = src_w / hsub;
 407         uint16_t cbcr_src_h = src_h / vsub;
 408         uint16_t vsu_mode;
 409         uint16_t lb_mode;
 410         uint32_t val;
 411         int vskiplines = 0;
 412
 413         if (!win->phy->scl)
 414                 return;
 415
 416         if (dst_w > 3840) {
 417                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 418                 return;
 419         }
 420
 421         if (!win->phy->scl->ext) {
 422                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 423                             scl_cal_scale2(src_w, dst_w));
 424                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 425                             scl_cal_scale2(src_h, dst_h));
 426                 if (is_yuv) {
 427                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 428                                     scl_cal_scale2(cbcr_src_w, dst_w));
 429                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 430                                     scl_cal_scale2(cbcr_src_h, dst_h));
 431                 }
 432                 return;
 433         }
 434
 435         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 436         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 437
 438         if (is_yuv) {
 439                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 440                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 441                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 442                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 443                 else
 444                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 445         } else {
 446                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 447                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 448                 else
 449                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 450         }
 451
 452         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 453         if (lb_mode == LB_RGB_3840X2) {
 454                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 455                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 456                         return;
 457                 }
 458                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 459                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 460                         return;
 461                 }
 462                 vsu_mode = SCALE_UP_BIL;
 463         } else if (lb_mode == LB_RGB_2560X4) {
 464                 vsu_mode = SCALE_UP_BIL;
 465         } else {
 466                 vsu_mode = SCALE_UP_BIC;
 467         }
 468
 469         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 470                                 true, 0, NULL);
 471         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 472         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 473                                 false, vsu_mode, &vskiplines);
 474         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 475
 476         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 477         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 478
 479         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 480         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 481         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 482         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 483         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 484         if (is_yuv) {
 485                 vskiplines = 0;
 486
 487                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 488                                         dst_w, true, 0, NULL);
 489                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 490                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 491                                         dst_h, false, vsu_mode, &vskiplines);
 492                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 493
 494                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 495                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 496                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 497                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 498                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 499                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 500                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 501         }
 502 }
 503
 504 /*
 505  * rk3399 colorspace path:
 506  *      Input        Win csc                     Output
 507  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 508  *    RGB        --> R2Y                  __/
 509  *
 510  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 511  *    RGB        --> 709To2020->R2Y       __/
 512  *
 513  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 514  *    RGB        --> R2Y                  __/
 515  *
 516  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 517  *    RGB        --> 709To2020->R2Y       __/
 518  *
 519  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 520  *    RGB        --> R2Y                  __/
 521  *
 522  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 523  *    RGB        --> R2Y(601)             __/
 524  *
 525  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 526  *    RGB        --> bypass               __/
 527  *
 528  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 529  *
 530  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 531  *
 532  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 533  *
 534  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 535  */
 536 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 537                          bool is_input_yuv, bool is_output_yuv,
 538                          int input_csc, int output_csc,
 539                          const uint32_t **y2r_table,
 540                          const uint32_t **r2r_table,
 541                          const uint32_t **r2y_table)
 542 {
 543         *y2r_table = NULL;
 544         *r2r_table = NULL;
 545         *r2y_table = NULL;
 546
 547         if (is_output_yuv) {
 548                 if (output_csc == CSC_BT2020) {
 549                         if (is_input_yuv) {
 550                                 if (input_csc == CSC_BT2020)
 551                                         return 0;
 552                                 *y2r_table = csc_table->y2r_bt709;
 553                         }
 554                         if (input_csc != CSC_BT2020)
 555                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 556                         *r2y_table = csc_table->r2y_bt2020;
 557                 } else {
 558                         if (is_input_yuv && input_csc == CSC_BT2020)
 559                                 *y2r_table = csc_table->y2r_bt2020;
 560                         if (input_csc == CSC_BT2020)
 561                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 562                         if (!is_input_yuv || y2r_table) {
 563                                 if (output_csc == CSC_BT709)
 564                                         *r2y_table = csc_table->r2y_bt709;
 565                                 else
 566                                         *r2y_table = csc_table->r2y_bt601;
 567                         }
 568                 }
 569
 570         } else {
 571                 if (!is_input_yuv)
 572                         return 0;
 573
 574                 /*
 575                  * is possible use bt2020 on rgb mode?
 576                  */
 577                 if (WARN_ON(output_csc == CSC_BT2020))
 578                         return -EINVAL;
 579
 580                 if (input_csc == CSC_BT2020)
 581                         *y2r_table = csc_table->y2r_bt2020;
 582                 else if (input_csc == CSC_BT709)
 583                         *y2r_table = csc_table->y2r_bt709;
 584                 else
 585                         *y2r_table = csc_table->y2r_bt601;
 586
 587                 if (input_csc == CSC_BT2020)
 588                         /*
 589                          * We don't have bt601 to bt709 table, force use bt709.
 590                          */
 591                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 592         }
 593
 594         return 0;
 595 }
 596
 597 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 598                                 struct drm_crtc_state *crtc_state)
 599 {
 600         struct vop *vop = to_vop(crtc);
 601         struct drm_atomic_state *state = crtc_state->state;
 602         const struct vop_csc_table *csc_table = vop->data->csc_table;
 603         struct drm_plane_state *pstate;
 604         struct drm_plane *plane;
 605         bool is_yuv;
 606         int ret;
 607
 608         if (!csc_table)
 609                 return 0;
 610
 611         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 612                 struct vop_plane_state *vop_plane_state;
 613
 614                 pstate = drm_atomic_get_plane_state(state, plane);
 615                 if (IS_ERR(pstate))
 616                         return PTR_ERR(pstate);
 617                 vop_plane_state = to_vop_plane_state(pstate);
 618
 619                 if (!pstate->fb)
 620                         continue;
 621                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 622
 623                 /*
 624                  * TODO: force set input and output csc mode.
 625                  */
 626                 ret = vop_csc_setup(csc_table, is_yuv, false,
 627                                     CSC_BT709, CSC_BT709,
 628                                     &vop_plane_state->y2r_table,
 629                                     &vop_plane_state->r2r_table,
 630                                     &vop_plane_state->r2y_table);
 631                 if (ret)
 632                         return ret;
 633         }
 634
 635         return 0;
 636 }
 637
 638 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 639 {
 640         unsigned long flags;
 641
 642         spin_lock_irqsave(&vop->irq_lock, flags);
 643
 644         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 645
 646         spin_unlock_irqrestore(&vop->irq_lock, flags);
 647 }
 648
 649 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 650 {
 651         unsigned long flags;
 652
 653         spin_lock_irqsave(&vop->irq_lock, flags);
 654
 655         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 656
 657         spin_unlock_irqrestore(&vop->irq_lock, flags);
 658 }
 659
 660 static void vop_enable(struct drm_crtc *crtc)
 661 {
 662         struct vop *vop = to_vop(crtc);
 663         int ret, i;
 664
 665         ret = clk_prepare_enable(vop->hclk);
 666         if (ret < 0) {
 667                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 668                 return;
 669         }
 670
 671         ret = clk_prepare_enable(vop->dclk);
 672         if (ret < 0) {
 673                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 674                 goto err_disable_hclk;
 675         }
 676
 677         ret = clk_prepare_enable(vop->aclk);
 678         if (ret < 0) {
 679                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 680                 goto err_disable_dclk;
 681         }
 682
 683         ret = pm_runtime_get_sync(vop->dev);
 684         if (ret < 0) {
 685                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 686                 return;
 687         }
 688
 689         memcpy(vop->regsbak, vop->regs, vop->len);
 690
 691         VOP_CTRL_SET(vop, global_regdone_en, 1);
 692         VOP_CTRL_SET(vop, dsp_blank, 0);
 693
 694         for (i = 0; i < vop->num_wins; i++) {
 695                 struct vop_win *win = &vop->win[i];
 696
 697                 VOP_WIN_SET(vop, win, gate, 1);
 698         }
 699         vop->is_enabled = true;
 700
 701         spin_lock(&vop->reg_lock);
 702
 703         VOP_CTRL_SET(vop, standby, 0);
 704
 705         spin_unlock(&vop->reg_lock);
 706
 707         enable_irq(vop->irq);
 708
 709         drm_crtc_vblank_on(crtc);
 710
 711         return;
 712
 713 err_disable_dclk:
 714         clk_disable_unprepare(vop->dclk);
 715 err_disable_hclk:
 716         clk_disable_unprepare(vop->hclk);
 717 }
 718
 719 static void vop_crtc_disable(struct drm_crtc *crtc)
 720 {
 721         struct vop *vop = to_vop(crtc);
 722         int i;
 723
 724         /*
 725          * We need to make sure that all windows are disabled before we
 726          * disable that crtc. Otherwise we might try to scan from a destroyed
 727          * buffer later.
 728          */
 729         for (i = 0; i < vop->num_wins; i++) {
 730                 struct vop_win *win = &vop->win[i];
 731
 732                 spin_lock(&vop->reg_lock);
 733                 VOP_WIN_SET(vop, win, enable, 0);
 734                 spin_unlock(&vop->reg_lock);
 735         }
 736         VOP_CTRL_SET(vop, afbdc_en, 0);
 737         vop_cfg_done(vop);
 738
 739         drm_crtc_vblank_off(crtc);
 740
 741         /*
 742          * Vop standby will take effect at end of current frame,
 743          * if dsp hold valid irq happen, it means standby complete.
 744          *
 745          * we must wait standby complete when we want to disable aclk,
 746          * if not, memory bus maybe dead.
 747          */
 748         reinit_completion(&vop->dsp_hold_completion);
 749         vop_dsp_hold_valid_irq_enable(vop);
 750
 751         spin_lock(&vop->reg_lock);
 752
 753         VOP_CTRL_SET(vop, standby, 1);
 754
 755         spin_unlock(&vop->reg_lock);
 756
 757         wait_for_completion(&vop->dsp_hold_completion);
 758
 759         vop_dsp_hold_valid_irq_disable(vop);
 760
 761         disable_irq(vop->irq);
 762
 763         vop->is_enabled = false;
 764         if (vop->is_iommu_enabled) {
 765                 /*
 766                  * vop standby complete, so iommu detach is safe.
 767                  */
 768                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 769                 vop->is_iommu_enabled = false;
 770         }
 771
 772         pm_runtime_put(vop->dev);
 773         clk_disable_unprepare(vop->dclk);
 774         clk_disable_unprepare(vop->aclk);
 775         clk_disable_unprepare(vop->hclk);
 776 }
 777
 778 static void vop_plane_destroy(struct drm_plane *plane)
 779 {
 780         drm_plane_cleanup(plane);
 781 }
 782
 783 static int vop_plane_prepare_fb(struct drm_plane *plane,
 784                                 const struct drm_plane_state *new_state)
 785 {
 786         if (plane->state->fb)
 787                 drm_framebuffer_reference(plane->state->fb);
 788
 789         return 0;
 790 }
 791
 792 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 793                                  const struct drm_plane_state *old_state)
 794 {
 795         if (old_state->fb)
 796                 drm_framebuffer_unreference(old_state->fb);
 797 }
 798
 799 static int vop_plane_atomic_check(struct drm_plane *plane,
 800                            struct drm_plane_state *state)
 801 {
 802         struct drm_crtc *crtc = state->crtc;
 803         struct drm_framebuffer *fb = state->fb;
 804         struct vop_win *win = to_vop_win(plane);
 805         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 806         struct drm_crtc_state *crtc_state;
 807         bool visible;
 808         int ret;
 809         struct drm_rect *dest = &vop_plane_state->dest;
 810         struct drm_rect *src = &vop_plane_state->src;
 811         struct drm_rect clip;
 812         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 813                                         DRM_PLANE_HELPER_NO_SCALING;
 814         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 815                                         DRM_PLANE_HELPER_NO_SCALING;
 816         unsigned long offset;
 817         dma_addr_t dma_addr;
 818
 819         crtc = crtc ? crtc : plane->state->crtc;
 820         /*
 821          * Both crtc or plane->state->crtc can be null.
 822          */
 823         if (!crtc || !fb)
 824                 goto out_disable;
 825
 826         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 827         if (IS_ERR(crtc_state))
 828                 return PTR_ERR(crtc_state);
 829
 830         src->x1 = state->src_x;
 831         src->y1 = state->src_y;
 832         src->x2 = state->src_x + state->src_w;
 833         src->y2 = state->src_y + state->src_h;
 834         dest->x1 = state->crtc_x;
 835         dest->y1 = state->crtc_y;
 836         dest->x2 = state->crtc_x + state->crtc_w;
 837         dest->y2 = state->crtc_y + state->crtc_h;
 838
 839         clip.x1 = 0;
 840         clip.y1 = 0;
 841         clip.x2 = crtc_state->mode.hdisplay;
 842         clip.y2 = crtc_state->mode.vdisplay;
 843
 844         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 845                                             src, dest, &clip,
 846                                             min_scale,
 847                                             max_scale,
 848                                             true, true, &visible);
 849         if (ret)
 850                 return ret;
 851
 852         if (!visible)
 853                 goto out_disable;
 854
 855         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 856         if (vop_plane_state->format < 0)
 857                 return vop_plane_state->format;
 858
 859         /*
 860          * Src.x1 can be odd when do clip, but yuv plane start point
 861          * need align with 2 pixel.
 862          */
 863         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 864                 return -EINVAL;
 865
 866         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 867         if (state->rotation & BIT(DRM_REFLECT_Y))
 868                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 869         else
 870                 offset += (src->y1 >> 16) * fb->pitches[0];
 871
 872         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 873         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 874         if (is_yuv_support(fb->pixel_format)) {
 875                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 876                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 877                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 878
 879                 offset = (src->x1 >> 16) * bpp / hsub;
 880                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 881
 882                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 883                 dma_addr += offset + fb->offsets[1];
 884                 vop_plane_state->uv_mst = dma_addr;
 885         }
 886
 887         vop_plane_state->enable = true;
 888
 889         return 0;
 890
 891 out_disable:
 892         vop_plane_state->enable = false;
 893         return 0;
 894 }
 895
 896 static void vop_plane_atomic_disable(struct drm_plane *plane,
 897                                      struct drm_plane_state *old_state)
 898 {
 899         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 900         struct vop_win *win = to_vop_win(plane);
 901         struct vop *vop = to_vop(old_state->crtc);
 902
 903         if (!old_state->crtc)
 904                 return;
 905
 906         spin_lock(&vop->reg_lock);
 907
 908         VOP_WIN_SET(vop, win, enable, 0);
 909
 910         spin_unlock(&vop->reg_lock);
 911
 912         vop_plane_state->enable = false;
 913 }
 914
 915 static void vop_plane_atomic_update(struct drm_plane *plane,
 916                 struct drm_plane_state *old_state)
 917 {
 918         struct drm_plane_state *state = plane->state;
 919         struct drm_crtc *crtc = state->crtc;
 920         struct vop_win *win = to_vop_win(plane);
 921         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 922         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 923         struct vop *vop = to_vop(state->crtc);
 924         struct drm_framebuffer *fb = state->fb;
 925         unsigned int actual_w, actual_h;
 926         unsigned int dsp_stx, dsp_sty;
 927         uint32_t act_info, dsp_info, dsp_st;
 928         struct drm_rect *src = &vop_plane_state->src;
 929         struct drm_rect *dest = &vop_plane_state->dest;
 930         const uint32_t *y2r_table = vop_plane_state->y2r_table;
 931         const uint32_t *r2r_table = vop_plane_state->r2r_table;
 932         const uint32_t *r2y_table = vop_plane_state->r2y_table;
 933         int ymirror, xmirror;
 934         uint32_t val;
 935         bool rb_swap;
 936
 937         /*
 938          * can't update plane when vop is disabled.
 939          */
 940         if (!crtc)
 941                 return;
 942
 943         if (!vop_plane_state->enable) {
 944                 vop_plane_atomic_disable(plane, old_state);
 945                 return;
 946         }
 947
 948         actual_w = drm_rect_width(src) >> 16;
 949         actual_h = drm_rect_height(src) >> 16;
 950         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 951
 952         dsp_info = (drm_rect_height(dest) - 1) << 16;
 953         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 954
 955         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 956         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 957         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 958
 959         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 960         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 961
 962         spin_lock(&vop->reg_lock);
 963
 964         VOP_WIN_SET(vop, win, xmirror, xmirror);
 965         VOP_WIN_SET(vop, win, ymirror, ymirror);
 966         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 967         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 968         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 969         if (is_yuv_support(fb->pixel_format)) {
 970                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 971                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
 972         }
 973
 974         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 975                             drm_rect_width(dest), drm_rect_height(dest),
 976                             fb->pixel_format);
 977
 978         VOP_WIN_SET(vop, win, act_info, act_info);
 979         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 980         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 981
 982         rb_swap = has_rb_swapped(fb->pixel_format);
 983         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 984
 985         if (is_alpha_support(fb->pixel_format) &&
 986             (s->dsp_layer_sel & 0x3) != win->win_id) {
 987                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 988                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 989                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 990                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 991                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 992                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 993                         SRC_FACTOR_M0(ALPHA_ONE);
 994                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 995                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 996                 VOP_WIN_SET(vop, win, alpha_en, 1);
 997         } else {
 998                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 999                 VOP_WIN_SET(vop, win, alpha_en, 0);
1000         }
1001
1002         if (win->csc) {
1003                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1004                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1005                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1006                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1007                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1008                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1009         }
1010         VOP_WIN_SET(vop, win, enable, 1);
1011         spin_unlock(&vop->reg_lock);
1012         vop->is_iommu_needed = true;
1013 }
1014
1015 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1016         .prepare_fb = vop_plane_prepare_fb,
1017         .cleanup_fb = vop_plane_cleanup_fb,
1018         .atomic_check = vop_plane_atomic_check,
1019         .atomic_update = vop_plane_atomic_update,
1020         .atomic_disable = vop_plane_atomic_disable,
1021 };
1022
1023 void vop_atomic_plane_reset(struct drm_plane *plane)
1024 {
1025         struct vop_win *win = to_vop_win(plane);
1026         struct vop_plane_state *vop_plane_state =
1027                                         to_vop_plane_state(plane->state);
1028
1029         if (plane->state && plane->state->fb)
1030                 drm_framebuffer_unreference(plane->state->fb);
1031
1032         kfree(vop_plane_state);
1033         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1034         if (!vop_plane_state)
1035                 return;
1036
1037         vop_plane_state->zpos = win->win_id;
1038         plane->state = &vop_plane_state->base;
1039         plane->state->plane = plane;
1040 }
1041
1042 struct drm_plane_state *
1043 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1044 {
1045         struct vop_plane_state *old_vop_plane_state;
1046         struct vop_plane_state *vop_plane_state;
1047
1048         if (WARN_ON(!plane->state))
1049                 return NULL;
1050
1051         old_vop_plane_state = to_vop_plane_state(plane->state);
1052         vop_plane_state = kmemdup(old_vop_plane_state,
1053                                   sizeof(*vop_plane_state), GFP_KERNEL);
1054         if (!vop_plane_state)
1055                 return NULL;
1056
1057         __drm_atomic_helper_plane_duplicate_state(plane,
1058                                                   &vop_plane_state->base);
1059
1060         return &vop_plane_state->base;
1061 }
1062
1063 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1064                                            struct drm_plane_state *state)
1065 {
1066         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1067
1068         __drm_atomic_helper_plane_destroy_state(plane, state);
1069
1070         kfree(vop_state);
1071 }
1072
1073 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1074                                          struct drm_plane_state *state,
1075                                          struct drm_property *property,
1076                                          uint64_t val)
1077 {
1078         struct vop_win *win = to_vop_win(plane);
1079         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1080
1081         if (property == win->vop->plane_zpos_prop) {
1082                 plane_state->zpos = val;
1083                 return 0;
1084         }
1085
1086         if (property == win->rotation_prop) {
1087                 state->rotation = val;
1088                 return 0;
1089         }
1090
1091         DRM_ERROR("failed to set vop plane property\n");
1092         return -EINVAL;
1093 }
1094
1095 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1096                                          const struct drm_plane_state *state,
1097                                          struct drm_property *property,
1098                                          uint64_t *val)
1099 {
1100         struct vop_win *win = to_vop_win(plane);
1101         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1102
1103         if (property == win->vop->plane_zpos_prop) {
1104                 *val = plane_state->zpos;
1105                 return 0;
1106         }
1107
1108         if (property == win->rotation_prop) {
1109                 *val = state->rotation;
1110                 return 0;
1111         }
1112
1113         DRM_ERROR("failed to get vop plane property\n");
1114         return -EINVAL;
1115 }
1116
1117 static const struct drm_plane_funcs vop_plane_funcs = {
1118         .update_plane   = drm_atomic_helper_update_plane,
1119         .disable_plane  = drm_atomic_helper_disable_plane,
1120         .destroy = vop_plane_destroy,
1121         .reset = vop_atomic_plane_reset,
1122         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1123         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1124         .atomic_set_property = vop_atomic_plane_set_property,
1125         .atomic_get_property = vop_atomic_plane_get_property,
1126 };
1127
1128 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1129 {
1130         struct vop *vop = to_vop(crtc);
1131         unsigned long flags;
1132
1133         if (!vop->is_enabled)
1134                 return -EPERM;
1135
1136         spin_lock_irqsave(&vop->irq_lock, flags);
1137
1138         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1139
1140         spin_unlock_irqrestore(&vop->irq_lock, flags);
1141
1142         return 0;
1143 }
1144
1145 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1146 {
1147         struct vop *vop = to_vop(crtc);
1148         unsigned long flags;
1149
1150         if (!vop->is_enabled)
1151                 return;
1152
1153         spin_lock_irqsave(&vop->irq_lock, flags);
1154
1155         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1156
1157         spin_unlock_irqrestore(&vop->irq_lock, flags);
1158 }
1159
1160 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1161 {
1162         struct vop *vop = to_vop(crtc);
1163
1164         reinit_completion(&vop->wait_update_complete);
1165         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1166 }
1167
1168 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1169                                            struct drm_file *file_priv)
1170 {
1171         struct drm_device *drm = crtc->dev;
1172         struct vop *vop = to_vop(crtc);
1173         struct drm_pending_vblank_event *e;
1174         unsigned long flags;
1175
1176         spin_lock_irqsave(&drm->event_lock, flags);
1177         e = vop->event;
1178         if (e && e->base.file_priv == file_priv) {
1179                 vop->event = NULL;
1180
1181                 e->base.destroy(&e->base);
1182                 file_priv->event_space += sizeof(e->event);
1183         }
1184         spin_unlock_irqrestore(&drm->event_lock, flags);
1185 }
1186
1187 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1188         .enable_vblank = vop_crtc_enable_vblank,
1189         .disable_vblank = vop_crtc_disable_vblank,
1190         .wait_for_update = vop_crtc_wait_for_update,
1191         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1192 };
1193
1194 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1195                                 const struct drm_display_mode *mode,
1196                                 struct drm_display_mode *adjusted_mode)
1197 {
1198         struct vop *vop = to_vop(crtc);
1199
1200         adjusted_mode->clock =
1201                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1202
1203         return true;
1204 }
1205
1206 static void vop_crtc_enable(struct drm_crtc *crtc)
1207 {
1208         struct vop *vop = to_vop(crtc);
1209         const struct vop_data *vop_data = vop->data;
1210         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1211         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1212         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1213         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1214         u16 htotal = adjusted_mode->crtc_htotal;
1215         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1216         u16 hact_end = hact_st + hdisplay;
1217         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1218         u16 vtotal = adjusted_mode->crtc_vtotal;
1219         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1220         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1221         u16 vact_end = vact_st + vdisplay;
1222         uint32_t val;
1223
1224         vop_enable(crtc);
1225         /*
1226          * If dclk rate is zero, mean that scanout is stop,
1227          * we don't need wait any more.
1228          */
1229         if (clk_get_rate(vop->dclk)) {
1230                 /*
1231                  * Rk3288 vop timing register is immediately, when configure
1232                  * display timing on display time, may cause tearing.
1233                  *
1234                  * Vop standby will take effect at end of current frame,
1235                  * if dsp hold valid irq happen, it means standby complete.
1236                  *
1237                  * mode set:
1238                  *    standby and wait complete --> |----
1239                  *                                  | display time
1240                  *                                  |----
1241                  *                                  |---> dsp hold irq
1242                  *     configure display timing --> |
1243                  *         standby exit             |
1244                  *                                  | new frame start.
1245                  */
1246
1247                 reinit_completion(&vop->dsp_hold_completion);
1248                 vop_dsp_hold_valid_irq_enable(vop);
1249
1250                 spin_lock(&vop->reg_lock);
1251
1252                 VOP_CTRL_SET(vop, standby, 1);
1253
1254                 spin_unlock(&vop->reg_lock);
1255
1256                 wait_for_completion(&vop->dsp_hold_completion);
1257
1258                 vop_dsp_hold_valid_irq_disable(vop);
1259         }
1260
1261         val = 0x8;
1262         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1263         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1264         VOP_CTRL_SET(vop, pin_pol, val);
1265         switch (s->output_type) {
1266         case DRM_MODE_CONNECTOR_LVDS:
1267                 VOP_CTRL_SET(vop, rgb_en, 1);
1268                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1269                 break;
1270         case DRM_MODE_CONNECTOR_eDP:
1271                 VOP_CTRL_SET(vop, edp_en, 1);
1272                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1273                 break;
1274         case DRM_MODE_CONNECTOR_HDMIA:
1275                 VOP_CTRL_SET(vop, hdmi_en, 1);
1276                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1277                 break;
1278         case DRM_MODE_CONNECTOR_DSI:
1279                 VOP_CTRL_SET(vop, mipi_en, 1);
1280                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1281                 break;
1282         default:
1283                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1284         }
1285
1286         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1287             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1288                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1289
1290         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1291
1292         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1293         val = hact_st << 16;
1294         val |= hact_end;
1295         VOP_CTRL_SET(vop, hact_st_end, val);
1296         VOP_CTRL_SET(vop, hpost_st_end, val);
1297
1298         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1299         val = vact_st << 16;
1300         val |= vact_end;
1301         VOP_CTRL_SET(vop, vact_st_end, val);
1302         VOP_CTRL_SET(vop, vpost_st_end, val);
1303         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1304                 u16 vact_st_f1 = vtotal + vact_st + 1;
1305                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1306
1307                 val = vact_st_f1 << 16 | vact_end_f1;
1308                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1309                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1310
1311                 val = vtotal << 16 | (vtotal + vsync_len);
1312                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1313                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1314                 VOP_CTRL_SET(vop, p2i_en, 1);
1315         } else {
1316                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1317                 VOP_CTRL_SET(vop, p2i_en, 0);
1318         }
1319
1320         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1321
1322         VOP_CTRL_SET(vop, standby, 0);
1323 }
1324
1325 static int vop_zpos_cmp(const void *a, const void *b)
1326 {
1327         struct vop_zpos *pa = (struct vop_zpos *)a;
1328         struct vop_zpos *pb = (struct vop_zpos *)b;
1329
1330         return pa->zpos - pb->zpos;
1331 }
1332
1333 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1334                                   struct drm_crtc_state *crtc_state)
1335 {
1336         struct vop *vop = to_vop(crtc);
1337         const struct vop_data *vop_data = vop->data;
1338         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1339         struct drm_atomic_state *state = crtc_state->state;
1340         struct drm_plane *plane;
1341         struct drm_plane_state *pstate;
1342         struct vop_plane_state *plane_state;
1343         struct vop_win *win;
1344         int afbdc_format;
1345         int i;
1346
1347         s->afbdc_en = 0;
1348
1349         for_each_plane_in_state(state, plane, pstate, i) {
1350                 struct drm_framebuffer *fb = pstate->fb;
1351                 struct drm_rect *src;
1352
1353                 win = to_vop_win(plane);
1354                 plane_state = to_vop_plane_state(pstate);
1355
1356                 if (pstate->crtc != crtc || !fb)
1357                         continue;
1358
1359                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1360                         continue;
1361
1362                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1363                         DRM_ERROR("not support afbdc\n");
1364                         return -EINVAL;
1365                 }
1366
1367                 switch (plane_state->format) {
1368                 case VOP_FMT_ARGB8888:
1369                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1370                         break;
1371                 case VOP_FMT_RGB888:
1372                         afbdc_format = AFBDC_FMT_U8U8U8;
1373                         break;
1374                 case VOP_FMT_RGB565:
1375                         afbdc_format = AFBDC_FMT_RGB565;
1376                         break;
1377                 default:
1378                         return -EINVAL;
1379                 }
1380
1381                 if (s->afbdc_en) {
1382                         DRM_ERROR("vop only support one afbc layer\n");
1383                         return -EINVAL;
1384                 }
1385
1386                 src = &plane_state->src;
1387                 if (src->x1 || src->y1 || fb->offsets[0]) {
1388                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1389                                   win->win_id);
1390                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1391                                   src->x1, src->y1, fb->offsets[0]);
1392                         return -EINVAL;
1393                 }
1394                 s->afbdc_win_format = afbdc_format;
1395                 s->afbdc_win_width = pstate->fb->width - 1;
1396                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1397                 s->afbdc_win_id = win->win_id;
1398                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1399                 s->afbdc_en = 1;
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1406                                  struct drm_crtc_state *crtc_state)
1407 {
1408         struct drm_atomic_state *state = crtc_state->state;
1409         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1410         struct vop *vop = to_vop(crtc);
1411         const struct vop_data *vop_data = vop->data;
1412         struct drm_plane *plane;
1413         struct drm_plane_state *pstate;
1414         struct vop_plane_state *plane_state;
1415         struct vop_zpos *pzpos;
1416         int dsp_layer_sel = 0;
1417         int i, j, cnt = 0, ret = 0;
1418
1419         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1420         if (ret)
1421                 return ret;
1422
1423         ret = vop_csc_atomic_check(crtc, crtc_state);
1424         if (ret)
1425                 return ret;
1426
1427         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1428         if (!pzpos)
1429                 return -ENOMEM;
1430
1431         for (i = 0; i < vop_data->win_size; i++) {
1432                 const struct vop_win_data *win_data = &vop_data->win[i];
1433                 struct vop_win *win;
1434
1435                 if (!win_data->phy)
1436                         continue;
1437
1438                 for (j = 0; j < vop->num_wins; j++) {
1439                         win = &vop->win[j];
1440
1441                         if (win->win_id == i && !win->area_id)
1442                                 break;
1443                 }
1444                 if (WARN_ON(j >= vop->num_wins)) {
1445                         ret = -EINVAL;
1446                         goto err_free_pzpos;
1447                 }
1448
1449                 plane = &win->base;
1450                 pstate = state->plane_states[drm_plane_index(plane)];
1451                 /*
1452                  * plane might not have changed, in which case take
1453                  * current state:
1454                  */
1455                 if (!pstate)
1456                         pstate = plane->state;
1457                 plane_state = to_vop_plane_state(pstate);
1458                 pzpos[cnt].zpos = plane_state->zpos;
1459                 pzpos[cnt++].win_id = win->win_id;
1460         }
1461
1462         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1463
1464         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1465                 const struct vop_win_data *win_data = &vop_data->win[i];
1466                 int shift = i * 2;
1467
1468                 if (win_data->phy) {
1469                         struct vop_zpos *zpos = &pzpos[cnt++];
1470
1471                         dsp_layer_sel |= zpos->win_id << shift;
1472                 } else {
1473                         dsp_layer_sel |= i << shift;
1474                 }
1475         }
1476
1477         s->dsp_layer_sel = dsp_layer_sel;
1478
1479 err_free_pzpos:
1480         kfree(pzpos);
1481         return ret;
1482 }
1483
1484 static void vop_cfg_update(struct drm_crtc *crtc,
1485                            struct drm_crtc_state *old_crtc_state)
1486 {
1487         struct rockchip_crtc_state *s =
1488                         to_rockchip_crtc_state(crtc->state);
1489         struct vop *vop = to_vop(crtc);
1490
1491         spin_lock(&vop->reg_lock);
1492
1493         if (s->afbdc_en) {
1494                 uint32_t pic_size;
1495
1496                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1497                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1498                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1499                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1500                 pic_size = (s->afbdc_win_width & 0xffff);
1501                 pic_size |= s->afbdc_win_height << 16;
1502                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1503         }
1504
1505         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1506         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1507         vop_cfg_done(vop);
1508
1509         spin_unlock(&vop->reg_lock);
1510 }
1511
1512 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1513                                   struct drm_crtc_state *old_crtc_state)
1514 {
1515         struct vop *vop = to_vop(crtc);
1516
1517         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1518                 int ret;
1519                 if (!vop_is_allwin_disabled(vop)) {
1520                         vop_cfg_update(crtc, old_crtc_state);
1521                         while(!vop_is_cfg_done_complete(vop));
1522                 }
1523                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1524                 if (ret) {
1525                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1526                 }
1527                 vop->is_iommu_enabled = true;
1528         }
1529
1530         vop_cfg_update(crtc, old_crtc_state);
1531 }
1532
1533 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1534                                   struct drm_crtc_state *old_crtc_state)
1535 {
1536         struct vop *vop = to_vop(crtc);
1537
1538         if (crtc->state->event) {
1539                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1540
1541                 vop->event = crtc->state->event;
1542                 crtc->state->event = NULL;
1543         }
1544 }
1545
1546 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1547         .enable = vop_crtc_enable,
1548         .disable = vop_crtc_disable,
1549         .mode_fixup = vop_crtc_mode_fixup,
1550         .atomic_check = vop_crtc_atomic_check,
1551         .atomic_flush = vop_crtc_atomic_flush,
1552         .atomic_begin = vop_crtc_atomic_begin,
1553 };
1554
1555 static void vop_crtc_destroy(struct drm_crtc *crtc)
1556 {
1557         drm_crtc_cleanup(crtc);
1558 }
1559
1560 static void vop_crtc_reset(struct drm_crtc *crtc)
1561 {
1562         if (crtc->state)
1563                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1564         kfree(crtc->state);
1565
1566         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1567         if (crtc->state)
1568                 crtc->state->crtc = crtc;
1569 }
1570
1571 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1572 {
1573         struct rockchip_crtc_state *rockchip_state;
1574
1575         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1576         if (!rockchip_state)
1577                 return NULL;
1578
1579         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1580         return &rockchip_state->base;
1581 }
1582
1583 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1584                                    struct drm_crtc_state *state)
1585 {
1586         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1587
1588         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1589         kfree(s);
1590 }
1591
1592 static const struct drm_crtc_funcs vop_crtc_funcs = {
1593         .set_config = drm_atomic_helper_set_config,
1594         .page_flip = drm_atomic_helper_page_flip,
1595         .destroy = vop_crtc_destroy,
1596         .reset = vop_crtc_reset,
1597         .atomic_duplicate_state = vop_crtc_duplicate_state,
1598         .atomic_destroy_state = vop_crtc_destroy_state,
1599 };
1600
1601 static void vop_handle_vblank(struct vop *vop)
1602 {
1603         struct drm_device *drm = vop->drm_dev;
1604         struct drm_crtc *crtc = &vop->crtc;
1605         unsigned long flags;
1606
1607         if (!vop_is_cfg_done_complete(vop))
1608                 return;
1609
1610         if (vop->event) {
1611                 spin_lock_irqsave(&drm->event_lock, flags);
1612
1613                 drm_crtc_send_vblank_event(crtc, vop->event);
1614                 drm_crtc_vblank_put(crtc);
1615                 vop->event = NULL;
1616
1617                 spin_unlock_irqrestore(&drm->event_lock, flags);
1618         }
1619         if (!completion_done(&vop->wait_update_complete))
1620                 complete(&vop->wait_update_complete);
1621 }
1622
1623 static irqreturn_t vop_isr(int irq, void *data)
1624 {
1625         struct vop *vop = data;
1626         struct drm_crtc *crtc = &vop->crtc;
1627         uint32_t active_irqs;
1628         unsigned long flags;
1629         int ret = IRQ_NONE;
1630
1631         /*
1632          * interrupt register has interrupt status, enable and clear bits, we
1633          * must hold irq_lock to avoid a race with enable/disable_vblank().
1634         */
1635         spin_lock_irqsave(&vop->irq_lock, flags);
1636
1637         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1638         /* Clear all active interrupt sources */
1639         if (active_irqs)
1640                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1641
1642         spin_unlock_irqrestore(&vop->irq_lock, flags);
1643
1644         /* This is expected for vop iommu irqs, since the irq is shared */
1645         if (!active_irqs)
1646                 return IRQ_NONE;
1647
1648         if (active_irqs & DSP_HOLD_VALID_INTR) {
1649                 complete(&vop->dsp_hold_completion);
1650                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1651                 ret = IRQ_HANDLED;
1652         }
1653
1654         if (active_irqs & FS_INTR) {
1655                 drm_crtc_handle_vblank(crtc);
1656                 vop_handle_vblank(vop);
1657                 active_irqs &= ~FS_INTR;
1658                 ret = IRQ_HANDLED;
1659         }
1660
1661         /* Unhandled irqs are spurious. */
1662         if (active_irqs)
1663                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1664
1665         return ret;
1666 }
1667
1668 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1669                           unsigned long possible_crtcs)
1670 {
1671         struct drm_plane *share = NULL;
1672         unsigned int rotations = 0;
1673         struct drm_property *prop;
1674         uint64_t feature = 0;
1675         int ret;
1676
1677         if (win->parent)
1678                 share = &win->parent->base;
1679
1680         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1681                                    possible_crtcs, &vop_plane_funcs,
1682                                    win->data_formats, win->nformats, win->type);
1683         if (ret) {
1684                 DRM_ERROR("failed to initialize plane\n");
1685                 return ret;
1686         }
1687         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1688         drm_object_attach_property(&win->base.base,
1689                                    vop->plane_zpos_prop, win->win_id);
1690
1691         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1692                 rotations |= BIT(DRM_REFLECT_X);
1693
1694         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1695                 rotations |= BIT(DRM_REFLECT_Y);
1696
1697         if (rotations) {
1698                 rotations |= BIT(DRM_ROTATE_0);
1699                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1700                                                          rotations);
1701                 if (!prop) {
1702                         DRM_ERROR("failed to create zpos property\n");
1703                         return -EINVAL;
1704                 }
1705                 drm_object_attach_property(&win->base.base, prop,
1706                                            BIT(DRM_ROTATE_0));
1707                 win->rotation_prop = prop;
1708         }
1709         if (win->phy->scl)
1710                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1711         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1712             VOP_WIN_SUPPORT(vop, win, alpha_en))
1713                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1714
1715         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1716                                    feature);
1717
1718         return 0;
1719 }
1720
1721 static int vop_create_crtc(struct vop *vop)
1722 {
1723         struct device *dev = vop->dev;
1724         struct drm_device *drm_dev = vop->drm_dev;
1725         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1726         struct drm_crtc *crtc = &vop->crtc;
1727         struct device_node *port;
1728         uint64_t feature = 0;
1729         int ret;
1730         int i;
1731
1732         /*
1733          * Create drm_plane for primary and cursor planes first, since we need
1734          * to pass them to drm_crtc_init_with_planes, which sets the
1735          * "possible_crtcs" to the newly initialized crtc.
1736          */
1737         for (i = 0; i < vop->num_wins; i++) {
1738                 struct vop_win *win = &vop->win[i];
1739
1740                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1741                     win->type != DRM_PLANE_TYPE_CURSOR)
1742                         continue;
1743
1744                 ret = vop_plane_init(vop, win, 0);
1745                 if (ret)
1746                         goto err_cleanup_planes;
1747
1748                 plane = &win->base;
1749                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1750                         primary = plane;
1751                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1752                         cursor = plane;
1753
1754         }
1755
1756         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1757                                         &vop_crtc_funcs, NULL);
1758         if (ret)
1759                 goto err_cleanup_planes;
1760
1761         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1762
1763         /*
1764          * Create drm_planes for overlay windows with possible_crtcs restricted
1765          * to the newly created crtc.
1766          */
1767         for (i = 0; i < vop->num_wins; i++) {
1768                 struct vop_win *win = &vop->win[i];
1769                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1770
1771                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1772                         continue;
1773
1774                 ret = vop_plane_init(vop, win, possible_crtcs);
1775                 if (ret)
1776                         goto err_cleanup_crtc;
1777         }
1778
1779         port = of_get_child_by_name(dev->of_node, "port");
1780         if (!port) {
1781                 DRM_ERROR("no port node found in %s\n",
1782                           dev->of_node->full_name);
1783                 ret = -ENOENT;
1784                 goto err_cleanup_crtc;
1785         }
1786
1787         init_completion(&vop->dsp_hold_completion);
1788         init_completion(&vop->wait_update_complete);
1789         crtc->port = port;
1790         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1791
1792         if (VOP_CTRL_SUPPORT(vop, afbdc_en))
1793                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
1794         drm_object_attach_property(&crtc->base, vop->feature_prop,
1795                                    feature);
1796
1797         return 0;
1798
1799 err_cleanup_crtc:
1800         drm_crtc_cleanup(crtc);
1801 err_cleanup_planes:
1802         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1803                                  head)
1804                 drm_plane_cleanup(plane);
1805         return ret;
1806 }
1807
1808 static void vop_destroy_crtc(struct vop *vop)
1809 {
1810         struct drm_crtc *crtc = &vop->crtc;
1811         struct drm_device *drm_dev = vop->drm_dev;
1812         struct drm_plane *plane, *tmp;
1813
1814         rockchip_unregister_crtc_funcs(crtc);
1815         of_node_put(crtc->port);
1816
1817         /*
1818          * We need to cleanup the planes now.  Why?
1819          *
1820          * The planes are "&vop->win[i].base".  That means the memory is
1821          * all part of the big "struct vop" chunk of memory.  That memory
1822          * was devm allocated and associated with this component.  We need to
1823          * free it ourselves before vop_unbind() finishes.
1824          */
1825         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1826                                  head)
1827                 vop_plane_destroy(plane);
1828
1829         /*
1830          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1831          * references the CRTC.
1832          */
1833         drm_crtc_cleanup(crtc);
1834 }
1835
1836 /*
1837  * Initialize the vop->win array elements.
1838  */
1839 static int vop_win_init(struct vop *vop)
1840 {
1841         const struct vop_data *vop_data = vop->data;
1842         unsigned int i, j;
1843         unsigned int num_wins = 0;
1844         struct drm_property *prop;
1845         static const struct drm_prop_enum_list props[] = {
1846                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1847                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1848         };
1849         static const struct drm_prop_enum_list crtc_props[] = {
1850                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
1851         };
1852
1853         for (i = 0; i < vop_data->win_size; i++) {
1854                 struct vop_win *vop_win = &vop->win[num_wins];
1855                 const struct vop_win_data *win_data = &vop_data->win[i];
1856
1857                 if (!win_data->phy)
1858                         continue;
1859
1860                 vop_win->phy = win_data->phy;
1861                 vop_win->csc = win_data->csc;
1862                 vop_win->offset = win_data->base;
1863                 vop_win->type = win_data->type;
1864                 vop_win->data_formats = win_data->phy->data_formats;
1865                 vop_win->nformats = win_data->phy->nformats;
1866                 vop_win->vop = vop;
1867                 vop_win->win_id = i;
1868                 vop_win->area_id = 0;
1869                 num_wins++;
1870
1871                 for (j = 0; j < win_data->area_size; j++) {
1872                         struct vop_win *vop_area = &vop->win[num_wins];
1873                         const struct vop_win_phy *area = win_data->area[j];
1874
1875                         vop_area->parent = vop_win;
1876                         vop_area->offset = vop_win->offset;
1877                         vop_area->phy = area;
1878                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1879                         vop_area->data_formats = vop_win->data_formats;
1880                         vop_area->nformats = vop_win->nformats;
1881                         vop_area->vop = vop;
1882                         vop_area->win_id = i;
1883                         vop_area->area_id = j;
1884                         num_wins++;
1885                 }
1886         }
1887
1888         vop->num_wins = num_wins;
1889
1890         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1891                                          "ZPOS", 0, vop->data->win_size);
1892         if (!prop) {
1893                 DRM_ERROR("failed to create zpos property\n");
1894                 return -EINVAL;
1895         }
1896         vop->plane_zpos_prop = prop;
1897
1898         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1899                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1900                                 props, ARRAY_SIZE(props),
1901                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1902                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1903         if (!vop->plane_feature_prop) {
1904                 DRM_ERROR("failed to create feature property\n");
1905                 return -EINVAL;
1906         }
1907
1908         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
1909                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1910                                 props, ARRAY_SIZE(crtc_props),
1911                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
1912         if (!vop->feature_prop) {
1913                 DRM_ERROR("failed to create vop feature property\n");
1914                 return -EINVAL;
1915         }
1916
1917         return 0;
1918 }
1919
1920 static int vop_bind(struct device *dev, struct device *master, void *data)
1921 {
1922         struct platform_device *pdev = to_platform_device(dev);
1923         const struct vop_data *vop_data;
1924         struct drm_device *drm_dev = data;
1925         struct vop *vop;
1926         struct resource *res;
1927         size_t alloc_size;
1928         int ret, irq, i;
1929         int num_wins = 0;
1930
1931         vop_data = of_device_get_match_data(dev);
1932         if (!vop_data)
1933                 return -ENODEV;
1934
1935         for (i = 0; i < vop_data->win_size; i++) {
1936                 const struct vop_win_data *win_data = &vop_data->win[i];
1937
1938                 num_wins += win_data->area_size + 1;
1939         }
1940
1941         /* Allocate vop struct and its vop_win array */
1942         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1943         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1944         if (!vop)
1945                 return -ENOMEM;
1946
1947         vop->dev = dev;
1948         vop->data = vop_data;
1949         vop->drm_dev = drm_dev;
1950         vop->num_wins = num_wins;
1951         dev_set_drvdata(dev, vop);
1952
1953         ret = vop_win_init(vop);
1954         if (ret)
1955                 return ret;
1956
1957         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1958         vop->len = resource_size(res);
1959         vop->regs = devm_ioremap_resource(dev, res);
1960         if (IS_ERR(vop->regs))
1961                 return PTR_ERR(vop->regs);
1962
1963         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1964         if (!vop->regsbak)
1965                 return -ENOMEM;
1966
1967         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1968         if (IS_ERR(vop->hclk)) {
1969                 dev_err(vop->dev, "failed to get hclk source\n");
1970                 return PTR_ERR(vop->hclk);
1971         }
1972         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1973         if (IS_ERR(vop->aclk)) {
1974                 dev_err(vop->dev, "failed to get aclk source\n");
1975                 return PTR_ERR(vop->aclk);
1976         }
1977         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1978         if (IS_ERR(vop->dclk)) {
1979                 dev_err(vop->dev, "failed to get dclk source\n");
1980                 return PTR_ERR(vop->dclk);
1981         }
1982
1983         irq = platform_get_irq(pdev, 0);
1984         if (irq < 0) {
1985                 dev_err(dev, "cannot find irq for vop\n");
1986                 return irq;
1987         }
1988         vop->irq = (unsigned int)irq;
1989
1990         spin_lock_init(&vop->reg_lock);
1991         spin_lock_init(&vop->irq_lock);
1992
1993         mutex_init(&vop->vsync_mutex);
1994
1995         ret = devm_request_irq(dev, vop->irq, vop_isr,
1996                                IRQF_SHARED, dev_name(dev), vop);
1997         if (ret)
1998                 return ret;
1999
2000         /* IRQ is initially disabled; it gets enabled in power_on */
2001         disable_irq(vop->irq);
2002
2003         ret = vop_create_crtc(vop);
2004         if (ret)
2005                 return ret;
2006
2007         pm_runtime_enable(&pdev->dev);
2008         return 0;
2009 }
2010
2011 static void vop_unbind(struct device *dev, struct device *master, void *data)
2012 {
2013         struct vop *vop = dev_get_drvdata(dev);
2014
2015         pm_runtime_disable(dev);
2016         vop_destroy_crtc(vop);
2017 }
2018
2019 const struct component_ops vop_component_ops = {
2020         .bind = vop_bind,
2021         .unbind = vop_unbind,
2022 };
2023 EXPORT_SYMBOL_GPL(vop_component_ops);