drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  76                 REG_SET(x, name, win->offset, win->ext->name, v, true)
  77 #define VOP_SCL_SET(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  79 #define VOP_SCL_SET_EXT(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  81
  82 #define VOP_CTRL_SET(x, name, v) \
  83                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  84
  85 #define VOP_INTR_GET(vop, name) \
  86                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  87
  88 #define VOP_INTR_SET(vop, name, v) \
  89                 REG_SET(vop, name, 0, vop->data->intr->name, \
  90                         v, false)
  91 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  92                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  93                              mask, v, false)
  94
  95 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  96         do { \
  97                 int i, reg = 0, mask = 0; \
  98                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  99                         if (vop->data->intr->intrs[i] & type) { \
 100                                 reg |= (v) << i; \
 101                                 mask |= 1 << i; \
 102                         } \
 103                 } \
 104                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 105         } while (0)
 106 #define VOP_INTR_GET_TYPE(vop, name, type) \
 107                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 108
 109 #define VOP_CTRL_GET(x, name) \
 110                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 111
 112 #define VOP_WIN_GET(x, win, name) \
 113                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 114
 115 #define VOP_WIN_NAME(win, name) \
 116                 (vop_get_win_phy(win, &win->phy->name)->name)
 117
 118 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 119                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 120
 121 #define to_vop(x) container_of(x, struct vop, crtc)
 122 #define to_vop_win(x) container_of(x, struct vop_win, base)
 123 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 124
 125 struct vop_zpos {
 126         int win_id;
 127         int zpos;
 128 };
 129
 130 struct vop_plane_state {
 131         struct drm_plane_state base;
 132         int format;
 133         int zpos;
 134         struct drm_rect src;
 135         struct drm_rect dest;
 136         dma_addr_t yrgb_mst;
 137         dma_addr_t uv_mst;
 138         const uint32_t *y2r_table;
 139         const uint32_t *r2r_table;
 140         const uint32_t *r2y_table;
 141         bool enable;
 142 };
 143
 144 struct vop_win {
 145         struct vop_win *parent;
 146         struct drm_plane base;
 147
 148         int win_id;
 149         int area_id;
 150         uint32_t offset;
 151         enum drm_plane_type type;
 152         const struct vop_win_phy *phy;
 153         const struct vop_csc *csc;
 154         const uint32_t *data_formats;
 155         uint32_t nformats;
 156         struct vop *vop;
 157
 158         struct drm_property *rotation_prop;
 159         struct vop_plane_state state;
 160 };
 161
 162 struct vop {
 163         struct drm_crtc crtc;
 164         struct device *dev;
 165         struct drm_device *drm_dev;
 166         struct drm_property *plane_zpos_prop;
 167         struct drm_property *plane_feature_prop;
 168         struct drm_property *feature_prop;
 169         bool is_iommu_enabled;
 170         bool is_iommu_needed;
 171         bool is_enabled;
 172
 173         /* mutex vsync_ work */
 174         struct mutex vsync_mutex;
 175         bool vsync_work_pending;
 176         struct completion dsp_hold_completion;
 177         struct completion wait_update_complete;
 178         struct drm_pending_vblank_event *event;
 179
 180         struct completion line_flag_completion;
 181
 182         const struct vop_data *data;
 183         int num_wins;
 184
 185         uint32_t *regsbak;
 186         void __iomem *regs;
 187
 188         /* physical map length of vop register */
 189         uint32_t len;
 190
 191         /* one time only one process allowed to config the register */
 192         spinlock_t reg_lock;
 193         /* lock vop irq reg */
 194         spinlock_t irq_lock;
 195
 196         unsigned int irq;
 197
 198         /* vop AHP clk */
 199         struct clk *hclk;
 200         /* vop dclk */
 201         struct clk *dclk;
 202         /* vop share memory frequency */
 203         struct clk *aclk;
 204
 205         /* vop dclk reset */
 206         struct reset_control *dclk_rst;
 207
 208         struct vop_win win[];
 209 };
 210
 211 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 212 {
 213         writel(v, vop->regs + offset);
 214         vop->regsbak[offset >> 2] = v;
 215 }
 216
 217 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 218 {
 219         return readl(vop->regs + offset);
 220 }
 221
 222 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 223                                     const struct vop_reg *reg)
 224 {
 225         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 226 }
 227
 228 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 229                                   uint32_t mask, uint32_t shift, uint32_t v,
 230                                   bool write_mask, bool relaxed)
 231 {
 232         if (!mask)
 233                 return;
 234
 235         if (write_mask) {
 236                 v = ((v & mask) << shift) | (mask << (shift + 16));
 237         } else {
 238                 uint32_t cached_val = vop->regsbak[offset >> 2];
 239
 240                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 241                 vop->regsbak[offset >> 2] = v;
 242         }
 243
 244         if (relaxed)
 245                 writel_relaxed(v, vop->regs + offset);
 246         else
 247                 writel(v, vop->regs + offset);
 248 }
 249
 250 static inline const struct vop_win_phy *
 251 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 252 {
 253         if (!reg->mask && win->parent)
 254                 return win->parent->phy;
 255
 256         return win->phy;
 257 }
 258
 259 static inline uint32_t vop_get_intr_type(struct vop *vop,
 260                                          const struct vop_reg *reg, int type)
 261 {
 262         uint32_t i, ret = 0;
 263         uint32_t regs = vop_read_reg(vop, 0, reg);
 264
 265         for (i = 0; i < vop->data->intr->nintrs; i++) {
 266                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 267                         ret |= vop->data->intr->intrs[i];
 268         }
 269
 270         return ret;
 271 }
 272
 273 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 274 {
 275         int i;
 276
 277         if (!table)
 278                 return;
 279
 280         for (i = 0; i < 8; i++)
 281                 vop_writel(vop, offset + i * 4, table[i]);
 282 }
 283
 284 static inline void vop_cfg_done(struct vop *vop)
 285 {
 286         VOP_CTRL_SET(vop, cfg_done, 1);
 287 }
 288
 289 static bool vop_is_allwin_disabled(struct vop *vop)
 290 {
 291         int i;
 292
 293         for (i = 0; i < vop->num_wins; i++) {
 294                 struct vop_win *win = &vop->win[i];
 295
 296                 if (VOP_WIN_GET(vop, win, enable) != 0)
 297                         return false;
 298         }
 299
 300         return true;
 301 }
 302
 303 static bool vop_is_cfg_done_complete(struct vop *vop)
 304 {
 305         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 306 }
 307
 308 static bool has_rb_swapped(uint32_t format)
 309 {
 310         switch (format) {
 311         case DRM_FORMAT_XBGR8888:
 312         case DRM_FORMAT_ABGR8888:
 313         case DRM_FORMAT_BGR888:
 314         case DRM_FORMAT_BGR565:
 315                 return true;
 316         default:
 317                 return false;
 318         }
 319 }
 320
 321 static enum vop_data_format vop_convert_format(uint32_t format)
 322 {
 323         switch (format) {
 324         case DRM_FORMAT_XRGB8888:
 325         case DRM_FORMAT_ARGB8888:
 326         case DRM_FORMAT_XBGR8888:
 327         case DRM_FORMAT_ABGR8888:
 328                 return VOP_FMT_ARGB8888;
 329         case DRM_FORMAT_RGB888:
 330         case DRM_FORMAT_BGR888:
 331                 return VOP_FMT_RGB888;
 332         case DRM_FORMAT_RGB565:
 333         case DRM_FORMAT_BGR565:
 334                 return VOP_FMT_RGB565;
 335         case DRM_FORMAT_NV12:
 336         case DRM_FORMAT_NV12_10:
 337                 return VOP_FMT_YUV420SP;
 338         case DRM_FORMAT_NV16:
 339         case DRM_FORMAT_NV16_10:
 340                 return VOP_FMT_YUV422SP;
 341         case DRM_FORMAT_NV24:
 342         case DRM_FORMAT_NV24_10:
 343                 return VOP_FMT_YUV444SP;
 344         default:
 345                 DRM_ERROR("unsupport format[%08x]\n", format);
 346                 return -EINVAL;
 347         }
 348 }
 349
 350 static bool is_yuv_support(uint32_t format)
 351 {
 352         switch (format) {
 353         case DRM_FORMAT_NV12:
 354         case DRM_FORMAT_NV12_10:
 355         case DRM_FORMAT_NV16:
 356         case DRM_FORMAT_NV16_10:
 357         case DRM_FORMAT_NV24:
 358         case DRM_FORMAT_NV24_10:
 359                 return true;
 360         default:
 361                 return false;
 362         }
 363 }
 364
 365 static bool is_yuv_10bit(uint32_t format)
 366 {
 367         switch (format) {
 368         case DRM_FORMAT_NV12_10:
 369         case DRM_FORMAT_NV16_10:
 370         case DRM_FORMAT_NV24_10:
 371                 return true;
 372         default:
 373                 return false;
 374         }
 375 }
 376
 377 static bool is_alpha_support(uint32_t format)
 378 {
 379         switch (format) {
 380         case DRM_FORMAT_ARGB8888:
 381         case DRM_FORMAT_ABGR8888:
 382                 return true;
 383         default:
 384                 return false;
 385         }
 386 }
 387
 388 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 389                                   uint32_t dst, bool is_horizontal,
 390                                   int vsu_mode, int *vskiplines)
 391 {
 392         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 393
 394         if (is_horizontal) {
 395                 if (mode == SCALE_UP)
 396                         val = GET_SCL_FT_BIC(src, dst);
 397                 else if (mode == SCALE_DOWN)
 398                         val = GET_SCL_FT_BILI_DN(src, dst);
 399         } else {
 400                 if (mode == SCALE_UP) {
 401                         if (vsu_mode == SCALE_UP_BIL)
 402                                 val = GET_SCL_FT_BILI_UP(src, dst);
 403                         else
 404                                 val = GET_SCL_FT_BIC(src, dst);
 405                 } else if (mode == SCALE_DOWN) {
 406                         if (vskiplines) {
 407                                 *vskiplines = scl_get_vskiplines(src, dst);
 408                                 val = scl_get_bili_dn_vskip(src, dst,
 409                                                             *vskiplines);
 410                         } else {
 411                                 val = GET_SCL_FT_BILI_DN(src, dst);
 412                         }
 413                 }
 414         }
 415
 416         return val;
 417 }
 418
 419 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 420                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 421                                 uint32_t dst_h, uint32_t pixel_format)
 422 {
 423         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 424         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 425         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 426         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 427         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 428         bool is_yuv = is_yuv_support(pixel_format);
 429         uint16_t cbcr_src_w = src_w / hsub;
 430         uint16_t cbcr_src_h = src_h / vsub;
 431         uint16_t vsu_mode;
 432         uint16_t lb_mode;
 433         uint32_t val;
 434         int vskiplines = 0;
 435
 436         if (!win->phy->scl)
 437                 return;
 438
 439         if (dst_w > 3840) {
 440                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 441                 return;
 442         }
 443
 444         if (!win->phy->scl->ext) {
 445                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 446                             scl_cal_scale2(src_w, dst_w));
 447                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 448                             scl_cal_scale2(src_h, dst_h));
 449                 if (is_yuv) {
 450                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 451                                     scl_cal_scale2(cbcr_src_w, dst_w));
 452                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 453                                     scl_cal_scale2(cbcr_src_h, dst_h));
 454                 }
 455                 return;
 456         }
 457
 458         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 459         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 460
 461         if (is_yuv) {
 462                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 463                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 464                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 465                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 466                 else
 467                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 468         } else {
 469                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 470                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 471                 else
 472                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 473         }
 474
 475         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 476         if (lb_mode == LB_RGB_3840X2) {
 477                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 478                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 479                         return;
 480                 }
 481                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 482                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 483                         return;
 484                 }
 485                 vsu_mode = SCALE_UP_BIL;
 486         } else if (lb_mode == LB_RGB_2560X4) {
 487                 vsu_mode = SCALE_UP_BIL;
 488         } else {
 489                 vsu_mode = SCALE_UP_BIC;
 490         }
 491
 492         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 493                                 true, 0, NULL);
 494         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 495         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 496                                 false, vsu_mode, &vskiplines);
 497         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 498
 499         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 500         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 501
 502         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 503         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 504         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 505         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 506         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 507         if (is_yuv) {
 508                 vskiplines = 0;
 509
 510                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 511                                         dst_w, true, 0, NULL);
 512                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 513                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 514                                         dst_h, false, vsu_mode, &vskiplines);
 515                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 516
 517                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 518                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 519                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 520                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 521                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 522                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 523                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 524         }
 525 }
 526
 527 /*
 528  * rk3399 colorspace path:
 529  *      Input        Win csc                     Output
 530  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 531  *    RGB        --> R2Y                  __/
 532  *
 533  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 534  *    RGB        --> 709To2020->R2Y       __/
 535  *
 536  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 537  *    RGB        --> R2Y                  __/
 538  *
 539  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 540  *    RGB        --> 709To2020->R2Y       __/
 541  *
 542  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 543  *    RGB        --> R2Y                  __/
 544  *
 545  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 546  *    RGB        --> R2Y(601)             __/
 547  *
 548  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 549  *    RGB        --> bypass               __/
 550  *
 551  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 552  *
 553  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 554  *
 555  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 556  *
 557  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 558  */
 559 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 560                          bool is_input_yuv, bool is_output_yuv,
 561                          int input_csc, int output_csc,
 562                          const uint32_t **y2r_table,
 563                          const uint32_t **r2r_table,
 564                          const uint32_t **r2y_table)
 565 {
 566         *y2r_table = NULL;
 567         *r2r_table = NULL;
 568         *r2y_table = NULL;
 569
 570         if (is_output_yuv) {
 571                 if (output_csc == CSC_BT2020) {
 572                         if (is_input_yuv) {
 573                                 if (input_csc == CSC_BT2020)
 574                                         return 0;
 575                                 *y2r_table = csc_table->y2r_bt709;
 576                         }
 577                         if (input_csc != CSC_BT2020)
 578                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 579                         *r2y_table = csc_table->r2y_bt2020;
 580                 } else {
 581                         if (is_input_yuv && input_csc == CSC_BT2020)
 582                                 *y2r_table = csc_table->y2r_bt2020;
 583                         if (input_csc == CSC_BT2020)
 584                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 585                         if (!is_input_yuv || y2r_table) {
 586                                 if (output_csc == CSC_BT709)
 587                                         *r2y_table = csc_table->r2y_bt709;
 588                                 else
 589                                         *r2y_table = csc_table->r2y_bt601;
 590                         }
 591                 }
 592
 593         } else {
 594                 if (!is_input_yuv)
 595                         return 0;
 596
 597                 /*
 598                  * is possible use bt2020 on rgb mode?
 599                  */
 600                 if (WARN_ON(output_csc == CSC_BT2020))
 601                         return -EINVAL;
 602
 603                 if (input_csc == CSC_BT2020)
 604                         *y2r_table = csc_table->y2r_bt2020;
 605                 else if (input_csc == CSC_BT709)
 606                         *y2r_table = csc_table->y2r_bt709;
 607                 else
 608                         *y2r_table = csc_table->y2r_bt601;
 609
 610                 if (input_csc == CSC_BT2020)
 611                         /*
 612                          * We don't have bt601 to bt709 table, force use bt709.
 613                          */
 614                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 621                                 struct drm_crtc_state *crtc_state)
 622 {
 623         struct vop *vop = to_vop(crtc);
 624         struct drm_atomic_state *state = crtc_state->state;
 625         const struct vop_csc_table *csc_table = vop->data->csc_table;
 626         struct drm_plane_state *pstate;
 627         struct drm_plane *plane;
 628         bool is_yuv;
 629         int ret;
 630
 631         if (!csc_table)
 632                 return 0;
 633
 634         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 635                 struct vop_plane_state *vop_plane_state;
 636
 637                 pstate = drm_atomic_get_plane_state(state, plane);
 638                 if (IS_ERR(pstate))
 639                         return PTR_ERR(pstate);
 640                 vop_plane_state = to_vop_plane_state(pstate);
 641
 642                 if (!pstate->fb)
 643                         continue;
 644                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 645
 646                 /*
 647                  * TODO: force set input and output csc mode.
 648                  */
 649                 ret = vop_csc_setup(csc_table, is_yuv, false,
 650                                     CSC_BT709, CSC_BT709,
 651                                     &vop_plane_state->y2r_table,
 652                                     &vop_plane_state->r2r_table,
 653                                     &vop_plane_state->r2y_table);
 654                 if (ret)
 655                         return ret;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 662 {
 663         unsigned long flags;
 664
 665         spin_lock_irqsave(&vop->irq_lock, flags);
 666
 667         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 668         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 669
 670         spin_unlock_irqrestore(&vop->irq_lock, flags);
 671 }
 672
 673 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 674 {
 675         unsigned long flags;
 676
 677         spin_lock_irqsave(&vop->irq_lock, flags);
 678
 679         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 680
 681         spin_unlock_irqrestore(&vop->irq_lock, flags);
 682 }
 683
 684 /*
 685  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 686  *     the "FRAME_SYNC" interrupt.
 687  * (2) the active data region of each frame ends at dsp_vact_end
 688  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 689  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 690  *
 691  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 692  * Interrupts
 693  * LINE_FLAG -------------------------------+
 694  * FRAME_SYNC ----+                         |
 695  *                |                         |
 696  *                v                         v
 697  *                | Vsync | Vbp |  Vactive  | Vfp |
 698  *                        ^     ^           ^     ^
 699  *                        |     |           |     |
 700  *                        |     |           |     |
 701  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 702  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 703  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 704  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 705  */
 706 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 707 {
 708         uint32_t line_flag_irq;
 709         unsigned long flags;
 710
 711         spin_lock_irqsave(&vop->irq_lock, flags);
 712
 713         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 714
 715         spin_unlock_irqrestore(&vop->irq_lock, flags);
 716
 717         return !!line_flag_irq;
 718 }
 719
 720 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 721 {
 722         unsigned long flags;
 723
 724         if (WARN_ON(!vop->is_enabled))
 725                 return;
 726
 727         spin_lock_irqsave(&vop->irq_lock, flags);
 728
 729         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 730         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 731         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 732
 733         spin_unlock_irqrestore(&vop->irq_lock, flags);
 734 }
 735
 736 static void vop_line_flag_irq_disable(struct vop *vop)
 737 {
 738         unsigned long flags;
 739
 740         if (WARN_ON(!vop->is_enabled))
 741                 return;
 742
 743         spin_lock_irqsave(&vop->irq_lock, flags);
 744
 745         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 746
 747         spin_unlock_irqrestore(&vop->irq_lock, flags);
 748 }
 749
 750 static void vop_enable(struct drm_crtc *crtc)
 751 {
 752         struct vop *vop = to_vop(crtc);
 753         int ret, i;
 754
 755         ret = clk_prepare_enable(vop->hclk);
 756         if (ret < 0) {
 757                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 758                 return;
 759         }
 760
 761         ret = clk_prepare_enable(vop->dclk);
 762         if (ret < 0) {
 763                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 764                 goto err_disable_hclk;
 765         }
 766
 767         ret = clk_prepare_enable(vop->aclk);
 768         if (ret < 0) {
 769                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 770                 goto err_disable_dclk;
 771         }
 772
 773         ret = pm_runtime_get_sync(vop->dev);
 774         if (ret < 0) {
 775                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 776                 return;
 777         }
 778
 779         memcpy(vop->regsbak, vop->regs, vop->len);
 780
 781         VOP_CTRL_SET(vop, global_regdone_en, 1);
 782         VOP_CTRL_SET(vop, dsp_blank, 0);
 783
 784         for (i = 0; i < vop->num_wins; i++) {
 785                 struct vop_win *win = &vop->win[i];
 786
 787                 VOP_WIN_SET(vop, win, gate, 1);
 788         }
 789         vop->is_enabled = true;
 790
 791         spin_lock(&vop->reg_lock);
 792
 793         VOP_CTRL_SET(vop, standby, 0);
 794
 795         spin_unlock(&vop->reg_lock);
 796
 797         enable_irq(vop->irq);
 798
 799         drm_crtc_vblank_on(crtc);
 800
 801         return;
 802
 803 err_disable_dclk:
 804         clk_disable_unprepare(vop->dclk);
 805 err_disable_hclk:
 806         clk_disable_unprepare(vop->hclk);
 807 }
 808
 809 static void vop_crtc_disable(struct drm_crtc *crtc)
 810 {
 811         struct vop *vop = to_vop(crtc);
 812         int i;
 813
 814         /*
 815          * We need to make sure that all windows are disabled before we
 816          * disable that crtc. Otherwise we might try to scan from a destroyed
 817          * buffer later.
 818          */
 819         for (i = 0; i < vop->num_wins; i++) {
 820                 struct vop_win *win = &vop->win[i];
 821
 822                 spin_lock(&vop->reg_lock);
 823                 if (win->phy->scl && win->phy->scl->ext) {
 824                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 825                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 826                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 827                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 828                 }
 829                 VOP_WIN_SET(vop, win, enable, 0);
 830                 spin_unlock(&vop->reg_lock);
 831         }
 832         VOP_CTRL_SET(vop, afbdc_en, 0);
 833         vop_cfg_done(vop);
 834
 835         drm_crtc_vblank_off(crtc);
 836
 837         /*
 838          * Vop standby will take effect at end of current frame,
 839          * if dsp hold valid irq happen, it means standby complete.
 840          *
 841          * we must wait standby complete when we want to disable aclk,
 842          * if not, memory bus maybe dead.
 843          */
 844         reinit_completion(&vop->dsp_hold_completion);
 845         vop_dsp_hold_valid_irq_enable(vop);
 846
 847         spin_lock(&vop->reg_lock);
 848
 849         VOP_CTRL_SET(vop, standby, 1);
 850
 851         spin_unlock(&vop->reg_lock);
 852
 853         wait_for_completion(&vop->dsp_hold_completion);
 854
 855         vop_dsp_hold_valid_irq_disable(vop);
 856
 857         disable_irq(vop->irq);
 858
 859         vop->is_enabled = false;
 860         if (vop->is_iommu_enabled) {
 861                 /*
 862                  * vop standby complete, so iommu detach is safe.
 863                  */
 864                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 865                 vop->is_iommu_enabled = false;
 866         }
 867
 868         pm_runtime_put(vop->dev);
 869         clk_disable_unprepare(vop->dclk);
 870         clk_disable_unprepare(vop->aclk);
 871         clk_disable_unprepare(vop->hclk);
 872 }
 873
 874 static void vop_plane_destroy(struct drm_plane *plane)
 875 {
 876         drm_plane_cleanup(plane);
 877 }
 878
 879 static int vop_plane_prepare_fb(struct drm_plane *plane,
 880                                 const struct drm_plane_state *new_state)
 881 {
 882         if (plane->state->fb)
 883                 drm_framebuffer_reference(plane->state->fb);
 884
 885         return 0;
 886 }
 887
 888 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 889                                  const struct drm_plane_state *old_state)
 890 {
 891         if (old_state->fb)
 892                 drm_framebuffer_unreference(old_state->fb);
 893 }
 894
 895 static int vop_plane_atomic_check(struct drm_plane *plane,
 896                            struct drm_plane_state *state)
 897 {
 898         struct drm_crtc *crtc = state->crtc;
 899         struct drm_framebuffer *fb = state->fb;
 900         struct vop_win *win = to_vop_win(plane);
 901         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 902         struct drm_crtc_state *crtc_state;
 903         bool visible;
 904         int ret;
 905         struct drm_rect *dest = &vop_plane_state->dest;
 906         struct drm_rect *src = &vop_plane_state->src;
 907         struct drm_rect clip;
 908         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 909                                         DRM_PLANE_HELPER_NO_SCALING;
 910         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 911                                         DRM_PLANE_HELPER_NO_SCALING;
 912         unsigned long offset;
 913         dma_addr_t dma_addr;
 914
 915         crtc = crtc ? crtc : plane->state->crtc;
 916         /*
 917          * Both crtc or plane->state->crtc can be null.
 918          */
 919         if (!crtc || !fb)
 920                 goto out_disable;
 921
 922         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 923         if (IS_ERR(crtc_state))
 924                 return PTR_ERR(crtc_state);
 925
 926         src->x1 = state->src_x;
 927         src->y1 = state->src_y;
 928         src->x2 = state->src_x + state->src_w;
 929         src->y2 = state->src_y + state->src_h;
 930         dest->x1 = state->crtc_x;
 931         dest->y1 = state->crtc_y;
 932         dest->x2 = state->crtc_x + state->crtc_w;
 933         dest->y2 = state->crtc_y + state->crtc_h;
 934
 935         clip.x1 = 0;
 936         clip.y1 = 0;
 937         clip.x2 = crtc_state->mode.hdisplay;
 938         clip.y2 = crtc_state->mode.vdisplay;
 939
 940         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 941                                             src, dest, &clip,
 942                                             min_scale,
 943                                             max_scale,
 944                                             true, true, &visible);
 945         if (ret)
 946                 return ret;
 947
 948         if (!visible)
 949                 goto out_disable;
 950
 951         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 952         if (vop_plane_state->format < 0)
 953                 return vop_plane_state->format;
 954
 955         /*
 956          * Src.x1 can be odd when do clip, but yuv plane start point
 957          * need align with 2 pixel.
 958          */
 959         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 960                 return -EINVAL;
 961
 962         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 963         if (state->rotation & BIT(DRM_REFLECT_Y))
 964                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 965         else
 966                 offset += (src->y1 >> 16) * fb->pitches[0];
 967
 968         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 969         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 970         if (is_yuv_support(fb->pixel_format)) {
 971                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 972                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 973                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
 974
 975                 offset = (src->x1 >> 16) * bpp / hsub / 8;
 976                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 977
 978                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 979                 dma_addr += offset + fb->offsets[1];
 980                 vop_plane_state->uv_mst = dma_addr;
 981         }
 982
 983         vop_plane_state->enable = true;
 984
 985         return 0;
 986
 987 out_disable:
 988         vop_plane_state->enable = false;
 989         return 0;
 990 }
 991
 992 static void vop_plane_atomic_disable(struct drm_plane *plane,
 993                                      struct drm_plane_state *old_state)
 994 {
 995         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 996         struct vop_win *win = to_vop_win(plane);
 997         struct vop *vop = to_vop(old_state->crtc);
 998
 999         if (!old_state->crtc)
1000                 return;
1001
1002         spin_lock(&vop->reg_lock);
1003
1004         /*
1005          * FIXUP: some of the vop scale would be abnormal after windows power
1006          * on/off so deinit scale to scale_none mode.
1007          */
1008         if (win->phy->scl && win->phy->scl->ext) {
1009                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1010                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1011                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1012                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1013         }
1014         VOP_WIN_SET(vop, win, enable, 0);
1015
1016         spin_unlock(&vop->reg_lock);
1017
1018         vop_plane_state->enable = false;
1019 }
1020
1021 static void vop_plane_atomic_update(struct drm_plane *plane,
1022                 struct drm_plane_state *old_state)
1023 {
1024         struct drm_plane_state *state = plane->state;
1025         struct drm_crtc *crtc = state->crtc;
1026         struct vop_win *win = to_vop_win(plane);
1027         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1028         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1029         struct vop *vop = to_vop(state->crtc);
1030         struct drm_framebuffer *fb = state->fb;
1031         unsigned int actual_w, actual_h;
1032         unsigned int dsp_stx, dsp_sty;
1033         uint32_t act_info, dsp_info, dsp_st;
1034         struct drm_rect *src = &vop_plane_state->src;
1035         struct drm_rect *dest = &vop_plane_state->dest;
1036         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1037         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1038         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1039         int ymirror, xmirror;
1040         uint32_t val;
1041         bool rb_swap;
1042
1043         /*
1044          * can't update plane when vop is disabled.
1045          */
1046         if (!crtc)
1047                 return;
1048
1049         if (!vop_plane_state->enable) {
1050                 vop_plane_atomic_disable(plane, old_state);
1051                 return;
1052         }
1053
1054         actual_w = drm_rect_width(src) >> 16;
1055         actual_h = drm_rect_height(src) >> 16;
1056         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1057
1058         dsp_info = (drm_rect_height(dest) - 1) << 16;
1059         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1060
1061         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1062         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1063         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1064
1065         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1066         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1067
1068         spin_lock(&vop->reg_lock);
1069
1070         VOP_WIN_SET(vop, win, xmirror, xmirror);
1071         VOP_WIN_SET(vop, win, ymirror, ymirror);
1072         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1073         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1074         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1075         if (is_yuv_support(fb->pixel_format)) {
1076                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1077                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1078         }
1079         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1080
1081         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1082                             drm_rect_width(dest), drm_rect_height(dest),
1083                             fb->pixel_format);
1084
1085         VOP_WIN_SET(vop, win, act_info, act_info);
1086         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1087         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1088
1089         rb_swap = has_rb_swapped(fb->pixel_format);
1090         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1091
1092         if (is_alpha_support(fb->pixel_format) &&
1093             (s->dsp_layer_sel & 0x3) != win->win_id) {
1094                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1095                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1096                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1097                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1098                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1099                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1100                         SRC_FACTOR_M0(ALPHA_ONE);
1101                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1102                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1103                 VOP_WIN_SET(vop, win, alpha_en, 1);
1104         } else {
1105                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1106                 VOP_WIN_SET(vop, win, alpha_en, 0);
1107         }
1108
1109         if (win->csc) {
1110                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1111                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1112                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1113                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1114                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1115                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1116         }
1117         VOP_WIN_SET(vop, win, enable, 1);
1118         spin_unlock(&vop->reg_lock);
1119         vop->is_iommu_needed = true;
1120 }
1121
1122 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1123         .prepare_fb = vop_plane_prepare_fb,
1124         .cleanup_fb = vop_plane_cleanup_fb,
1125         .atomic_check = vop_plane_atomic_check,
1126         .atomic_update = vop_plane_atomic_update,
1127         .atomic_disable = vop_plane_atomic_disable,
1128 };
1129
1130 void vop_atomic_plane_reset(struct drm_plane *plane)
1131 {
1132         struct vop_win *win = to_vop_win(plane);
1133         struct vop_plane_state *vop_plane_state =
1134                                         to_vop_plane_state(plane->state);
1135
1136         if (plane->state && plane->state->fb)
1137                 drm_framebuffer_unreference(plane->state->fb);
1138
1139         kfree(vop_plane_state);
1140         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1141         if (!vop_plane_state)
1142                 return;
1143
1144         vop_plane_state->zpos = win->win_id;
1145         plane->state = &vop_plane_state->base;
1146         plane->state->plane = plane;
1147 }
1148
1149 struct drm_plane_state *
1150 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1151 {
1152         struct vop_plane_state *old_vop_plane_state;
1153         struct vop_plane_state *vop_plane_state;
1154
1155         if (WARN_ON(!plane->state))
1156                 return NULL;
1157
1158         old_vop_plane_state = to_vop_plane_state(plane->state);
1159         vop_plane_state = kmemdup(old_vop_plane_state,
1160                                   sizeof(*vop_plane_state), GFP_KERNEL);
1161         if (!vop_plane_state)
1162                 return NULL;
1163
1164         __drm_atomic_helper_plane_duplicate_state(plane,
1165                                                   &vop_plane_state->base);
1166
1167         return &vop_plane_state->base;
1168 }
1169
1170 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1171                                            struct drm_plane_state *state)
1172 {
1173         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1174
1175         __drm_atomic_helper_plane_destroy_state(plane, state);
1176
1177         kfree(vop_state);
1178 }
1179
1180 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1181                                          struct drm_plane_state *state,
1182                                          struct drm_property *property,
1183                                          uint64_t val)
1184 {
1185         struct vop_win *win = to_vop_win(plane);
1186         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1187
1188         if (property == win->vop->plane_zpos_prop) {
1189                 plane_state->zpos = val;
1190                 return 0;
1191         }
1192
1193         if (property == win->rotation_prop) {
1194                 state->rotation = val;
1195                 return 0;
1196         }
1197
1198         DRM_ERROR("failed to set vop plane property\n");
1199         return -EINVAL;
1200 }
1201
1202 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1203                                          const struct drm_plane_state *state,
1204                                          struct drm_property *property,
1205                                          uint64_t *val)
1206 {
1207         struct vop_win *win = to_vop_win(plane);
1208         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1209
1210         if (property == win->vop->plane_zpos_prop) {
1211                 *val = plane_state->zpos;
1212                 return 0;
1213         }
1214
1215         if (property == win->rotation_prop) {
1216                 *val = state->rotation;
1217                 return 0;
1218         }
1219
1220         DRM_ERROR("failed to get vop plane property\n");
1221         return -EINVAL;
1222 }
1223
1224 static const struct drm_plane_funcs vop_plane_funcs = {
1225         .update_plane   = drm_atomic_helper_update_plane,
1226         .disable_plane  = drm_atomic_helper_disable_plane,
1227         .destroy = vop_plane_destroy,
1228         .reset = vop_atomic_plane_reset,
1229         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1230         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1231         .atomic_set_property = vop_atomic_plane_set_property,
1232         .atomic_get_property = vop_atomic_plane_get_property,
1233 };
1234
1235 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1236 {
1237         struct vop *vop = to_vop(crtc);
1238         unsigned long flags;
1239
1240         if (!vop->is_enabled)
1241                 return -EPERM;
1242
1243         spin_lock_irqsave(&vop->irq_lock, flags);
1244
1245         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1246         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1247
1248         spin_unlock_irqrestore(&vop->irq_lock, flags);
1249
1250         return 0;
1251 }
1252
1253 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1254 {
1255         struct vop *vop = to_vop(crtc);
1256         unsigned long flags;
1257
1258         if (!vop->is_enabled)
1259                 return;
1260
1261         spin_lock_irqsave(&vop->irq_lock, flags);
1262
1263         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1264
1265         spin_unlock_irqrestore(&vop->irq_lock, flags);
1266 }
1267
1268 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1269 {
1270         struct vop *vop = to_vop(crtc);
1271
1272         reinit_completion(&vop->wait_update_complete);
1273         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1274 }
1275
1276 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1277                                            struct drm_file *file_priv)
1278 {
1279         struct drm_device *drm = crtc->dev;
1280         struct vop *vop = to_vop(crtc);
1281         struct drm_pending_vblank_event *e;
1282         unsigned long flags;
1283
1284         spin_lock_irqsave(&drm->event_lock, flags);
1285         e = vop->event;
1286         if (e && e->base.file_priv == file_priv) {
1287                 vop->event = NULL;
1288
1289                 e->base.destroy(&e->base);
1290                 file_priv->event_space += sizeof(e->event);
1291         }
1292         spin_unlock_irqrestore(&drm->event_lock, flags);
1293 }
1294
1295 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1296         .enable_vblank = vop_crtc_enable_vblank,
1297         .disable_vblank = vop_crtc_disable_vblank,
1298         .wait_for_update = vop_crtc_wait_for_update,
1299         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1300 };
1301
1302 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1303                                 const struct drm_display_mode *mode,
1304                                 struct drm_display_mode *adjusted_mode)
1305 {
1306         struct vop *vop = to_vop(crtc);
1307
1308         adjusted_mode->clock =
1309                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1310
1311         return true;
1312 }
1313
1314 static void vop_crtc_enable(struct drm_crtc *crtc)
1315 {
1316         struct vop *vop = to_vop(crtc);
1317         const struct vop_data *vop_data = vop->data;
1318         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1319         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1320         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1321         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1322         u16 htotal = adjusted_mode->crtc_htotal;
1323         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1324         u16 hact_end = hact_st + hdisplay;
1325         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1326         u16 vtotal = adjusted_mode->crtc_vtotal;
1327         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1328         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1329         u16 vact_end = vact_st + vdisplay;
1330         uint32_t val;
1331
1332         vop_enable(crtc);
1333         /*
1334          * If dclk rate is zero, mean that scanout is stop,
1335          * we don't need wait any more.
1336          */
1337         if (clk_get_rate(vop->dclk)) {
1338                 /*
1339                  * Rk3288 vop timing register is immediately, when configure
1340                  * display timing on display time, may cause tearing.
1341                  *
1342                  * Vop standby will take effect at end of current frame,
1343                  * if dsp hold valid irq happen, it means standby complete.
1344                  *
1345                  * mode set:
1346                  *    standby and wait complete --> |----
1347                  *                                  | display time
1348                  *                                  |----
1349                  *                                  |---> dsp hold irq
1350                  *     configure display timing --> |
1351                  *         standby exit             |
1352                  *                                  | new frame start.
1353                  */
1354
1355                 reinit_completion(&vop->dsp_hold_completion);
1356                 vop_dsp_hold_valid_irq_enable(vop);
1357
1358                 spin_lock(&vop->reg_lock);
1359
1360                 VOP_CTRL_SET(vop, standby, 1);
1361
1362                 spin_unlock(&vop->reg_lock);
1363
1364                 wait_for_completion(&vop->dsp_hold_completion);
1365
1366                 vop_dsp_hold_valid_irq_disable(vop);
1367         }
1368
1369         val = 0x8;
1370         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1371         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1372         VOP_CTRL_SET(vop, pin_pol, val);
1373         switch (s->output_type) {
1374         case DRM_MODE_CONNECTOR_LVDS:
1375                 VOP_CTRL_SET(vop, rgb_en, 1);
1376                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1377                 break;
1378         case DRM_MODE_CONNECTOR_eDP:
1379                 VOP_CTRL_SET(vop, edp_en, 1);
1380                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1381                 break;
1382         case DRM_MODE_CONNECTOR_HDMIA:
1383                 VOP_CTRL_SET(vop, hdmi_en, 1);
1384                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1385                 break;
1386         case DRM_MODE_CONNECTOR_DSI:
1387                 VOP_CTRL_SET(vop, mipi_en, 1);
1388                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1389                 break;
1390         default:
1391                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1392         }
1393
1394         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1395             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1396                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1397
1398         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1399
1400         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1401         val = hact_st << 16;
1402         val |= hact_end;
1403         VOP_CTRL_SET(vop, hact_st_end, val);
1404         VOP_CTRL_SET(vop, hpost_st_end, val);
1405
1406         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1407         val = vact_st << 16;
1408         val |= vact_end;
1409         VOP_CTRL_SET(vop, vact_st_end, val);
1410         VOP_CTRL_SET(vop, vpost_st_end, val);
1411         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1412                 u16 vact_st_f1 = vtotal + vact_st + 1;
1413                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1414
1415                 val = vact_st_f1 << 16 | vact_end_f1;
1416                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1417                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1418
1419                 val = vtotal << 16 | (vtotal + vsync_len);
1420                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1421                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1422                 VOP_CTRL_SET(vop, p2i_en, 1);
1423         } else {
1424                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1425                 VOP_CTRL_SET(vop, p2i_en, 0);
1426         }
1427
1428         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1429
1430         VOP_CTRL_SET(vop, standby, 0);
1431 }
1432
1433 static int vop_zpos_cmp(const void *a, const void *b)
1434 {
1435         struct vop_zpos *pa = (struct vop_zpos *)a;
1436         struct vop_zpos *pb = (struct vop_zpos *)b;
1437
1438         return pa->zpos - pb->zpos;
1439 }
1440
1441 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1442                                   struct drm_crtc_state *crtc_state)
1443 {
1444         struct vop *vop = to_vop(crtc);
1445         const struct vop_data *vop_data = vop->data;
1446         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1447         struct drm_atomic_state *state = crtc_state->state;
1448         struct drm_plane *plane;
1449         struct drm_plane_state *pstate;
1450         struct vop_plane_state *plane_state;
1451         struct vop_win *win;
1452         int afbdc_format;
1453         int i;
1454
1455         s->afbdc_en = 0;
1456
1457         for_each_plane_in_state(state, plane, pstate, i) {
1458                 struct drm_framebuffer *fb = pstate->fb;
1459                 struct drm_rect *src;
1460
1461                 win = to_vop_win(plane);
1462                 plane_state = to_vop_plane_state(pstate);
1463
1464                 if (pstate->crtc != crtc || !fb)
1465                         continue;
1466
1467                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1468                         continue;
1469
1470                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1471                         DRM_ERROR("not support afbdc\n");
1472                         return -EINVAL;
1473                 }
1474
1475                 switch (plane_state->format) {
1476                 case VOP_FMT_ARGB8888:
1477                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1478                         break;
1479                 case VOP_FMT_RGB888:
1480                         afbdc_format = AFBDC_FMT_U8U8U8;
1481                         break;
1482                 case VOP_FMT_RGB565:
1483                         afbdc_format = AFBDC_FMT_RGB565;
1484                         break;
1485                 default:
1486                         return -EINVAL;
1487                 }
1488
1489                 if (s->afbdc_en) {
1490                         DRM_ERROR("vop only support one afbc layer\n");
1491                         return -EINVAL;
1492                 }
1493
1494                 src = &plane_state->src;
1495                 if (src->x1 || src->y1 || fb->offsets[0]) {
1496                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1497                                   win->win_id);
1498                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1499                                   src->x1, src->y1, fb->offsets[0]);
1500                         return -EINVAL;
1501                 }
1502                 s->afbdc_win_format = afbdc_format;
1503                 s->afbdc_win_width = pstate->fb->width - 1;
1504                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1505                 s->afbdc_win_id = win->win_id;
1506                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1507                 s->afbdc_en = 1;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1514                                  struct drm_crtc_state *crtc_state)
1515 {
1516         struct drm_atomic_state *state = crtc_state->state;
1517         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1518         struct vop *vop = to_vop(crtc);
1519         const struct vop_data *vop_data = vop->data;
1520         struct drm_plane *plane;
1521         struct drm_plane_state *pstate;
1522         struct vop_plane_state *plane_state;
1523         struct vop_zpos *pzpos;
1524         int dsp_layer_sel = 0;
1525         int i, j, cnt = 0, ret = 0;
1526
1527         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1528         if (ret)
1529                 return ret;
1530
1531         ret = vop_csc_atomic_check(crtc, crtc_state);
1532         if (ret)
1533                 return ret;
1534
1535         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1536         if (!pzpos)
1537                 return -ENOMEM;
1538
1539         for (i = 0; i < vop_data->win_size; i++) {
1540                 const struct vop_win_data *win_data = &vop_data->win[i];
1541                 struct vop_win *win;
1542
1543                 if (!win_data->phy)
1544                         continue;
1545
1546                 for (j = 0; j < vop->num_wins; j++) {
1547                         win = &vop->win[j];
1548
1549                         if (win->win_id == i && !win->area_id)
1550                                 break;
1551                 }
1552                 if (WARN_ON(j >= vop->num_wins)) {
1553                         ret = -EINVAL;
1554                         goto err_free_pzpos;
1555                 }
1556
1557                 plane = &win->base;
1558                 pstate = state->plane_states[drm_plane_index(plane)];
1559                 /*
1560                  * plane might not have changed, in which case take
1561                  * current state:
1562                  */
1563                 if (!pstate)
1564                         pstate = plane->state;
1565                 plane_state = to_vop_plane_state(pstate);
1566                 pzpos[cnt].zpos = plane_state->zpos;
1567                 pzpos[cnt++].win_id = win->win_id;
1568         }
1569
1570         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1571
1572         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1573                 const struct vop_win_data *win_data = &vop_data->win[i];
1574                 int shift = i * 2;
1575
1576                 if (win_data->phy) {
1577                         struct vop_zpos *zpos = &pzpos[cnt++];
1578
1579                         dsp_layer_sel |= zpos->win_id << shift;
1580                 } else {
1581                         dsp_layer_sel |= i << shift;
1582                 }
1583         }
1584
1585         s->dsp_layer_sel = dsp_layer_sel;
1586
1587 err_free_pzpos:
1588         kfree(pzpos);
1589         return ret;
1590 }
1591
1592 static void vop_cfg_update(struct drm_crtc *crtc,
1593                            struct drm_crtc_state *old_crtc_state)
1594 {
1595         struct rockchip_crtc_state *s =
1596                         to_rockchip_crtc_state(crtc->state);
1597         struct vop *vop = to_vop(crtc);
1598
1599         spin_lock(&vop->reg_lock);
1600
1601         if (s->afbdc_en) {
1602                 uint32_t pic_size;
1603
1604                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1605                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1606                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1607                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1608                 pic_size = (s->afbdc_win_width & 0xffff);
1609                 pic_size |= s->afbdc_win_height << 16;
1610                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1611         }
1612
1613         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1614         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1615         vop_cfg_done(vop);
1616
1617         spin_unlock(&vop->reg_lock);
1618 }
1619
1620 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1621                                   struct drm_crtc_state *old_crtc_state)
1622 {
1623         struct vop *vop = to_vop(crtc);
1624
1625         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1626                 int ret;
1627                 if (!vop_is_allwin_disabled(vop)) {
1628                         reinit_completion(&vop->dsp_hold_completion);
1629                         vop_dsp_hold_valid_irq_enable(vop);
1630
1631                         vop_cfg_update(crtc, old_crtc_state);
1632                         spin_lock(&vop->reg_lock);
1633
1634                         VOP_CTRL_SET(vop, standby, 1);
1635
1636                         spin_unlock(&vop->reg_lock);
1637
1638                         wait_for_completion(&vop->dsp_hold_completion);
1639
1640                         vop_dsp_hold_valid_irq_disable(vop);
1641                 }
1642                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1643                 if (ret) {
1644                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1645                 }
1646                 VOP_CTRL_SET(vop, standby, 0);
1647                 vop->is_iommu_enabled = true;
1648         }
1649
1650         vop_cfg_update(crtc, old_crtc_state);
1651 }
1652
1653 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1654                                   struct drm_crtc_state *old_crtc_state)
1655 {
1656         struct vop *vop = to_vop(crtc);
1657
1658         if (crtc->state->event) {
1659                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1660
1661                 vop->event = crtc->state->event;
1662                 crtc->state->event = NULL;
1663         }
1664 }
1665
1666 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1667         .enable = vop_crtc_enable,
1668         .disable = vop_crtc_disable,
1669         .mode_fixup = vop_crtc_mode_fixup,
1670         .atomic_check = vop_crtc_atomic_check,
1671         .atomic_flush = vop_crtc_atomic_flush,
1672         .atomic_begin = vop_crtc_atomic_begin,
1673 };
1674
1675 static void vop_crtc_destroy(struct drm_crtc *crtc)
1676 {
1677         drm_crtc_cleanup(crtc);
1678 }
1679
1680 static void vop_crtc_reset(struct drm_crtc *crtc)
1681 {
1682         if (crtc->state)
1683                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1684         kfree(crtc->state);
1685
1686         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1687         if (crtc->state)
1688                 crtc->state->crtc = crtc;
1689 }
1690
1691 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1692 {
1693         struct rockchip_crtc_state *rockchip_state;
1694
1695         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1696         if (!rockchip_state)
1697                 return NULL;
1698
1699         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1700         return &rockchip_state->base;
1701 }
1702
1703 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1704                                    struct drm_crtc_state *state)
1705 {
1706         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1707
1708         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1709         kfree(s);
1710 }
1711
1712 static const struct drm_crtc_funcs vop_crtc_funcs = {
1713         .set_config = drm_atomic_helper_set_config,
1714         .page_flip = drm_atomic_helper_page_flip,
1715         .destroy = vop_crtc_destroy,
1716         .reset = vop_crtc_reset,
1717         .atomic_duplicate_state = vop_crtc_duplicate_state,
1718         .atomic_destroy_state = vop_crtc_destroy_state,
1719 };
1720
1721 static void vop_handle_vblank(struct vop *vop)
1722 {
1723         struct drm_device *drm = vop->drm_dev;
1724         struct drm_crtc *crtc = &vop->crtc;
1725         unsigned long flags;
1726
1727         if (!vop_is_cfg_done_complete(vop))
1728                 return;
1729
1730         if (vop->event) {
1731                 spin_lock_irqsave(&drm->event_lock, flags);
1732
1733                 drm_crtc_send_vblank_event(crtc, vop->event);
1734                 drm_crtc_vblank_put(crtc);
1735                 vop->event = NULL;
1736
1737                 spin_unlock_irqrestore(&drm->event_lock, flags);
1738         }
1739         if (!completion_done(&vop->wait_update_complete))
1740                 complete(&vop->wait_update_complete);
1741 }
1742
1743 static irqreturn_t vop_isr(int irq, void *data)
1744 {
1745         struct vop *vop = data;
1746         struct drm_crtc *crtc = &vop->crtc;
1747         uint32_t active_irqs;
1748         unsigned long flags;
1749         int ret = IRQ_NONE;
1750
1751         /*
1752          * interrupt register has interrupt status, enable and clear bits, we
1753          * must hold irq_lock to avoid a race with enable/disable_vblank().
1754         */
1755         spin_lock_irqsave(&vop->irq_lock, flags);
1756
1757         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1758         /* Clear all active interrupt sources */
1759         if (active_irqs)
1760                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1761
1762         spin_unlock_irqrestore(&vop->irq_lock, flags);
1763
1764         /* This is expected for vop iommu irqs, since the irq is shared */
1765         if (!active_irqs)
1766                 return IRQ_NONE;
1767
1768         if (active_irqs & DSP_HOLD_VALID_INTR) {
1769                 complete(&vop->dsp_hold_completion);
1770                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1771                 ret = IRQ_HANDLED;
1772         }
1773
1774         if (active_irqs & LINE_FLAG_INTR) {
1775                 complete(&vop->line_flag_completion);
1776                 active_irqs &= ~LINE_FLAG_INTR;
1777                 ret = IRQ_HANDLED;
1778         }
1779
1780         if (active_irqs & FS_INTR) {
1781                 drm_crtc_handle_vblank(crtc);
1782                 vop_handle_vblank(vop);
1783                 active_irqs &= ~FS_INTR;
1784                 ret = IRQ_HANDLED;
1785         }
1786
1787         /* Unhandled irqs are spurious. */
1788         if (active_irqs)
1789                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1790
1791         return ret;
1792 }
1793
1794 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1795                           unsigned long possible_crtcs)
1796 {
1797         struct drm_plane *share = NULL;
1798         unsigned int rotations = 0;
1799         struct drm_property *prop;
1800         uint64_t feature = 0;
1801         int ret;
1802
1803         if (win->parent)
1804                 share = &win->parent->base;
1805
1806         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1807                                    possible_crtcs, &vop_plane_funcs,
1808                                    win->data_formats, win->nformats, win->type);
1809         if (ret) {
1810                 DRM_ERROR("failed to initialize plane\n");
1811                 return ret;
1812         }
1813         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1814         drm_object_attach_property(&win->base.base,
1815                                    vop->plane_zpos_prop, win->win_id);
1816
1817         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1818                 rotations |= BIT(DRM_REFLECT_X);
1819
1820         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1821                 rotations |= BIT(DRM_REFLECT_Y);
1822
1823         if (rotations) {
1824                 rotations |= BIT(DRM_ROTATE_0);
1825                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1826                                                          rotations);
1827                 if (!prop) {
1828                         DRM_ERROR("failed to create zpos property\n");
1829                         return -EINVAL;
1830                 }
1831                 drm_object_attach_property(&win->base.base, prop,
1832                                            BIT(DRM_ROTATE_0));
1833                 win->rotation_prop = prop;
1834         }
1835         if (win->phy->scl)
1836                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1837         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1838             VOP_WIN_SUPPORT(vop, win, alpha_en))
1839                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1840
1841         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1842                                    feature);
1843
1844         return 0;
1845 }
1846
1847 static int vop_create_crtc(struct vop *vop)
1848 {
1849         struct device *dev = vop->dev;
1850         struct drm_device *drm_dev = vop->drm_dev;
1851         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1852         struct drm_crtc *crtc = &vop->crtc;
1853         struct device_node *port;
1854         uint64_t feature = 0;
1855         int ret;
1856         int i;
1857
1858         /*
1859          * Create drm_plane for primary and cursor planes first, since we need
1860          * to pass them to drm_crtc_init_with_planes, which sets the
1861          * "possible_crtcs" to the newly initialized crtc.
1862          */
1863         for (i = 0; i < vop->num_wins; i++) {
1864                 struct vop_win *win = &vop->win[i];
1865
1866                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1867                     win->type != DRM_PLANE_TYPE_CURSOR)
1868                         continue;
1869
1870                 ret = vop_plane_init(vop, win, 0);
1871                 if (ret)
1872                         goto err_cleanup_planes;
1873
1874                 plane = &win->base;
1875                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1876                         primary = plane;
1877                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1878                         cursor = plane;
1879
1880         }
1881
1882         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1883                                         &vop_crtc_funcs, NULL);
1884         if (ret)
1885                 goto err_cleanup_planes;
1886
1887         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1888
1889         /*
1890          * Create drm_planes for overlay windows with possible_crtcs restricted
1891          * to the newly created crtc.
1892          */
1893         for (i = 0; i < vop->num_wins; i++) {
1894                 struct vop_win *win = &vop->win[i];
1895                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1896
1897                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1898                         continue;
1899
1900                 ret = vop_plane_init(vop, win, possible_crtcs);
1901                 if (ret)
1902                         goto err_cleanup_crtc;
1903         }
1904
1905         port = of_get_child_by_name(dev->of_node, "port");
1906         if (!port) {
1907                 DRM_ERROR("no port node found in %s\n",
1908                           dev->of_node->full_name);
1909                 ret = -ENOENT;
1910                 goto err_cleanup_crtc;
1911         }
1912
1913         init_completion(&vop->dsp_hold_completion);
1914         init_completion(&vop->wait_update_complete);
1915         init_completion(&vop->line_flag_completion);
1916         crtc->port = port;
1917         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1918
1919         if (VOP_CTRL_SUPPORT(vop, afbdc_en))
1920                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
1921         drm_object_attach_property(&crtc->base, vop->feature_prop,
1922                                    feature);
1923
1924         return 0;
1925
1926 err_cleanup_crtc:
1927         drm_crtc_cleanup(crtc);
1928 err_cleanup_planes:
1929         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1930                                  head)
1931                 drm_plane_cleanup(plane);
1932         return ret;
1933 }
1934
1935 static void vop_destroy_crtc(struct vop *vop)
1936 {
1937         struct drm_crtc *crtc = &vop->crtc;
1938         struct drm_device *drm_dev = vop->drm_dev;
1939         struct drm_plane *plane, *tmp;
1940
1941         rockchip_unregister_crtc_funcs(crtc);
1942         of_node_put(crtc->port);
1943
1944         /*
1945          * We need to cleanup the planes now.  Why?
1946          *
1947          * The planes are "&vop->win[i].base".  That means the memory is
1948          * all part of the big "struct vop" chunk of memory.  That memory
1949          * was devm allocated and associated with this component.  We need to
1950          * free it ourselves before vop_unbind() finishes.
1951          */
1952         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1953                                  head)
1954                 vop_plane_destroy(plane);
1955
1956         /*
1957          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1958          * references the CRTC.
1959          */
1960         drm_crtc_cleanup(crtc);
1961 }
1962
1963 /*
1964  * Initialize the vop->win array elements.
1965  */
1966 static int vop_win_init(struct vop *vop)
1967 {
1968         const struct vop_data *vop_data = vop->data;
1969         unsigned int i, j;
1970         unsigned int num_wins = 0;
1971         struct drm_property *prop;
1972         static const struct drm_prop_enum_list props[] = {
1973                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1974                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1975         };
1976         static const struct drm_prop_enum_list crtc_props[] = {
1977                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
1978         };
1979
1980         for (i = 0; i < vop_data->win_size; i++) {
1981                 struct vop_win *vop_win = &vop->win[num_wins];
1982                 const struct vop_win_data *win_data = &vop_data->win[i];
1983
1984                 if (!win_data->phy)
1985                         continue;
1986
1987                 vop_win->phy = win_data->phy;
1988                 vop_win->csc = win_data->csc;
1989                 vop_win->offset = win_data->base;
1990                 vop_win->type = win_data->type;
1991                 vop_win->data_formats = win_data->phy->data_formats;
1992                 vop_win->nformats = win_data->phy->nformats;
1993                 vop_win->vop = vop;
1994                 vop_win->win_id = i;
1995                 vop_win->area_id = 0;
1996                 num_wins++;
1997
1998                 for (j = 0; j < win_data->area_size; j++) {
1999                         struct vop_win *vop_area = &vop->win[num_wins];
2000                         const struct vop_win_phy *area = win_data->area[j];
2001
2002                         vop_area->parent = vop_win;
2003                         vop_area->offset = vop_win->offset;
2004                         vop_area->phy = area;
2005                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2006                         vop_area->data_formats = vop_win->data_formats;
2007                         vop_area->nformats = vop_win->nformats;
2008                         vop_area->vop = vop;
2009                         vop_area->win_id = i;
2010                         vop_area->area_id = j;
2011                         num_wins++;
2012                 }
2013         }
2014
2015         vop->num_wins = num_wins;
2016
2017         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2018                                          "ZPOS", 0, vop->data->win_size);
2019         if (!prop) {
2020                 DRM_ERROR("failed to create zpos property\n");
2021                 return -EINVAL;
2022         }
2023         vop->plane_zpos_prop = prop;
2024
2025         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2026                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2027                                 props, ARRAY_SIZE(props),
2028                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2029                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2030         if (!vop->plane_feature_prop) {
2031                 DRM_ERROR("failed to create feature property\n");
2032                 return -EINVAL;
2033         }
2034
2035         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2036                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2037                                 props, ARRAY_SIZE(crtc_props),
2038                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2039         if (!vop->feature_prop) {
2040                 DRM_ERROR("failed to create vop feature property\n");
2041                 return -EINVAL;
2042         }
2043
2044         return 0;
2045 }
2046
2047 /**
2048  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2049  * @crtc: CRTC to enable line flag
2050  * @line_num: interested line number
2051  * @mstimeout: millisecond for timeout
2052  *
2053  * Driver would hold here until the interested line flag interrupt have
2054  * happened or timeout to wait.
2055  *
2056  * Returns:
2057  * Zero on success, negative errno on failure.
2058  */
2059 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2060                                 unsigned int mstimeout)
2061 {
2062         struct vop *vop = to_vop(crtc);
2063         unsigned long jiffies_left;
2064
2065         if (!crtc || !vop->is_enabled)
2066                 return -ENODEV;
2067
2068         if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2069                 return -EINVAL;
2070
2071         if (vop_line_flag_irq_is_enabled(vop))
2072                 return -EBUSY;
2073
2074         reinit_completion(&vop->line_flag_completion);
2075         vop_line_flag_irq_enable(vop, line_num);
2076
2077         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2078                                                    msecs_to_jiffies(mstimeout));
2079         vop_line_flag_irq_disable(vop);
2080
2081         if (jiffies_left == 0) {
2082                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2083                 return -ETIMEDOUT;
2084         }
2085
2086         return 0;
2087 }
2088 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2089
2090 static int vop_bind(struct device *dev, struct device *master, void *data)
2091 {
2092         struct platform_device *pdev = to_platform_device(dev);
2093         const struct vop_data *vop_data;
2094         struct drm_device *drm_dev = data;
2095         struct vop *vop;
2096         struct resource *res;
2097         size_t alloc_size;
2098         int ret, irq, i;
2099         int num_wins = 0;
2100
2101         vop_data = of_device_get_match_data(dev);
2102         if (!vop_data)
2103                 return -ENODEV;
2104
2105         for (i = 0; i < vop_data->win_size; i++) {
2106                 const struct vop_win_data *win_data = &vop_data->win[i];
2107
2108                 num_wins += win_data->area_size + 1;
2109         }
2110
2111         /* Allocate vop struct and its vop_win array */
2112         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2113         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2114         if (!vop)
2115                 return -ENOMEM;
2116
2117         vop->dev = dev;
2118         vop->data = vop_data;
2119         vop->drm_dev = drm_dev;
2120         vop->num_wins = num_wins;
2121         dev_set_drvdata(dev, vop);
2122
2123         ret = vop_win_init(vop);
2124         if (ret)
2125                 return ret;
2126
2127         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2128         vop->len = resource_size(res);
2129         vop->regs = devm_ioremap_resource(dev, res);
2130         if (IS_ERR(vop->regs))
2131                 return PTR_ERR(vop->regs);
2132
2133         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2134         if (!vop->regsbak)
2135                 return -ENOMEM;
2136
2137         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2138         if (IS_ERR(vop->hclk)) {
2139                 dev_err(vop->dev, "failed to get hclk source\n");
2140                 return PTR_ERR(vop->hclk);
2141         }
2142         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2143         if (IS_ERR(vop->aclk)) {
2144                 dev_err(vop->dev, "failed to get aclk source\n");
2145                 return PTR_ERR(vop->aclk);
2146         }
2147         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2148         if (IS_ERR(vop->dclk)) {
2149                 dev_err(vop->dev, "failed to get dclk source\n");
2150                 return PTR_ERR(vop->dclk);
2151         }
2152
2153         irq = platform_get_irq(pdev, 0);
2154         if (irq < 0) {
2155                 dev_err(dev, "cannot find irq for vop\n");
2156                 return irq;
2157         }
2158         vop->irq = (unsigned int)irq;
2159
2160         spin_lock_init(&vop->reg_lock);
2161         spin_lock_init(&vop->irq_lock);
2162
2163         mutex_init(&vop->vsync_mutex);
2164
2165         ret = devm_request_irq(dev, vop->irq, vop_isr,
2166                                IRQF_SHARED, dev_name(dev), vop);
2167         if (ret)
2168                 return ret;
2169
2170         /* IRQ is initially disabled; it gets enabled in power_on */
2171         disable_irq(vop->irq);
2172
2173         ret = vop_create_crtc(vop);
2174         if (ret)
2175                 return ret;
2176
2177         pm_runtime_enable(&pdev->dev);
2178         return 0;
2179 }
2180
2181 static void vop_unbind(struct device *dev, struct device *master, void *data)
2182 {
2183         struct vop *vop = dev_get_drvdata(dev);
2184
2185         pm_runtime_disable(dev);
2186         vop_destroy_crtc(vop);
2187 }
2188
2189 const struct component_ops vop_component_ops = {
2190         .bind = vop_bind,
2191         .unbind = vop_unbind,
2192 };
2193 EXPORT_SYMBOL_GPL(vop_component_ops);