drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33
  34 #include "rockchip_drm_drv.h"
  35 #include "rockchip_drm_gem.h"
  36 #include "rockchip_drm_fb.h"
  37 #include "rockchip_drm_vop.h"
  38
  39 #define VOP_REG(off, _mask, s) \
  40                 {.offset = off, \
  41                  .mask = _mask, \
  42                  .shift = s,}
  43
  44 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  45                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  46 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  47                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  48
  49 #define REG_SET(x, base, reg, v, mode) \
  50                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  51
  52 #define VOP_WIN_SET(x, win, name, v) \
  53                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  54 #define VOP_SCL_SET(x, win, name, v) \
  55                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  56 #define VOP_CTRL_SET(x, name, v) \
  57                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  58
  59 #define VOP_WIN_GET(x, win, name) \
  60                 vop_read_reg(x, win->base, &win->phy->name)
  61
  62 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  63                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  64
  65 #define to_vop(x) container_of(x, struct vop, crtc)
  66 #define to_vop_win(x) container_of(x, struct vop_win, base)
  67 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  68
  69 struct vop_plane_state {
  70         struct drm_plane_state base;
  71         int format;
  72         struct drm_rect src;
  73         struct drm_rect dest;
  74         dma_addr_t yrgb_mst;
  75         bool enable;
  76 };
  77
  78 struct vop_win {
  79         struct drm_plane base;
  80         const struct vop_win_data *data;
  81         struct vop *vop;
  82
  83         struct vop_plane_state state;
  84 };
  85
  86 struct vop {
  87         struct drm_crtc crtc;
  88         struct device *dev;
  89         struct drm_device *drm_dev;
  90         bool is_enabled;
  91
  92         int connector_type;
  93         int connector_out_mode;
  94
  95         /* mutex vsync_ work */
  96         struct mutex vsync_mutex;
  97         bool vsync_work_pending;
  98         struct completion dsp_hold_completion;
  99         struct completion wait_update_complete;
 100         struct drm_pending_vblank_event *event;
 101
 102         const struct vop_data *data;
 103
 104         uint32_t *regsbak;
 105         void __iomem *regs;
 106
 107         /* physical map length of vop register */
 108         uint32_t len;
 109
 110         /* one time only one process allowed to config the register */
 111         spinlock_t reg_lock;
 112         /* lock vop irq reg */
 113         spinlock_t irq_lock;
 114
 115         unsigned int irq;
 116
 117         /* vop AHP clk */
 118         struct clk *hclk;
 119         /* vop dclk */
 120         struct clk *dclk;
 121         /* vop share memory frequency */
 122         struct clk *aclk;
 123
 124         /* vop dclk reset */
 125         struct reset_control *dclk_rst;
 126
 127         struct vop_win win[];
 128 };
 129
 130 enum vop_data_format {
 131         VOP_FMT_ARGB8888 = 0,
 132         VOP_FMT_RGB888,
 133         VOP_FMT_RGB565,
 134         VOP_FMT_YUV420SP = 4,
 135         VOP_FMT_YUV422SP,
 136         VOP_FMT_YUV444SP,
 137 };
 138
 139 struct vop_reg_data {
 140         uint32_t offset;
 141         uint32_t value;
 142 };
 143
 144 struct vop_reg {
 145         uint32_t offset;
 146         uint32_t shift;
 147         uint32_t mask;
 148 };
 149
 150 struct vop_ctrl {
 151         struct vop_reg standby;
 152         struct vop_reg data_blank;
 153         struct vop_reg gate_en;
 154         struct vop_reg mmu_en;
 155         struct vop_reg rgb_en;
 156         struct vop_reg edp_en;
 157         struct vop_reg hdmi_en;
 158         struct vop_reg mipi_en;
 159         struct vop_reg out_mode;
 160         struct vop_reg dither_down;
 161         struct vop_reg dither_up;
 162         struct vop_reg pin_pol;
 163
 164         struct vop_reg htotal_pw;
 165         struct vop_reg hact_st_end;
 166         struct vop_reg vtotal_pw;
 167         struct vop_reg vact_st_end;
 168         struct vop_reg hpost_st_end;
 169         struct vop_reg vpost_st_end;
 170 };
 171
 172 struct vop_scl_regs {
 173         struct vop_reg cbcr_vsd_mode;
 174         struct vop_reg cbcr_vsu_mode;
 175         struct vop_reg cbcr_hsd_mode;
 176         struct vop_reg cbcr_ver_scl_mode;
 177         struct vop_reg cbcr_hor_scl_mode;
 178         struct vop_reg yrgb_vsd_mode;
 179         struct vop_reg yrgb_vsu_mode;
 180         struct vop_reg yrgb_hsd_mode;
 181         struct vop_reg yrgb_ver_scl_mode;
 182         struct vop_reg yrgb_hor_scl_mode;
 183         struct vop_reg line_load_mode;
 184         struct vop_reg cbcr_axi_gather_num;
 185         struct vop_reg yrgb_axi_gather_num;
 186         struct vop_reg vsd_cbcr_gt2;
 187         struct vop_reg vsd_cbcr_gt4;
 188         struct vop_reg vsd_yrgb_gt2;
 189         struct vop_reg vsd_yrgb_gt4;
 190         struct vop_reg bic_coe_sel;
 191         struct vop_reg cbcr_axi_gather_en;
 192         struct vop_reg yrgb_axi_gather_en;
 193
 194         struct vop_reg lb_mode;
 195         struct vop_reg scale_yrgb_x;
 196         struct vop_reg scale_yrgb_y;
 197         struct vop_reg scale_cbcr_x;
 198         struct vop_reg scale_cbcr_y;
 199 };
 200
 201 struct vop_win_phy {
 202         const struct vop_scl_regs *scl;
 203         const uint32_t *data_formats;
 204         uint32_t nformats;
 205
 206         struct vop_reg enable;
 207         struct vop_reg format;
 208         struct vop_reg rb_swap;
 209         struct vop_reg act_info;
 210         struct vop_reg dsp_info;
 211         struct vop_reg dsp_st;
 212         struct vop_reg yrgb_mst;
 213         struct vop_reg uv_mst;
 214         struct vop_reg yrgb_vir;
 215         struct vop_reg uv_vir;
 216
 217         struct vop_reg dst_alpha_ctl;
 218         struct vop_reg src_alpha_ctl;
 219 };
 220
 221 struct vop_win_data {
 222         uint32_t base;
 223         const struct vop_win_phy *phy;
 224         enum drm_plane_type type;
 225 };
 226
 227 struct vop_data {
 228         const struct vop_reg_data *init_table;
 229         unsigned int table_size;
 230         const struct vop_ctrl *ctrl;
 231         const struct vop_win_data *win;
 232         unsigned int win_size;
 233 };
 234
 235 static const uint32_t formats_01[] = {
 236         DRM_FORMAT_XRGB8888,
 237         DRM_FORMAT_ARGB8888,
 238         DRM_FORMAT_XBGR8888,
 239         DRM_FORMAT_ABGR8888,
 240         DRM_FORMAT_RGB888,
 241         DRM_FORMAT_BGR888,
 242         DRM_FORMAT_RGB565,
 243         DRM_FORMAT_BGR565,
 244         DRM_FORMAT_NV12,
 245         DRM_FORMAT_NV16,
 246         DRM_FORMAT_NV24,
 247 };
 248
 249 static const uint32_t formats_234[] = {
 250         DRM_FORMAT_XRGB8888,
 251         DRM_FORMAT_ARGB8888,
 252         DRM_FORMAT_XBGR8888,
 253         DRM_FORMAT_ABGR8888,
 254         DRM_FORMAT_RGB888,
 255         DRM_FORMAT_BGR888,
 256         DRM_FORMAT_RGB565,
 257         DRM_FORMAT_BGR565,
 258 };
 259
 260 static const struct vop_scl_regs win_full_scl = {
 261         .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
 262         .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
 263         .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
 264         .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
 265         .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
 266         .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
 267         .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
 268         .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
 269         .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
 270         .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
 271         .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
 272         .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
 273         .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
 274         .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
 275         .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
 276         .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
 277         .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
 278         .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
 279         .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
 280         .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
 281         .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
 282         .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 283         .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 284         .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 285         .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 286 };
 287
 288 static const struct vop_win_phy win01_data = {
 289         .scl = &win_full_scl,
 290         .data_formats = formats_01,
 291         .nformats = ARRAY_SIZE(formats_01),
 292         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 293         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 294         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
 295         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 296         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 297         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 298         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 299         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 300         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 301         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 302         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 303         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 304 };
 305
 306 static const struct vop_win_phy win23_data = {
 307         .data_formats = formats_234,
 308         .nformats = ARRAY_SIZE(formats_234),
 309         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 310         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 311         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 312         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 313         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 314         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 315         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 316         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 317         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 318 };
 319
 320 static const struct vop_ctrl ctrl_data = {
 321         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 322         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 323         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 324         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 325         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 326         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 327         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 328         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 329         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 330         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 331         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 332         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 333         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 334         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 335         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 336         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 337         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 338         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 339 };
 340
 341 static const struct vop_reg_data vop_init_reg_table[] = {
 342         {SYS_CTRL, 0x00c00000},
 343         {DSP_CTRL0, 0x00000000},
 344         {WIN0_CTRL0, 0x00000080},
 345         {WIN1_CTRL0, 0x00000080},
 346         /* TODO: Win2/3 support multiple area function, but we haven't found
 347          * a suitable way to use it yet, so let's just use them as other windows
 348          * with only area 0 enabled.
 349          */
 350         {WIN2_CTRL0, 0x00000010},
 351         {WIN3_CTRL0, 0x00000010},
 352 };
 353
 354 /*
 355  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 356  * special support to get alpha blending working.  For now, just use overlay
 357  * window 3 for the drm cursor.
 358  *
 359  */
 360 static const struct vop_win_data rk3288_vop_win_data[] = {
 361         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 362         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 363         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 364         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 365 };
 366
 367 static const struct vop_data rk3288_vop = {
 368         .init_table = vop_init_reg_table,
 369         .table_size = ARRAY_SIZE(vop_init_reg_table),
 370         .ctrl = &ctrl_data,
 371         .win = rk3288_vop_win_data,
 372         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 373 };
 374
 375 static const struct of_device_id vop_driver_dt_match[] = {
 376         { .compatible = "rockchip,rk3288-vop",
 377           .data = &rk3288_vop },
 378         {},
 379 };
 380 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 381
 382 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 383 {
 384         writel(v, vop->regs + offset);
 385         vop->regsbak[offset >> 2] = v;
 386 }
 387
 388 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 389 {
 390         return readl(vop->regs + offset);
 391 }
 392
 393 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 394                                     const struct vop_reg *reg)
 395 {
 396         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 397 }
 398
 399 static inline void vop_cfg_done(struct vop *vop)
 400 {
 401         writel(0x01, vop->regs + REG_CFG_DONE);
 402 }
 403
 404 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 405                                   uint32_t mask, uint32_t v)
 406 {
 407         if (mask) {
 408                 uint32_t cached_val = vop->regsbak[offset >> 2];
 409
 410                 cached_val = (cached_val & ~mask) | v;
 411                 writel(cached_val, vop->regs + offset);
 412                 vop->regsbak[offset >> 2] = cached_val;
 413         }
 414 }
 415
 416 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 417                                           uint32_t mask, uint32_t v)
 418 {
 419         if (mask) {
 420                 uint32_t cached_val = vop->regsbak[offset >> 2];
 421
 422                 cached_val = (cached_val & ~mask) | v;
 423                 writel_relaxed(cached_val, vop->regs + offset);
 424                 vop->regsbak[offset >> 2] = cached_val;
 425         }
 426 }
 427
 428 static bool has_rb_swapped(uint32_t format)
 429 {
 430         switch (format) {
 431         case DRM_FORMAT_XBGR8888:
 432         case DRM_FORMAT_ABGR8888:
 433         case DRM_FORMAT_BGR888:
 434         case DRM_FORMAT_BGR565:
 435                 return true;
 436         default:
 437                 return false;
 438         }
 439 }
 440
 441 static enum vop_data_format vop_convert_format(uint32_t format)
 442 {
 443         switch (format) {
 444         case DRM_FORMAT_XRGB8888:
 445         case DRM_FORMAT_ARGB8888:
 446         case DRM_FORMAT_XBGR8888:
 447         case DRM_FORMAT_ABGR8888:
 448                 return VOP_FMT_ARGB8888;
 449         case DRM_FORMAT_RGB888:
 450         case DRM_FORMAT_BGR888:
 451                 return VOP_FMT_RGB888;
 452         case DRM_FORMAT_RGB565:
 453         case DRM_FORMAT_BGR565:
 454                 return VOP_FMT_RGB565;
 455         case DRM_FORMAT_NV12:
 456                 return VOP_FMT_YUV420SP;
 457         case DRM_FORMAT_NV16:
 458                 return VOP_FMT_YUV422SP;
 459         case DRM_FORMAT_NV24:
 460                 return VOP_FMT_YUV444SP;
 461         default:
 462                 DRM_ERROR("unsupport format[%08x]\n", format);
 463                 return -EINVAL;
 464         }
 465 }
 466
 467 static bool is_yuv_support(uint32_t format)
 468 {
 469         switch (format) {
 470         case DRM_FORMAT_NV12:
 471         case DRM_FORMAT_NV16:
 472         case DRM_FORMAT_NV24:
 473                 return true;
 474         default:
 475                 return false;
 476         }
 477 }
 478
 479 static bool is_alpha_support(uint32_t format)
 480 {
 481         switch (format) {
 482         case DRM_FORMAT_ARGB8888:
 483         case DRM_FORMAT_ABGR8888:
 484                 return true;
 485         default:
 486                 return false;
 487         }
 488 }
 489
 490 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 491                                   uint32_t dst, bool is_horizontal,
 492                                   int vsu_mode, int *vskiplines)
 493 {
 494         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 495
 496         if (is_horizontal) {
 497                 if (mode == SCALE_UP)
 498                         val = GET_SCL_FT_BIC(src, dst);
 499                 else if (mode == SCALE_DOWN)
 500                         val = GET_SCL_FT_BILI_DN(src, dst);
 501         } else {
 502                 if (mode == SCALE_UP) {
 503                         if (vsu_mode == SCALE_UP_BIL)
 504                                 val = GET_SCL_FT_BILI_UP(src, dst);
 505                         else
 506                                 val = GET_SCL_FT_BIC(src, dst);
 507                 } else if (mode == SCALE_DOWN) {
 508                         if (vskiplines) {
 509                                 *vskiplines = scl_get_vskiplines(src, dst);
 510                                 val = scl_get_bili_dn_vskip(src, dst,
 511                                                             *vskiplines);
 512                         } else {
 513                                 val = GET_SCL_FT_BILI_DN(src, dst);
 514                         }
 515                 }
 516         }
 517
 518         return val;
 519 }
 520
 521 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 522                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 523                              uint32_t dst_h, uint32_t pixel_format)
 524 {
 525         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 526         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 527         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 528         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 529         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 530         bool is_yuv = is_yuv_support(pixel_format);
 531         uint16_t cbcr_src_w = src_w / hsub;
 532         uint16_t cbcr_src_h = src_h / vsub;
 533         uint16_t vsu_mode;
 534         uint16_t lb_mode;
 535         uint32_t val;
 536         int vskiplines;
 537
 538         if (dst_w > 3840) {
 539                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 540                 return;
 541         }
 542
 543         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 544         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 545
 546         if (is_yuv) {
 547                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 548                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 549                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 550                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 551                 else
 552                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 553         } else {
 554                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 555                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 556                 else
 557                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 558         }
 559
 560         VOP_SCL_SET(vop, win, lb_mode, lb_mode);
 561         if (lb_mode == LB_RGB_3840X2) {
 562                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 563                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 564                         return;
 565                 }
 566                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 567                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 568                         return;
 569                 }
 570                 vsu_mode = SCALE_UP_BIL;
 571         } else if (lb_mode == LB_RGB_2560X4) {
 572                 vsu_mode = SCALE_UP_BIL;
 573         } else {
 574                 vsu_mode = SCALE_UP_BIC;
 575         }
 576
 577         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 578                                 true, 0, NULL);
 579         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 580         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 581                                 false, vsu_mode, &vskiplines);
 582         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 583
 584         VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 585         VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 586
 587         VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 588         VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 589         VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 590         VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 591         VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
 592         if (is_yuv) {
 593                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 594                                         dst_w, true, 0, NULL);
 595                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 596                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 597                                         dst_h, false, vsu_mode, &vskiplines);
 598                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 599
 600                 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 601                 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 602                 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 603                 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 604                 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 605                 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 606                 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
 607         }
 608 }
 609
 610 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 611 {
 612         unsigned long flags;
 613
 614         if (WARN_ON(!vop->is_enabled))
 615                 return;
 616
 617         spin_lock_irqsave(&vop->irq_lock, flags);
 618
 619         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 620                        DSP_HOLD_VALID_INTR_EN(1));
 621
 622         spin_unlock_irqrestore(&vop->irq_lock, flags);
 623 }
 624
 625 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 626 {
 627         unsigned long flags;
 628
 629         if (WARN_ON(!vop->is_enabled))
 630                 return;
 631
 632         spin_lock_irqsave(&vop->irq_lock, flags);
 633
 634         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 635                        DSP_HOLD_VALID_INTR_EN(0));
 636
 637         spin_unlock_irqrestore(&vop->irq_lock, flags);
 638 }
 639
 640 static void vop_enable(struct drm_crtc *crtc)
 641 {
 642         struct vop *vop = to_vop(crtc);
 643         int ret;
 644
 645         if (vop->is_enabled)
 646                 return;
 647
 648         ret = pm_runtime_get_sync(vop->dev);
 649         if (ret < 0) {
 650                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 651                 return;
 652         }
 653
 654         ret = clk_enable(vop->hclk);
 655         if (ret < 0) {
 656                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 657                 return;
 658         }
 659
 660         ret = clk_enable(vop->dclk);
 661         if (ret < 0) {
 662                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 663                 goto err_disable_hclk;
 664         }
 665
 666         ret = clk_enable(vop->aclk);
 667         if (ret < 0) {
 668                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 669                 goto err_disable_dclk;
 670         }
 671
 672         /*
 673          * Slave iommu shares power, irq and clock with vop.  It was associated
 674          * automatically with this master device via common driver code.
 675          * Now that we have enabled the clock we attach it to the shared drm
 676          * mapping.
 677          */
 678         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 679         if (ret) {
 680                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 681                 goto err_disable_aclk;
 682         }
 683
 684         memcpy(vop->regs, vop->regsbak, vop->len);
 685         /*
 686          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 687          */
 688         vop->is_enabled = true;
 689
 690         spin_lock(&vop->reg_lock);
 691
 692         VOP_CTRL_SET(vop, standby, 0);
 693
 694         spin_unlock(&vop->reg_lock);
 695
 696         enable_irq(vop->irq);
 697
 698         drm_crtc_vblank_on(crtc);
 699
 700         return;
 701
 702 err_disable_aclk:
 703         clk_disable(vop->aclk);
 704 err_disable_dclk:
 705         clk_disable(vop->dclk);
 706 err_disable_hclk:
 707         clk_disable(vop->hclk);
 708 }
 709
 710 static void vop_crtc_disable(struct drm_crtc *crtc)
 711 {
 712         struct vop *vop = to_vop(crtc);
 713
 714         if (!vop->is_enabled)
 715                 return;
 716
 717         drm_crtc_vblank_off(crtc);
 718
 719         /*
 720          * Vop standby will take effect at end of current frame,
 721          * if dsp hold valid irq happen, it means standby complete.
 722          *
 723          * we must wait standby complete when we want to disable aclk,
 724          * if not, memory bus maybe dead.
 725          */
 726         reinit_completion(&vop->dsp_hold_completion);
 727         vop_dsp_hold_valid_irq_enable(vop);
 728
 729         spin_lock(&vop->reg_lock);
 730
 731         VOP_CTRL_SET(vop, standby, 1);
 732
 733         spin_unlock(&vop->reg_lock);
 734
 735         wait_for_completion(&vop->dsp_hold_completion);
 736
 737         vop_dsp_hold_valid_irq_disable(vop);
 738
 739         disable_irq(vop->irq);
 740
 741         vop->is_enabled = false;
 742
 743         /*
 744          * vop standby complete, so iommu detach is safe.
 745          */
 746         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 747
 748         clk_disable(vop->dclk);
 749         clk_disable(vop->aclk);
 750         clk_disable(vop->hclk);
 751         pm_runtime_put(vop->dev);
 752 }
 753
 754 static void vop_plane_destroy(struct drm_plane *plane)
 755 {
 756         drm_plane_cleanup(plane);
 757 }
 758
 759 static int vop_plane_atomic_check(struct drm_plane *plane,
 760                            struct drm_plane_state *state)
 761 {
 762         struct drm_crtc *crtc = state->crtc;
 763         struct drm_framebuffer *fb = state->fb;
 764         struct vop_win *vop_win = to_vop_win(plane);
 765         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 766         const struct vop_win_data *win = vop_win->data;
 767         bool visible;
 768         int ret;
 769         struct drm_rect *dest = &vop_plane_state->dest;
 770         struct drm_rect *src = &vop_plane_state->src;
 771         struct drm_rect clip;
 772         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 773                                         DRM_PLANE_HELPER_NO_SCALING;
 774         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 775                                         DRM_PLANE_HELPER_NO_SCALING;
 776
 777         crtc = crtc ? crtc : plane->state->crtc;
 778         /*
 779          * Both crtc or plane->state->crtc can be null.
 780          */
 781         if (!crtc || !fb)
 782                 goto out_disable;
 783         src->x1 = state->src_x;
 784         src->y1 = state->src_y;
 785         src->x2 = state->src_x + state->src_w;
 786         src->y2 = state->src_y + state->src_h;
 787         dest->x1 = state->crtc_x;
 788         dest->y1 = state->crtc_y;
 789         dest->x2 = state->crtc_x + state->crtc_w;
 790         dest->y2 = state->crtc_y + state->crtc_h;
 791
 792         clip.x1 = 0;
 793         clip.y1 = 0;
 794         clip.x2 = crtc->mode.hdisplay;
 795         clip.y2 = crtc->mode.vdisplay;
 796
 797         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 798                                             src, dest, &clip,
 799                                             min_scale,
 800                                             max_scale,
 801                                             true, true, &visible);
 802         if (ret)
 803                 return ret;
 804
 805         if (!visible)
 806                 goto out_disable;
 807
 808         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 809         if (vop_plane_state->format < 0)
 810                 return vop_plane_state->format;
 811
 812         /*
 813          * Src.x1 can be odd when do clip, but yuv plane start point
 814          * need align with 2 pixel.
 815          */
 816         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 817                 return -EINVAL;
 818
 819         vop_plane_state->enable = true;
 820
 821         return 0;
 822
 823 out_disable:
 824         vop_plane_state->enable = false;
 825         return 0;
 826 }
 827
 828 static void vop_plane_atomic_disable(struct drm_plane *plane,
 829                                      struct drm_plane_state *old_state)
 830 {
 831         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 832         struct vop_win *vop_win = to_vop_win(plane);
 833         const struct vop_win_data *win = vop_win->data;
 834         struct vop *vop = to_vop(old_state->crtc);
 835
 836         if (!old_state->crtc)
 837                 return;
 838
 839         spin_lock(&vop->reg_lock);
 840
 841         VOP_WIN_SET(vop, win, enable, 0);
 842
 843         spin_unlock(&vop->reg_lock);
 844
 845         vop_plane_state->enable = false;
 846 }
 847
 848 static void vop_plane_atomic_update(struct drm_plane *plane,
 849                 struct drm_plane_state *old_state)
 850 {
 851         struct drm_plane_state *state = plane->state;
 852         struct drm_crtc *crtc = state->crtc;
 853         struct vop_win *vop_win = to_vop_win(plane);
 854         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 855         const struct vop_win_data *win = vop_win->data;
 856         struct vop *vop = to_vop(state->crtc);
 857         struct drm_framebuffer *fb = state->fb;
 858         unsigned int actual_w, actual_h;
 859         unsigned int dsp_stx, dsp_sty;
 860         uint32_t act_info, dsp_info, dsp_st;
 861         struct drm_rect *src = &vop_plane_state->src;
 862         struct drm_rect *dest = &vop_plane_state->dest;
 863         struct drm_gem_object *obj, *uv_obj;
 864         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 865         unsigned long offset;
 866         dma_addr_t dma_addr;
 867         uint32_t val;
 868         bool rb_swap;
 869
 870         /*
 871          * can't update plane when vop is disabled.
 872          */
 873         if (!crtc)
 874                 return;
 875
 876         if (WARN_ON(!vop->is_enabled))
 877                 return;
 878
 879         if (!vop_plane_state->enable) {
 880                 vop_plane_atomic_disable(plane, old_state);
 881                 return;
 882         }
 883
 884         obj = rockchip_fb_get_gem_obj(fb, 0);
 885         rk_obj = to_rockchip_obj(obj);
 886
 887         actual_w = drm_rect_width(src) >> 16;
 888         actual_h = drm_rect_height(src) >> 16;
 889         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 890
 891         dsp_info = (drm_rect_height(dest) - 1) << 16;
 892         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 893
 894         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 895         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 896         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 897
 898         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 899         offset += (src->y1 >> 16) * fb->pitches[0];
 900         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 901
 902         spin_lock(&vop->reg_lock);
 903
 904         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 905         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 906         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 907         if (is_yuv_support(fb->pixel_format)) {
 908                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 909                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 910                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 911
 912                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 913                 rk_uv_obj = to_rockchip_obj(uv_obj);
 914
 915                 offset = (src->x1 >> 16) * bpp / hsub;
 916                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 917
 918                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 919                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 920                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 921         }
 922
 923         if (win->phy->scl)
 924                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 925                                     drm_rect_width(dest), drm_rect_height(dest),
 926                                     fb->pixel_format);
 927
 928         VOP_WIN_SET(vop, win, act_info, act_info);
 929         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 930         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 931
 932         rb_swap = has_rb_swapped(fb->pixel_format);
 933         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 934
 935         if (is_alpha_support(fb->pixel_format)) {
 936                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 937                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 938                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 939                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 940                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 941                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 942                         SRC_FACTOR_M0(ALPHA_ONE);
 943                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 944         } else {
 945                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 946         }
 947
 948         VOP_WIN_SET(vop, win, enable, 1);
 949         spin_unlock(&vop->reg_lock);
 950 }
 951
 952 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 953         .atomic_check = vop_plane_atomic_check,
 954         .atomic_update = vop_plane_atomic_update,
 955         .atomic_disable = vop_plane_atomic_disable,
 956 };
 957
 958 void vop_atomic_plane_reset(struct drm_plane *plane)
 959 {
 960         struct vop_plane_state *vop_plane_state =
 961                                         to_vop_plane_state(plane->state);
 962
 963         if (plane->state && plane->state->fb)
 964                 drm_framebuffer_unreference(plane->state->fb);
 965
 966         kfree(vop_plane_state);
 967         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 968         if (!vop_plane_state)
 969                 return;
 970
 971         plane->state = &vop_plane_state->base;
 972         plane->state->plane = plane;
 973 }
 974
 975 struct drm_plane_state *
 976 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 977 {
 978         struct vop_plane_state *old_vop_plane_state;
 979         struct vop_plane_state *vop_plane_state;
 980
 981         if (WARN_ON(!plane->state))
 982                 return NULL;
 983
 984         old_vop_plane_state = to_vop_plane_state(plane->state);
 985         vop_plane_state = kmemdup(old_vop_plane_state,
 986                                   sizeof(*vop_plane_state), GFP_KERNEL);
 987         if (!vop_plane_state)
 988                 return NULL;
 989
 990         __drm_atomic_helper_plane_duplicate_state(plane,
 991                                                   &vop_plane_state->base);
 992
 993         return &vop_plane_state->base;
 994 }
 995
 996 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 997                                            struct drm_plane_state *state)
 998 {
 999         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1000
1001         __drm_atomic_helper_plane_destroy_state(plane, state);
1002
1003         kfree(vop_state);
1004 }
1005
1006 static const struct drm_plane_funcs vop_plane_funcs = {
1007         .update_plane   = drm_atomic_helper_update_plane,
1008         .disable_plane  = drm_atomic_helper_disable_plane,
1009         .destroy = vop_plane_destroy,
1010         .reset = vop_atomic_plane_reset,
1011         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1012         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1013 };
1014
1015 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1016                                   int connector_type,
1017                                   int out_mode)
1018 {
1019         struct vop *vop = to_vop(crtc);
1020
1021         vop->connector_type = connector_type;
1022         vop->connector_out_mode = out_mode;
1023
1024         return 0;
1025 }
1026 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
1027
1028 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1029 {
1030         struct vop *vop = to_vop(crtc);
1031         unsigned long flags;
1032
1033         if (WARN_ON(!vop->is_enabled))
1034                 return -EPERM;
1035
1036         spin_lock_irqsave(&vop->irq_lock, flags);
1037
1038         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
1039
1040         spin_unlock_irqrestore(&vop->irq_lock, flags);
1041
1042         return 0;
1043 }
1044
1045 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1046 {
1047         struct vop *vop = to_vop(crtc);
1048         unsigned long flags;
1049
1050         if (WARN_ON(!vop->is_enabled))
1051                 return;
1052
1053         spin_lock_irqsave(&vop->irq_lock, flags);
1054         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
1055         spin_unlock_irqrestore(&vop->irq_lock, flags);
1056 }
1057
1058 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1059 {
1060         struct vop *vop = to_vop(crtc);
1061
1062         reinit_completion(&vop->wait_update_complete);
1063         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1064 }
1065
1066 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1067         .enable_vblank = vop_crtc_enable_vblank,
1068         .disable_vblank = vop_crtc_disable_vblank,
1069         .wait_for_update = vop_crtc_wait_for_update,
1070 };
1071
1072 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1073                                 const struct drm_display_mode *mode,
1074                                 struct drm_display_mode *adjusted_mode)
1075 {
1076         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1077                 return false;
1078
1079         return true;
1080 }
1081
1082 static void vop_crtc_enable(struct drm_crtc *crtc)
1083 {
1084         struct vop *vop = to_vop(crtc);
1085         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1086         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1087         u16 hdisplay = adjusted_mode->hdisplay;
1088         u16 htotal = adjusted_mode->htotal;
1089         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1090         u16 hact_end = hact_st + hdisplay;
1091         u16 vdisplay = adjusted_mode->vdisplay;
1092         u16 vtotal = adjusted_mode->vtotal;
1093         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1094         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1095         u16 vact_end = vact_st + vdisplay;
1096         uint32_t val;
1097
1098         vop_enable(crtc);
1099         /*
1100          * If dclk rate is zero, mean that scanout is stop,
1101          * we don't need wait any more.
1102          */
1103         if (clk_get_rate(vop->dclk)) {
1104                 /*
1105                  * Rk3288 vop timing register is immediately, when configure
1106                  * display timing on display time, may cause tearing.
1107                  *
1108                  * Vop standby will take effect at end of current frame,
1109                  * if dsp hold valid irq happen, it means standby complete.
1110                  *
1111                  * mode set:
1112                  *    standby and wait complete --> |----
1113                  *                                  | display time
1114                  *                                  |----
1115                  *                                  |---> dsp hold irq
1116                  *     configure display timing --> |
1117                  *         standby exit             |
1118                  *                                  | new frame start.
1119                  */
1120
1121                 reinit_completion(&vop->dsp_hold_completion);
1122                 vop_dsp_hold_valid_irq_enable(vop);
1123
1124                 spin_lock(&vop->reg_lock);
1125
1126                 VOP_CTRL_SET(vop, standby, 1);
1127
1128                 spin_unlock(&vop->reg_lock);
1129
1130                 wait_for_completion(&vop->dsp_hold_completion);
1131
1132                 vop_dsp_hold_valid_irq_disable(vop);
1133         }
1134
1135         switch (vop->connector_type) {
1136         case DRM_MODE_CONNECTOR_LVDS:
1137                 VOP_CTRL_SET(vop, rgb_en, 1);
1138                 break;
1139         case DRM_MODE_CONNECTOR_eDP:
1140                 VOP_CTRL_SET(vop, edp_en, 1);
1141                 break;
1142         case DRM_MODE_CONNECTOR_HDMIA:
1143                 VOP_CTRL_SET(vop, hdmi_en, 1);
1144                 break;
1145         default:
1146                 DRM_ERROR("unsupport connector_type[%d]\n",
1147                           vop->connector_type);
1148         };
1149         VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
1150
1151         val = 0x8;
1152         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1153         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1154         VOP_CTRL_SET(vop, pin_pol, val);
1155
1156         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1157         val = hact_st << 16;
1158         val |= hact_end;
1159         VOP_CTRL_SET(vop, hact_st_end, val);
1160         VOP_CTRL_SET(vop, hpost_st_end, val);
1161
1162         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1163         val = vact_st << 16;
1164         val |= vact_end;
1165         VOP_CTRL_SET(vop, vact_st_end, val);
1166         VOP_CTRL_SET(vop, vpost_st_end, val);
1167
1168         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1169
1170         VOP_CTRL_SET(vop, standby, 0);
1171 }
1172
1173 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1174                                   struct drm_crtc_state *old_crtc_state)
1175 {
1176         struct vop *vop = to_vop(crtc);
1177
1178         if (WARN_ON(!vop->is_enabled))
1179                 return;
1180
1181         spin_lock(&vop->reg_lock);
1182
1183         vop_cfg_done(vop);
1184
1185         spin_unlock(&vop->reg_lock);
1186 }
1187
1188 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1189                                   struct drm_crtc_state *old_crtc_state)
1190 {
1191         struct vop *vop = to_vop(crtc);
1192
1193         if (crtc->state->event) {
1194                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1195
1196                 vop->event = crtc->state->event;
1197                 crtc->state->event = NULL;
1198         }
1199 }
1200
1201 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1202         .enable = vop_crtc_enable,
1203         .disable = vop_crtc_disable,
1204         .mode_fixup = vop_crtc_mode_fixup,
1205         .atomic_flush = vop_crtc_atomic_flush,
1206         .atomic_begin = vop_crtc_atomic_begin,
1207 };
1208
1209 static void vop_crtc_destroy(struct drm_crtc *crtc)
1210 {
1211         drm_crtc_cleanup(crtc);
1212 }
1213
1214 static const struct drm_crtc_funcs vop_crtc_funcs = {
1215         .set_config = drm_atomic_helper_set_config,
1216         .page_flip = drm_atomic_helper_page_flip,
1217         .destroy = vop_crtc_destroy,
1218         .reset = drm_atomic_helper_crtc_reset,
1219         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1220         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1221 };
1222
1223 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1224 {
1225         struct drm_plane *plane = &vop_win->base;
1226         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1227         dma_addr_t yrgb_mst;
1228
1229         if (!state->enable)
1230                 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1231
1232         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1233
1234         return yrgb_mst == state->yrgb_mst;
1235 }
1236
1237 static void vop_handle_vblank(struct vop *vop)
1238 {
1239         struct drm_device *drm = vop->drm_dev;
1240         struct drm_crtc *crtc = &vop->crtc;
1241         unsigned long flags;
1242         int i;
1243
1244         for (i = 0; i < vop->data->win_size; i++) {
1245                 if (!vop_win_pending_is_complete(&vop->win[i]))
1246                         return;
1247         }
1248
1249         if (vop->event) {
1250                 spin_lock_irqsave(&drm->event_lock, flags);
1251
1252                 drm_crtc_send_vblank_event(crtc, vop->event);
1253                 drm_crtc_vblank_put(crtc);
1254                 vop->event = NULL;
1255
1256                 spin_unlock_irqrestore(&drm->event_lock, flags);
1257         }
1258         if (!completion_done(&vop->wait_update_complete))
1259                 complete(&vop->wait_update_complete);
1260 }
1261
1262 static irqreturn_t vop_isr(int irq, void *data)
1263 {
1264         struct vop *vop = data;
1265         struct drm_crtc *crtc = &vop->crtc;
1266         uint32_t intr0_reg, active_irqs;
1267         unsigned long flags;
1268         int ret = IRQ_NONE;
1269
1270         /*
1271          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1272          * must hold irq_lock to avoid a race with enable/disable_vblank().
1273         */
1274         spin_lock_irqsave(&vop->irq_lock, flags);
1275         intr0_reg = vop_readl(vop, INTR_CTRL0);
1276         active_irqs = intr0_reg & INTR_MASK;
1277         /* Clear all active interrupt sources */
1278         if (active_irqs)
1279                 vop_writel(vop, INTR_CTRL0,
1280                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1281         spin_unlock_irqrestore(&vop->irq_lock, flags);
1282
1283         /* This is expected for vop iommu irqs, since the irq is shared */
1284         if (!active_irqs)
1285                 return IRQ_NONE;
1286
1287         if (active_irqs & DSP_HOLD_VALID_INTR) {
1288                 complete(&vop->dsp_hold_completion);
1289                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1290                 ret = IRQ_HANDLED;
1291         }
1292
1293         if (active_irqs & FS_INTR) {
1294                 drm_crtc_handle_vblank(crtc);
1295                 vop_handle_vblank(vop);
1296                 active_irqs &= ~FS_INTR;
1297                 ret = IRQ_HANDLED;
1298         }
1299
1300         /* Unhandled irqs are spurious. */
1301         if (active_irqs)
1302                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1303
1304         return ret;
1305 }
1306
1307 static int vop_create_crtc(struct vop *vop)
1308 {
1309         const struct vop_data *vop_data = vop->data;
1310         struct device *dev = vop->dev;
1311         struct drm_device *drm_dev = vop->drm_dev;
1312         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1313         struct drm_crtc *crtc = &vop->crtc;
1314         struct device_node *port;
1315         int ret;
1316         int i;
1317
1318         /*
1319          * Create drm_plane for primary and cursor planes first, since we need
1320          * to pass them to drm_crtc_init_with_planes, which sets the
1321          * "possible_crtcs" to the newly initialized crtc.
1322          */
1323         for (i = 0; i < vop_data->win_size; i++) {
1324                 struct vop_win *vop_win = &vop->win[i];
1325                 const struct vop_win_data *win_data = vop_win->data;
1326
1327                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1328                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1329                         continue;
1330
1331                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1332                                                0, &vop_plane_funcs,
1333                                                win_data->phy->data_formats,
1334                                                win_data->phy->nformats,
1335                                                win_data->type, NULL);
1336                 if (ret) {
1337                         DRM_ERROR("failed to initialize plane\n");
1338                         goto err_cleanup_planes;
1339                 }
1340
1341                 plane = &vop_win->base;
1342                 drm_plane_helper_add(plane, &plane_helper_funcs);
1343                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1344                         primary = plane;
1345                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1346                         cursor = plane;
1347         }
1348
1349         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1350                                         &vop_crtc_funcs, NULL);
1351         if (ret)
1352                 return ret;
1353
1354         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1355
1356         /*
1357          * Create drm_planes for overlay windows with possible_crtcs restricted
1358          * to the newly created crtc.
1359          */
1360         for (i = 0; i < vop_data->win_size; i++) {
1361                 struct vop_win *vop_win = &vop->win[i];
1362                 const struct vop_win_data *win_data = vop_win->data;
1363                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1364
1365                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1366                         continue;
1367
1368                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1369                                                possible_crtcs,
1370                                                &vop_plane_funcs,
1371                                                win_data->phy->data_formats,
1372                                                win_data->phy->nformats,
1373                                                win_data->type, NULL);
1374                 if (ret) {
1375                         DRM_ERROR("failed to initialize overlay plane\n");
1376                         goto err_cleanup_crtc;
1377                 }
1378                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1379         }
1380
1381         port = of_get_child_by_name(dev->of_node, "port");
1382         if (!port) {
1383                 DRM_ERROR("no port node found in %s\n",
1384                           dev->of_node->full_name);
1385                 goto err_cleanup_crtc;
1386         }
1387
1388         init_completion(&vop->dsp_hold_completion);
1389         init_completion(&vop->wait_update_complete);
1390         crtc->port = port;
1391         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1392
1393         return 0;
1394
1395 err_cleanup_crtc:
1396         drm_crtc_cleanup(crtc);
1397 err_cleanup_planes:
1398         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1399                 drm_plane_cleanup(plane);
1400         return ret;
1401 }
1402
1403 static void vop_destroy_crtc(struct vop *vop)
1404 {
1405         struct drm_crtc *crtc = &vop->crtc;
1406
1407         rockchip_unregister_crtc_funcs(crtc);
1408         of_node_put(crtc->port);
1409         drm_crtc_cleanup(crtc);
1410 }
1411
1412 static int vop_initial(struct vop *vop)
1413 {
1414         const struct vop_data *vop_data = vop->data;
1415         const struct vop_reg_data *init_table = vop_data->init_table;
1416         struct reset_control *ahb_rst;
1417         int i, ret;
1418
1419         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1420         if (IS_ERR(vop->hclk)) {
1421                 dev_err(vop->dev, "failed to get hclk source\n");
1422                 return PTR_ERR(vop->hclk);
1423         }
1424         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1425         if (IS_ERR(vop->aclk)) {
1426                 dev_err(vop->dev, "failed to get aclk source\n");
1427                 return PTR_ERR(vop->aclk);
1428         }
1429         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1430         if (IS_ERR(vop->dclk)) {
1431                 dev_err(vop->dev, "failed to get dclk source\n");
1432                 return PTR_ERR(vop->dclk);
1433         }
1434
1435         ret = clk_prepare(vop->dclk);
1436         if (ret < 0) {
1437                 dev_err(vop->dev, "failed to prepare dclk\n");
1438                 return ret;
1439         }
1440
1441         /* Enable both the hclk and aclk to setup the vop */
1442         ret = clk_prepare_enable(vop->hclk);
1443         if (ret < 0) {
1444                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1445                 goto err_unprepare_dclk;
1446         }
1447
1448         ret = clk_prepare_enable(vop->aclk);
1449         if (ret < 0) {
1450                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1451                 goto err_disable_hclk;
1452         }
1453
1454         /*
1455          * do hclk_reset, reset all vop registers.
1456          */
1457         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1458         if (IS_ERR(ahb_rst)) {
1459                 dev_err(vop->dev, "failed to get ahb reset\n");
1460                 ret = PTR_ERR(ahb_rst);
1461                 goto err_disable_aclk;
1462         }
1463         reset_control_assert(ahb_rst);
1464         usleep_range(10, 20);
1465         reset_control_deassert(ahb_rst);
1466
1467         memcpy(vop->regsbak, vop->regs, vop->len);
1468
1469         for (i = 0; i < vop_data->table_size; i++)
1470                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1471
1472         for (i = 0; i < vop_data->win_size; i++) {
1473                 const struct vop_win_data *win = &vop_data->win[i];
1474
1475                 VOP_WIN_SET(vop, win, enable, 0);
1476         }
1477
1478         vop_cfg_done(vop);
1479
1480         /*
1481          * do dclk_reset, let all config take affect.
1482          */
1483         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1484         if (IS_ERR(vop->dclk_rst)) {
1485                 dev_err(vop->dev, "failed to get dclk reset\n");
1486                 ret = PTR_ERR(vop->dclk_rst);
1487                 goto err_disable_aclk;
1488         }
1489         reset_control_assert(vop->dclk_rst);
1490         usleep_range(10, 20);
1491         reset_control_deassert(vop->dclk_rst);
1492
1493         clk_disable(vop->hclk);
1494         clk_disable(vop->aclk);
1495
1496         vop->is_enabled = false;
1497
1498         return 0;
1499
1500 err_disable_aclk:
1501         clk_disable_unprepare(vop->aclk);
1502 err_disable_hclk:
1503         clk_disable_unprepare(vop->hclk);
1504 err_unprepare_dclk:
1505         clk_unprepare(vop->dclk);
1506         return ret;
1507 }
1508
1509 /*
1510  * Initialize the vop->win array elements.
1511  */
1512 static void vop_win_init(struct vop *vop)
1513 {
1514         const struct vop_data *vop_data = vop->data;
1515         unsigned int i;
1516
1517         for (i = 0; i < vop_data->win_size; i++) {
1518                 struct vop_win *vop_win = &vop->win[i];
1519                 const struct vop_win_data *win_data = &vop_data->win[i];
1520
1521                 vop_win->data = win_data;
1522                 vop_win->vop = vop;
1523         }
1524 }
1525
1526 static int vop_bind(struct device *dev, struct device *master, void *data)
1527 {
1528         struct platform_device *pdev = to_platform_device(dev);
1529         const struct of_device_id *of_id;
1530         const struct vop_data *vop_data;
1531         struct drm_device *drm_dev = data;
1532         struct vop *vop;
1533         struct resource *res;
1534         size_t alloc_size;
1535         int ret, irq;
1536
1537         of_id = of_match_device(vop_driver_dt_match, dev);
1538         vop_data = of_id->data;
1539         if (!vop_data)
1540                 return -ENODEV;
1541
1542         /* Allocate vop struct and its vop_win array */
1543         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1544         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1545         if (!vop)
1546                 return -ENOMEM;
1547
1548         vop->dev = dev;
1549         vop->data = vop_data;
1550         vop->drm_dev = drm_dev;
1551         dev_set_drvdata(dev, vop);
1552
1553         vop_win_init(vop);
1554
1555         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1556         vop->len = resource_size(res);
1557         vop->regs = devm_ioremap_resource(dev, res);
1558         if (IS_ERR(vop->regs))
1559                 return PTR_ERR(vop->regs);
1560
1561         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1562         if (!vop->regsbak)
1563                 return -ENOMEM;
1564
1565         ret = vop_initial(vop);
1566         if (ret < 0) {
1567                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1568                 return ret;
1569         }
1570
1571         irq = platform_get_irq(pdev, 0);
1572         if (irq < 0) {
1573                 dev_err(dev, "cannot find irq for vop\n");
1574                 return irq;
1575         }
1576         vop->irq = (unsigned int)irq;
1577
1578         spin_lock_init(&vop->reg_lock);
1579         spin_lock_init(&vop->irq_lock);
1580
1581         mutex_init(&vop->vsync_mutex);
1582
1583         ret = devm_request_irq(dev, vop->irq, vop_isr,
1584                                IRQF_SHARED, dev_name(dev), vop);
1585         if (ret)
1586                 return ret;
1587
1588         /* IRQ is initially disabled; it gets enabled in power_on */
1589         disable_irq(vop->irq);
1590
1591         ret = vop_create_crtc(vop);
1592         if (ret)
1593                 return ret;
1594
1595         pm_runtime_enable(&pdev->dev);
1596         return 0;
1597 }
1598
1599 static void vop_unbind(struct device *dev, struct device *master, void *data)
1600 {
1601         struct vop *vop = dev_get_drvdata(dev);
1602
1603         pm_runtime_disable(dev);
1604         vop_destroy_crtc(vop);
1605 }
1606
1607 static const struct component_ops vop_component_ops = {
1608         .bind = vop_bind,
1609         .unbind = vop_unbind,
1610 };
1611
1612 static int vop_probe(struct platform_device *pdev)
1613 {
1614         struct device *dev = &pdev->dev;
1615
1616         if (!dev->of_node) {
1617                 dev_err(dev, "can't find vop devices\n");
1618                 return -ENODEV;
1619         }
1620
1621         return component_add(dev, &vop_component_ops);
1622 }
1623
1624 static int vop_remove(struct platform_device *pdev)
1625 {
1626         component_del(&pdev->dev, &vop_component_ops);
1627
1628         return 0;
1629 }
1630
1631 struct platform_driver vop_platform_driver = {
1632         .probe = vop_probe,
1633         .remove = vop_remove,
1634         .driver = {
1635                 .name = "rockchip-vop",
1636                 .owner = THIS_MODULE,
1637                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1638         },
1639 };
1640
1641 module_platform_driver(vop_platform_driver);
1642
1643 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1644 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1645 MODULE_LICENSE("GPL v2");