drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/iopoll.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/component.h>
  31
  32 #include <linux/reset.h>
  33 #include <linux/delay.h>
  34 #include <linux/sort.h>
  35 #include <uapi/drm/rockchip_drm.h>
  36
  37 #include "rockchip_drm_drv.h"
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_fb.h"
  40 #include "rockchip_drm_vop.h"
  41
  42 #define VOP_REG_SUPPORT(vop, reg) \
  43                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  44                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  45                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  46                 reg.mask))
  47
  48 #define VOP_WIN_SUPPORT(vop, win, name) \
  49                 VOP_REG_SUPPORT(vop, win->phy->name)
  50
  51 #define VOP_CTRL_SUPPORT(vop, name) \
  52                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  53
  54 #define VOP_INTR_SUPPORT(vop, name) \
  55                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  56
  57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  58                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  59
  60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  61         do { \
  62                 if (VOP_REG_SUPPORT(vop, reg)) \
  63                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  64                                   v, reg.write_mask, relaxed); \
  65                 else \
  66                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  67         } while(0)
  68
  69 #define REG_SET(x, name, off, reg, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  72                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  73
  74 #define VOP_WIN_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  77                 REG_SET(x, name, 0, win->ext->name, v, true)
  78 #define VOP_SCL_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  80 #define VOP_SCL_SET_EXT(x, win, name, v) \
  81                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  82
  83 #define VOP_CTRL_SET(x, name, v) \
  84                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  85
  86 #define VOP_INTR_GET(vop, name) \
  87                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  88
  89 #define VOP_INTR_SET(vop, name, v) \
  90                 REG_SET(vop, name, 0, vop->data->intr->name, \
  91                         v, false)
  92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  93                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  94                              mask, v, false)
  95
  96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  97         do { \
  98                 int i, reg = 0, mask = 0; \
  99                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 100                         if (vop->data->intr->intrs[i] & type) { \
 101                                 reg |= (v) << i; \
 102                                 mask |= 1 << i; \
 103                         } \
 104                 } \
 105                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 106         } while (0)
 107 #define VOP_INTR_GET_TYPE(vop, name, type) \
 108                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 109
 110 #define VOP_CTRL_GET(x, name) \
 111                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 112
 113 #define VOP_WIN_GET(x, win, name) \
 114                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 115
 116 #define VOP_WIN_NAME(win, name) \
 117                 (vop_get_win_phy(win, &win->phy->name)->name)
 118
 119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 120                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 121
 122 #define to_vop(x) container_of(x, struct vop, crtc)
 123 #define to_vop_win(x) container_of(x, struct vop_win, base)
 124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 125
 126 struct vop_zpos {
 127         int win_id;
 128         int zpos;
 129 };
 130
 131 struct vop_plane_state {
 132         struct drm_plane_state base;
 133         int format;
 134         int zpos;
 135         struct drm_rect src;
 136         struct drm_rect dest;
 137         dma_addr_t yrgb_mst;
 138         dma_addr_t uv_mst;
 139         const uint32_t *y2r_table;
 140         const uint32_t *r2r_table;
 141         const uint32_t *r2y_table;
 142         bool enable;
 143 };
 144
 145 struct vop_win {
 146         struct vop_win *parent;
 147         struct drm_plane base;
 148
 149         int win_id;
 150         int area_id;
 151         uint32_t offset;
 152         enum drm_plane_type type;
 153         const struct vop_win_phy *phy;
 154         const struct vop_csc *csc;
 155         const uint32_t *data_formats;
 156         uint32_t nformats;
 157         struct vop *vop;
 158
 159         struct drm_property *rotation_prop;
 160         struct vop_plane_state state;
 161 };
 162
 163 struct vop {
 164         struct drm_crtc crtc;
 165         struct device *dev;
 166         struct drm_device *drm_dev;
 167         struct drm_property *plane_zpos_prop;
 168         struct drm_property *plane_feature_prop;
 169         struct drm_property *feature_prop;
 170         bool is_iommu_enabled;
 171         bool is_iommu_needed;
 172         bool is_enabled;
 173
 174         /* mutex vsync_ work */
 175         struct mutex vsync_mutex;
 176         bool vsync_work_pending;
 177         bool loader_protect;
 178         struct completion dsp_hold_completion;
 179         struct completion wait_update_complete;
 180         struct drm_pending_vblank_event *event;
 181
 182         struct completion line_flag_completion;
 183
 184         const struct vop_data *data;
 185         int num_wins;
 186
 187         uint32_t *regsbak;
 188         void __iomem *regs;
 189
 190         /* physical map length of vop register */
 191         uint32_t len;
 192
 193         /* one time only one process allowed to config the register */
 194         spinlock_t reg_lock;
 195         /* lock vop irq reg */
 196         spinlock_t irq_lock;
 197
 198         unsigned int irq;
 199
 200         /* vop AHP clk */
 201         struct clk *hclk;
 202         /* vop dclk */
 203         struct clk *dclk;
 204         /* vop share memory frequency */
 205         struct clk *aclk;
 206
 207         /* vop dclk reset */
 208         struct reset_control *dclk_rst;
 209
 210         struct vop_win win[];
 211 };
 212
 213 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 214 {
 215         writel(v, vop->regs + offset);
 216         vop->regsbak[offset >> 2] = v;
 217 }
 218
 219 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 220 {
 221         return readl(vop->regs + offset);
 222 }
 223
 224 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 225                                     const struct vop_reg *reg)
 226 {
 227         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 228 }
 229
 230 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 231                                   uint32_t mask, uint32_t shift, uint32_t v,
 232                                   bool write_mask, bool relaxed)
 233 {
 234         if (!mask)
 235                 return;
 236
 237         if (write_mask) {
 238                 v = ((v & mask) << shift) | (mask << (shift + 16));
 239         } else {
 240                 uint32_t cached_val = vop->regsbak[offset >> 2];
 241
 242                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 243                 vop->regsbak[offset >> 2] = v;
 244         }
 245
 246         if (relaxed)
 247                 writel_relaxed(v, vop->regs + offset);
 248         else
 249                 writel(v, vop->regs + offset);
 250 }
 251
 252 static inline const struct vop_win_phy *
 253 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 254 {
 255         if (!reg->mask && win->parent)
 256                 return win->parent->phy;
 257
 258         return win->phy;
 259 }
 260
 261 static inline uint32_t vop_get_intr_type(struct vop *vop,
 262                                          const struct vop_reg *reg, int type)
 263 {
 264         uint32_t i, ret = 0;
 265         uint32_t regs = vop_read_reg(vop, 0, reg);
 266
 267         for (i = 0; i < vop->data->intr->nintrs; i++) {
 268                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 269                         ret |= vop->data->intr->intrs[i];
 270         }
 271
 272         return ret;
 273 }
 274
 275 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 276 {
 277         int i;
 278
 279         if (!table)
 280                 return;
 281
 282         for (i = 0; i < 8; i++)
 283                 vop_writel(vop, offset + i * 4, table[i]);
 284 }
 285
 286 static inline void vop_cfg_done(struct vop *vop)
 287 {
 288         VOP_CTRL_SET(vop, cfg_done, 1);
 289 }
 290
 291 static bool vop_is_allwin_disabled(struct vop *vop)
 292 {
 293         int i;
 294
 295         for (i = 0; i < vop->num_wins; i++) {
 296                 struct vop_win *win = &vop->win[i];
 297
 298                 if (VOP_WIN_GET(vop, win, enable) != 0)
 299                         return false;
 300         }
 301
 302         return true;
 303 }
 304
 305 static bool vop_is_cfg_done_complete(struct vop *vop)
 306 {
 307         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 308 }
 309
 310 static bool vop_fs_irq_is_active(struct vop *vop)
 311 {
 312         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 313 }
 314
 315 static bool vop_line_flag_is_active(struct vop *vop)
 316 {
 317         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 318 }
 319
 320 static bool has_rb_swapped(uint32_t format)
 321 {
 322         switch (format) {
 323         case DRM_FORMAT_XBGR8888:
 324         case DRM_FORMAT_ABGR8888:
 325         case DRM_FORMAT_BGR888:
 326         case DRM_FORMAT_BGR565:
 327                 return true;
 328         default:
 329                 return false;
 330         }
 331 }
 332
 333 static enum vop_data_format vop_convert_format(uint32_t format)
 334 {
 335         switch (format) {
 336         case DRM_FORMAT_XRGB8888:
 337         case DRM_FORMAT_ARGB8888:
 338         case DRM_FORMAT_XBGR8888:
 339         case DRM_FORMAT_ABGR8888:
 340                 return VOP_FMT_ARGB8888;
 341         case DRM_FORMAT_RGB888:
 342         case DRM_FORMAT_BGR888:
 343                 return VOP_FMT_RGB888;
 344         case DRM_FORMAT_RGB565:
 345         case DRM_FORMAT_BGR565:
 346                 return VOP_FMT_RGB565;
 347         case DRM_FORMAT_NV12:
 348         case DRM_FORMAT_NV12_10:
 349                 return VOP_FMT_YUV420SP;
 350         case DRM_FORMAT_NV16:
 351         case DRM_FORMAT_NV16_10:
 352                 return VOP_FMT_YUV422SP;
 353         case DRM_FORMAT_NV24:
 354         case DRM_FORMAT_NV24_10:
 355                 return VOP_FMT_YUV444SP;
 356         default:
 357                 DRM_ERROR("unsupport format[%08x]\n", format);
 358                 return -EINVAL;
 359         }
 360 }
 361
 362 static bool is_yuv_support(uint32_t format)
 363 {
 364         switch (format) {
 365         case DRM_FORMAT_NV12:
 366         case DRM_FORMAT_NV12_10:
 367         case DRM_FORMAT_NV16:
 368         case DRM_FORMAT_NV16_10:
 369         case DRM_FORMAT_NV24:
 370         case DRM_FORMAT_NV24_10:
 371                 return true;
 372         default:
 373                 return false;
 374         }
 375 }
 376
 377 static bool is_yuv_10bit(uint32_t format)
 378 {
 379         switch (format) {
 380         case DRM_FORMAT_NV12_10:
 381         case DRM_FORMAT_NV16_10:
 382         case DRM_FORMAT_NV24_10:
 383                 return true;
 384         default:
 385                 return false;
 386         }
 387 }
 388
 389 static bool is_alpha_support(uint32_t format)
 390 {
 391         switch (format) {
 392         case DRM_FORMAT_ARGB8888:
 393         case DRM_FORMAT_ABGR8888:
 394                 return true;
 395         default:
 396                 return false;
 397         }
 398 }
 399
 400 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 401                                   uint32_t dst, bool is_horizontal,
 402                                   int vsu_mode, int *vskiplines)
 403 {
 404         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 405
 406         if (is_horizontal) {
 407                 if (mode == SCALE_UP)
 408                         val = GET_SCL_FT_BIC(src, dst);
 409                 else if (mode == SCALE_DOWN)
 410                         val = GET_SCL_FT_BILI_DN(src, dst);
 411         } else {
 412                 if (mode == SCALE_UP) {
 413                         if (vsu_mode == SCALE_UP_BIL)
 414                                 val = GET_SCL_FT_BILI_UP(src, dst);
 415                         else
 416                                 val = GET_SCL_FT_BIC(src, dst);
 417                 } else if (mode == SCALE_DOWN) {
 418                         if (vskiplines) {
 419                                 *vskiplines = scl_get_vskiplines(src, dst);
 420                                 val = scl_get_bili_dn_vskip(src, dst,
 421                                                             *vskiplines);
 422                         } else {
 423                                 val = GET_SCL_FT_BILI_DN(src, dst);
 424                         }
 425                 }
 426         }
 427
 428         return val;
 429 }
 430
 431 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 432                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 433                                 uint32_t dst_h, uint32_t pixel_format)
 434 {
 435         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 436         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 437         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 438         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 439         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 440         bool is_yuv = is_yuv_support(pixel_format);
 441         uint16_t cbcr_src_w = src_w / hsub;
 442         uint16_t cbcr_src_h = src_h / vsub;
 443         uint16_t vsu_mode;
 444         uint16_t lb_mode;
 445         uint32_t val;
 446         int vskiplines = 0;
 447
 448         if (!win->phy->scl)
 449                 return;
 450
 451         if (!win->phy->scl->ext) {
 452                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 453                             scl_cal_scale2(src_w, dst_w));
 454                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 455                             scl_cal_scale2(src_h, dst_h));
 456                 if (is_yuv) {
 457                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 458                                     scl_cal_scale2(cbcr_src_w, dst_w));
 459                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 460                                     scl_cal_scale2(cbcr_src_h, dst_h));
 461                 }
 462                 return;
 463         }
 464
 465         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 466         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 467
 468         if (is_yuv) {
 469                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 470                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 471                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 472                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 473                 else
 474                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 475         } else {
 476                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 477                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 478                 else
 479                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 480         }
 481
 482         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 483         if (lb_mode == LB_RGB_3840X2) {
 484                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 485                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 486                         return;
 487                 }
 488                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 489                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 490                         return;
 491                 }
 492                 vsu_mode = SCALE_UP_BIL;
 493         } else if (lb_mode == LB_RGB_2560X4) {
 494                 vsu_mode = SCALE_UP_BIL;
 495         } else {
 496                 vsu_mode = SCALE_UP_BIC;
 497         }
 498
 499         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 500                                 true, 0, NULL);
 501         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 502         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 503                                 false, vsu_mode, &vskiplines);
 504         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 505
 506         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 507         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 508
 509         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 510         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 511         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 512         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 513         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 514         if (is_yuv) {
 515                 vskiplines = 0;
 516
 517                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 518                                         dst_w, true, 0, NULL);
 519                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 520                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 521                                         dst_h, false, vsu_mode, &vskiplines);
 522                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 523
 524                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 525                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 526                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 527                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 528                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 529                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 530                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 531         }
 532 }
 533
 534 /*
 535  * rk3399 colorspace path:
 536  *      Input        Win csc                     Output
 537  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 538  *    RGB        --> R2Y                  __/
 539  *
 540  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 541  *    RGB        --> 709To2020->R2Y       __/
 542  *
 543  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 544  *    RGB        --> R2Y                  __/
 545  *
 546  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 547  *    RGB        --> 709To2020->R2Y       __/
 548  *
 549  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 550  *    RGB        --> R2Y                  __/
 551  *
 552  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 553  *    RGB        --> R2Y(601)             __/
 554  *
 555  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 556  *    RGB        --> bypass               __/
 557  *
 558  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 559  *
 560  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 561  *
 562  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 563  *
 564  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 565  */
 566 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 567                          bool is_input_yuv, bool is_output_yuv,
 568                          int input_csc, int output_csc,
 569                          const uint32_t **y2r_table,
 570                          const uint32_t **r2r_table,
 571                          const uint32_t **r2y_table)
 572 {
 573         *y2r_table = NULL;
 574         *r2r_table = NULL;
 575         *r2y_table = NULL;
 576
 577         if (is_output_yuv) {
 578                 if (output_csc == CSC_BT2020) {
 579                         if (is_input_yuv) {
 580                                 if (input_csc == CSC_BT2020)
 581                                         return 0;
 582                                 *y2r_table = csc_table->y2r_bt709;
 583                         }
 584                         if (input_csc != CSC_BT2020)
 585                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 586                         *r2y_table = csc_table->r2y_bt2020;
 587                 } else {
 588                         if (is_input_yuv && input_csc == CSC_BT2020)
 589                                 *y2r_table = csc_table->y2r_bt2020;
 590                         if (input_csc == CSC_BT2020)
 591                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 592                         if (!is_input_yuv || *y2r_table) {
 593                                 if (output_csc == CSC_BT709)
 594                                         *r2y_table = csc_table->r2y_bt709;
 595                                 else
 596                                         *r2y_table = csc_table->r2y_bt601;
 597                         }
 598                 }
 599         } else {
 600                 if (!is_input_yuv)
 601                         return 0;
 602
 603                 /*
 604                  * is possible use bt2020 on rgb mode?
 605                  */
 606                 if (WARN_ON(output_csc == CSC_BT2020))
 607                         return -EINVAL;
 608
 609                 if (input_csc == CSC_BT2020)
 610                         *y2r_table = csc_table->y2r_bt2020;
 611                 else if (input_csc == CSC_BT709)
 612                         *y2r_table = csc_table->y2r_bt709;
 613                 else
 614                         *y2r_table = csc_table->y2r_bt601;
 615
 616                 if (input_csc == CSC_BT2020)
 617                         /*
 618                          * We don't have bt601 to bt709 table, force use bt709.
 619                          */
 620                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 627                                 struct drm_crtc_state *crtc_state)
 628 {
 629         struct vop *vop = to_vop(crtc);
 630         struct drm_atomic_state *state = crtc_state->state;
 631         const struct vop_csc_table *csc_table = vop->data->csc_table;
 632         struct drm_plane_state *pstate;
 633         struct drm_plane *plane;
 634         bool is_yuv;
 635         int ret;
 636
 637         if (!csc_table)
 638                 return 0;
 639
 640         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 641                 struct vop_plane_state *vop_plane_state;
 642
 643                 pstate = drm_atomic_get_plane_state(state, plane);
 644                 if (IS_ERR(pstate))
 645                         return PTR_ERR(pstate);
 646                 vop_plane_state = to_vop_plane_state(pstate);
 647
 648                 if (!pstate->fb)
 649                         continue;
 650                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 651
 652                 /*
 653                  * TODO: force set input and output csc mode.
 654                  */
 655                 ret = vop_csc_setup(csc_table, is_yuv, false,
 656                                     CSC_BT709, CSC_BT709,
 657                                     &vop_plane_state->y2r_table,
 658                                     &vop_plane_state->r2r_table,
 659                                     &vop_plane_state->r2y_table);
 660                 if (ret)
 661                         return ret;
 662         }
 663
 664         return 0;
 665 }
 666
 667 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 668 {
 669         unsigned long flags;
 670
 671         spin_lock_irqsave(&vop->irq_lock, flags);
 672
 673         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 674         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 675
 676         spin_unlock_irqrestore(&vop->irq_lock, flags);
 677 }
 678
 679 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 680 {
 681         unsigned long flags;
 682
 683         spin_lock_irqsave(&vop->irq_lock, flags);
 684
 685         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 686
 687         spin_unlock_irqrestore(&vop->irq_lock, flags);
 688 }
 689
 690 /*
 691  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 692  *     the "FRAME_SYNC" interrupt.
 693  * (2) the active data region of each frame ends at dsp_vact_end
 694  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 695  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 696  *
 697  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 698  * Interrupts
 699  * LINE_FLAG -------------------------------+
 700  * FRAME_SYNC ----+                         |
 701  *                |                         |
 702  *                v                         v
 703  *                | Vsync | Vbp |  Vactive  | Vfp |
 704  *                        ^     ^           ^     ^
 705  *                        |     |           |     |
 706  *                        |     |           |     |
 707  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 708  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 709  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 710  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 711  */
 712 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 713 {
 714         uint32_t line_flag_irq;
 715         unsigned long flags;
 716
 717         spin_lock_irqsave(&vop->irq_lock, flags);
 718
 719         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 720
 721         spin_unlock_irqrestore(&vop->irq_lock, flags);
 722
 723         return !!line_flag_irq;
 724 }
 725
 726 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 727 {
 728         unsigned long flags;
 729
 730         if (WARN_ON(!vop->is_enabled))
 731                 return;
 732
 733         spin_lock_irqsave(&vop->irq_lock, flags);
 734
 735         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 736         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 737         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 738
 739         spin_unlock_irqrestore(&vop->irq_lock, flags);
 740 }
 741
 742 static void vop_line_flag_irq_disable(struct vop *vop)
 743 {
 744         unsigned long flags;
 745
 746         if (WARN_ON(!vop->is_enabled))
 747                 return;
 748
 749         spin_lock_irqsave(&vop->irq_lock, flags);
 750
 751         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 752
 753         spin_unlock_irqrestore(&vop->irq_lock, flags);
 754 }
 755
 756 static void vop_power_enable(struct drm_crtc *crtc)
 757 {
 758         struct vop *vop = to_vop(crtc);
 759         int ret;
 760
 761         ret = clk_prepare_enable(vop->hclk);
 762         if (ret < 0) {
 763                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 764                 return;
 765         }
 766
 767         ret = clk_prepare_enable(vop->dclk);
 768         if (ret < 0) {
 769                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 770                 goto err_disable_hclk;
 771         }
 772
 773         ret = clk_prepare_enable(vop->aclk);
 774         if (ret < 0) {
 775                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 776                 goto err_disable_dclk;
 777         }
 778
 779         ret = pm_runtime_get_sync(vop->dev);
 780         if (ret < 0) {
 781                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 782                 return;
 783         }
 784
 785         memcpy(vop->regsbak, vop->regs, vop->len);
 786
 787         vop->is_enabled = true;
 788
 789         return;
 790
 791 err_disable_dclk:
 792         clk_disable_unprepare(vop->dclk);
 793 err_disable_hclk:
 794         clk_disable_unprepare(vop->hclk);
 795 }
 796
 797 static void vop_initial(struct drm_crtc *crtc)
 798 {
 799         struct vop *vop = to_vop(crtc);
 800         int i;
 801
 802         vop_power_enable(crtc);
 803
 804         VOP_CTRL_SET(vop, global_regdone_en, 1);
 805         VOP_CTRL_SET(vop, dsp_blank, 0);
 806
 807         /*
 808          * We need to make sure that all windows are disabled before resume
 809          * the crtc. Otherwise we might try to scan from a destroyed
 810          * buffer later.
 811          */
 812         for (i = 0; i < vop->num_wins; i++) {
 813                 struct vop_win *win = &vop->win[i];
 814
 815                 if (win->phy->scl && win->phy->scl->ext) {
 816                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 817                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 818                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 819                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 820                 }
 821                 VOP_WIN_SET(vop, win, enable, 0);
 822                 VOP_WIN_SET(vop, win, gate, 1);
 823         }
 824         VOP_CTRL_SET(vop, afbdc_en, 0);
 825 }
 826
 827 static void vop_crtc_disable(struct drm_crtc *crtc)
 828 {
 829         struct vop *vop = to_vop(crtc);
 830
 831         drm_crtc_vblank_off(crtc);
 832
 833         /*
 834          * Vop standby will take effect at end of current frame,
 835          * if dsp hold valid irq happen, it means standby complete.
 836          *
 837          * we must wait standby complete when we want to disable aclk,
 838          * if not, memory bus maybe dead.
 839          */
 840         reinit_completion(&vop->dsp_hold_completion);
 841         vop_dsp_hold_valid_irq_enable(vop);
 842
 843         spin_lock(&vop->reg_lock);
 844
 845         VOP_CTRL_SET(vop, standby, 1);
 846
 847         spin_unlock(&vop->reg_lock);
 848
 849         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 850                                              msecs_to_jiffies(50)));
 851
 852         vop_dsp_hold_valid_irq_disable(vop);
 853
 854         disable_irq(vop->irq);
 855
 856         vop->is_enabled = false;
 857         if (vop->is_iommu_enabled) {
 858                 /*
 859                  * vop standby complete, so iommu detach is safe.
 860                  */
 861                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 862                 vop->is_iommu_enabled = false;
 863         }
 864
 865         pm_runtime_put(vop->dev);
 866         clk_disable_unprepare(vop->dclk);
 867         clk_disable_unprepare(vop->aclk);
 868         clk_disable_unprepare(vop->hclk);
 869 }
 870
 871 static void vop_plane_destroy(struct drm_plane *plane)
 872 {
 873         drm_plane_cleanup(plane);
 874 }
 875
 876 static int vop_plane_prepare_fb(struct drm_plane *plane,
 877                                 const struct drm_plane_state *new_state)
 878 {
 879         if (plane->state->fb)
 880                 drm_framebuffer_reference(plane->state->fb);
 881
 882         return 0;
 883 }
 884
 885 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 886                                  const struct drm_plane_state *old_state)
 887 {
 888         if (old_state->fb)
 889                 drm_framebuffer_unreference(old_state->fb);
 890 }
 891
 892 static int vop_plane_atomic_check(struct drm_plane *plane,
 893                            struct drm_plane_state *state)
 894 {
 895         struct drm_crtc *crtc = state->crtc;
 896         struct drm_framebuffer *fb = state->fb;
 897         struct vop_win *win = to_vop_win(plane);
 898         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 899         struct drm_crtc_state *crtc_state;
 900         const struct vop_data *vop_data;
 901         struct vop *vop;
 902         bool visible;
 903         int ret;
 904         struct drm_rect *dest = &vop_plane_state->dest;
 905         struct drm_rect *src = &vop_plane_state->src;
 906         struct drm_rect clip;
 907         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 908                                         DRM_PLANE_HELPER_NO_SCALING;
 909         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 910                                         DRM_PLANE_HELPER_NO_SCALING;
 911         unsigned long offset;
 912         dma_addr_t dma_addr;
 913
 914         crtc = crtc ? crtc : plane->state->crtc;
 915         /*
 916          * Both crtc or plane->state->crtc can be null.
 917          */
 918         if (!crtc || !fb)
 919                 goto out_disable;
 920
 921         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 922         if (IS_ERR(crtc_state))
 923                 return PTR_ERR(crtc_state);
 924
 925         src->x1 = state->src_x;
 926         src->y1 = state->src_y;
 927         src->x2 = state->src_x + state->src_w;
 928         src->y2 = state->src_y + state->src_h;
 929         dest->x1 = state->crtc_x;
 930         dest->y1 = state->crtc_y;
 931         dest->x2 = state->crtc_x + state->crtc_w;
 932         dest->y2 = state->crtc_y + state->crtc_h;
 933
 934         clip.x1 = 0;
 935         clip.y1 = 0;
 936         clip.x2 = crtc_state->mode.hdisplay;
 937         clip.y2 = crtc_state->mode.vdisplay;
 938
 939         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 940                                             src, dest, &clip,
 941                                             min_scale,
 942                                             max_scale,
 943                                             true, true, &visible);
 944         if (ret)
 945                 return ret;
 946
 947         if (!visible)
 948                 goto out_disable;
 949
 950         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 951         if (vop_plane_state->format < 0)
 952                 return vop_plane_state->format;
 953
 954         vop = to_vop(crtc);
 955         vop_data = vop->data;
 956
 957         if (drm_rect_width(src) >> 16 > vop_data->max_input_fb.width ||
 958             drm_rect_height(src) >> 16 > vop_data->max_input_fb.height) {
 959                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
 960                           drm_rect_width(src) >> 16,
 961                           drm_rect_height(src) >> 16,
 962                           vop_data->max_input_fb.width,
 963                           vop_data->max_input_fb.height);
 964                 return -EINVAL;
 965         }
 966
 967         /*
 968          * Src.x1 can be odd when do clip, but yuv plane start point
 969          * need align with 2 pixel.
 970          */
 971         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 972                 return -EINVAL;
 973
 974         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 975         if (state->rotation & BIT(DRM_REFLECT_Y))
 976                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 977         else
 978                 offset += (src->y1 >> 16) * fb->pitches[0];
 979
 980         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 981         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 982         if (is_yuv_support(fb->pixel_format)) {
 983                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 984                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 985                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
 986
 987                 offset = (src->x1 >> 16) * bpp / hsub / 8;
 988                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 989
 990                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 991                 dma_addr += offset + fb->offsets[1];
 992                 vop_plane_state->uv_mst = dma_addr;
 993         }
 994
 995         vop_plane_state->enable = true;
 996
 997         return 0;
 998
 999 out_disable:
1000         vop_plane_state->enable = false;
1001         return 0;
1002 }
1003
1004 static void vop_plane_atomic_disable(struct drm_plane *plane,
1005                                      struct drm_plane_state *old_state)
1006 {
1007         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1008         struct vop_win *win = to_vop_win(plane);
1009         struct vop *vop = to_vop(old_state->crtc);
1010
1011         if (!old_state->crtc)
1012                 return;
1013
1014         spin_lock(&vop->reg_lock);
1015
1016         /*
1017          * FIXUP: some of the vop scale would be abnormal after windows power
1018          * on/off so deinit scale to scale_none mode.
1019          */
1020         if (win->phy->scl && win->phy->scl->ext) {
1021                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1022                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1023                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1024                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1025         }
1026         VOP_WIN_SET(vop, win, enable, 0);
1027
1028         spin_unlock(&vop->reg_lock);
1029
1030         vop_plane_state->enable = false;
1031 }
1032
1033 static void vop_plane_atomic_update(struct drm_plane *plane,
1034                 struct drm_plane_state *old_state)
1035 {
1036         struct drm_plane_state *state = plane->state;
1037         struct drm_crtc *crtc = state->crtc;
1038         struct vop_win *win = to_vop_win(plane);
1039         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1040         struct rockchip_crtc_state *s;
1041         struct vop *vop;
1042         struct drm_framebuffer *fb = state->fb;
1043         unsigned int actual_w, actual_h;
1044         unsigned int dsp_stx, dsp_sty;
1045         uint32_t act_info, dsp_info, dsp_st;
1046         struct drm_rect *src = &vop_plane_state->src;
1047         struct drm_rect *dest = &vop_plane_state->dest;
1048         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1049         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1050         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1051         int ymirror, xmirror;
1052         uint32_t val;
1053         bool rb_swap;
1054
1055         /*
1056          * can't update plane when vop is disabled.
1057          */
1058         if (!crtc)
1059                 return;
1060
1061         if (!vop_plane_state->enable) {
1062                 vop_plane_atomic_disable(plane, old_state);
1063                 return;
1064         }
1065
1066         actual_w = drm_rect_width(src) >> 16;
1067         actual_h = drm_rect_height(src) >> 16;
1068         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1069
1070         dsp_info = (drm_rect_height(dest) - 1) << 16;
1071         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1072
1073         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1074         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1075         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1076
1077         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1078         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1079
1080         vop = to_vop(state->crtc);
1081         s = to_rockchip_crtc_state(crtc->state);
1082
1083         spin_lock(&vop->reg_lock);
1084
1085         VOP_WIN_SET(vop, win, xmirror, xmirror);
1086         VOP_WIN_SET(vop, win, ymirror, ymirror);
1087         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1088         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1089         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1090         if (is_yuv_support(fb->pixel_format)) {
1091                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1092                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1093         }
1094         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1095
1096         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1097                             drm_rect_width(dest), drm_rect_height(dest),
1098                             fb->pixel_format);
1099
1100         VOP_WIN_SET(vop, win, act_info, act_info);
1101         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1102         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1103
1104         rb_swap = has_rb_swapped(fb->pixel_format);
1105         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1106
1107         if (is_alpha_support(fb->pixel_format) &&
1108             (s->dsp_layer_sel & 0x3) != win->win_id) {
1109                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1110                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1111                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1112                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1113                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1114                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1115                         SRC_FACTOR_M0(ALPHA_ONE);
1116                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1117                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1118                 VOP_WIN_SET(vop, win, alpha_en, 1);
1119         } else {
1120                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1121                 VOP_WIN_SET(vop, win, alpha_en, 0);
1122         }
1123
1124         if (win->csc) {
1125                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1126                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1127                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1128                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1129                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1130                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1131         }
1132         VOP_WIN_SET(vop, win, enable, 1);
1133         spin_unlock(&vop->reg_lock);
1134         vop->is_iommu_needed = true;
1135 }
1136
1137 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1138         .prepare_fb = vop_plane_prepare_fb,
1139         .cleanup_fb = vop_plane_cleanup_fb,
1140         .atomic_check = vop_plane_atomic_check,
1141         .atomic_update = vop_plane_atomic_update,
1142         .atomic_disable = vop_plane_atomic_disable,
1143 };
1144
1145 void vop_atomic_plane_reset(struct drm_plane *plane)
1146 {
1147         struct vop_win *win = to_vop_win(plane);
1148         struct vop_plane_state *vop_plane_state =
1149                                         to_vop_plane_state(plane->state);
1150
1151         if (plane->state && plane->state->fb)
1152                 drm_framebuffer_unreference(plane->state->fb);
1153
1154         kfree(vop_plane_state);
1155         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1156         if (!vop_plane_state)
1157                 return;
1158
1159         vop_plane_state->zpos = win->win_id;
1160         plane->state = &vop_plane_state->base;
1161         plane->state->plane = plane;
1162 }
1163
1164 struct drm_plane_state *
1165 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1166 {
1167         struct vop_plane_state *old_vop_plane_state;
1168         struct vop_plane_state *vop_plane_state;
1169
1170         if (WARN_ON(!plane->state))
1171                 return NULL;
1172
1173         old_vop_plane_state = to_vop_plane_state(plane->state);
1174         vop_plane_state = kmemdup(old_vop_plane_state,
1175                                   sizeof(*vop_plane_state), GFP_KERNEL);
1176         if (!vop_plane_state)
1177                 return NULL;
1178
1179         __drm_atomic_helper_plane_duplicate_state(plane,
1180                                                   &vop_plane_state->base);
1181
1182         return &vop_plane_state->base;
1183 }
1184
1185 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1186                                            struct drm_plane_state *state)
1187 {
1188         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1189
1190         __drm_atomic_helper_plane_destroy_state(plane, state);
1191
1192         kfree(vop_state);
1193 }
1194
1195 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1196                                          struct drm_plane_state *state,
1197                                          struct drm_property *property,
1198                                          uint64_t val)
1199 {
1200         struct vop_win *win = to_vop_win(plane);
1201         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1202
1203         if (property == win->vop->plane_zpos_prop) {
1204                 plane_state->zpos = val;
1205                 return 0;
1206         }
1207
1208         if (property == win->rotation_prop) {
1209                 state->rotation = val;
1210                 return 0;
1211         }
1212
1213         DRM_ERROR("failed to set vop plane property\n");
1214         return -EINVAL;
1215 }
1216
1217 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1218                                          const struct drm_plane_state *state,
1219                                          struct drm_property *property,
1220                                          uint64_t *val)
1221 {
1222         struct vop_win *win = to_vop_win(plane);
1223         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1224
1225         if (property == win->vop->plane_zpos_prop) {
1226                 *val = plane_state->zpos;
1227                 return 0;
1228         }
1229
1230         if (property == win->rotation_prop) {
1231                 *val = state->rotation;
1232                 return 0;
1233         }
1234
1235         DRM_ERROR("failed to get vop plane property\n");
1236         return -EINVAL;
1237 }
1238
1239 static const struct drm_plane_funcs vop_plane_funcs = {
1240         .update_plane   = drm_atomic_helper_update_plane,
1241         .disable_plane  = drm_atomic_helper_disable_plane,
1242         .destroy = vop_plane_destroy,
1243         .reset = vop_atomic_plane_reset,
1244         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1245         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1246         .atomic_set_property = vop_atomic_plane_set_property,
1247         .atomic_get_property = vop_atomic_plane_get_property,
1248 };
1249
1250 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1251 {
1252         struct vop *vop = to_vop(crtc);
1253         unsigned long flags;
1254
1255         if (!vop->is_enabled)
1256                 return -EPERM;
1257
1258         spin_lock_irqsave(&vop->irq_lock, flags);
1259
1260         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1261         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1262
1263         spin_unlock_irqrestore(&vop->irq_lock, flags);
1264
1265         return 0;
1266 }
1267
1268 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1269 {
1270         struct vop *vop = to_vop(crtc);
1271         unsigned long flags;
1272
1273         if (!vop->is_enabled)
1274                 return;
1275
1276         spin_lock_irqsave(&vop->irq_lock, flags);
1277
1278         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1279
1280         spin_unlock_irqrestore(&vop->irq_lock, flags);
1281 }
1282
1283 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1284 {
1285         struct vop *vop = to_vop(crtc);
1286
1287         reinit_completion(&vop->wait_update_complete);
1288         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1289 }
1290
1291 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1292                                            struct drm_file *file_priv)
1293 {
1294         struct drm_device *drm = crtc->dev;
1295         struct vop *vop = to_vop(crtc);
1296         struct drm_pending_vblank_event *e;
1297         unsigned long flags;
1298
1299         spin_lock_irqsave(&drm->event_lock, flags);
1300         e = vop->event;
1301         if (e && e->base.file_priv == file_priv) {
1302                 vop->event = NULL;
1303
1304                 e->base.destroy(&e->base);
1305                 file_priv->event_space += sizeof(e->event);
1306         }
1307         spin_unlock_irqrestore(&drm->event_lock, flags);
1308 }
1309
1310 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1311 {
1312         struct vop *vop = to_vop(crtc);
1313
1314         if (on == vop->loader_protect)
1315                 return 0;
1316
1317         if (on) {
1318                 vop_power_enable(crtc);
1319                 enable_irq(vop->irq);
1320                 drm_crtc_vblank_on(crtc);
1321                 vop->loader_protect = true;
1322         } else {
1323                 vop_crtc_disable(crtc);
1324
1325                 vop->loader_protect = false;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1332 {
1333         struct vop_win *win = to_vop_win(plane);
1334         struct drm_plane_state *state = plane->state;
1335         struct vop_plane_state *pstate = to_vop_plane_state(state);
1336         struct drm_rect *src, *dest;
1337         struct drm_framebuffer *fb = state->fb;
1338         int i;
1339
1340         seq_printf(s, "win%d-%d: status=%s\n", win->win_id, win->area_id,
1341                    pstate->enable ? "active" : "disabled");
1342         if (!fb)
1343                 return 0;
1344
1345         src = &pstate->src;
1346         dest = &pstate->dest;
1347
1348         seq_printf(s, "\tformat: %s\n", drm_get_format_name(fb->pixel_format));
1349         seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1350         seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1351                    src->y1 >> 16, drm_rect_width(src) >> 16,
1352                    drm_rect_height(src) >> 16);
1353         seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1354                    drm_rect_width(dest), drm_rect_height(dest));
1355
1356         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1357                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1358                 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1359                            i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1360         }
1361
1362         return 0;
1363 }
1364
1365 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1366 {
1367         struct vop *vop = to_vop(crtc);
1368         struct drm_crtc_state *crtc_state = crtc->state;
1369         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1370         struct drm_plane *plane;
1371         int i;
1372
1373         seq_printf(s, "vop name: %s status=%s\n", dev_name(vop->dev),
1374                    crtc_state->active ? "active" : "disabled");
1375
1376         if (!crtc_state->active)
1377                 return 0;
1378
1379         seq_printf(s, "Display mode: %s fps[%d] clk[%d] type[%d] flag[%x]\n",
1380                    mode->name, drm_mode_vrefresh(mode), mode->clock,
1381                    mode->type, mode->flags);
1382         seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1383                    mode->hsync_end, mode->htotal);
1384         seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1385                    mode->vsync_end, mode->vtotal);
1386
1387         for (i = 0; i < vop->num_wins; i++) {
1388                 plane = &vop->win[i].base;
1389                 vop_plane_info_dump(s, plane);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static enum drm_mode_status
1396 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1397                     int output_type)
1398 {
1399         struct vop *vop = to_vop(crtc);
1400         const struct vop_data *vop_data = vop->data;
1401         int clock;
1402
1403         if (mode->hdisplay > vop_data->max_disably_output.width)
1404                 return MODE_BAD_HVALUE;
1405         if (mode->vdisplay > vop_data->max_disably_output.height)
1406                 return MODE_BAD_VVALUE;
1407
1408         clock = clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1409         /*
1410          * Hdmi or DisplayPort request a Accurate clock.
1411          */
1412         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1413             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1414                 if (clock != mode->clock)
1415                         return MODE_CLOCK_RANGE;
1416
1417         return MODE_OK;
1418 }
1419
1420 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1421         .loader_protect = vop_crtc_loader_protect,
1422         .enable_vblank = vop_crtc_enable_vblank,
1423         .disable_vblank = vop_crtc_disable_vblank,
1424         .wait_for_update = vop_crtc_wait_for_update,
1425         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1426         .debugfs_dump = vop_crtc_debugfs_dump,
1427         .mode_valid = vop_crtc_mode_valid,
1428 };
1429
1430 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1431                                 const struct drm_display_mode *mode,
1432                                 struct drm_display_mode *adjusted_mode)
1433 {
1434         struct vop *vop = to_vop(crtc);
1435         const struct vop_data *vop_data = vop->data;
1436
1437         if (mode->hdisplay > vop_data->max_disably_output.width ||
1438             mode->vdisplay > vop_data->max_disably_output.height)
1439                 return false;
1440
1441         adjusted_mode->clock =
1442                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1443
1444         return true;
1445 }
1446
1447 static void vop_crtc_enable(struct drm_crtc *crtc)
1448 {
1449         struct vop *vop = to_vop(crtc);
1450         const struct vop_data *vop_data = vop->data;
1451         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1452         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1453         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1454         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1455         u16 htotal = adjusted_mode->crtc_htotal;
1456         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1457         u16 hact_end = hact_st + hdisplay;
1458         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1459         u16 vtotal = adjusted_mode->crtc_vtotal;
1460         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1461         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1462         u16 vact_end = vact_st + vdisplay;
1463         uint32_t val;
1464
1465         vop_initial(crtc);
1466
1467         val = BIT(DCLK_INVERT);
1468         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1469                    0 : BIT(HSYNC_POSITIVE);
1470         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1471                    0 : BIT(VSYNC_POSITIVE);
1472         VOP_CTRL_SET(vop, pin_pol, val);
1473         switch (s->output_type) {
1474         case DRM_MODE_CONNECTOR_LVDS:
1475                 VOP_CTRL_SET(vop, rgb_en, 1);
1476                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1477                 break;
1478         case DRM_MODE_CONNECTOR_eDP:
1479                 VOP_CTRL_SET(vop, edp_en, 1);
1480                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1481                 break;
1482         case DRM_MODE_CONNECTOR_HDMIA:
1483                 VOP_CTRL_SET(vop, hdmi_en, 1);
1484                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1485                 break;
1486         case DRM_MODE_CONNECTOR_DSI:
1487                 VOP_CTRL_SET(vop, mipi_en, 1);
1488                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1489                 break;
1490         case DRM_MODE_CONNECTOR_DisplayPort:
1491                 val &= ~BIT(DCLK_INVERT);
1492                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1493                 VOP_CTRL_SET(vop, dp_en, 1);
1494                 break;
1495         default:
1496                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1497         }
1498
1499         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1500             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1501                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1502
1503         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1504         switch (s->bus_format) {
1505         case MEDIA_BUS_FMT_RGB565_1X16:
1506                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1507                 break;
1508         case MEDIA_BUS_FMT_RGB666_1X18:
1509         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1510                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1511                 break;
1512         case MEDIA_BUS_FMT_RGB888_1X24:
1513         default:
1514                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1515                 break;
1516         }
1517         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1518                 val |= PRE_DITHER_DOWN_EN(0);
1519         else
1520                 val |= PRE_DITHER_DOWN_EN(1);
1521         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1522         VOP_CTRL_SET(vop, dither_down, val);
1523
1524         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1525         val = hact_st << 16;
1526         val |= hact_end;
1527         VOP_CTRL_SET(vop, hact_st_end, val);
1528         VOP_CTRL_SET(vop, hpost_st_end, val);
1529
1530         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1531         val = vact_st << 16;
1532         val |= vact_end;
1533         VOP_CTRL_SET(vop, vact_st_end, val);
1534         VOP_CTRL_SET(vop, vpost_st_end, val);
1535         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1536                 u16 vact_st_f1 = vtotal + vact_st + 1;
1537                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1538
1539                 val = vact_st_f1 << 16 | vact_end_f1;
1540                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1541                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1542
1543                 val = vtotal << 16 | (vtotal + vsync_len);
1544                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1545                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1546                 VOP_CTRL_SET(vop, p2i_en, 1);
1547         } else {
1548                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1549                 VOP_CTRL_SET(vop, p2i_en, 0);
1550         }
1551
1552         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1553
1554         vop_cfg_done(vop);
1555         /*
1556          * enable vop, all the register would take effect when vop exit standby
1557          */
1558         VOP_CTRL_SET(vop, standby, 0);
1559
1560         enable_irq(vop->irq);
1561         drm_crtc_vblank_on(crtc);
1562 }
1563
1564 static int vop_zpos_cmp(const void *a, const void *b)
1565 {
1566         struct vop_zpos *pa = (struct vop_zpos *)a;
1567         struct vop_zpos *pb = (struct vop_zpos *)b;
1568
1569         return pa->zpos - pb->zpos;
1570 }
1571
1572 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1573                                   struct drm_crtc_state *crtc_state)
1574 {
1575         struct vop *vop = to_vop(crtc);
1576         const struct vop_data *vop_data = vop->data;
1577         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1578         struct drm_atomic_state *state = crtc_state->state;
1579         struct drm_plane *plane;
1580         struct drm_plane_state *pstate;
1581         struct vop_plane_state *plane_state;
1582         struct vop_win *win;
1583         int afbdc_format;
1584         int i;
1585
1586         s->afbdc_en = 0;
1587
1588         for_each_plane_in_state(state, plane, pstate, i) {
1589                 struct drm_framebuffer *fb = pstate->fb;
1590                 struct drm_rect *src;
1591
1592                 win = to_vop_win(plane);
1593                 plane_state = to_vop_plane_state(pstate);
1594
1595                 if (pstate->crtc != crtc || !fb)
1596                         continue;
1597
1598                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1599                         continue;
1600
1601                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1602                         DRM_ERROR("not support afbdc\n");
1603                         return -EINVAL;
1604                 }
1605
1606                 switch (plane_state->format) {
1607                 case VOP_FMT_ARGB8888:
1608                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1609                         break;
1610                 case VOP_FMT_RGB888:
1611                         afbdc_format = AFBDC_FMT_U8U8U8;
1612                         break;
1613                 case VOP_FMT_RGB565:
1614                         afbdc_format = AFBDC_FMT_RGB565;
1615                         break;
1616                 default:
1617                         return -EINVAL;
1618                 }
1619
1620                 if (s->afbdc_en) {
1621                         DRM_ERROR("vop only support one afbc layer\n");
1622                         return -EINVAL;
1623                 }
1624
1625                 src = &plane_state->src;
1626                 if (src->x1 || src->y1 || fb->offsets[0]) {
1627                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1628                                   win->win_id);
1629                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1630                                   src->x1, src->y1, fb->offsets[0]);
1631                         return -EINVAL;
1632                 }
1633                 s->afbdc_win_format = afbdc_format;
1634                 s->afbdc_win_width = pstate->fb->width - 1;
1635                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1636                 s->afbdc_win_id = win->win_id;
1637                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1638                 s->afbdc_en = 1;
1639         }
1640
1641         return 0;
1642 }
1643
1644 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1645                                  struct drm_crtc_state *crtc_state)
1646 {
1647         struct drm_atomic_state *state = crtc_state->state;
1648         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1649         struct vop *vop = to_vop(crtc);
1650         const struct vop_data *vop_data = vop->data;
1651         struct drm_plane *plane;
1652         struct drm_plane_state *pstate;
1653         struct vop_plane_state *plane_state;
1654         struct vop_zpos *pzpos;
1655         int dsp_layer_sel = 0;
1656         int i, j, cnt = 0, ret = 0;
1657
1658         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1659         if (ret)
1660                 return ret;
1661
1662         ret = vop_csc_atomic_check(crtc, crtc_state);
1663         if (ret)
1664                 return ret;
1665
1666         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1667         if (!pzpos)
1668                 return -ENOMEM;
1669
1670         for (i = 0; i < vop_data->win_size; i++) {
1671                 const struct vop_win_data *win_data = &vop_data->win[i];
1672                 struct vop_win *win;
1673
1674                 if (!win_data->phy)
1675                         continue;
1676
1677                 for (j = 0; j < vop->num_wins; j++) {
1678                         win = &vop->win[j];
1679
1680                         if (win->win_id == i && !win->area_id)
1681                                 break;
1682                 }
1683                 if (WARN_ON(j >= vop->num_wins)) {
1684                         ret = -EINVAL;
1685                         goto err_free_pzpos;
1686                 }
1687
1688                 plane = &win->base;
1689                 pstate = state->plane_states[drm_plane_index(plane)];
1690                 /*
1691                  * plane might not have changed, in which case take
1692                  * current state:
1693                  */
1694                 if (!pstate)
1695                         pstate = plane->state;
1696                 plane_state = to_vop_plane_state(pstate);
1697                 pzpos[cnt].zpos = plane_state->zpos;
1698                 pzpos[cnt++].win_id = win->win_id;
1699         }
1700
1701         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1702
1703         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1704                 const struct vop_win_data *win_data = &vop_data->win[i];
1705                 int shift = i * 2;
1706
1707                 if (win_data->phy) {
1708                         struct vop_zpos *zpos = &pzpos[cnt++];
1709
1710                         dsp_layer_sel |= zpos->win_id << shift;
1711                 } else {
1712                         dsp_layer_sel |= i << shift;
1713                 }
1714         }
1715
1716         s->dsp_layer_sel = dsp_layer_sel;
1717
1718 err_free_pzpos:
1719         kfree(pzpos);
1720         return ret;
1721 }
1722
1723 static void vop_post_config(struct drm_crtc *crtc)
1724 {
1725         struct vop *vop = to_vop(crtc);
1726         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1727         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1728         u16 vtotal = mode->crtc_vtotal;
1729         u16 hdisplay = mode->crtc_hdisplay;
1730         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1731         u16 vdisplay = mode->crtc_vdisplay;
1732         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1733         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1734         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1735         u16 hact_end, vact_end;
1736         u32 val;
1737
1738         hact_st += hdisplay * (100 - s->left_margin) / 200;
1739         hact_end = hact_st + hsize;
1740         val = hact_st << 16;
1741         val |= hact_end;
1742         VOP_CTRL_SET(vop, hpost_st_end, val);
1743         vact_st += vdisplay * (100 - s->top_margin) / 200;
1744         vact_end = vact_st + vsize;
1745         val = vact_st << 16;
1746         val |= vact_end;
1747         VOP_CTRL_SET(vop, vpost_st_end, val);
1748         val = scl_cal_scale2(vdisplay, vsize) << 16;
1749         val |= scl_cal_scale2(hdisplay, hsize);
1750         VOP_CTRL_SET(vop, post_scl_factor, val);
1751         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1752         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1753                 u16 vact_st_f1 = vtotal + vact_st + 1;
1754                 u16 vact_end_f1 = vact_st_f1 + vsize;
1755
1756                 val = vact_st_f1 << 16 | vact_end_f1;
1757                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1758         }
1759 }
1760
1761 static void vop_cfg_update(struct drm_crtc *crtc,
1762                            struct drm_crtc_state *old_crtc_state)
1763 {
1764         struct rockchip_crtc_state *s =
1765                         to_rockchip_crtc_state(crtc->state);
1766         struct vop *vop = to_vop(crtc);
1767
1768         spin_lock(&vop->reg_lock);
1769
1770         if (s->afbdc_en) {
1771                 uint32_t pic_size;
1772
1773                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1774                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1775                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1776                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1777                 pic_size = (s->afbdc_win_width & 0xffff);
1778                 pic_size |= s->afbdc_win_height << 16;
1779                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1780         }
1781
1782         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1783         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1784         vop_post_config(crtc);
1785
1786         spin_unlock(&vop->reg_lock);
1787 }
1788
1789 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1790                                   struct drm_crtc_state *old_crtc_state)
1791 {
1792         struct vop *vop = to_vop(crtc);
1793
1794         vop_cfg_update(crtc, old_crtc_state);
1795
1796         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1797                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1798                 int ret;
1799
1800                 if (need_wait_vblank) {
1801                         bool active;
1802
1803                         disable_irq(vop->irq);
1804                         drm_crtc_vblank_get(crtc);
1805                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1806
1807                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1808                                                         vop, active, active,
1809                                                         0, 50 * 1000);
1810                         if (ret)
1811                                 dev_err(vop->dev, "wait fs irq timeout\n");
1812
1813                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1814                         vop_cfg_done(vop);
1815
1816                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1817                                                         vop, active, active,
1818                                                         0, 50 * 1000);
1819                         if (ret)
1820                                 dev_err(vop->dev, "wait line flag timeout\n");
1821
1822                         enable_irq(vop->irq);
1823                 }
1824                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1825                 if (ret)
1826                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1827                                 ret);
1828
1829                 if (need_wait_vblank) {
1830                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1831                         drm_crtc_vblank_put(crtc);
1832                 }
1833
1834                 vop->is_iommu_enabled = true;
1835         }
1836
1837         vop_cfg_done(vop);
1838 }
1839
1840 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1841                                   struct drm_crtc_state *old_crtc_state)
1842 {
1843         struct vop *vop = to_vop(crtc);
1844
1845         if (crtc->state->event) {
1846                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1847
1848                 vop->event = crtc->state->event;
1849                 crtc->state->event = NULL;
1850         }
1851 }
1852
1853 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1854         .enable = vop_crtc_enable,
1855         .disable = vop_crtc_disable,
1856         .mode_fixup = vop_crtc_mode_fixup,
1857         .atomic_check = vop_crtc_atomic_check,
1858         .atomic_flush = vop_crtc_atomic_flush,
1859         .atomic_begin = vop_crtc_atomic_begin,
1860 };
1861
1862 static void vop_crtc_destroy(struct drm_crtc *crtc)
1863 {
1864         drm_crtc_cleanup(crtc);
1865 }
1866
1867 static void vop_crtc_reset(struct drm_crtc *crtc)
1868 {
1869         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1870
1871         if (crtc->state) {
1872                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1873                 kfree(s);
1874         }
1875
1876         s = kzalloc(sizeof(*s), GFP_KERNEL);
1877         if (!s)
1878                 return;
1879         crtc->state = &s->base;
1880         crtc->state->crtc = crtc;
1881         s->left_margin = 100;
1882         s->right_margin = 100;
1883         s->top_margin = 100;
1884         s->bottom_margin = 100;
1885 }
1886
1887 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1888 {
1889         struct rockchip_crtc_state *rockchip_state, *old_state;
1890
1891         old_state = to_rockchip_crtc_state(crtc->state);
1892         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1893         if (!rockchip_state)
1894                 return NULL;
1895
1896         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1897         return &rockchip_state->base;
1898 }
1899
1900 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1901                                    struct drm_crtc_state *state)
1902 {
1903         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1904
1905         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1906         kfree(s);
1907 }
1908
1909 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
1910                                         const struct drm_crtc_state *state,
1911                                         struct drm_property *property,
1912                                         uint64_t *val)
1913 {
1914         struct drm_device *drm_dev = crtc->dev;
1915         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1916         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1917
1918         if (property == mode_config->tv_left_margin_property) {
1919                 *val = s->left_margin;
1920                 return 0;
1921         }
1922
1923         if (property == mode_config->tv_right_margin_property) {
1924                 *val = s->right_margin;
1925                 return 0;
1926         }
1927
1928         if (property == mode_config->tv_top_margin_property) {
1929                 *val = s->top_margin;
1930                 return 0;
1931         }
1932
1933         if (property == mode_config->tv_bottom_margin_property) {
1934                 *val = s->bottom_margin;
1935                 return 0;
1936         }
1937
1938         DRM_ERROR("failed to get vop crtc property\n");
1939         return -EINVAL;
1940 }
1941
1942 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
1943                                         struct drm_crtc_state *state,
1944                                         struct drm_property *property,
1945                                         uint64_t val)
1946 {
1947         struct drm_device *drm_dev = crtc->dev;
1948         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1949         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1950
1951         if (property == mode_config->tv_left_margin_property) {
1952                 s->left_margin = val;
1953                 return 0;
1954         }
1955
1956         if (property == mode_config->tv_right_margin_property) {
1957                 s->right_margin = val;
1958                 return 0;
1959         }
1960
1961         if (property == mode_config->tv_top_margin_property) {
1962                 s->top_margin = val;
1963                 return 0;
1964         }
1965
1966         if (property == mode_config->tv_bottom_margin_property) {
1967                 s->bottom_margin = val;
1968                 return 0;
1969         }
1970
1971         DRM_ERROR("failed to set vop crtc property\n");
1972         return -EINVAL;
1973 }
1974
1975 static const struct drm_crtc_funcs vop_crtc_funcs = {
1976         .set_config = drm_atomic_helper_set_config,
1977         .page_flip = drm_atomic_helper_page_flip,
1978         .destroy = vop_crtc_destroy,
1979         .reset = vop_crtc_reset,
1980         .atomic_get_property = vop_crtc_atomic_get_property,
1981         .atomic_set_property = vop_crtc_atomic_set_property,
1982         .atomic_duplicate_state = vop_crtc_duplicate_state,
1983         .atomic_destroy_state = vop_crtc_destroy_state,
1984 };
1985
1986 static void vop_handle_vblank(struct vop *vop)
1987 {
1988         struct drm_device *drm = vop->drm_dev;
1989         struct drm_crtc *crtc = &vop->crtc;
1990         unsigned long flags;
1991
1992         if (!vop_is_cfg_done_complete(vop))
1993                 return;
1994
1995         if (vop->event) {
1996                 spin_lock_irqsave(&drm->event_lock, flags);
1997
1998                 drm_crtc_send_vblank_event(crtc, vop->event);
1999                 drm_crtc_vblank_put(crtc);
2000                 vop->event = NULL;
2001
2002                 spin_unlock_irqrestore(&drm->event_lock, flags);
2003         }
2004         if (!completion_done(&vop->wait_update_complete))
2005                 complete(&vop->wait_update_complete);
2006 }
2007
2008 static irqreturn_t vop_isr(int irq, void *data)
2009 {
2010         struct vop *vop = data;
2011         struct drm_crtc *crtc = &vop->crtc;
2012         uint32_t active_irqs;
2013         unsigned long flags;
2014         int ret = IRQ_NONE;
2015
2016         /*
2017          * interrupt register has interrupt status, enable and clear bits, we
2018          * must hold irq_lock to avoid a race with enable/disable_vblank().
2019         */
2020         spin_lock_irqsave(&vop->irq_lock, flags);
2021
2022         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2023         /* Clear all active interrupt sources */
2024         if (active_irqs)
2025                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2026
2027         spin_unlock_irqrestore(&vop->irq_lock, flags);
2028
2029         /* This is expected for vop iommu irqs, since the irq is shared */
2030         if (!active_irqs)
2031                 return IRQ_NONE;
2032
2033         if (active_irqs & DSP_HOLD_VALID_INTR) {
2034                 complete(&vop->dsp_hold_completion);
2035                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2036                 ret = IRQ_HANDLED;
2037         }
2038
2039         if (active_irqs & LINE_FLAG_INTR) {
2040                 complete(&vop->line_flag_completion);
2041                 active_irqs &= ~LINE_FLAG_INTR;
2042                 ret = IRQ_HANDLED;
2043         }
2044
2045         if (active_irqs & FS_INTR) {
2046                 drm_crtc_handle_vblank(crtc);
2047                 vop_handle_vblank(vop);
2048                 active_irqs &= ~FS_INTR;
2049                 ret = IRQ_HANDLED;
2050         }
2051
2052         /* Unhandled irqs are spurious. */
2053         if (active_irqs)
2054                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2055
2056         return ret;
2057 }
2058
2059 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2060                           unsigned long possible_crtcs)
2061 {
2062         struct drm_plane *share = NULL;
2063         unsigned int rotations = 0;
2064         struct drm_property *prop;
2065         uint64_t feature = 0;
2066         int ret;
2067
2068         if (win->parent)
2069                 share = &win->parent->base;
2070
2071         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2072                                    possible_crtcs, &vop_plane_funcs,
2073                                    win->data_formats, win->nformats, win->type);
2074         if (ret) {
2075                 DRM_ERROR("failed to initialize plane\n");
2076                 return ret;
2077         }
2078         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2079         drm_object_attach_property(&win->base.base,
2080                                    vop->plane_zpos_prop, win->win_id);
2081
2082         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2083                 rotations |= BIT(DRM_REFLECT_X);
2084
2085         if (VOP_WIN_SUPPORT(vop, win, ymirror))
2086                 rotations |= BIT(DRM_REFLECT_Y);
2087
2088         if (rotations) {
2089                 rotations |= BIT(DRM_ROTATE_0);
2090                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2091                                                          rotations);
2092                 if (!prop) {
2093                         DRM_ERROR("failed to create zpos property\n");
2094                         return -EINVAL;
2095                 }
2096                 drm_object_attach_property(&win->base.base, prop,
2097                                            BIT(DRM_ROTATE_0));
2098                 win->rotation_prop = prop;
2099         }
2100         if (win->phy->scl)
2101                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2102         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2103             VOP_WIN_SUPPORT(vop, win, alpha_en))
2104                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2105
2106         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2107                                    feature);
2108
2109         return 0;
2110 }
2111
2112 static int vop_create_crtc(struct vop *vop)
2113 {
2114         struct device *dev = vop->dev;
2115         const struct vop_data *vop_data = vop->data;
2116         struct drm_device *drm_dev = vop->drm_dev;
2117         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2118         struct drm_crtc *crtc = &vop->crtc;
2119         struct device_node *port;
2120         uint64_t feature = 0;
2121         int ret;
2122         int i;
2123
2124         /*
2125          * Create drm_plane for primary and cursor planes first, since we need
2126          * to pass them to drm_crtc_init_with_planes, which sets the
2127          * "possible_crtcs" to the newly initialized crtc.
2128          */
2129         for (i = 0; i < vop->num_wins; i++) {
2130                 struct vop_win *win = &vop->win[i];
2131
2132                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2133                     win->type != DRM_PLANE_TYPE_CURSOR)
2134                         continue;
2135
2136                 ret = vop_plane_init(vop, win, 0);
2137                 if (ret)
2138                         goto err_cleanup_planes;
2139
2140                 plane = &win->base;
2141                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2142                         primary = plane;
2143                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2144                         cursor = plane;
2145
2146         }
2147
2148         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2149                                         &vop_crtc_funcs, NULL);
2150         if (ret)
2151                 goto err_cleanup_planes;
2152
2153         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2154
2155         /*
2156          * Create drm_planes for overlay windows with possible_crtcs restricted
2157          * to the newly created crtc.
2158          */
2159         for (i = 0; i < vop->num_wins; i++) {
2160                 struct vop_win *win = &vop->win[i];
2161                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2162
2163                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2164                         continue;
2165
2166                 ret = vop_plane_init(vop, win, possible_crtcs);
2167                 if (ret)
2168                         goto err_cleanup_crtc;
2169         }
2170
2171         port = of_get_child_by_name(dev->of_node, "port");
2172         if (!port) {
2173                 DRM_ERROR("no port node found in %s\n",
2174                           dev->of_node->full_name);
2175                 ret = -ENOENT;
2176                 goto err_cleanup_crtc;
2177         }
2178
2179         init_completion(&vop->dsp_hold_completion);
2180         init_completion(&vop->wait_update_complete);
2181         init_completion(&vop->line_flag_completion);
2182         crtc->port = port;
2183         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2184
2185         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2186         if (ret)
2187                 goto err_unregister_crtc_funcs;
2188 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2189         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2190
2191         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2192         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2193         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2194         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2195 #undef VOP_ATTACH_MODE_CONFIG_PROP
2196
2197         if (vop_data->feature & VOP_FEATURE_AFBDC)
2198                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2199         drm_object_attach_property(&crtc->base, vop->feature_prop,
2200                                    feature);
2201
2202         return 0;
2203
2204 err_unregister_crtc_funcs:
2205         rockchip_unregister_crtc_funcs(crtc);
2206 err_cleanup_crtc:
2207         drm_crtc_cleanup(crtc);
2208 err_cleanup_planes:
2209         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2210                                  head)
2211                 drm_plane_cleanup(plane);
2212         return ret;
2213 }
2214
2215 static void vop_destroy_crtc(struct vop *vop)
2216 {
2217         struct drm_crtc *crtc = &vop->crtc;
2218         struct drm_device *drm_dev = vop->drm_dev;
2219         struct drm_plane *plane, *tmp;
2220
2221         rockchip_unregister_crtc_funcs(crtc);
2222         of_node_put(crtc->port);
2223
2224         /*
2225          * We need to cleanup the planes now.  Why?
2226          *
2227          * The planes are "&vop->win[i].base".  That means the memory is
2228          * all part of the big "struct vop" chunk of memory.  That memory
2229          * was devm allocated and associated with this component.  We need to
2230          * free it ourselves before vop_unbind() finishes.
2231          */
2232         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2233                                  head)
2234                 vop_plane_destroy(plane);
2235
2236         /*
2237          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2238          * references the CRTC.
2239          */
2240         drm_crtc_cleanup(crtc);
2241 }
2242
2243 /*
2244  * Initialize the vop->win array elements.
2245  */
2246 static int vop_win_init(struct vop *vop)
2247 {
2248         const struct vop_data *vop_data = vop->data;
2249         unsigned int i, j;
2250         unsigned int num_wins = 0;
2251         struct drm_property *prop;
2252         static const struct drm_prop_enum_list props[] = {
2253                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2254                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2255         };
2256         static const struct drm_prop_enum_list crtc_props[] = {
2257                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2258         };
2259
2260         for (i = 0; i < vop_data->win_size; i++) {
2261                 struct vop_win *vop_win = &vop->win[num_wins];
2262                 const struct vop_win_data *win_data = &vop_data->win[i];
2263
2264                 if (!win_data->phy)
2265                         continue;
2266
2267                 vop_win->phy = win_data->phy;
2268                 vop_win->csc = win_data->csc;
2269                 vop_win->offset = win_data->base;
2270                 vop_win->type = win_data->type;
2271                 vop_win->data_formats = win_data->phy->data_formats;
2272                 vop_win->nformats = win_data->phy->nformats;
2273                 vop_win->vop = vop;
2274                 vop_win->win_id = i;
2275                 vop_win->area_id = 0;
2276                 num_wins++;
2277
2278                 for (j = 0; j < win_data->area_size; j++) {
2279                         struct vop_win *vop_area = &vop->win[num_wins];
2280                         const struct vop_win_phy *area = win_data->area[j];
2281
2282                         vop_area->parent = vop_win;
2283                         vop_area->offset = vop_win->offset;
2284                         vop_area->phy = area;
2285                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2286                         vop_area->data_formats = vop_win->data_formats;
2287                         vop_area->nformats = vop_win->nformats;
2288                         vop_area->vop = vop;
2289                         vop_area->win_id = i;
2290                         vop_area->area_id = j;
2291                         num_wins++;
2292                 }
2293         }
2294
2295         vop->num_wins = num_wins;
2296
2297         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2298                                          "ZPOS", 0, vop->data->win_size);
2299         if (!prop) {
2300                 DRM_ERROR("failed to create zpos property\n");
2301                 return -EINVAL;
2302         }
2303         vop->plane_zpos_prop = prop;
2304
2305         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2306                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2307                                 props, ARRAY_SIZE(props),
2308                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2309                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2310         if (!vop->plane_feature_prop) {
2311                 DRM_ERROR("failed to create feature property\n");
2312                 return -EINVAL;
2313         }
2314
2315         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2316                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2317                                 crtc_props, ARRAY_SIZE(crtc_props),
2318                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2319         if (!vop->feature_prop) {
2320                 DRM_ERROR("failed to create vop feature property\n");
2321                 return -EINVAL;
2322         }
2323
2324         return 0;
2325 }
2326
2327 /**
2328  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2329  * @crtc: CRTC to enable line flag
2330  * @line_num: interested line number
2331  * @mstimeout: millisecond for timeout
2332  *
2333  * Driver would hold here until the interested line flag interrupt have
2334  * happened or timeout to wait.
2335  *
2336  * Returns:
2337  * Zero on success, negative errno on failure.
2338  */
2339 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2340                                 unsigned int mstimeout)
2341 {
2342         struct vop *vop = to_vop(crtc);
2343         unsigned long jiffies_left;
2344
2345         if (!crtc || !vop->is_enabled)
2346                 return -ENODEV;
2347
2348         if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2349                 return -EINVAL;
2350
2351         if (vop_line_flag_irq_is_enabled(vop))
2352                 return -EBUSY;
2353
2354         reinit_completion(&vop->line_flag_completion);
2355         vop_line_flag_irq_enable(vop, line_num);
2356
2357         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2358                                                    msecs_to_jiffies(mstimeout));
2359         vop_line_flag_irq_disable(vop);
2360
2361         if (jiffies_left == 0) {
2362                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2363                 return -ETIMEDOUT;
2364         }
2365
2366         return 0;
2367 }
2368 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2369
2370 static int vop_bind(struct device *dev, struct device *master, void *data)
2371 {
2372         struct platform_device *pdev = to_platform_device(dev);
2373         const struct vop_data *vop_data;
2374         struct drm_device *drm_dev = data;
2375         struct vop *vop;
2376         struct resource *res;
2377         size_t alloc_size;
2378         int ret, irq, i;
2379         int num_wins = 0;
2380
2381         vop_data = of_device_get_match_data(dev);
2382         if (!vop_data)
2383                 return -ENODEV;
2384
2385         for (i = 0; i < vop_data->win_size; i++) {
2386                 const struct vop_win_data *win_data = &vop_data->win[i];
2387
2388                 num_wins += win_data->area_size + 1;
2389         }
2390
2391         /* Allocate vop struct and its vop_win array */
2392         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2393         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2394         if (!vop)
2395                 return -ENOMEM;
2396
2397         vop->dev = dev;
2398         vop->data = vop_data;
2399         vop->drm_dev = drm_dev;
2400         vop->num_wins = num_wins;
2401         dev_set_drvdata(dev, vop);
2402
2403         ret = vop_win_init(vop);
2404         if (ret)
2405                 return ret;
2406
2407         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2408         vop->len = resource_size(res);
2409         vop->regs = devm_ioremap_resource(dev, res);
2410         if (IS_ERR(vop->regs))
2411                 return PTR_ERR(vop->regs);
2412
2413         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2414         if (!vop->regsbak)
2415                 return -ENOMEM;
2416
2417         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2418         if (IS_ERR(vop->hclk)) {
2419                 dev_err(vop->dev, "failed to get hclk source\n");
2420                 return PTR_ERR(vop->hclk);
2421         }
2422         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2423         if (IS_ERR(vop->aclk)) {
2424                 dev_err(vop->dev, "failed to get aclk source\n");
2425                 return PTR_ERR(vop->aclk);
2426         }
2427         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2428         if (IS_ERR(vop->dclk)) {
2429                 dev_err(vop->dev, "failed to get dclk source\n");
2430                 return PTR_ERR(vop->dclk);
2431         }
2432
2433         irq = platform_get_irq(pdev, 0);
2434         if (irq < 0) {
2435                 dev_err(dev, "cannot find irq for vop\n");
2436                 return irq;
2437         }
2438         vop->irq = (unsigned int)irq;
2439
2440         spin_lock_init(&vop->reg_lock);
2441         spin_lock_init(&vop->irq_lock);
2442
2443         mutex_init(&vop->vsync_mutex);
2444
2445         ret = devm_request_irq(dev, vop->irq, vop_isr,
2446                                IRQF_SHARED, dev_name(dev), vop);
2447         if (ret)
2448                 return ret;
2449
2450         /* IRQ is initially disabled; it gets enabled in power_on */
2451         disable_irq(vop->irq);
2452
2453         ret = vop_create_crtc(vop);
2454         if (ret)
2455                 return ret;
2456
2457         pm_runtime_enable(&pdev->dev);
2458         return 0;
2459 }
2460
2461 static void vop_unbind(struct device *dev, struct device *master, void *data)
2462 {
2463         struct vop *vop = dev_get_drvdata(dev);
2464
2465         pm_runtime_disable(dev);
2466         vop_destroy_crtc(vop);
2467 }
2468
2469 const struct component_ops vop_component_ops = {
2470         .bind = vop_bind,
2471         .unbind = vop_unbind,
2472 };
2473 EXPORT_SYMBOL_GPL(vop_component_ops);