drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33
  34 #include "rockchip_drm_drv.h"
  35 #include "rockchip_drm_gem.h"
  36 #include "rockchip_drm_fb.h"
  37 #include "rockchip_drm_vop.h"
  38
  39 #define VOP_REG(off, _mask, s) \
  40                 {.offset = off, \
  41                  .mask = _mask, \
  42                  .shift = s,}
  43
  44 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  45                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  46 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  47                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  48
  49 #define REG_SET(x, base, reg, v, mode) \
  50                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  51 #define REG_SET_MASK(x, base, reg, v, mode) \
  52                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  53
  54 #define VOP_WIN_SET(x, win, name, v) \
  55                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  56 #define VOP_SCL_SET(x, win, name, v) \
  57                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  58 #define VOP_CTRL_SET(x, name, v) \
  59                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  60
  61 #define VOP_INTR_GET(vop, name) \
  62                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  63
  64 #define VOP_INTR_SET(vop, name, v) \
  65                 REG_SET(vop, 0, vop->data->intr->name, v, NORMAL)
  66 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  67         do { \
  68                 int i, reg = 0; \
  69                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  70                         if (vop->data->intr->intrs[i] & type) \
  71                                 reg |= (v) << i; \
  72                 } \
  73                 VOP_INTR_SET(vop, name, reg); \
  74         } while (0)
  75 #define VOP_INTR_GET_TYPE(vop, name, type) \
  76                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  77
  78 #define VOP_WIN_GET(x, win, name) \
  79                 vop_read_reg(x, win->base, &win->phy->name)
  80
  81 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  82                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  83
  84 #define to_vop(x) container_of(x, struct vop, crtc)
  85 #define to_vop_win(x) container_of(x, struct vop_win, base)
  86 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  87
  88 struct vop_plane_state {
  89         struct drm_plane_state base;
  90         int format;
  91         struct drm_rect src;
  92         struct drm_rect dest;
  93         dma_addr_t yrgb_mst;
  94         bool enable;
  95 };
  96
  97 struct vop_win {
  98         struct drm_plane base;
  99         const struct vop_win_data *data;
 100         struct vop *vop;
 101
 102         struct vop_plane_state state;
 103 };
 104
 105 struct vop {
 106         struct drm_crtc crtc;
 107         struct device *dev;
 108         struct drm_device *drm_dev;
 109         bool is_enabled;
 110
 111         /* mutex vsync_ work */
 112         struct mutex vsync_mutex;
 113         bool vsync_work_pending;
 114         struct completion dsp_hold_completion;
 115         struct completion wait_update_complete;
 116         struct drm_pending_vblank_event *event;
 117
 118         const struct vop_data *data;
 119
 120         uint32_t *regsbak;
 121         void __iomem *regs;
 122
 123         /* physical map length of vop register */
 124         uint32_t len;
 125
 126         /* one time only one process allowed to config the register */
 127         spinlock_t reg_lock;
 128         /* lock vop irq reg */
 129         spinlock_t irq_lock;
 130
 131         unsigned int irq;
 132
 133         /* vop AHP clk */
 134         struct clk *hclk;
 135         /* vop dclk */
 136         struct clk *dclk;
 137         /* vop share memory frequency */
 138         struct clk *aclk;
 139
 140         /* vop dclk reset */
 141         struct reset_control *dclk_rst;
 142
 143         struct vop_win win[];
 144 };
 145
 146 enum vop_data_format {
 147         VOP_FMT_ARGB8888 = 0,
 148         VOP_FMT_RGB888,
 149         VOP_FMT_RGB565,
 150         VOP_FMT_YUV420SP = 4,
 151         VOP_FMT_YUV422SP,
 152         VOP_FMT_YUV444SP,
 153 };
 154
 155 struct vop_reg_data {
 156         uint32_t offset;
 157         uint32_t value;
 158 };
 159
 160 struct vop_reg {
 161         uint32_t offset;
 162         uint32_t shift;
 163         uint32_t mask;
 164 };
 165
 166 struct vop_ctrl {
 167         struct vop_reg standby;
 168         struct vop_reg data_blank;
 169         struct vop_reg gate_en;
 170         struct vop_reg mmu_en;
 171         struct vop_reg rgb_en;
 172         struct vop_reg edp_en;
 173         struct vop_reg hdmi_en;
 174         struct vop_reg mipi_en;
 175         struct vop_reg out_mode;
 176         struct vop_reg dither_down;
 177         struct vop_reg dither_up;
 178         struct vop_reg pin_pol;
 179
 180         struct vop_reg htotal_pw;
 181         struct vop_reg hact_st_end;
 182         struct vop_reg vtotal_pw;
 183         struct vop_reg vact_st_end;
 184         struct vop_reg hpost_st_end;
 185         struct vop_reg vpost_st_end;
 186
 187         struct vop_reg cfg_done;
 188 };
 189
 190 struct vop_intr {
 191         const int *intrs;
 192         uint32_t nintrs;
 193         struct vop_reg enable;
 194         struct vop_reg clear;
 195         struct vop_reg status;
 196 };
 197 struct vop_scl_regs {
 198         struct vop_reg cbcr_vsd_mode;
 199         struct vop_reg cbcr_vsu_mode;
 200         struct vop_reg cbcr_hsd_mode;
 201         struct vop_reg cbcr_ver_scl_mode;
 202         struct vop_reg cbcr_hor_scl_mode;
 203         struct vop_reg yrgb_vsd_mode;
 204         struct vop_reg yrgb_vsu_mode;
 205         struct vop_reg yrgb_hsd_mode;
 206         struct vop_reg yrgb_ver_scl_mode;
 207         struct vop_reg yrgb_hor_scl_mode;
 208         struct vop_reg line_load_mode;
 209         struct vop_reg cbcr_axi_gather_num;
 210         struct vop_reg yrgb_axi_gather_num;
 211         struct vop_reg vsd_cbcr_gt2;
 212         struct vop_reg vsd_cbcr_gt4;
 213         struct vop_reg vsd_yrgb_gt2;
 214         struct vop_reg vsd_yrgb_gt4;
 215         struct vop_reg bic_coe_sel;
 216         struct vop_reg cbcr_axi_gather_en;
 217         struct vop_reg yrgb_axi_gather_en;
 218
 219         struct vop_reg lb_mode;
 220         struct vop_reg scale_yrgb_x;
 221         struct vop_reg scale_yrgb_y;
 222         struct vop_reg scale_cbcr_x;
 223         struct vop_reg scale_cbcr_y;
 224 };
 225
 226 struct vop_win_phy {
 227         const struct vop_scl_regs *scl;
 228         const uint32_t *data_formats;
 229         uint32_t nformats;
 230
 231         struct vop_reg enable;
 232         struct vop_reg format;
 233         struct vop_reg rb_swap;
 234         struct vop_reg act_info;
 235         struct vop_reg dsp_info;
 236         struct vop_reg dsp_st;
 237         struct vop_reg yrgb_mst;
 238         struct vop_reg uv_mst;
 239         struct vop_reg yrgb_vir;
 240         struct vop_reg uv_vir;
 241
 242         struct vop_reg dst_alpha_ctl;
 243         struct vop_reg src_alpha_ctl;
 244 };
 245
 246 struct vop_win_data {
 247         uint32_t base;
 248         const struct vop_win_phy *phy;
 249         enum drm_plane_type type;
 250 };
 251
 252 struct vop_data {
 253         const struct vop_reg_data *init_table;
 254         unsigned int table_size;
 255         const struct vop_ctrl *ctrl;
 256         const struct vop_intr *intr;
 257         const struct vop_win_data *win;
 258         unsigned int win_size;
 259 };
 260
 261 static const uint32_t formats_01[] = {
 262         DRM_FORMAT_XRGB8888,
 263         DRM_FORMAT_ARGB8888,
 264         DRM_FORMAT_XBGR8888,
 265         DRM_FORMAT_ABGR8888,
 266         DRM_FORMAT_RGB888,
 267         DRM_FORMAT_BGR888,
 268         DRM_FORMAT_RGB565,
 269         DRM_FORMAT_BGR565,
 270         DRM_FORMAT_NV12,
 271         DRM_FORMAT_NV16,
 272         DRM_FORMAT_NV24,
 273 };
 274
 275 static const uint32_t formats_234[] = {
 276         DRM_FORMAT_XRGB8888,
 277         DRM_FORMAT_ARGB8888,
 278         DRM_FORMAT_XBGR8888,
 279         DRM_FORMAT_ABGR8888,
 280         DRM_FORMAT_RGB888,
 281         DRM_FORMAT_BGR888,
 282         DRM_FORMAT_RGB565,
 283         DRM_FORMAT_BGR565,
 284 };
 285
 286 static const struct vop_scl_regs win_full_scl = {
 287         .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
 288         .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
 289         .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
 290         .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
 291         .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
 292         .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
 293         .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
 294         .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
 295         .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
 296         .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
 297         .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
 298         .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
 299         .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
 300         .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
 301         .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
 302         .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
 303         .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
 304         .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
 305         .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
 306         .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
 307         .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
 308         .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 309         .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 310         .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 311         .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 312 };
 313
 314 static const struct vop_win_phy win01_data = {
 315         .scl = &win_full_scl,
 316         .data_formats = formats_01,
 317         .nformats = ARRAY_SIZE(formats_01),
 318         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 319         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 320         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
 321         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 322         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 323         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 324         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 325         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 326         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 327         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 328         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 329         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 330 };
 331
 332 static const struct vop_win_phy win23_data = {
 333         .data_formats = formats_234,
 334         .nformats = ARRAY_SIZE(formats_234),
 335         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 336         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 337         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 338         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 339         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 340         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 341         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 342         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 343         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 344 };
 345
 346 static const struct vop_ctrl ctrl_data = {
 347         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 348         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 349         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 350         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 351         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 352         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 353         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 354         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 355         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 356         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 357         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 358         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 359         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 360         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 361         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 362         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 363         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 364         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 365         .cfg_done = VOP_REG(REG_CFG_DONE, 0x1, 0),
 366 };
 367
 368 static const struct vop_reg_data vop_init_reg_table[] = {
 369         {SYS_CTRL, 0x00c00000},
 370         {DSP_CTRL0, 0x00000000},
 371         {WIN0_CTRL0, 0x00000080},
 372         {WIN1_CTRL0, 0x00000080},
 373         /* TODO: Win2/3 support multiple area function, but we haven't found
 374          * a suitable way to use it yet, so let's just use them as other windows
 375          * with only area 0 enabled.
 376          */
 377         {WIN2_CTRL0, 0x00000010},
 378         {WIN3_CTRL0, 0x00000010},
 379 };
 380
 381 /*
 382  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 383  * special support to get alpha blending working.  For now, just use overlay
 384  * window 3 for the drm cursor.
 385  *
 386  */
 387 static const struct vop_win_data rk3288_vop_win_data[] = {
 388         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 389         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 390         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 391         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 392 };
 393
 394 static const int rk3288_vop_intrs[] = {
 395         DSP_HOLD_VALID_INTR,
 396         FS_INTR,
 397         LINE_FLAG_INTR,
 398         BUS_ERROR_INTR,
 399 };
 400
 401 static const struct vop_intr rk3288_vop_intr = {
 402         .intrs = rk3288_vop_intrs,
 403         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 404         .status = VOP_REG(INTR_CTRL0, 0xf, 0),
 405         .enable = VOP_REG(INTR_CTRL0, 0xf, 4),
 406         .clear = VOP_REG(INTR_CTRL0, 0xf, 8),
 407 };
 408
 409 static const struct vop_data rk3288_vop = {
 410         .init_table = vop_init_reg_table,
 411         .intr = &rk3288_vop_intr,
 412         .table_size = ARRAY_SIZE(vop_init_reg_table),
 413         .ctrl = &ctrl_data,
 414         .win = rk3288_vop_win_data,
 415         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 416 };
 417
 418 static const struct of_device_id vop_driver_dt_match[] = {
 419         { .compatible = "rockchip,rk3288-vop",
 420           .data = &rk3288_vop },
 421         {},
 422 };
 423 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 424
 425 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 426 {
 427         writel(v, vop->regs + offset);
 428         vop->regsbak[offset >> 2] = v;
 429 }
 430
 431 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 432 {
 433         return readl(vop->regs + offset);
 434 }
 435
 436 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 437                                     const struct vop_reg *reg)
 438 {
 439         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 440 }
 441
 442 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 443                                   uint32_t mask, uint32_t v)
 444 {
 445         if (mask) {
 446                 uint32_t cached_val = vop->regsbak[offset >> 2];
 447
 448                 cached_val = (cached_val & ~mask) | v;
 449                 writel(cached_val, vop->regs + offset);
 450                 vop->regsbak[offset >> 2] = cached_val;
 451         }
 452 }
 453
 454 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 455                                           uint32_t mask, uint32_t v)
 456 {
 457         if (mask) {
 458                 uint32_t cached_val = vop->regsbak[offset >> 2];
 459
 460                 cached_val = (cached_val & ~mask) | v;
 461                 writel_relaxed(cached_val, vop->regs + offset);
 462                 vop->regsbak[offset >> 2] = cached_val;
 463         }
 464 }
 465
 466 static inline uint32_t vop_get_intr_type(struct vop *vop,
 467                                          const struct vop_reg *reg, int type)
 468 {
 469         uint32_t i, ret = 0;
 470         uint32_t regs = vop_read_reg(vop, 0, reg);
 471
 472         for (i = 0; i < vop->data->intr->nintrs; i++) {
 473                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 474                         ret |= vop->data->intr->intrs[i];
 475         }
 476
 477         return ret;
 478 }
 479
 480 static inline void vop_cfg_done(struct vop *vop)
 481 {
 482         VOP_CTRL_SET(vop, cfg_done, 1);
 483 }
 484
 485 static bool has_rb_swapped(uint32_t format)
 486 {
 487         switch (format) {
 488         case DRM_FORMAT_XBGR8888:
 489         case DRM_FORMAT_ABGR8888:
 490         case DRM_FORMAT_BGR888:
 491         case DRM_FORMAT_BGR565:
 492                 return true;
 493         default:
 494                 return false;
 495         }
 496 }
 497
 498 static enum vop_data_format vop_convert_format(uint32_t format)
 499 {
 500         switch (format) {
 501         case DRM_FORMAT_XRGB8888:
 502         case DRM_FORMAT_ARGB8888:
 503         case DRM_FORMAT_XBGR8888:
 504         case DRM_FORMAT_ABGR8888:
 505                 return VOP_FMT_ARGB8888;
 506         case DRM_FORMAT_RGB888:
 507         case DRM_FORMAT_BGR888:
 508                 return VOP_FMT_RGB888;
 509         case DRM_FORMAT_RGB565:
 510         case DRM_FORMAT_BGR565:
 511                 return VOP_FMT_RGB565;
 512         case DRM_FORMAT_NV12:
 513                 return VOP_FMT_YUV420SP;
 514         case DRM_FORMAT_NV16:
 515                 return VOP_FMT_YUV422SP;
 516         case DRM_FORMAT_NV24:
 517                 return VOP_FMT_YUV444SP;
 518         default:
 519                 DRM_ERROR("unsupport format[%08x]\n", format);
 520                 return -EINVAL;
 521         }
 522 }
 523
 524 static bool is_yuv_support(uint32_t format)
 525 {
 526         switch (format) {
 527         case DRM_FORMAT_NV12:
 528         case DRM_FORMAT_NV16:
 529         case DRM_FORMAT_NV24:
 530                 return true;
 531         default:
 532                 return false;
 533         }
 534 }
 535
 536 static bool is_alpha_support(uint32_t format)
 537 {
 538         switch (format) {
 539         case DRM_FORMAT_ARGB8888:
 540         case DRM_FORMAT_ABGR8888:
 541                 return true;
 542         default:
 543                 return false;
 544         }
 545 }
 546
 547 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 548                                   uint32_t dst, bool is_horizontal,
 549                                   int vsu_mode, int *vskiplines)
 550 {
 551         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 552
 553         if (is_horizontal) {
 554                 if (mode == SCALE_UP)
 555                         val = GET_SCL_FT_BIC(src, dst);
 556                 else if (mode == SCALE_DOWN)
 557                         val = GET_SCL_FT_BILI_DN(src, dst);
 558         } else {
 559                 if (mode == SCALE_UP) {
 560                         if (vsu_mode == SCALE_UP_BIL)
 561                                 val = GET_SCL_FT_BILI_UP(src, dst);
 562                         else
 563                                 val = GET_SCL_FT_BIC(src, dst);
 564                 } else if (mode == SCALE_DOWN) {
 565                         if (vskiplines) {
 566                                 *vskiplines = scl_get_vskiplines(src, dst);
 567                                 val = scl_get_bili_dn_vskip(src, dst,
 568                                                             *vskiplines);
 569                         } else {
 570                                 val = GET_SCL_FT_BILI_DN(src, dst);
 571                         }
 572                 }
 573         }
 574
 575         return val;
 576 }
 577
 578 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 579                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 580                              uint32_t dst_h, uint32_t pixel_format)
 581 {
 582         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 583         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 584         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 585         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 586         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 587         bool is_yuv = is_yuv_support(pixel_format);
 588         uint16_t cbcr_src_w = src_w / hsub;
 589         uint16_t cbcr_src_h = src_h / vsub;
 590         uint16_t vsu_mode;
 591         uint16_t lb_mode;
 592         uint32_t val;
 593         int vskiplines;
 594
 595         if (dst_w > 3840) {
 596                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 597                 return;
 598         }
 599
 600         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 601         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 602
 603         if (is_yuv) {
 604                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 605                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 606                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 607                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 608                 else
 609                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 610         } else {
 611                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 612                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 613                 else
 614                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 615         }
 616
 617         VOP_SCL_SET(vop, win, lb_mode, lb_mode);
 618         if (lb_mode == LB_RGB_3840X2) {
 619                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 620                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 621                         return;
 622                 }
 623                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 624                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 625                         return;
 626                 }
 627                 vsu_mode = SCALE_UP_BIL;
 628         } else if (lb_mode == LB_RGB_2560X4) {
 629                 vsu_mode = SCALE_UP_BIL;
 630         } else {
 631                 vsu_mode = SCALE_UP_BIC;
 632         }
 633
 634         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 635                                 true, 0, NULL);
 636         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 637         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 638                                 false, vsu_mode, &vskiplines);
 639         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 640
 641         VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 642         VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 643
 644         VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 645         VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 646         VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 647         VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 648         VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
 649         if (is_yuv) {
 650                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 651                                         dst_w, true, 0, NULL);
 652                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 653                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 654                                         dst_h, false, vsu_mode, &vskiplines);
 655                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 656
 657                 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 658                 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 659                 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 660                 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 661                 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 662                 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 663                 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
 664         }
 665 }
 666
 667 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 668 {
 669         unsigned long flags;
 670
 671         if (WARN_ON(!vop->is_enabled))
 672                 return;
 673
 674         spin_lock_irqsave(&vop->irq_lock, flags);
 675
 676         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 677
 678         spin_unlock_irqrestore(&vop->irq_lock, flags);
 679 }
 680
 681 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 682 {
 683         unsigned long flags;
 684
 685         if (WARN_ON(!vop->is_enabled))
 686                 return;
 687
 688         spin_lock_irqsave(&vop->irq_lock, flags);
 689
 690         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 691
 692         spin_unlock_irqrestore(&vop->irq_lock, flags);
 693 }
 694
 695 static void vop_enable(struct drm_crtc *crtc)
 696 {
 697         struct vop *vop = to_vop(crtc);
 698         int ret;
 699
 700         if (vop->is_enabled)
 701                 return;
 702
 703         ret = pm_runtime_get_sync(vop->dev);
 704         if (ret < 0) {
 705                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 706                 return;
 707         }
 708
 709         ret = clk_enable(vop->hclk);
 710         if (ret < 0) {
 711                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 712                 return;
 713         }
 714
 715         ret = clk_enable(vop->dclk);
 716         if (ret < 0) {
 717                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 718                 goto err_disable_hclk;
 719         }
 720
 721         ret = clk_enable(vop->aclk);
 722         if (ret < 0) {
 723                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 724                 goto err_disable_dclk;
 725         }
 726
 727         /*
 728          * Slave iommu shares power, irq and clock with vop.  It was associated
 729          * automatically with this master device via common driver code.
 730          * Now that we have enabled the clock we attach it to the shared drm
 731          * mapping.
 732          */
 733         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 734         if (ret) {
 735                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 736                 goto err_disable_aclk;
 737         }
 738
 739         memcpy(vop->regs, vop->regsbak, vop->len);
 740         /*
 741          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 742          */
 743         vop->is_enabled = true;
 744
 745         spin_lock(&vop->reg_lock);
 746
 747         VOP_CTRL_SET(vop, standby, 0);
 748
 749         spin_unlock(&vop->reg_lock);
 750
 751         enable_irq(vop->irq);
 752
 753         drm_crtc_vblank_on(crtc);
 754
 755         return;
 756
 757 err_disable_aclk:
 758         clk_disable(vop->aclk);
 759 err_disable_dclk:
 760         clk_disable(vop->dclk);
 761 err_disable_hclk:
 762         clk_disable(vop->hclk);
 763 }
 764
 765 static void vop_crtc_disable(struct drm_crtc *crtc)
 766 {
 767         struct vop *vop = to_vop(crtc);
 768
 769         if (!vop->is_enabled)
 770                 return;
 771
 772         drm_crtc_vblank_off(crtc);
 773
 774         /*
 775          * Vop standby will take effect at end of current frame,
 776          * if dsp hold valid irq happen, it means standby complete.
 777          *
 778          * we must wait standby complete when we want to disable aclk,
 779          * if not, memory bus maybe dead.
 780          */
 781         reinit_completion(&vop->dsp_hold_completion);
 782         vop_dsp_hold_valid_irq_enable(vop);
 783
 784         spin_lock(&vop->reg_lock);
 785
 786         VOP_CTRL_SET(vop, standby, 1);
 787
 788         spin_unlock(&vop->reg_lock);
 789
 790         wait_for_completion(&vop->dsp_hold_completion);
 791
 792         vop_dsp_hold_valid_irq_disable(vop);
 793
 794         disable_irq(vop->irq);
 795
 796         vop->is_enabled = false;
 797
 798         /*
 799          * vop standby complete, so iommu detach is safe.
 800          */
 801         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 802
 803         clk_disable(vop->dclk);
 804         clk_disable(vop->aclk);
 805         clk_disable(vop->hclk);
 806         pm_runtime_put(vop->dev);
 807 }
 808
 809 static void vop_plane_destroy(struct drm_plane *plane)
 810 {
 811         drm_plane_cleanup(plane);
 812 }
 813
 814 static int vop_plane_atomic_check(struct drm_plane *plane,
 815                            struct drm_plane_state *state)
 816 {
 817         struct drm_crtc *crtc = state->crtc;
 818         struct drm_framebuffer *fb = state->fb;
 819         struct vop_win *vop_win = to_vop_win(plane);
 820         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 821         const struct vop_win_data *win = vop_win->data;
 822         bool visible;
 823         int ret;
 824         struct drm_rect *dest = &vop_plane_state->dest;
 825         struct drm_rect *src = &vop_plane_state->src;
 826         struct drm_rect clip;
 827         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 828                                         DRM_PLANE_HELPER_NO_SCALING;
 829         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 830                                         DRM_PLANE_HELPER_NO_SCALING;
 831
 832         crtc = crtc ? crtc : plane->state->crtc;
 833         /*
 834          * Both crtc or plane->state->crtc can be null.
 835          */
 836         if (!crtc || !fb)
 837                 goto out_disable;
 838         src->x1 = state->src_x;
 839         src->y1 = state->src_y;
 840         src->x2 = state->src_x + state->src_w;
 841         src->y2 = state->src_y + state->src_h;
 842         dest->x1 = state->crtc_x;
 843         dest->y1 = state->crtc_y;
 844         dest->x2 = state->crtc_x + state->crtc_w;
 845         dest->y2 = state->crtc_y + state->crtc_h;
 846
 847         clip.x1 = 0;
 848         clip.y1 = 0;
 849         clip.x2 = crtc->mode.hdisplay;
 850         clip.y2 = crtc->mode.vdisplay;
 851
 852         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 853                                             src, dest, &clip,
 854                                             min_scale,
 855                                             max_scale,
 856                                             true, true, &visible);
 857         if (ret)
 858                 return ret;
 859
 860         if (!visible)
 861                 goto out_disable;
 862
 863         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 864         if (vop_plane_state->format < 0)
 865                 return vop_plane_state->format;
 866
 867         /*
 868          * Src.x1 can be odd when do clip, but yuv plane start point
 869          * need align with 2 pixel.
 870          */
 871         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 872                 return -EINVAL;
 873
 874         vop_plane_state->enable = true;
 875
 876         return 0;
 877
 878 out_disable:
 879         vop_plane_state->enable = false;
 880         return 0;
 881 }
 882
 883 static void vop_plane_atomic_disable(struct drm_plane *plane,
 884                                      struct drm_plane_state *old_state)
 885 {
 886         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 887         struct vop_win *vop_win = to_vop_win(plane);
 888         const struct vop_win_data *win = vop_win->data;
 889         struct vop *vop = to_vop(old_state->crtc);
 890
 891         if (!old_state->crtc)
 892                 return;
 893
 894         spin_lock(&vop->reg_lock);
 895
 896         VOP_WIN_SET(vop, win, enable, 0);
 897
 898         spin_unlock(&vop->reg_lock);
 899
 900         vop_plane_state->enable = false;
 901 }
 902
 903 static void vop_plane_atomic_update(struct drm_plane *plane,
 904                 struct drm_plane_state *old_state)
 905 {
 906         struct drm_plane_state *state = plane->state;
 907         struct drm_crtc *crtc = state->crtc;
 908         struct vop_win *vop_win = to_vop_win(plane);
 909         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 910         const struct vop_win_data *win = vop_win->data;
 911         struct vop *vop = to_vop(state->crtc);
 912         struct drm_framebuffer *fb = state->fb;
 913         unsigned int actual_w, actual_h;
 914         unsigned int dsp_stx, dsp_sty;
 915         uint32_t act_info, dsp_info, dsp_st;
 916         struct drm_rect *src = &vop_plane_state->src;
 917         struct drm_rect *dest = &vop_plane_state->dest;
 918         struct drm_gem_object *obj, *uv_obj;
 919         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 920         unsigned long offset;
 921         dma_addr_t dma_addr;
 922         uint32_t val;
 923         bool rb_swap;
 924
 925         /*
 926          * can't update plane when vop is disabled.
 927          */
 928         if (!crtc)
 929                 return;
 930
 931         if (WARN_ON(!vop->is_enabled))
 932                 return;
 933
 934         if (!vop_plane_state->enable) {
 935                 vop_plane_atomic_disable(plane, old_state);
 936                 return;
 937         }
 938
 939         obj = rockchip_fb_get_gem_obj(fb, 0);
 940         rk_obj = to_rockchip_obj(obj);
 941
 942         actual_w = drm_rect_width(src) >> 16;
 943         actual_h = drm_rect_height(src) >> 16;
 944         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 945
 946         dsp_info = (drm_rect_height(dest) - 1) << 16;
 947         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 948
 949         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 950         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 951         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 952
 953         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 954         offset += (src->y1 >> 16) * fb->pitches[0];
 955         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 956
 957         spin_lock(&vop->reg_lock);
 958
 959         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 960         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 961         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 962         if (is_yuv_support(fb->pixel_format)) {
 963                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 964                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 965                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 966
 967                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 968                 rk_uv_obj = to_rockchip_obj(uv_obj);
 969
 970                 offset = (src->x1 >> 16) * bpp / hsub;
 971                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 972
 973                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 974                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 975                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 976         }
 977
 978         if (win->phy->scl)
 979                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 980                                     drm_rect_width(dest), drm_rect_height(dest),
 981                                     fb->pixel_format);
 982
 983         VOP_WIN_SET(vop, win, act_info, act_info);
 984         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 985         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 986
 987         rb_swap = has_rb_swapped(fb->pixel_format);
 988         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 989
 990         if (is_alpha_support(fb->pixel_format)) {
 991                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 992                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 993                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 994                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 995                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 996                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 997                         SRC_FACTOR_M0(ALPHA_ONE);
 998                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 999         } else {
1000                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1001         }
1002
1003         VOP_WIN_SET(vop, win, enable, 1);
1004         spin_unlock(&vop->reg_lock);
1005 }
1006
1007 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1008         .atomic_check = vop_plane_atomic_check,
1009         .atomic_update = vop_plane_atomic_update,
1010         .atomic_disable = vop_plane_atomic_disable,
1011 };
1012
1013 void vop_atomic_plane_reset(struct drm_plane *plane)
1014 {
1015         struct vop_plane_state *vop_plane_state =
1016                                         to_vop_plane_state(plane->state);
1017
1018         if (plane->state && plane->state->fb)
1019                 drm_framebuffer_unreference(plane->state->fb);
1020
1021         kfree(vop_plane_state);
1022         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1023         if (!vop_plane_state)
1024                 return;
1025
1026         plane->state = &vop_plane_state->base;
1027         plane->state->plane = plane;
1028 }
1029
1030 struct drm_plane_state *
1031 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1032 {
1033         struct vop_plane_state *old_vop_plane_state;
1034         struct vop_plane_state *vop_plane_state;
1035
1036         if (WARN_ON(!plane->state))
1037                 return NULL;
1038
1039         old_vop_plane_state = to_vop_plane_state(plane->state);
1040         vop_plane_state = kmemdup(old_vop_plane_state,
1041                                   sizeof(*vop_plane_state), GFP_KERNEL);
1042         if (!vop_plane_state)
1043                 return NULL;
1044
1045         __drm_atomic_helper_plane_duplicate_state(plane,
1046                                                   &vop_plane_state->base);
1047
1048         return &vop_plane_state->base;
1049 }
1050
1051 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1052                                            struct drm_plane_state *state)
1053 {
1054         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1055
1056         __drm_atomic_helper_plane_destroy_state(plane, state);
1057
1058         kfree(vop_state);
1059 }
1060
1061 static const struct drm_plane_funcs vop_plane_funcs = {
1062         .update_plane   = drm_atomic_helper_update_plane,
1063         .disable_plane  = drm_atomic_helper_disable_plane,
1064         .destroy = vop_plane_destroy,
1065         .reset = vop_atomic_plane_reset,
1066         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1067         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1068 };
1069
1070 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1071                                   int connector_type,
1072                                   int out_mode)
1073 {
1074         struct vop *vop = to_vop(crtc);
1075
1076         if (WARN_ON(!vop->is_enabled))
1077                 return -EINVAL;
1078
1079         switch (connector_type) {
1080         case DRM_MODE_CONNECTOR_LVDS:
1081                 VOP_CTRL_SET(vop, rgb_en, 1);
1082                 break;
1083         case DRM_MODE_CONNECTOR_eDP:
1084                 VOP_CTRL_SET(vop, edp_en, 1);
1085                 break;
1086         case DRM_MODE_CONNECTOR_HDMIA:
1087                 VOP_CTRL_SET(vop, hdmi_en, 1);
1088                 break;
1089         default:
1090                 DRM_ERROR("unsupport connector_type[%d]\n", connector_type);
1091                 return -EINVAL;
1092         };
1093         VOP_CTRL_SET(vop, out_mode, out_mode);
1094
1095         return 0;
1096 }
1097 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
1098
1099 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1100 {
1101         struct vop *vop = to_vop(crtc);
1102         unsigned long flags;
1103
1104         if (WARN_ON(!vop->is_enabled))
1105                 return -EPERM;
1106
1107         spin_lock_irqsave(&vop->irq_lock, flags);
1108
1109         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1110
1111         spin_unlock_irqrestore(&vop->irq_lock, flags);
1112
1113         return 0;
1114 }
1115
1116 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1117 {
1118         struct vop *vop = to_vop(crtc);
1119         unsigned long flags;
1120
1121         if (WARN_ON(!vop->is_enabled))
1122                 return;
1123
1124         spin_lock_irqsave(&vop->irq_lock, flags);
1125
1126         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1127
1128         spin_unlock_irqrestore(&vop->irq_lock, flags);
1129 }
1130
1131 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1132 {
1133         struct vop *vop = to_vop(crtc);
1134
1135         reinit_completion(&vop->wait_update_complete);
1136         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1137 }
1138
1139 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1140         .enable_vblank = vop_crtc_enable_vblank,
1141         .disable_vblank = vop_crtc_disable_vblank,
1142         .wait_for_update = vop_crtc_wait_for_update,
1143 };
1144
1145 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1146                                 const struct drm_display_mode *mode,
1147                                 struct drm_display_mode *adjusted_mode)
1148 {
1149         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1150                 return false;
1151
1152         return true;
1153 }
1154
1155 static void vop_crtc_enable(struct drm_crtc *crtc)
1156 {
1157         struct vop *vop = to_vop(crtc);
1158         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1159         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1160         u16 hdisplay = adjusted_mode->hdisplay;
1161         u16 htotal = adjusted_mode->htotal;
1162         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1163         u16 hact_end = hact_st + hdisplay;
1164         u16 vdisplay = adjusted_mode->vdisplay;
1165         u16 vtotal = adjusted_mode->vtotal;
1166         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1167         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1168         u16 vact_end = vact_st + vdisplay;
1169         uint32_t val;
1170
1171         vop_enable(crtc);
1172         /*
1173          * If dclk rate is zero, mean that scanout is stop,
1174          * we don't need wait any more.
1175          */
1176         if (clk_get_rate(vop->dclk)) {
1177                 /*
1178                  * Rk3288 vop timing register is immediately, when configure
1179                  * display timing on display time, may cause tearing.
1180                  *
1181                  * Vop standby will take effect at end of current frame,
1182                  * if dsp hold valid irq happen, it means standby complete.
1183                  *
1184                  * mode set:
1185                  *    standby and wait complete --> |----
1186                  *                                  | display time
1187                  *                                  |----
1188                  *                                  |---> dsp hold irq
1189                  *     configure display timing --> |
1190                  *         standby exit             |
1191                  *                                  | new frame start.
1192                  */
1193
1194                 reinit_completion(&vop->dsp_hold_completion);
1195                 vop_dsp_hold_valid_irq_enable(vop);
1196
1197                 spin_lock(&vop->reg_lock);
1198
1199                 VOP_CTRL_SET(vop, standby, 1);
1200
1201                 spin_unlock(&vop->reg_lock);
1202
1203                 wait_for_completion(&vop->dsp_hold_completion);
1204
1205                 vop_dsp_hold_valid_irq_disable(vop);
1206         }
1207
1208         val = 0x8;
1209         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1210         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1211         VOP_CTRL_SET(vop, pin_pol, val);
1212
1213         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1214         val = hact_st << 16;
1215         val |= hact_end;
1216         VOP_CTRL_SET(vop, hact_st_end, val);
1217         VOP_CTRL_SET(vop, hpost_st_end, val);
1218
1219         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1220         val = vact_st << 16;
1221         val |= vact_end;
1222         VOP_CTRL_SET(vop, vact_st_end, val);
1223         VOP_CTRL_SET(vop, vpost_st_end, val);
1224
1225         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1226
1227         VOP_CTRL_SET(vop, standby, 0);
1228 }
1229
1230 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1231                                   struct drm_crtc_state *old_crtc_state)
1232 {
1233         struct vop *vop = to_vop(crtc);
1234
1235         if (WARN_ON(!vop->is_enabled))
1236                 return;
1237
1238         spin_lock(&vop->reg_lock);
1239
1240         vop_cfg_done(vop);
1241
1242         spin_unlock(&vop->reg_lock);
1243 }
1244
1245 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1246                                   struct drm_crtc_state *old_crtc_state)
1247 {
1248         struct vop *vop = to_vop(crtc);
1249
1250         if (crtc->state->event) {
1251                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1252
1253                 vop->event = crtc->state->event;
1254                 crtc->state->event = NULL;
1255         }
1256 }
1257
1258 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1259         .enable = vop_crtc_enable,
1260         .disable = vop_crtc_disable,
1261         .mode_fixup = vop_crtc_mode_fixup,
1262         .atomic_flush = vop_crtc_atomic_flush,
1263         .atomic_begin = vop_crtc_atomic_begin,
1264 };
1265
1266 static void vop_crtc_destroy(struct drm_crtc *crtc)
1267 {
1268         drm_crtc_cleanup(crtc);
1269 }
1270
1271 static const struct drm_crtc_funcs vop_crtc_funcs = {
1272         .set_config = drm_atomic_helper_set_config,
1273         .page_flip = drm_atomic_helper_page_flip,
1274         .destroy = vop_crtc_destroy,
1275         .reset = drm_atomic_helper_crtc_reset,
1276         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1277         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1278 };
1279
1280 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1281 {
1282         struct drm_plane *plane = &vop_win->base;
1283         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1284         dma_addr_t yrgb_mst;
1285
1286         if (!state->enable)
1287                 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1288
1289         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1290
1291         return yrgb_mst == state->yrgb_mst;
1292 }
1293
1294 static void vop_handle_vblank(struct vop *vop)
1295 {
1296         struct drm_device *drm = vop->drm_dev;
1297         struct drm_crtc *crtc = &vop->crtc;
1298         unsigned long flags;
1299         int i;
1300
1301         for (i = 0; i < vop->data->win_size; i++) {
1302                 if (!vop_win_pending_is_complete(&vop->win[i]))
1303                         return;
1304         }
1305
1306         if (vop->event) {
1307                 spin_lock_irqsave(&drm->event_lock, flags);
1308
1309                 drm_crtc_send_vblank_event(crtc, vop->event);
1310                 drm_crtc_vblank_put(crtc);
1311                 vop->event = NULL;
1312
1313                 spin_unlock_irqrestore(&drm->event_lock, flags);
1314         }
1315         if (!completion_done(&vop->wait_update_complete))
1316                 complete(&vop->wait_update_complete);
1317 }
1318
1319 static irqreturn_t vop_isr(int irq, void *data)
1320 {
1321         struct vop *vop = data;
1322         struct drm_crtc *crtc = &vop->crtc;
1323         uint32_t active_irqs;
1324         unsigned long flags;
1325         int ret = IRQ_NONE;
1326
1327         /*
1328          * interrupt register has interrupt status, enable and clear bits, we
1329          * must hold irq_lock to avoid a race with enable/disable_vblank().
1330         */
1331         spin_lock_irqsave(&vop->irq_lock, flags);
1332
1333         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1334         /* Clear all active interrupt sources */
1335         if (active_irqs)
1336                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1337
1338         spin_unlock_irqrestore(&vop->irq_lock, flags);
1339
1340         /* This is expected for vop iommu irqs, since the irq is shared */
1341         if (!active_irqs)
1342                 return IRQ_NONE;
1343
1344         if (active_irqs & DSP_HOLD_VALID_INTR) {
1345                 complete(&vop->dsp_hold_completion);
1346                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1347                 ret = IRQ_HANDLED;
1348         }
1349
1350         if (active_irqs & FS_INTR) {
1351                 drm_crtc_handle_vblank(crtc);
1352                 vop_handle_vblank(vop);
1353                 active_irqs &= ~FS_INTR;
1354                 ret = IRQ_HANDLED;
1355         }
1356
1357         /* Unhandled irqs are spurious. */
1358         if (active_irqs)
1359                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1360
1361         return ret;
1362 }
1363
1364 static int vop_create_crtc(struct vop *vop)
1365 {
1366         const struct vop_data *vop_data = vop->data;
1367         struct device *dev = vop->dev;
1368         struct drm_device *drm_dev = vop->drm_dev;
1369         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1370         struct drm_crtc *crtc = &vop->crtc;
1371         struct device_node *port;
1372         int ret;
1373         int i;
1374
1375         /*
1376          * Create drm_plane for primary and cursor planes first, since we need
1377          * to pass them to drm_crtc_init_with_planes, which sets the
1378          * "possible_crtcs" to the newly initialized crtc.
1379          */
1380         for (i = 0; i < vop_data->win_size; i++) {
1381                 struct vop_win *vop_win = &vop->win[i];
1382                 const struct vop_win_data *win_data = vop_win->data;
1383
1384                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1385                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1386                         continue;
1387
1388                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1389                                                0, &vop_plane_funcs,
1390                                                win_data->phy->data_formats,
1391                                                win_data->phy->nformats,
1392                                                win_data->type, NULL);
1393                 if (ret) {
1394                         DRM_ERROR("failed to initialize plane\n");
1395                         goto err_cleanup_planes;
1396                 }
1397
1398                 plane = &vop_win->base;
1399                 drm_plane_helper_add(plane, &plane_helper_funcs);
1400                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1401                         primary = plane;
1402                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1403                         cursor = plane;
1404         }
1405
1406         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1407                                         &vop_crtc_funcs, NULL);
1408         if (ret)
1409                 return ret;
1410
1411         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1412
1413         /*
1414          * Create drm_planes for overlay windows with possible_crtcs restricted
1415          * to the newly created crtc.
1416          */
1417         for (i = 0; i < vop_data->win_size; i++) {
1418                 struct vop_win *vop_win = &vop->win[i];
1419                 const struct vop_win_data *win_data = vop_win->data;
1420                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1421
1422                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1423                         continue;
1424
1425                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1426                                                possible_crtcs,
1427                                                &vop_plane_funcs,
1428                                                win_data->phy->data_formats,
1429                                                win_data->phy->nformats,
1430                                                win_data->type, NULL);
1431                 if (ret) {
1432                         DRM_ERROR("failed to initialize overlay plane\n");
1433                         goto err_cleanup_crtc;
1434                 }
1435                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1436         }
1437
1438         port = of_get_child_by_name(dev->of_node, "port");
1439         if (!port) {
1440                 DRM_ERROR("no port node found in %s\n",
1441                           dev->of_node->full_name);
1442                 goto err_cleanup_crtc;
1443         }
1444
1445         init_completion(&vop->dsp_hold_completion);
1446         init_completion(&vop->wait_update_complete);
1447         crtc->port = port;
1448         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1449
1450         return 0;
1451
1452 err_cleanup_crtc:
1453         drm_crtc_cleanup(crtc);
1454 err_cleanup_planes:
1455         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1456                 drm_plane_cleanup(plane);
1457         return ret;
1458 }
1459
1460 static void vop_destroy_crtc(struct vop *vop)
1461 {
1462         struct drm_crtc *crtc = &vop->crtc;
1463
1464         rockchip_unregister_crtc_funcs(crtc);
1465         of_node_put(crtc->port);
1466         drm_crtc_cleanup(crtc);
1467 }
1468
1469 static int vop_initial(struct vop *vop)
1470 {
1471         const struct vop_data *vop_data = vop->data;
1472         const struct vop_reg_data *init_table = vop_data->init_table;
1473         struct reset_control *ahb_rst;
1474         int i, ret;
1475
1476         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1477         if (IS_ERR(vop->hclk)) {
1478                 dev_err(vop->dev, "failed to get hclk source\n");
1479                 return PTR_ERR(vop->hclk);
1480         }
1481         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1482         if (IS_ERR(vop->aclk)) {
1483                 dev_err(vop->dev, "failed to get aclk source\n");
1484                 return PTR_ERR(vop->aclk);
1485         }
1486         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1487         if (IS_ERR(vop->dclk)) {
1488                 dev_err(vop->dev, "failed to get dclk source\n");
1489                 return PTR_ERR(vop->dclk);
1490         }
1491
1492         ret = clk_prepare(vop->dclk);
1493         if (ret < 0) {
1494                 dev_err(vop->dev, "failed to prepare dclk\n");
1495                 return ret;
1496         }
1497
1498         /* Enable both the hclk and aclk to setup the vop */
1499         ret = clk_prepare_enable(vop->hclk);
1500         if (ret < 0) {
1501                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1502                 goto err_unprepare_dclk;
1503         }
1504
1505         ret = clk_prepare_enable(vop->aclk);
1506         if (ret < 0) {
1507                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1508                 goto err_disable_hclk;
1509         }
1510
1511         /*
1512          * do hclk_reset, reset all vop registers.
1513          */
1514         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1515         if (IS_ERR(ahb_rst)) {
1516                 dev_err(vop->dev, "failed to get ahb reset\n");
1517                 ret = PTR_ERR(ahb_rst);
1518                 goto err_disable_aclk;
1519         }
1520         reset_control_assert(ahb_rst);
1521         usleep_range(10, 20);
1522         reset_control_deassert(ahb_rst);
1523
1524         memcpy(vop->regsbak, vop->regs, vop->len);
1525
1526         for (i = 0; i < vop_data->table_size; i++)
1527                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1528
1529         for (i = 0; i < vop_data->win_size; i++) {
1530                 const struct vop_win_data *win = &vop_data->win[i];
1531
1532                 VOP_WIN_SET(vop, win, enable, 0);
1533         }
1534
1535         vop_cfg_done(vop);
1536
1537         /*
1538          * do dclk_reset, let all config take affect.
1539          */
1540         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1541         if (IS_ERR(vop->dclk_rst)) {
1542                 dev_err(vop->dev, "failed to get dclk reset\n");
1543                 ret = PTR_ERR(vop->dclk_rst);
1544                 goto err_disable_aclk;
1545         }
1546         reset_control_assert(vop->dclk_rst);
1547         usleep_range(10, 20);
1548         reset_control_deassert(vop->dclk_rst);
1549
1550         clk_disable(vop->hclk);
1551         clk_disable(vop->aclk);
1552
1553         vop->is_enabled = false;
1554
1555         return 0;
1556
1557 err_disable_aclk:
1558         clk_disable_unprepare(vop->aclk);
1559 err_disable_hclk:
1560         clk_disable_unprepare(vop->hclk);
1561 err_unprepare_dclk:
1562         clk_unprepare(vop->dclk);
1563         return ret;
1564 }
1565
1566 /*
1567  * Initialize the vop->win array elements.
1568  */
1569 static void vop_win_init(struct vop *vop)
1570 {
1571         const struct vop_data *vop_data = vop->data;
1572         unsigned int i;
1573
1574         for (i = 0; i < vop_data->win_size; i++) {
1575                 struct vop_win *vop_win = &vop->win[i];
1576                 const struct vop_win_data *win_data = &vop_data->win[i];
1577
1578                 vop_win->data = win_data;
1579                 vop_win->vop = vop;
1580         }
1581 }
1582
1583 static int vop_bind(struct device *dev, struct device *master, void *data)
1584 {
1585         struct platform_device *pdev = to_platform_device(dev);
1586         const struct of_device_id *of_id;
1587         const struct vop_data *vop_data;
1588         struct drm_device *drm_dev = data;
1589         struct vop *vop;
1590         struct resource *res;
1591         size_t alloc_size;
1592         int ret, irq;
1593
1594         of_id = of_match_device(vop_driver_dt_match, dev);
1595         vop_data = of_id->data;
1596         if (!vop_data)
1597                 return -ENODEV;
1598
1599         /* Allocate vop struct and its vop_win array */
1600         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1601         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1602         if (!vop)
1603                 return -ENOMEM;
1604
1605         vop->dev = dev;
1606         vop->data = vop_data;
1607         vop->drm_dev = drm_dev;
1608         dev_set_drvdata(dev, vop);
1609
1610         vop_win_init(vop);
1611
1612         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1613         vop->len = resource_size(res);
1614         vop->regs = devm_ioremap_resource(dev, res);
1615         if (IS_ERR(vop->regs))
1616                 return PTR_ERR(vop->regs);
1617
1618         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1619         if (!vop->regsbak)
1620                 return -ENOMEM;
1621
1622         ret = vop_initial(vop);
1623         if (ret < 0) {
1624                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1625                 return ret;
1626         }
1627
1628         irq = platform_get_irq(pdev, 0);
1629         if (irq < 0) {
1630                 dev_err(dev, "cannot find irq for vop\n");
1631                 return irq;
1632         }
1633         vop->irq = (unsigned int)irq;
1634
1635         spin_lock_init(&vop->reg_lock);
1636         spin_lock_init(&vop->irq_lock);
1637
1638         mutex_init(&vop->vsync_mutex);
1639
1640         ret = devm_request_irq(dev, vop->irq, vop_isr,
1641                                IRQF_SHARED, dev_name(dev), vop);
1642         if (ret)
1643                 return ret;
1644
1645         /* IRQ is initially disabled; it gets enabled in power_on */
1646         disable_irq(vop->irq);
1647
1648         ret = vop_create_crtc(vop);
1649         if (ret)
1650                 return ret;
1651
1652         pm_runtime_enable(&pdev->dev);
1653         return 0;
1654 }
1655
1656 static void vop_unbind(struct device *dev, struct device *master, void *data)
1657 {
1658         struct vop *vop = dev_get_drvdata(dev);
1659
1660         pm_runtime_disable(dev);
1661         vop_destroy_crtc(vop);
1662 }
1663
1664 static const struct component_ops vop_component_ops = {
1665         .bind = vop_bind,
1666         .unbind = vop_unbind,
1667 };
1668
1669 static int vop_probe(struct platform_device *pdev)
1670 {
1671         struct device *dev = &pdev->dev;
1672
1673         if (!dev->of_node) {
1674                 dev_err(dev, "can't find vop devices\n");
1675                 return -ENODEV;
1676         }
1677
1678         return component_add(dev, &vop_component_ops);
1679 }
1680
1681 static int vop_remove(struct platform_device *pdev)
1682 {
1683         component_del(&pdev->dev, &vop_component_ops);
1684
1685         return 0;
1686 }
1687
1688 struct platform_driver vop_platform_driver = {
1689         .probe = vop_probe,
1690         .remove = vop_remove,
1691         .driver = {
1692                 .name = "rockchip-vop",
1693                 .owner = THIS_MODULE,
1694                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1695         },
1696 };
1697
1698 module_platform_driver(vop_platform_driver);
1699
1700 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1701 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1702 MODULE_LICENSE("GPL v2");