drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34 #include <uapi/drm/rockchip_drm.h>
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40
  41 #define VOP_REG_SUPPORT(vop, reg) \
  42                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  43                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  44                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  45                 reg.mask))
  46
  47 #define VOP_WIN_SUPPORT(vop, win, name) \
  48                 VOP_REG_SUPPORT(vop, win->phy->name)
  49
  50 #define VOP_CTRL_SUPPORT(vop, win, name) \
  51                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  52
  53 #define VOP_INTR_SUPPORT(vop, win, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  55
  56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  57                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  58
  59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  60         do { \
  61                 if (VOP_REG_SUPPORT(vop, reg)) \
  62                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  63                                   v, reg.write_mask, relaxed); \
  64                 else \
  65                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  66         } while(0)
  67
  68 #define REG_SET(x, name, off, reg, v, relaxed) \
  69                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  72
  73 #define VOP_WIN_SET(x, win, name, v) \
  74                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  75 #define VOP_SCL_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  77 #define VOP_SCL_SET_EXT(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  79
  80 #define VOP_CTRL_SET(x, name, v) \
  81                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  82
  83 #define VOP_INTR_GET(vop, name) \
  84                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  85
  86 #define VOP_INTR_SET(vop, name, mask, v) \
  87                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  88                              mask, v, false)
  89
  90 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  91         do { \
  92                 int i, reg = 0, mask = 0; \
  93                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  94                         if (vop->data->intr->intrs[i] & type) { \
  95                                 reg |= (v) << i; \
  96                                 mask |= 1 << i; \
  97                         } \
  98                 } \
  99                 VOP_INTR_SET(vop, name, mask, reg); \
 100         } while (0)
 101 #define VOP_INTR_GET_TYPE(vop, name, type) \
 102                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 103
 104 #define VOP_CTRL_GET(x, name) \
 105                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 106
 107 #define VOP_WIN_GET(x, win, name) \
 108                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 109
 110 #define VOP_WIN_NAME(win, name) \
 111                 (vop_get_win_phy(win, &win->phy->name)->name)
 112
 113 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 114                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 115
 116 #define to_vop(x) container_of(x, struct vop, crtc)
 117 #define to_vop_win(x) container_of(x, struct vop_win, base)
 118 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 119
 120 struct vop_zpos {
 121         int win_id;
 122         int zpos;
 123 };
 124
 125 struct vop_plane_state {
 126         struct drm_plane_state base;
 127         int format;
 128         int zpos;
 129         struct drm_rect src;
 130         struct drm_rect dest;
 131         dma_addr_t yrgb_mst;
 132         dma_addr_t uv_mst;
 133         bool enable;
 134 };
 135
 136 struct vop_win {
 137         struct vop_win *parent;
 138         struct drm_plane base;
 139
 140         int win_id;
 141         int area_id;
 142         uint32_t offset;
 143         enum drm_plane_type type;
 144         const struct vop_win_phy *phy;
 145         const uint32_t *data_formats;
 146         uint32_t nformats;
 147         struct vop *vop;
 148
 149         struct drm_property *rotation_prop;
 150         struct vop_plane_state state;
 151 };
 152
 153 struct vop {
 154         struct drm_crtc crtc;
 155         struct device *dev;
 156         struct drm_device *drm_dev;
 157         struct drm_property *plane_zpos_prop;
 158         struct drm_property *plane_feature_prop;
 159         bool is_iommu_enabled;
 160         bool is_iommu_needed;
 161         bool is_enabled;
 162
 163         /* mutex vsync_ work */
 164         struct mutex vsync_mutex;
 165         bool vsync_work_pending;
 166         struct completion dsp_hold_completion;
 167         struct completion wait_update_complete;
 168         struct drm_pending_vblank_event *event;
 169
 170         const struct vop_data *data;
 171         int num_wins;
 172
 173         uint32_t *regsbak;
 174         void __iomem *regs;
 175
 176         /* physical map length of vop register */
 177         uint32_t len;
 178
 179         /* one time only one process allowed to config the register */
 180         spinlock_t reg_lock;
 181         /* lock vop irq reg */
 182         spinlock_t irq_lock;
 183
 184         unsigned int irq;
 185
 186         /* vop AHP clk */
 187         struct clk *hclk;
 188         /* vop dclk */
 189         struct clk *dclk;
 190         /* vop share memory frequency */
 191         struct clk *aclk;
 192
 193         /* vop dclk reset */
 194         struct reset_control *dclk_rst;
 195
 196         struct vop_win win[];
 197 };
 198
 199 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 200 {
 201         writel(v, vop->regs + offset);
 202         vop->regsbak[offset >> 2] = v;
 203 }
 204
 205 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 206 {
 207         return readl(vop->regs + offset);
 208 }
 209
 210 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 211                                     const struct vop_reg *reg)
 212 {
 213         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 214 }
 215
 216 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 217                                   uint32_t mask, uint32_t shift, uint32_t v,
 218                                   bool write_mask, bool relaxed)
 219 {
 220         if (!mask)
 221                 return;
 222
 223         if (write_mask) {
 224                 v = ((v & mask) << shift) | (mask << (shift + 16));
 225         } else {
 226                 uint32_t cached_val = vop->regsbak[offset >> 2];
 227
 228                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 229                 vop->regsbak[offset >> 2] = v;
 230         }
 231
 232         if (relaxed)
 233                 writel_relaxed(v, vop->regs + offset);
 234         else
 235                 writel(v, vop->regs + offset);
 236 }
 237
 238 static inline const struct vop_win_phy *
 239 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 240 {
 241         if (!reg->mask && win->parent)
 242                 return win->parent->phy;
 243
 244         return win->phy;
 245 }
 246
 247 static inline uint32_t vop_get_intr_type(struct vop *vop,
 248                                          const struct vop_reg *reg, int type)
 249 {
 250         uint32_t i, ret = 0;
 251         uint32_t regs = vop_read_reg(vop, 0, reg);
 252
 253         for (i = 0; i < vop->data->intr->nintrs; i++) {
 254                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 255                         ret |= vop->data->intr->intrs[i];
 256         }
 257
 258         return ret;
 259 }
 260
 261 static inline void vop_cfg_done(struct vop *vop)
 262 {
 263         VOP_CTRL_SET(vop, cfg_done, 1);
 264 }
 265
 266 static bool vop_is_allwin_disabled(struct vop *vop)
 267 {
 268         int i;
 269
 270         for (i = 0; i < vop->num_wins; i++) {
 271                 struct vop_win *win = &vop->win[i];
 272
 273                 if (VOP_WIN_GET(vop, win, enable) != 0)
 274                         return false;
 275         }
 276
 277         return true;
 278 }
 279
 280 static bool vop_is_cfg_done_complete(struct vop *vop)
 281 {
 282         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 283 }
 284
 285 static bool has_rb_swapped(uint32_t format)
 286 {
 287         switch (format) {
 288         case DRM_FORMAT_XBGR8888:
 289         case DRM_FORMAT_ABGR8888:
 290         case DRM_FORMAT_BGR888:
 291         case DRM_FORMAT_BGR565:
 292                 return true;
 293         default:
 294                 return false;
 295         }
 296 }
 297
 298 static enum vop_data_format vop_convert_format(uint32_t format)
 299 {
 300         switch (format) {
 301         case DRM_FORMAT_XRGB8888:
 302         case DRM_FORMAT_ARGB8888:
 303         case DRM_FORMAT_XBGR8888:
 304         case DRM_FORMAT_ABGR8888:
 305                 return VOP_FMT_ARGB8888;
 306         case DRM_FORMAT_RGB888:
 307         case DRM_FORMAT_BGR888:
 308                 return VOP_FMT_RGB888;
 309         case DRM_FORMAT_RGB565:
 310         case DRM_FORMAT_BGR565:
 311                 return VOP_FMT_RGB565;
 312         case DRM_FORMAT_NV12:
 313                 return VOP_FMT_YUV420SP;
 314         case DRM_FORMAT_NV16:
 315                 return VOP_FMT_YUV422SP;
 316         case DRM_FORMAT_NV24:
 317                 return VOP_FMT_YUV444SP;
 318         default:
 319                 DRM_ERROR("unsupport format[%08x]\n", format);
 320                 return -EINVAL;
 321         }
 322 }
 323
 324 static bool is_yuv_support(uint32_t format)
 325 {
 326         switch (format) {
 327         case DRM_FORMAT_NV12:
 328         case DRM_FORMAT_NV16:
 329         case DRM_FORMAT_NV24:
 330                 return true;
 331         default:
 332                 return false;
 333         }
 334 }
 335
 336 static bool is_alpha_support(uint32_t format)
 337 {
 338         switch (format) {
 339         case DRM_FORMAT_ARGB8888:
 340         case DRM_FORMAT_ABGR8888:
 341                 return true;
 342         default:
 343                 return false;
 344         }
 345 }
 346
 347 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 348                                   uint32_t dst, bool is_horizontal,
 349                                   int vsu_mode, int *vskiplines)
 350 {
 351         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 352
 353         if (is_horizontal) {
 354                 if (mode == SCALE_UP)
 355                         val = GET_SCL_FT_BIC(src, dst);
 356                 else if (mode == SCALE_DOWN)
 357                         val = GET_SCL_FT_BILI_DN(src, dst);
 358         } else {
 359                 if (mode == SCALE_UP) {
 360                         if (vsu_mode == SCALE_UP_BIL)
 361                                 val = GET_SCL_FT_BILI_UP(src, dst);
 362                         else
 363                                 val = GET_SCL_FT_BIC(src, dst);
 364                 } else if (mode == SCALE_DOWN) {
 365                         if (vskiplines) {
 366                                 *vskiplines = scl_get_vskiplines(src, dst);
 367                                 val = scl_get_bili_dn_vskip(src, dst,
 368                                                             *vskiplines);
 369                         } else {
 370                                 val = GET_SCL_FT_BILI_DN(src, dst);
 371                         }
 372                 }
 373         }
 374
 375         return val;
 376 }
 377
 378 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 379                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 380                                 uint32_t dst_h, uint32_t pixel_format)
 381 {
 382         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 383         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 384         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 385         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 386         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 387         bool is_yuv = is_yuv_support(pixel_format);
 388         uint16_t cbcr_src_w = src_w / hsub;
 389         uint16_t cbcr_src_h = src_h / vsub;
 390         uint16_t vsu_mode;
 391         uint16_t lb_mode;
 392         uint32_t val;
 393         int vskiplines = 0;
 394
 395         if (!win->phy->scl)
 396                 return;
 397
 398         if (dst_w > 3840) {
 399                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 400                 return;
 401         }
 402
 403         if (!win->phy->scl->ext) {
 404                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 405                             scl_cal_scale2(src_w, dst_w));
 406                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 407                             scl_cal_scale2(src_h, dst_h));
 408                 if (is_yuv) {
 409                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 410                                     scl_cal_scale2(cbcr_src_w, dst_w));
 411                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 412                                     scl_cal_scale2(cbcr_src_h, dst_h));
 413                 }
 414                 return;
 415         }
 416
 417         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 418         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 419
 420         if (is_yuv) {
 421                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 422                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 423                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 424                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 425                 else
 426                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 427         } else {
 428                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 429                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 430                 else
 431                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 432         }
 433
 434         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 435         if (lb_mode == LB_RGB_3840X2) {
 436                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 437                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 438                         return;
 439                 }
 440                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 441                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 442                         return;
 443                 }
 444                 vsu_mode = SCALE_UP_BIL;
 445         } else if (lb_mode == LB_RGB_2560X4) {
 446                 vsu_mode = SCALE_UP_BIL;
 447         } else {
 448                 vsu_mode = SCALE_UP_BIC;
 449         }
 450
 451         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 452                                 true, 0, NULL);
 453         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 454         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 455                                 false, vsu_mode, &vskiplines);
 456         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 457
 458         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 459         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 460
 461         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 462         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 463         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 464         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 465         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 466         if (is_yuv) {
 467                 vskiplines = 0;
 468
 469                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 470                                         dst_w, true, 0, NULL);
 471                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 472                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 473                                         dst_h, false, vsu_mode, &vskiplines);
 474                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 475
 476                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 477                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 478                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 479                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 480                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 481                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 482                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 483         }
 484 }
 485
 486 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 487 {
 488         unsigned long flags;
 489
 490         spin_lock_irqsave(&vop->irq_lock, flags);
 491
 492         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 493
 494         spin_unlock_irqrestore(&vop->irq_lock, flags);
 495 }
 496
 497 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 498 {
 499         unsigned long flags;
 500
 501         spin_lock_irqsave(&vop->irq_lock, flags);
 502
 503         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 504
 505         spin_unlock_irqrestore(&vop->irq_lock, flags);
 506 }
 507
 508 static void vop_enable(struct drm_crtc *crtc)
 509 {
 510         struct vop *vop = to_vop(crtc);
 511         int ret, i;
 512
 513         ret = clk_prepare_enable(vop->hclk);
 514         if (ret < 0) {
 515                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 516                 return;
 517         }
 518
 519         ret = clk_prepare_enable(vop->dclk);
 520         if (ret < 0) {
 521                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 522                 goto err_disable_hclk;
 523         }
 524
 525         ret = clk_prepare_enable(vop->aclk);
 526         if (ret < 0) {
 527                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 528                 goto err_disable_dclk;
 529         }
 530
 531         ret = pm_runtime_get_sync(vop->dev);
 532         if (ret < 0) {
 533                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 534                 return;
 535         }
 536
 537         memcpy(vop->regsbak, vop->regs, vop->len);
 538
 539         VOP_CTRL_SET(vop, global_regdone_en, 1);
 540         VOP_CTRL_SET(vop, dsp_blank, 0);
 541
 542         for (i = 0; i < vop->num_wins; i++) {
 543                 struct vop_win *win = &vop->win[i];
 544
 545                 VOP_WIN_SET(vop, win, gate, 1);
 546         }
 547         vop->is_enabled = true;
 548
 549         spin_lock(&vop->reg_lock);
 550
 551         VOP_CTRL_SET(vop, standby, 0);
 552
 553         spin_unlock(&vop->reg_lock);
 554
 555         enable_irq(vop->irq);
 556
 557         drm_crtc_vblank_on(crtc);
 558
 559         return;
 560
 561 err_disable_dclk:
 562         clk_disable_unprepare(vop->dclk);
 563 err_disable_hclk:
 564         clk_disable_unprepare(vop->hclk);
 565 }
 566
 567 static void vop_crtc_disable(struct drm_crtc *crtc)
 568 {
 569         struct vop *vop = to_vop(crtc);
 570         int i;
 571
 572         /*
 573          * We need to make sure that all windows are disabled before we
 574          * disable that crtc. Otherwise we might try to scan from a destroyed
 575          * buffer later.
 576          */
 577         for (i = 0; i < vop->num_wins; i++) {
 578                 struct vop_win *win = &vop->win[i];
 579
 580                 spin_lock(&vop->reg_lock);
 581                 VOP_WIN_SET(vop, win, enable, 0);
 582                 spin_unlock(&vop->reg_lock);
 583         }
 584         vop_cfg_done(vop);
 585
 586         drm_crtc_vblank_off(crtc);
 587
 588         /*
 589          * Vop standby will take effect at end of current frame,
 590          * if dsp hold valid irq happen, it means standby complete.
 591          *
 592          * we must wait standby complete when we want to disable aclk,
 593          * if not, memory bus maybe dead.
 594          */
 595         reinit_completion(&vop->dsp_hold_completion);
 596         vop_dsp_hold_valid_irq_enable(vop);
 597
 598         spin_lock(&vop->reg_lock);
 599
 600         VOP_CTRL_SET(vop, standby, 1);
 601
 602         spin_unlock(&vop->reg_lock);
 603
 604         wait_for_completion(&vop->dsp_hold_completion);
 605
 606         vop_dsp_hold_valid_irq_disable(vop);
 607
 608         disable_irq(vop->irq);
 609
 610         vop->is_enabled = false;
 611         if (vop->is_iommu_enabled) {
 612                 /*
 613                  * vop standby complete, so iommu detach is safe.
 614                  */
 615                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 616                 vop->is_iommu_enabled = false;
 617         }
 618
 619         pm_runtime_put(vop->dev);
 620         clk_disable_unprepare(vop->dclk);
 621         clk_disable_unprepare(vop->aclk);
 622         clk_disable_unprepare(vop->hclk);
 623 }
 624
 625 static void vop_plane_destroy(struct drm_plane *plane)
 626 {
 627         drm_plane_cleanup(plane);
 628 }
 629
 630 static int vop_plane_prepare_fb(struct drm_plane *plane,
 631                                 const struct drm_plane_state *new_state)
 632 {
 633         if (plane->state->fb)
 634                 drm_framebuffer_reference(plane->state->fb);
 635
 636         return 0;
 637 }
 638
 639 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 640                                  const struct drm_plane_state *old_state)
 641 {
 642         if (old_state->fb)
 643                 drm_framebuffer_unreference(old_state->fb);
 644 }
 645
 646 static int vop_plane_atomic_check(struct drm_plane *plane,
 647                            struct drm_plane_state *state)
 648 {
 649         struct drm_crtc *crtc = state->crtc;
 650         struct drm_framebuffer *fb = state->fb;
 651         struct vop_win *win = to_vop_win(plane);
 652         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 653         struct drm_crtc_state *crtc_state;
 654         bool visible;
 655         int ret;
 656         struct drm_rect *dest = &vop_plane_state->dest;
 657         struct drm_rect *src = &vop_plane_state->src;
 658         struct drm_rect clip;
 659         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 660                                         DRM_PLANE_HELPER_NO_SCALING;
 661         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 662                                         DRM_PLANE_HELPER_NO_SCALING;
 663         unsigned long offset;
 664         dma_addr_t dma_addr;
 665
 666         crtc = crtc ? crtc : plane->state->crtc;
 667         /*
 668          * Both crtc or plane->state->crtc can be null.
 669          */
 670         if (!crtc || !fb)
 671                 goto out_disable;
 672
 673         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 674         if (IS_ERR(crtc_state))
 675                 return PTR_ERR(crtc_state);
 676
 677         src->x1 = state->src_x;
 678         src->y1 = state->src_y;
 679         src->x2 = state->src_x + state->src_w;
 680         src->y2 = state->src_y + state->src_h;
 681         dest->x1 = state->crtc_x;
 682         dest->y1 = state->crtc_y;
 683         dest->x2 = state->crtc_x + state->crtc_w;
 684         dest->y2 = state->crtc_y + state->crtc_h;
 685
 686         clip.x1 = 0;
 687         clip.y1 = 0;
 688         clip.x2 = crtc_state->mode.hdisplay;
 689         clip.y2 = crtc_state->mode.vdisplay;
 690
 691         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 692                                             src, dest, &clip,
 693                                             min_scale,
 694                                             max_scale,
 695                                             true, true, &visible);
 696         if (ret)
 697                 return ret;
 698
 699         if (!visible)
 700                 goto out_disable;
 701
 702         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 703         if (vop_plane_state->format < 0)
 704                 return vop_plane_state->format;
 705
 706         /*
 707          * Src.x1 can be odd when do clip, but yuv plane start point
 708          * need align with 2 pixel.
 709          */
 710         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 711                 return -EINVAL;
 712
 713         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 714         if (state->rotation & BIT(DRM_REFLECT_Y))
 715                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 716         else
 717                 offset += (src->y1 >> 16) * fb->pitches[0];
 718
 719         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 720         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 721         if (is_yuv_support(fb->pixel_format)) {
 722                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 723                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 724                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 725
 726                 offset = (src->x1 >> 16) * bpp / hsub;
 727                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 728
 729                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 730                 dma_addr += offset + fb->offsets[1];
 731                 vop_plane_state->uv_mst = dma_addr;
 732         }
 733
 734         vop_plane_state->enable = true;
 735
 736         return 0;
 737
 738 out_disable:
 739         vop_plane_state->enable = false;
 740         return 0;
 741 }
 742
 743 static void vop_plane_atomic_disable(struct drm_plane *plane,
 744                                      struct drm_plane_state *old_state)
 745 {
 746         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 747         struct vop_win *win = to_vop_win(plane);
 748         struct vop *vop = to_vop(old_state->crtc);
 749
 750         if (!old_state->crtc)
 751                 return;
 752
 753         spin_lock(&vop->reg_lock);
 754
 755         VOP_WIN_SET(vop, win, enable, 0);
 756
 757         spin_unlock(&vop->reg_lock);
 758
 759         vop_plane_state->enable = false;
 760 }
 761
 762 static void vop_plane_atomic_update(struct drm_plane *plane,
 763                 struct drm_plane_state *old_state)
 764 {
 765         struct drm_plane_state *state = plane->state;
 766         struct drm_crtc *crtc = state->crtc;
 767         struct vop_win *win = to_vop_win(plane);
 768         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 769         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 770         struct vop *vop = to_vop(state->crtc);
 771         struct drm_framebuffer *fb = state->fb;
 772         unsigned int actual_w, actual_h;
 773         unsigned int dsp_stx, dsp_sty;
 774         uint32_t act_info, dsp_info, dsp_st;
 775         struct drm_rect *src = &vop_plane_state->src;
 776         struct drm_rect *dest = &vop_plane_state->dest;
 777         int ymirror, xmirror;
 778         uint32_t val;
 779         bool rb_swap;
 780
 781         /*
 782          * can't update plane when vop is disabled.
 783          */
 784         if (!crtc)
 785                 return;
 786
 787         if (!vop_plane_state->enable) {
 788                 vop_plane_atomic_disable(plane, old_state);
 789                 return;
 790         }
 791
 792         actual_w = drm_rect_width(src) >> 16;
 793         actual_h = drm_rect_height(src) >> 16;
 794         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 795
 796         dsp_info = (drm_rect_height(dest) - 1) << 16;
 797         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 798
 799         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 800         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 801         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 802
 803         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 804         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 805
 806         spin_lock(&vop->reg_lock);
 807
 808         VOP_WIN_SET(vop, win, xmirror, xmirror);
 809         VOP_WIN_SET(vop, win, ymirror, ymirror);
 810         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 811         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 812         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 813         if (is_yuv_support(fb->pixel_format)) {
 814                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 815                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
 816         }
 817
 818         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 819                             drm_rect_width(dest), drm_rect_height(dest),
 820                             fb->pixel_format);
 821
 822         VOP_WIN_SET(vop, win, act_info, act_info);
 823         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 824         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 825
 826         rb_swap = has_rb_swapped(fb->pixel_format);
 827         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 828
 829         if (is_alpha_support(fb->pixel_format) &&
 830             (s->dsp_layer_sel & 0x3) != win->win_id) {
 831                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 832                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 833                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 834                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 835                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 836                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 837                         SRC_FACTOR_M0(ALPHA_ONE);
 838                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 839                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 840                 VOP_WIN_SET(vop, win, alpha_en, 1);
 841         } else {
 842                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 843                 VOP_WIN_SET(vop, win, alpha_en, 0);
 844         }
 845
 846         VOP_WIN_SET(vop, win, enable, 1);
 847         spin_unlock(&vop->reg_lock);
 848         vop->is_iommu_needed = true;
 849 }
 850
 851 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 852         .prepare_fb = vop_plane_prepare_fb,
 853         .cleanup_fb = vop_plane_cleanup_fb,
 854         .atomic_check = vop_plane_atomic_check,
 855         .atomic_update = vop_plane_atomic_update,
 856         .atomic_disable = vop_plane_atomic_disable,
 857 };
 858
 859 void vop_atomic_plane_reset(struct drm_plane *plane)
 860 {
 861         struct vop_win *win = to_vop_win(plane);
 862         struct vop_plane_state *vop_plane_state =
 863                                         to_vop_plane_state(plane->state);
 864
 865         if (plane->state && plane->state->fb)
 866                 drm_framebuffer_unreference(plane->state->fb);
 867
 868         kfree(vop_plane_state);
 869         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 870         if (!vop_plane_state)
 871                 return;
 872
 873         vop_plane_state->zpos = win->win_id;
 874         plane->state = &vop_plane_state->base;
 875         plane->state->plane = plane;
 876 }
 877
 878 struct drm_plane_state *
 879 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 880 {
 881         struct vop_plane_state *old_vop_plane_state;
 882         struct vop_plane_state *vop_plane_state;
 883
 884         if (WARN_ON(!plane->state))
 885                 return NULL;
 886
 887         old_vop_plane_state = to_vop_plane_state(plane->state);
 888         vop_plane_state = kmemdup(old_vop_plane_state,
 889                                   sizeof(*vop_plane_state), GFP_KERNEL);
 890         if (!vop_plane_state)
 891                 return NULL;
 892
 893         __drm_atomic_helper_plane_duplicate_state(plane,
 894                                                   &vop_plane_state->base);
 895
 896         return &vop_plane_state->base;
 897 }
 898
 899 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 900                                            struct drm_plane_state *state)
 901 {
 902         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 903
 904         __drm_atomic_helper_plane_destroy_state(plane, state);
 905
 906         kfree(vop_state);
 907 }
 908
 909 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 910                                          struct drm_plane_state *state,
 911                                          struct drm_property *property,
 912                                          uint64_t val)
 913 {
 914         struct vop_win *win = to_vop_win(plane);
 915         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 916
 917         if (property == win->vop->plane_zpos_prop) {
 918                 plane_state->zpos = val;
 919                 return 0;
 920         }
 921
 922         if (property == win->rotation_prop) {
 923                 state->rotation = val;
 924                 return 0;
 925         }
 926
 927         DRM_ERROR("failed to set vop plane property\n");
 928         return -EINVAL;
 929 }
 930
 931 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 932                                          const struct drm_plane_state *state,
 933                                          struct drm_property *property,
 934                                          uint64_t *val)
 935 {
 936         struct vop_win *win = to_vop_win(plane);
 937         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 938
 939         if (property == win->vop->plane_zpos_prop) {
 940                 *val = plane_state->zpos;
 941                 return 0;
 942         }
 943
 944         if (property == win->rotation_prop) {
 945                 *val = state->rotation;
 946                 return 0;
 947         }
 948
 949         DRM_ERROR("failed to get vop plane property\n");
 950         return -EINVAL;
 951 }
 952
 953 static const struct drm_plane_funcs vop_plane_funcs = {
 954         .update_plane   = drm_atomic_helper_update_plane,
 955         .disable_plane  = drm_atomic_helper_disable_plane,
 956         .destroy = vop_plane_destroy,
 957         .reset = vop_atomic_plane_reset,
 958         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 959         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 960         .atomic_set_property = vop_atomic_plane_set_property,
 961         .atomic_get_property = vop_atomic_plane_get_property,
 962 };
 963
 964 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 965 {
 966         struct vop *vop = to_vop(crtc);
 967         unsigned long flags;
 968
 969         if (!vop->is_enabled)
 970                 return -EPERM;
 971
 972         spin_lock_irqsave(&vop->irq_lock, flags);
 973
 974         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 975
 976         spin_unlock_irqrestore(&vop->irq_lock, flags);
 977
 978         return 0;
 979 }
 980
 981 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 982 {
 983         struct vop *vop = to_vop(crtc);
 984         unsigned long flags;
 985
 986         if (!vop->is_enabled)
 987                 return;
 988
 989         spin_lock_irqsave(&vop->irq_lock, flags);
 990
 991         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 992
 993         spin_unlock_irqrestore(&vop->irq_lock, flags);
 994 }
 995
 996 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 997 {
 998         struct vop *vop = to_vop(crtc);
 999
1000         reinit_completion(&vop->wait_update_complete);
1001         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1002 }
1003
1004 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1005                                            struct drm_file *file_priv)
1006 {
1007         struct drm_device *drm = crtc->dev;
1008         struct vop *vop = to_vop(crtc);
1009         struct drm_pending_vblank_event *e;
1010         unsigned long flags;
1011
1012         spin_lock_irqsave(&drm->event_lock, flags);
1013         e = vop->event;
1014         if (e && e->base.file_priv == file_priv) {
1015                 vop->event = NULL;
1016
1017                 e->base.destroy(&e->base);
1018                 file_priv->event_space += sizeof(e->event);
1019         }
1020         spin_unlock_irqrestore(&drm->event_lock, flags);
1021 }
1022
1023 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1024         .enable_vblank = vop_crtc_enable_vblank,
1025         .disable_vblank = vop_crtc_disable_vblank,
1026         .wait_for_update = vop_crtc_wait_for_update,
1027         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1028 };
1029
1030 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1031                                 const struct drm_display_mode *mode,
1032                                 struct drm_display_mode *adjusted_mode)
1033 {
1034         struct vop *vop = to_vop(crtc);
1035
1036         adjusted_mode->clock =
1037                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1038
1039         return true;
1040 }
1041
1042 static void vop_crtc_enable(struct drm_crtc *crtc)
1043 {
1044         struct vop *vop = to_vop(crtc);
1045         const struct vop_data *vop_data = vop->data;
1046         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1047         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1048         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1049         u16 hdisplay = adjusted_mode->hdisplay;
1050         u16 htotal = adjusted_mode->htotal;
1051         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1052         u16 hact_end = hact_st + hdisplay;
1053         u16 vdisplay = adjusted_mode->vdisplay;
1054         u16 vtotal = adjusted_mode->vtotal;
1055         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1056         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1057         u16 vact_end = vact_st + vdisplay;
1058         uint32_t val;
1059
1060         vop_enable(crtc);
1061         /*
1062          * If dclk rate is zero, mean that scanout is stop,
1063          * we don't need wait any more.
1064          */
1065         if (clk_get_rate(vop->dclk)) {
1066                 /*
1067                  * Rk3288 vop timing register is immediately, when configure
1068                  * display timing on display time, may cause tearing.
1069                  *
1070                  * Vop standby will take effect at end of current frame,
1071                  * if dsp hold valid irq happen, it means standby complete.
1072                  *
1073                  * mode set:
1074                  *    standby and wait complete --> |----
1075                  *                                  | display time
1076                  *                                  |----
1077                  *                                  |---> dsp hold irq
1078                  *     configure display timing --> |
1079                  *         standby exit             |
1080                  *                                  | new frame start.
1081                  */
1082
1083                 reinit_completion(&vop->dsp_hold_completion);
1084                 vop_dsp_hold_valid_irq_enable(vop);
1085
1086                 spin_lock(&vop->reg_lock);
1087
1088                 VOP_CTRL_SET(vop, standby, 1);
1089
1090                 spin_unlock(&vop->reg_lock);
1091
1092                 wait_for_completion(&vop->dsp_hold_completion);
1093
1094                 vop_dsp_hold_valid_irq_disable(vop);
1095         }
1096
1097         val = 0x8;
1098         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1099         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1100         VOP_CTRL_SET(vop, pin_pol, val);
1101         switch (s->output_type) {
1102         case DRM_MODE_CONNECTOR_LVDS:
1103                 VOP_CTRL_SET(vop, rgb_en, 1);
1104                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1105                 break;
1106         case DRM_MODE_CONNECTOR_eDP:
1107                 VOP_CTRL_SET(vop, edp_en, 1);
1108                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1109                 break;
1110         case DRM_MODE_CONNECTOR_HDMIA:
1111                 VOP_CTRL_SET(vop, hdmi_en, 1);
1112                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1113                 break;
1114         case DRM_MODE_CONNECTOR_DSI:
1115                 VOP_CTRL_SET(vop, mipi_en, 1);
1116                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1117                 break;
1118         default:
1119                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1120         }
1121
1122         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1123             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1124                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1125
1126         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1127
1128         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1129         val = hact_st << 16;
1130         val |= hact_end;
1131         VOP_CTRL_SET(vop, hact_st_end, val);
1132         VOP_CTRL_SET(vop, hpost_st_end, val);
1133
1134         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1135         val = vact_st << 16;
1136         val |= vact_end;
1137         VOP_CTRL_SET(vop, vact_st_end, val);
1138         VOP_CTRL_SET(vop, vpost_st_end, val);
1139
1140         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1141
1142         VOP_CTRL_SET(vop, standby, 0);
1143 }
1144
1145 static int vop_zpos_cmp(const void *a, const void *b)
1146 {
1147         struct vop_zpos *pa = (struct vop_zpos *)a;
1148         struct vop_zpos *pb = (struct vop_zpos *)b;
1149
1150         return pa->zpos - pb->zpos;
1151 }
1152
1153 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1154                                  struct drm_crtc_state *crtc_state)
1155 {
1156         struct drm_atomic_state *state = crtc_state->state;
1157         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1158         struct vop *vop = to_vop(crtc);
1159         const struct vop_data *vop_data = vop->data;
1160         struct drm_plane *plane;
1161         struct drm_plane_state *pstate;
1162         struct vop_plane_state *plane_state;
1163         struct vop_zpos *pzpos;
1164         int dsp_layer_sel = 0;
1165         int i, j, cnt = 0, ret = 0;
1166
1167         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1168         if (!pzpos)
1169                 return -ENOMEM;
1170
1171         for (i = 0; i < vop_data->win_size; i++) {
1172                 const struct vop_win_data *win_data = &vop_data->win[i];
1173                 struct vop_win *win;
1174
1175                 if (!win_data->phy)
1176                         continue;
1177
1178                 for (j = 0; j < vop->num_wins; j++) {
1179                         win = &vop->win[j];
1180
1181                         if (win->win_id == i && !win->area_id)
1182                                 break;
1183                 }
1184                 if (WARN_ON(j >= vop->num_wins)) {
1185                         ret = -EINVAL;
1186                         goto err_free_pzpos;
1187                 }
1188
1189                 plane = &win->base;
1190                 pstate = state->plane_states[drm_plane_index(plane)];
1191                 /*
1192                  * plane might not have changed, in which case take
1193                  * current state:
1194                  */
1195                 if (!pstate)
1196                         pstate = plane->state;
1197                 plane_state = to_vop_plane_state(pstate);
1198                 pzpos[cnt].zpos = plane_state->zpos;
1199                 pzpos[cnt++].win_id = win->win_id;
1200         }
1201
1202         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1203
1204         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1205                 const struct vop_win_data *win_data = &vop_data->win[i];
1206                 int shift = i * 2;
1207
1208                 if (win_data->phy) {
1209                         struct vop_zpos *zpos = &pzpos[cnt++];
1210
1211                         dsp_layer_sel |= zpos->win_id << shift;
1212                 } else {
1213                         dsp_layer_sel |= i << shift;
1214                 }
1215         }
1216
1217         s->dsp_layer_sel = dsp_layer_sel;
1218
1219 err_free_pzpos:
1220         kfree(pzpos);
1221         return ret;
1222 }
1223
1224 static void vop_cfg_update(struct drm_crtc *crtc,
1225                            struct drm_crtc_state *old_crtc_state)
1226 {
1227         struct rockchip_crtc_state *s =
1228                         to_rockchip_crtc_state(crtc->state);
1229         struct vop *vop = to_vop(crtc);
1230
1231         spin_lock(&vop->reg_lock);
1232
1233         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1234         vop_cfg_done(vop);
1235
1236         spin_unlock(&vop->reg_lock);
1237 }
1238
1239 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1240                                   struct drm_crtc_state *old_crtc_state)
1241 {
1242         struct vop *vop = to_vop(crtc);
1243
1244         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1245                 int ret;
1246                 if (!vop_is_allwin_disabled(vop)) {
1247                         vop_cfg_update(crtc, old_crtc_state);
1248                         while(!vop_is_cfg_done_complete(vop));
1249                 }
1250                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1251                 if (ret) {
1252                         dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1253                 }
1254                 vop->is_iommu_enabled = true;
1255         }
1256
1257         vop_cfg_update(crtc, old_crtc_state);
1258 }
1259
1260 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1261                                   struct drm_crtc_state *old_crtc_state)
1262 {
1263         struct vop *vop = to_vop(crtc);
1264
1265         if (crtc->state->event) {
1266                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1267
1268                 vop->event = crtc->state->event;
1269                 crtc->state->event = NULL;
1270         }
1271 }
1272
1273 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1274         .enable = vop_crtc_enable,
1275         .disable = vop_crtc_disable,
1276         .mode_fixup = vop_crtc_mode_fixup,
1277         .atomic_check = vop_crtc_atomic_check,
1278         .atomic_flush = vop_crtc_atomic_flush,
1279         .atomic_begin = vop_crtc_atomic_begin,
1280 };
1281
1282 static void vop_crtc_destroy(struct drm_crtc *crtc)
1283 {
1284         drm_crtc_cleanup(crtc);
1285 }
1286
1287 static void vop_crtc_reset(struct drm_crtc *crtc)
1288 {
1289         if (crtc->state)
1290                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1291         kfree(crtc->state);
1292
1293         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1294         if (crtc->state)
1295                 crtc->state->crtc = crtc;
1296 }
1297
1298 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1299 {
1300         struct rockchip_crtc_state *rockchip_state;
1301
1302         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1303         if (!rockchip_state)
1304                 return NULL;
1305
1306         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1307         return &rockchip_state->base;
1308 }
1309
1310 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1311                                    struct drm_crtc_state *state)
1312 {
1313         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1314
1315         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1316         kfree(s);
1317 }
1318
1319 static const struct drm_crtc_funcs vop_crtc_funcs = {
1320         .set_config = drm_atomic_helper_set_config,
1321         .page_flip = drm_atomic_helper_page_flip,
1322         .destroy = vop_crtc_destroy,
1323         .reset = vop_crtc_reset,
1324         .atomic_duplicate_state = vop_crtc_duplicate_state,
1325         .atomic_destroy_state = vop_crtc_destroy_state,
1326 };
1327
1328 static void vop_handle_vblank(struct vop *vop)
1329 {
1330         struct drm_device *drm = vop->drm_dev;
1331         struct drm_crtc *crtc = &vop->crtc;
1332         unsigned long flags;
1333
1334         if (!vop_is_cfg_done_complete(vop))
1335                 return;
1336
1337         if (vop->event) {
1338                 spin_lock_irqsave(&drm->event_lock, flags);
1339
1340                 drm_crtc_send_vblank_event(crtc, vop->event);
1341                 drm_crtc_vblank_put(crtc);
1342                 vop->event = NULL;
1343
1344                 spin_unlock_irqrestore(&drm->event_lock, flags);
1345         }
1346         if (!completion_done(&vop->wait_update_complete))
1347                 complete(&vop->wait_update_complete);
1348 }
1349
1350 static irqreturn_t vop_isr(int irq, void *data)
1351 {
1352         struct vop *vop = data;
1353         struct drm_crtc *crtc = &vop->crtc;
1354         uint32_t active_irqs;
1355         unsigned long flags;
1356         int ret = IRQ_NONE;
1357
1358         /*
1359          * interrupt register has interrupt status, enable and clear bits, we
1360          * must hold irq_lock to avoid a race with enable/disable_vblank().
1361         */
1362         spin_lock_irqsave(&vop->irq_lock, flags);
1363
1364         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1365         /* Clear all active interrupt sources */
1366         if (active_irqs)
1367                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1368
1369         spin_unlock_irqrestore(&vop->irq_lock, flags);
1370
1371         /* This is expected for vop iommu irqs, since the irq is shared */
1372         if (!active_irqs)
1373                 return IRQ_NONE;
1374
1375         if (active_irqs & DSP_HOLD_VALID_INTR) {
1376                 complete(&vop->dsp_hold_completion);
1377                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1378                 ret = IRQ_HANDLED;
1379         }
1380
1381         if (active_irqs & FS_INTR) {
1382                 drm_crtc_handle_vblank(crtc);
1383                 vop_handle_vblank(vop);
1384                 active_irqs &= ~FS_INTR;
1385                 ret = IRQ_HANDLED;
1386         }
1387
1388         /* Unhandled irqs are spurious. */
1389         if (active_irqs)
1390                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1391
1392         return ret;
1393 }
1394
1395 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1396                           unsigned long possible_crtcs)
1397 {
1398         struct drm_plane *share = NULL;
1399         unsigned int rotations = 0;
1400         struct drm_property *prop;
1401         uint64_t feature = 0;
1402         int ret;
1403
1404         if (win->parent)
1405                 share = &win->parent->base;
1406
1407         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1408                                    possible_crtcs, &vop_plane_funcs,
1409                                    win->data_formats, win->nformats, win->type);
1410         if (ret) {
1411                 DRM_ERROR("failed to initialize plane\n");
1412                 return ret;
1413         }
1414         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1415         drm_object_attach_property(&win->base.base,
1416                                    vop->plane_zpos_prop, win->win_id);
1417
1418         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1419                 rotations |= BIT(DRM_REFLECT_X);
1420
1421         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1422                 rotations |= BIT(DRM_REFLECT_Y);
1423
1424         if (rotations) {
1425                 rotations |= BIT(DRM_ROTATE_0);
1426                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1427                                                          rotations);
1428                 if (!prop) {
1429                         DRM_ERROR("failed to create zpos property\n");
1430                         return -EINVAL;
1431                 }
1432                 drm_object_attach_property(&win->base.base, prop,
1433                                            BIT(DRM_ROTATE_0));
1434                 win->rotation_prop = prop;
1435         }
1436         if (win->phy->scl)
1437                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1438         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1439             VOP_WIN_SUPPORT(vop, win, alpha_en))
1440                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1441
1442         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1443                                    feature);
1444
1445         return 0;
1446 }
1447
1448 static int vop_create_crtc(struct vop *vop)
1449 {
1450         struct device *dev = vop->dev;
1451         struct drm_device *drm_dev = vop->drm_dev;
1452         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1453         struct drm_crtc *crtc = &vop->crtc;
1454         struct device_node *port;
1455         int ret;
1456         int i;
1457
1458         /*
1459          * Create drm_plane for primary and cursor planes first, since we need
1460          * to pass them to drm_crtc_init_with_planes, which sets the
1461          * "possible_crtcs" to the newly initialized crtc.
1462          */
1463         for (i = 0; i < vop->num_wins; i++) {
1464                 struct vop_win *win = &vop->win[i];
1465
1466                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1467                     win->type != DRM_PLANE_TYPE_CURSOR)
1468                         continue;
1469
1470                 ret = vop_plane_init(vop, win, 0);
1471                 if (ret)
1472                         goto err_cleanup_planes;
1473
1474                 plane = &win->base;
1475                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1476                         primary = plane;
1477                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1478                         cursor = plane;
1479
1480         }
1481
1482         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1483                                         &vop_crtc_funcs, NULL);
1484         if (ret)
1485                 goto err_cleanup_planes;
1486
1487         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1488
1489         /*
1490          * Create drm_planes for overlay windows with possible_crtcs restricted
1491          * to the newly created crtc.
1492          */
1493         for (i = 0; i < vop->num_wins; i++) {
1494                 struct vop_win *win = &vop->win[i];
1495                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1496
1497                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1498                         continue;
1499
1500                 ret = vop_plane_init(vop, win, possible_crtcs);
1501                 if (ret)
1502                         goto err_cleanup_crtc;
1503         }
1504
1505         port = of_get_child_by_name(dev->of_node, "port");
1506         if (!port) {
1507                 DRM_ERROR("no port node found in %s\n",
1508                           dev->of_node->full_name);
1509                 ret = -ENOENT;
1510                 goto err_cleanup_crtc;
1511         }
1512
1513         init_completion(&vop->dsp_hold_completion);
1514         init_completion(&vop->wait_update_complete);
1515         crtc->port = port;
1516         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1517
1518         return 0;
1519
1520 err_cleanup_crtc:
1521         drm_crtc_cleanup(crtc);
1522 err_cleanup_planes:
1523         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1524                                  head)
1525                 drm_plane_cleanup(plane);
1526         return ret;
1527 }
1528
1529 static void vop_destroy_crtc(struct vop *vop)
1530 {
1531         struct drm_crtc *crtc = &vop->crtc;
1532         struct drm_device *drm_dev = vop->drm_dev;
1533         struct drm_plane *plane, *tmp;
1534
1535         rockchip_unregister_crtc_funcs(crtc);
1536         of_node_put(crtc->port);
1537
1538         /*
1539          * We need to cleanup the planes now.  Why?
1540          *
1541          * The planes are "&vop->win[i].base".  That means the memory is
1542          * all part of the big "struct vop" chunk of memory.  That memory
1543          * was devm allocated and associated with this component.  We need to
1544          * free it ourselves before vop_unbind() finishes.
1545          */
1546         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1547                                  head)
1548                 vop_plane_destroy(plane);
1549
1550         /*
1551          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1552          * references the CRTC.
1553          */
1554         drm_crtc_cleanup(crtc);
1555 }
1556
1557 /*
1558  * Initialize the vop->win array elements.
1559  */
1560 static int vop_win_init(struct vop *vop)
1561 {
1562         const struct vop_data *vop_data = vop->data;
1563         unsigned int i, j;
1564         unsigned int num_wins = 0;
1565         struct drm_property *prop;
1566         static const struct drm_prop_enum_list props[] = {
1567                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1568                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1569         };
1570
1571         for (i = 0; i < vop_data->win_size; i++) {
1572                 struct vop_win *vop_win = &vop->win[num_wins];
1573                 const struct vop_win_data *win_data = &vop_data->win[i];
1574
1575                 if (!win_data->phy)
1576                         continue;
1577
1578                 vop_win->phy = win_data->phy;
1579                 vop_win->offset = win_data->base;
1580                 vop_win->type = win_data->type;
1581                 vop_win->data_formats = win_data->phy->data_formats;
1582                 vop_win->nformats = win_data->phy->nformats;
1583                 vop_win->vop = vop;
1584                 vop_win->win_id = i;
1585                 vop_win->area_id = 0;
1586                 num_wins++;
1587
1588                 for (j = 0; j < win_data->area_size; j++) {
1589                         struct vop_win *vop_area = &vop->win[num_wins];
1590                         const struct vop_win_phy *area = win_data->area[j];
1591
1592                         vop_area->parent = vop_win;
1593                         vop_area->offset = vop_win->offset;
1594                         vop_area->phy = area;
1595                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1596                         vop_area->data_formats = vop_win->data_formats;
1597                         vop_area->nformats = vop_win->nformats;
1598                         vop_area->vop = vop;
1599                         vop_area->win_id = i;
1600                         vop_area->area_id = j;
1601                         num_wins++;
1602                 }
1603         }
1604
1605         vop->num_wins = num_wins;
1606
1607         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1608                                          "ZPOS", 0, vop->data->win_size);
1609         if (!prop) {
1610                 DRM_ERROR("failed to create zpos property\n");
1611                 return -EINVAL;
1612         }
1613         vop->plane_zpos_prop = prop;
1614
1615         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1616                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1617                                 props, ARRAY_SIZE(props),
1618                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1619                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1620         if (!vop->plane_feature_prop) {
1621                 DRM_ERROR("failed to create feature property\n");
1622                 return -EINVAL;
1623         }
1624
1625         return 0;
1626 }
1627
1628 static int vop_bind(struct device *dev, struct device *master, void *data)
1629 {
1630         struct platform_device *pdev = to_platform_device(dev);
1631         const struct vop_data *vop_data;
1632         struct drm_device *drm_dev = data;
1633         struct vop *vop;
1634         struct resource *res;
1635         size_t alloc_size;
1636         int ret, irq, i;
1637         int num_wins = 0;
1638
1639         vop_data = of_device_get_match_data(dev);
1640         if (!vop_data)
1641                 return -ENODEV;
1642
1643         for (i = 0; i < vop_data->win_size; i++) {
1644                 const struct vop_win_data *win_data = &vop_data->win[i];
1645
1646                 num_wins += win_data->area_size + 1;
1647         }
1648
1649         /* Allocate vop struct and its vop_win array */
1650         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1651         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1652         if (!vop)
1653                 return -ENOMEM;
1654
1655         vop->dev = dev;
1656         vop->data = vop_data;
1657         vop->drm_dev = drm_dev;
1658         vop->num_wins = num_wins;
1659         dev_set_drvdata(dev, vop);
1660
1661         ret = vop_win_init(vop);
1662         if (ret)
1663                 return ret;
1664
1665         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1666         vop->len = resource_size(res);
1667         vop->regs = devm_ioremap_resource(dev, res);
1668         if (IS_ERR(vop->regs))
1669                 return PTR_ERR(vop->regs);
1670
1671         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1672         if (!vop->regsbak)
1673                 return -ENOMEM;
1674
1675         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1676         if (IS_ERR(vop->hclk)) {
1677                 dev_err(vop->dev, "failed to get hclk source\n");
1678                 return PTR_ERR(vop->hclk);
1679         }
1680         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1681         if (IS_ERR(vop->aclk)) {
1682                 dev_err(vop->dev, "failed to get aclk source\n");
1683                 return PTR_ERR(vop->aclk);
1684         }
1685         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1686         if (IS_ERR(vop->dclk)) {
1687                 dev_err(vop->dev, "failed to get dclk source\n");
1688                 return PTR_ERR(vop->dclk);
1689         }
1690
1691         irq = platform_get_irq(pdev, 0);
1692         if (irq < 0) {
1693                 dev_err(dev, "cannot find irq for vop\n");
1694                 return irq;
1695         }
1696         vop->irq = (unsigned int)irq;
1697
1698         spin_lock_init(&vop->reg_lock);
1699         spin_lock_init(&vop->irq_lock);
1700
1701         mutex_init(&vop->vsync_mutex);
1702
1703         ret = devm_request_irq(dev, vop->irq, vop_isr,
1704                                IRQF_SHARED, dev_name(dev), vop);
1705         if (ret)
1706                 return ret;
1707
1708         /* IRQ is initially disabled; it gets enabled in power_on */
1709         disable_irq(vop->irq);
1710
1711         ret = vop_create_crtc(vop);
1712         if (ret)
1713                 return ret;
1714
1715         pm_runtime_enable(&pdev->dev);
1716         return 0;
1717 }
1718
1719 static void vop_unbind(struct device *dev, struct device *master, void *data)
1720 {
1721         struct vop *vop = dev_get_drvdata(dev);
1722
1723         pm_runtime_disable(dev);
1724         vop_destroy_crtc(vop);
1725 }
1726
1727 const struct component_ops vop_component_ops = {
1728         .bind = vop_bind,
1729         .unbind = vop_unbind,
1730 };
1731 EXPORT_SYMBOL_GPL(vop_component_ops);