drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34
  35 #include "rockchip_drm_drv.h"
  36 #include "rockchip_drm_gem.h"
  37 #include "rockchip_drm_fb.h"
  38 #include "rockchip_drm_vop.h"
  39
  40 #define VOP_REG_SUPPORT(vop, reg) \
  41                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  42                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  43                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  44                 reg.mask))
  45
  46 #define VOP_WIN_SUPPORT(vop, win, name) \
  47                 VOP_REG_SUPPORT(vop, win->phy->name)
  48
  49 #define VOP_CTRL_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  51
  52 #define VOP_INTR_SUPPORT(vop, win, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  54
  55 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  56                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  57
  58 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  59         do { \
  60                 if (VOP_REG_SUPPORT(vop, reg)) \
  61                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  62                                   v, reg.write_mask, relaxed); \
  63                 else \
  64                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  65         } while(0)
  66
  67 #define REG_SET(x, name, off, reg, v, relaxed) \
  68                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  69 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  71
  72 #define VOP_WIN_SET(x, win, name, v) \
  73                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  74 #define VOP_SCL_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  76 #define VOP_SCL_SET_EXT(x, win, name, v) \
  77                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  78
  79 #define VOP_CTRL_SET(x, name, v) \
  80                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  81
  82 #define VOP_INTR_GET(vop, name) \
  83                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  84
  85 #define VOP_INTR_SET(vop, name, mask, v) \
  86                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  87                              mask, v, false)
  88
  89 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  90         do { \
  91                 int i, reg = 0, mask = 0; \
  92                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  93                         if (vop->data->intr->intrs[i] & type) { \
  94                                 reg |= (v) << i; \
  95                                 mask |= 1 << i; \
  96                         } \
  97                 } \
  98                 VOP_INTR_SET(vop, name, mask, reg); \
  99         } while (0)
 100 #define VOP_INTR_GET_TYPE(vop, name, type) \
 101                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 102
 103 #define VOP_CTRL_GET(x, name) \
 104                 vop_read_reg(x, 0, vop->data->ctrl->name)
 105
 106 #define VOP_WIN_GET(x, win, name) \
 107                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 108
 109 #define VOP_WIN_NAME(win, name) \
 110                 (vop_get_win_phy(win, &win->phy->name)->name)
 111
 112 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 113                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 114
 115 #define to_vop(x) container_of(x, struct vop, crtc)
 116 #define to_vop_win(x) container_of(x, struct vop_win, base)
 117 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 118
 119 struct vop_zpos {
 120         int win_id;
 121         int zpos;
 122 };
 123
 124 struct vop_plane_state {
 125         struct drm_plane_state base;
 126         int format;
 127         int zpos;
 128         struct drm_rect src;
 129         struct drm_rect dest;
 130         dma_addr_t yrgb_mst;
 131         bool enable;
 132 };
 133
 134 struct vop_win {
 135         struct vop_win *parent;
 136         struct drm_plane base;
 137
 138         int win_id;
 139         int area_id;
 140         uint32_t offset;
 141         enum drm_plane_type type;
 142         const struct vop_win_phy *phy;
 143         const uint32_t *data_formats;
 144         uint32_t nformats;
 145         struct vop *vop;
 146
 147         struct drm_property *rotation_prop;
 148         struct vop_plane_state state;
 149 };
 150
 151 struct vop {
 152         struct drm_crtc crtc;
 153         struct device *dev;
 154         struct drm_device *drm_dev;
 155         struct drm_property *plane_zpos_prop;
 156         bool is_enabled;
 157
 158         /* mutex vsync_ work */
 159         struct mutex vsync_mutex;
 160         bool vsync_work_pending;
 161         struct completion dsp_hold_completion;
 162         struct completion wait_update_complete;
 163         struct drm_pending_vblank_event *event;
 164
 165         const struct vop_data *data;
 166         int num_wins;
 167
 168         uint32_t *regsbak;
 169         void __iomem *regs;
 170
 171         /* physical map length of vop register */
 172         uint32_t len;
 173
 174         /* one time only one process allowed to config the register */
 175         spinlock_t reg_lock;
 176         /* lock vop irq reg */
 177         spinlock_t irq_lock;
 178
 179         unsigned int irq;
 180
 181         /* vop AHP clk */
 182         struct clk *hclk;
 183         /* vop dclk */
 184         struct clk *dclk;
 185         /* vop share memory frequency */
 186         struct clk *aclk;
 187
 188         /* vop dclk reset */
 189         struct reset_control *dclk_rst;
 190
 191         struct vop_win win[];
 192 };
 193
 194 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 195 {
 196         writel(v, vop->regs + offset);
 197         vop->regsbak[offset >> 2] = v;
 198 }
 199
 200 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 201 {
 202         return readl(vop->regs + offset);
 203 }
 204
 205 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 206                                     const struct vop_reg *reg)
 207 {
 208         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 209 }
 210
 211 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 212                                   uint32_t mask, uint32_t shift, uint32_t v,
 213                                   bool write_mask, bool relaxed)
 214 {
 215         if (!mask)
 216                 return;
 217
 218         if (write_mask) {
 219                 v = ((v & mask) << shift) | (mask << (shift + 16));
 220         } else {
 221                 uint32_t cached_val = vop->regsbak[offset >> 2];
 222
 223                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 224                 vop->regsbak[offset >> 2] = v;
 225         }
 226
 227         if (relaxed)
 228                 writel_relaxed(v, vop->regs + offset);
 229         else
 230                 writel(v, vop->regs + offset);
 231 }
 232
 233 static inline const struct vop_win_phy *
 234 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 235 {
 236         if (!reg->mask && win->parent)
 237                 return win->parent->phy;
 238
 239         return win->phy;
 240 }
 241
 242 static inline uint32_t vop_get_intr_type(struct vop *vop,
 243                                          const struct vop_reg *reg, int type)
 244 {
 245         uint32_t i, ret = 0;
 246         uint32_t regs = vop_read_reg(vop, 0, reg);
 247
 248         for (i = 0; i < vop->data->intr->nintrs; i++) {
 249                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 250                         ret |= vop->data->intr->intrs[i];
 251         }
 252
 253         return ret;
 254 }
 255
 256 static inline void vop_cfg_done(struct vop *vop)
 257 {
 258         VOP_CTRL_SET(vop, cfg_done, 1);
 259 }
 260
 261 static bool has_rb_swapped(uint32_t format)
 262 {
 263         switch (format) {
 264         case DRM_FORMAT_XBGR8888:
 265         case DRM_FORMAT_ABGR8888:
 266         case DRM_FORMAT_BGR888:
 267         case DRM_FORMAT_BGR565:
 268                 return true;
 269         default:
 270                 return false;
 271         }
 272 }
 273
 274 static enum vop_data_format vop_convert_format(uint32_t format)
 275 {
 276         switch (format) {
 277         case DRM_FORMAT_XRGB8888:
 278         case DRM_FORMAT_ARGB8888:
 279         case DRM_FORMAT_XBGR8888:
 280         case DRM_FORMAT_ABGR8888:
 281                 return VOP_FMT_ARGB8888;
 282         case DRM_FORMAT_RGB888:
 283         case DRM_FORMAT_BGR888:
 284                 return VOP_FMT_RGB888;
 285         case DRM_FORMAT_RGB565:
 286         case DRM_FORMAT_BGR565:
 287                 return VOP_FMT_RGB565;
 288         case DRM_FORMAT_NV12:
 289                 return VOP_FMT_YUV420SP;
 290         case DRM_FORMAT_NV16:
 291                 return VOP_FMT_YUV422SP;
 292         case DRM_FORMAT_NV24:
 293                 return VOP_FMT_YUV444SP;
 294         default:
 295                 DRM_ERROR("unsupport format[%08x]\n", format);
 296                 return -EINVAL;
 297         }
 298 }
 299
 300 static bool is_yuv_support(uint32_t format)
 301 {
 302         switch (format) {
 303         case DRM_FORMAT_NV12:
 304         case DRM_FORMAT_NV16:
 305         case DRM_FORMAT_NV24:
 306                 return true;
 307         default:
 308                 return false;
 309         }
 310 }
 311
 312 static bool is_alpha_support(uint32_t format)
 313 {
 314         switch (format) {
 315         case DRM_FORMAT_ARGB8888:
 316         case DRM_FORMAT_ABGR8888:
 317                 return true;
 318         default:
 319                 return false;
 320         }
 321 }
 322
 323 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 324                                   uint32_t dst, bool is_horizontal,
 325                                   int vsu_mode, int *vskiplines)
 326 {
 327         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 328
 329         if (is_horizontal) {
 330                 if (mode == SCALE_UP)
 331                         val = GET_SCL_FT_BIC(src, dst);
 332                 else if (mode == SCALE_DOWN)
 333                         val = GET_SCL_FT_BILI_DN(src, dst);
 334         } else {
 335                 if (mode == SCALE_UP) {
 336                         if (vsu_mode == SCALE_UP_BIL)
 337                                 val = GET_SCL_FT_BILI_UP(src, dst);
 338                         else
 339                                 val = GET_SCL_FT_BIC(src, dst);
 340                 } else if (mode == SCALE_DOWN) {
 341                         if (vskiplines) {
 342                                 *vskiplines = scl_get_vskiplines(src, dst);
 343                                 val = scl_get_bili_dn_vskip(src, dst,
 344                                                             *vskiplines);
 345                         } else {
 346                                 val = GET_SCL_FT_BILI_DN(src, dst);
 347                         }
 348                 }
 349         }
 350
 351         return val;
 352 }
 353
 354 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 355                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 356                                 uint32_t dst_h, uint32_t pixel_format)
 357 {
 358         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 359         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 360         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 361         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 362         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 363         bool is_yuv = is_yuv_support(pixel_format);
 364         uint16_t cbcr_src_w = src_w / hsub;
 365         uint16_t cbcr_src_h = src_h / vsub;
 366         uint16_t vsu_mode;
 367         uint16_t lb_mode;
 368         uint32_t val;
 369         int vskiplines = 0;
 370
 371         if (!win->phy->scl)
 372                 return;
 373
 374         if (dst_w > 3840) {
 375                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 376                 return;
 377         }
 378
 379         if (!win->phy->scl->ext) {
 380                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 381                             scl_cal_scale2(src_w, dst_w));
 382                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 383                             scl_cal_scale2(src_h, dst_h));
 384                 if (is_yuv) {
 385                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 386                                     scl_cal_scale2(cbcr_src_w, dst_w));
 387                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 388                                     scl_cal_scale2(cbcr_src_h, dst_h));
 389                 }
 390                 return;
 391         }
 392
 393         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 394         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 395
 396         if (is_yuv) {
 397                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 398                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 399                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 400                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 401                 else
 402                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 403         } else {
 404                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 405                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 406                 else
 407                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 408         }
 409
 410         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 411         if (lb_mode == LB_RGB_3840X2) {
 412                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 413                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 414                         return;
 415                 }
 416                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 417                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 418                         return;
 419                 }
 420                 vsu_mode = SCALE_UP_BIL;
 421         } else if (lb_mode == LB_RGB_2560X4) {
 422                 vsu_mode = SCALE_UP_BIL;
 423         } else {
 424                 vsu_mode = SCALE_UP_BIC;
 425         }
 426
 427         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 428                                 true, 0, NULL);
 429         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 430         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 431                                 false, vsu_mode, &vskiplines);
 432         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 433
 434         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 435         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 436
 437         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 438         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 439         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 440         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 441         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 442         if (is_yuv) {
 443                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 444                                         dst_w, true, 0, NULL);
 445                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 446                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 447                                         dst_h, false, vsu_mode, &vskiplines);
 448                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 449
 450                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 451                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 452                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 453                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 454                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 455                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 456                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 457         }
 458 }
 459
 460 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 461 {
 462         unsigned long flags;
 463
 464         if (WARN_ON(!vop->is_enabled))
 465                 return;
 466
 467         spin_lock_irqsave(&vop->irq_lock, flags);
 468
 469         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 470
 471         spin_unlock_irqrestore(&vop->irq_lock, flags);
 472 }
 473
 474 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 475 {
 476         unsigned long flags;
 477
 478         if (WARN_ON(!vop->is_enabled))
 479                 return;
 480
 481         spin_lock_irqsave(&vop->irq_lock, flags);
 482
 483         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 484
 485         spin_unlock_irqrestore(&vop->irq_lock, flags);
 486 }
 487
 488 static void vop_enable(struct drm_crtc *crtc)
 489 {
 490         struct vop *vop = to_vop(crtc);
 491         int ret, i;
 492
 493         ret = clk_prepare_enable(vop->hclk);
 494         if (ret < 0) {
 495                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 496                 return;
 497         }
 498
 499         ret = clk_prepare_enable(vop->dclk);
 500         if (ret < 0) {
 501                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 502                 goto err_disable_hclk;
 503         }
 504
 505         ret = clk_prepare_enable(vop->aclk);
 506         if (ret < 0) {
 507                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 508                 goto err_disable_dclk;
 509         }
 510
 511         ret = pm_runtime_get_sync(vop->dev);
 512         if (ret < 0) {
 513                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 514                 return;
 515         }
 516
 517         /*
 518          * Slave iommu shares power, irq and clock with vop.  It was associated
 519          * automatically with this master device via common driver code.
 520          * Now that we have enabled the clock we attach it to the shared drm
 521          * mapping.
 522          */
 523         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 524         if (ret) {
 525                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 526                 goto err_disable_aclk;
 527         }
 528
 529         memcpy(vop->regsbak, vop->regs, vop->len);
 530
 531         VOP_CTRL_SET(vop, global_regdone_en, 1);
 532
 533         for (i = 0; i < vop->num_wins; i++) {
 534                 struct vop_win *win = &vop->win[i];
 535
 536                 VOP_WIN_SET(vop, win, gate, 1);
 537         }
 538
 539         /*
 540          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 541          */
 542         vop->is_enabled = true;
 543
 544         spin_lock(&vop->reg_lock);
 545
 546         VOP_CTRL_SET(vop, standby, 0);
 547
 548         spin_unlock(&vop->reg_lock);
 549
 550         enable_irq(vop->irq);
 551
 552         drm_crtc_vblank_on(crtc);
 553
 554         return;
 555
 556 err_disable_aclk:
 557         clk_disable_unprepare(vop->aclk);
 558 err_disable_dclk:
 559         clk_disable_unprepare(vop->dclk);
 560 err_disable_hclk:
 561         clk_disable_unprepare(vop->hclk);
 562 }
 563
 564 static void vop_crtc_disable(struct drm_crtc *crtc)
 565 {
 566         struct vop *vop = to_vop(crtc);
 567         int i;
 568
 569         /*
 570          * We need to make sure that all windows are disabled before we
 571          * disable that crtc. Otherwise we might try to scan from a destroyed
 572          * buffer later.
 573          */
 574         for (i = 0; i < vop->num_wins; i++) {
 575                 struct vop_win *win = &vop->win[i];
 576
 577                 spin_lock(&vop->reg_lock);
 578                 VOP_WIN_SET(vop, win, enable, 0);
 579                 spin_unlock(&vop->reg_lock);
 580         }
 581         vop_cfg_done(vop);
 582
 583         drm_crtc_vblank_off(crtc);
 584
 585         /*
 586          * Vop standby will take effect at end of current frame,
 587          * if dsp hold valid irq happen, it means standby complete.
 588          *
 589          * we must wait standby complete when we want to disable aclk,
 590          * if not, memory bus maybe dead.
 591          */
 592         reinit_completion(&vop->dsp_hold_completion);
 593         vop_dsp_hold_valid_irq_enable(vop);
 594
 595         spin_lock(&vop->reg_lock);
 596
 597         VOP_CTRL_SET(vop, standby, 1);
 598
 599         spin_unlock(&vop->reg_lock);
 600
 601         wait_for_completion(&vop->dsp_hold_completion);
 602
 603         vop_dsp_hold_valid_irq_disable(vop);
 604
 605         disable_irq(vop->irq);
 606
 607         vop->is_enabled = false;
 608
 609         /*
 610          * vop standby complete, so iommu detach is safe.
 611          */
 612         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 613
 614         pm_runtime_put(vop->dev);
 615         clk_disable_unprepare(vop->dclk);
 616         clk_disable_unprepare(vop->aclk);
 617         clk_disable_unprepare(vop->hclk);
 618 }
 619
 620 static void vop_plane_destroy(struct drm_plane *plane)
 621 {
 622         drm_plane_cleanup(plane);
 623 }
 624
 625 static int vop_plane_prepare_fb(struct drm_plane *plane,
 626                                 const struct drm_plane_state *new_state)
 627 {
 628         if (plane->state->fb)
 629                 drm_framebuffer_reference(plane->state->fb);
 630
 631         return 0;
 632 }
 633
 634 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 635                                  const struct drm_plane_state *old_state)
 636 {
 637         if (old_state->fb)
 638                 drm_framebuffer_unreference(old_state->fb);
 639 }
 640
 641 static int vop_plane_atomic_check(struct drm_plane *plane,
 642                            struct drm_plane_state *state)
 643 {
 644         struct drm_crtc *crtc = state->crtc;
 645         struct drm_framebuffer *fb = state->fb;
 646         struct vop_win *win = to_vop_win(plane);
 647         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 648         struct drm_crtc_state *crtc_state;
 649         bool visible;
 650         int ret;
 651         struct drm_rect *dest = &vop_plane_state->dest;
 652         struct drm_rect *src = &vop_plane_state->src;
 653         struct drm_rect clip;
 654         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 655                                         DRM_PLANE_HELPER_NO_SCALING;
 656         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 657                                         DRM_PLANE_HELPER_NO_SCALING;
 658
 659         crtc = crtc ? crtc : plane->state->crtc;
 660         /*
 661          * Both crtc or plane->state->crtc can be null.
 662          */
 663         if (!crtc || !fb)
 664                 goto out_disable;
 665
 666         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 667         if (IS_ERR(crtc_state))
 668                 return PTR_ERR(crtc_state);
 669
 670         src->x1 = state->src_x;
 671         src->y1 = state->src_y;
 672         src->x2 = state->src_x + state->src_w;
 673         src->y2 = state->src_y + state->src_h;
 674         dest->x1 = state->crtc_x;
 675         dest->y1 = state->crtc_y;
 676         dest->x2 = state->crtc_x + state->crtc_w;
 677         dest->y2 = state->crtc_y + state->crtc_h;
 678
 679         clip.x1 = 0;
 680         clip.y1 = 0;
 681         clip.x2 = crtc_state->mode.hdisplay;
 682         clip.y2 = crtc_state->mode.vdisplay;
 683
 684         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 685                                             src, dest, &clip,
 686                                             min_scale,
 687                                             max_scale,
 688                                             true, true, &visible);
 689         if (ret)
 690                 return ret;
 691
 692         if (!visible)
 693                 goto out_disable;
 694
 695         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 696         if (vop_plane_state->format < 0)
 697                 return vop_plane_state->format;
 698
 699         /*
 700          * Src.x1 can be odd when do clip, but yuv plane start point
 701          * need align with 2 pixel.
 702          */
 703         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 704                 return -EINVAL;
 705
 706         vop_plane_state->enable = true;
 707
 708         return 0;
 709
 710 out_disable:
 711         vop_plane_state->enable = false;
 712         return 0;
 713 }
 714
 715 static void vop_plane_atomic_disable(struct drm_plane *plane,
 716                                      struct drm_plane_state *old_state)
 717 {
 718         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 719         struct vop_win *win = to_vop_win(plane);
 720         struct vop *vop = to_vop(old_state->crtc);
 721
 722         if (!old_state->crtc)
 723                 return;
 724
 725         spin_lock(&vop->reg_lock);
 726
 727         VOP_WIN_SET(vop, win, enable, 0);
 728
 729         spin_unlock(&vop->reg_lock);
 730
 731         vop_plane_state->enable = false;
 732 }
 733
 734 static void vop_plane_atomic_update(struct drm_plane *plane,
 735                 struct drm_plane_state *old_state)
 736 {
 737         struct drm_plane_state *state = plane->state;
 738         struct drm_crtc *crtc = state->crtc;
 739         struct vop_win *win = to_vop_win(plane);
 740         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 741         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 742         struct vop *vop = to_vop(state->crtc);
 743         struct drm_framebuffer *fb = state->fb;
 744         unsigned int actual_w, actual_h;
 745         unsigned int dsp_stx, dsp_sty;
 746         uint32_t act_info, dsp_info, dsp_st;
 747         struct drm_rect *src = &vop_plane_state->src;
 748         struct drm_rect *dest = &vop_plane_state->dest;
 749         struct drm_gem_object *obj, *uv_obj;
 750         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 751         unsigned long offset;
 752         dma_addr_t dma_addr;
 753         int ymirror, xmirror;
 754         uint32_t val;
 755         bool rb_swap;
 756
 757         /*
 758          * can't update plane when vop is disabled.
 759          */
 760         if (!crtc)
 761                 return;
 762
 763         if (WARN_ON(!vop->is_enabled))
 764                 return;
 765
 766         if (!vop_plane_state->enable) {
 767                 vop_plane_atomic_disable(plane, old_state);
 768                 return;
 769         }
 770
 771         obj = rockchip_fb_get_gem_obj(fb, 0);
 772         rk_obj = to_rockchip_obj(obj);
 773
 774         actual_w = drm_rect_width(src) >> 16;
 775         actual_h = drm_rect_height(src) >> 16;
 776         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 777
 778         dsp_info = (drm_rect_height(dest) - 1) << 16;
 779         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 780
 781         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 782         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 783         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 784
 785         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 786         if (state->rotation & BIT(DRM_REFLECT_Y))
 787                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 788         else
 789                 offset += (src->y1 >> 16) * fb->pitches[0];
 790         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 791
 792         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 793         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 794
 795         spin_lock(&vop->reg_lock);
 796
 797         VOP_WIN_SET(vop, win, xmirror, xmirror);
 798         VOP_WIN_SET(vop, win, ymirror, ymirror);
 799         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 800         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 801         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 802         if (is_yuv_support(fb->pixel_format)) {
 803                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 804                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 805                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 806
 807                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 808                 rk_uv_obj = to_rockchip_obj(uv_obj);
 809
 810                 offset = (src->x1 >> 16) * bpp / hsub;
 811                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 812
 813                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 814                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 815                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 816         }
 817
 818         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 819                             drm_rect_width(dest), drm_rect_height(dest),
 820                             fb->pixel_format);
 821
 822         VOP_WIN_SET(vop, win, act_info, act_info);
 823         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 824         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 825
 826         rb_swap = has_rb_swapped(fb->pixel_format);
 827         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 828
 829         if (is_alpha_support(fb->pixel_format) &&
 830             (s->dsp_layer_sel & 0x3) != win->win_id) {
 831                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 832                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 833                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 834                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 835                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 836                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 837                         SRC_FACTOR_M0(ALPHA_ONE);
 838                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 839                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 840                 VOP_WIN_SET(vop, win, alpha_en, 1);
 841         } else {
 842                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 843                 VOP_WIN_SET(vop, win, alpha_en, 0);
 844         }
 845
 846         VOP_WIN_SET(vop, win, enable, 1);
 847         spin_unlock(&vop->reg_lock);
 848 }
 849
 850 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 851         .prepare_fb = vop_plane_prepare_fb,
 852         .cleanup_fb = vop_plane_cleanup_fb,
 853         .atomic_check = vop_plane_atomic_check,
 854         .atomic_update = vop_plane_atomic_update,
 855         .atomic_disable = vop_plane_atomic_disable,
 856 };
 857
 858 void vop_atomic_plane_reset(struct drm_plane *plane)
 859 {
 860         struct vop_win *win = to_vop_win(plane);
 861         struct vop_plane_state *vop_plane_state =
 862                                         to_vop_plane_state(plane->state);
 863
 864         if (plane->state && plane->state->fb)
 865                 drm_framebuffer_unreference(plane->state->fb);
 866
 867         kfree(vop_plane_state);
 868         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 869         if (!vop_plane_state)
 870                 return;
 871
 872         vop_plane_state->zpos = win->win_id;
 873         plane->state = &vop_plane_state->base;
 874         plane->state->plane = plane;
 875 }
 876
 877 struct drm_plane_state *
 878 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 879 {
 880         struct vop_plane_state *old_vop_plane_state;
 881         struct vop_plane_state *vop_plane_state;
 882
 883         if (WARN_ON(!plane->state))
 884                 return NULL;
 885
 886         old_vop_plane_state = to_vop_plane_state(plane->state);
 887         vop_plane_state = kmemdup(old_vop_plane_state,
 888                                   sizeof(*vop_plane_state), GFP_KERNEL);
 889         if (!vop_plane_state)
 890                 return NULL;
 891
 892         __drm_atomic_helper_plane_duplicate_state(plane,
 893                                                   &vop_plane_state->base);
 894
 895         return &vop_plane_state->base;
 896 }
 897
 898 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 899                                            struct drm_plane_state *state)
 900 {
 901         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 902
 903         __drm_atomic_helper_plane_destroy_state(plane, state);
 904
 905         kfree(vop_state);
 906 }
 907
 908 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 909                                          struct drm_plane_state *state,
 910                                          struct drm_property *property,
 911                                          uint64_t val)
 912 {
 913         struct vop_win *win = to_vop_win(plane);
 914         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 915
 916         if (property == win->vop->plane_zpos_prop) {
 917                 plane_state->zpos = val;
 918                 return 0;
 919         }
 920
 921         if (property == win->rotation_prop) {
 922                 state->rotation = val;
 923                 return 0;
 924         }
 925
 926         DRM_ERROR("failed to set vop plane property\n");
 927         return -EINVAL;
 928 }
 929
 930 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 931                                          const struct drm_plane_state *state,
 932                                          struct drm_property *property,
 933                                          uint64_t *val)
 934 {
 935         struct vop_win *win = to_vop_win(plane);
 936         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 937
 938         if (property == win->vop->plane_zpos_prop) {
 939                 *val = plane_state->zpos;
 940                 return 0;
 941         }
 942
 943         if (property == win->rotation_prop) {
 944                 *val = state->rotation;
 945                 return 0;
 946         }
 947
 948         DRM_ERROR("failed to get vop plane property\n");
 949         return -EINVAL;
 950 }
 951
 952 static const struct drm_plane_funcs vop_plane_funcs = {
 953         .update_plane   = drm_atomic_helper_update_plane,
 954         .disable_plane  = drm_atomic_helper_disable_plane,
 955         .destroy = vop_plane_destroy,
 956         .reset = vop_atomic_plane_reset,
 957         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 958         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 959         .atomic_set_property = vop_atomic_plane_set_property,
 960         .atomic_get_property = vop_atomic_plane_get_property,
 961 };
 962
 963 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 964 {
 965         struct vop *vop = to_vop(crtc);
 966         unsigned long flags;
 967
 968         if (WARN_ON(!vop->is_enabled))
 969                 return -EPERM;
 970
 971         spin_lock_irqsave(&vop->irq_lock, flags);
 972
 973         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 974
 975         spin_unlock_irqrestore(&vop->irq_lock, flags);
 976
 977         return 0;
 978 }
 979
 980 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 981 {
 982         struct vop *vop = to_vop(crtc);
 983         unsigned long flags;
 984
 985         if (WARN_ON(!vop->is_enabled))
 986                 return;
 987
 988         spin_lock_irqsave(&vop->irq_lock, flags);
 989
 990         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 991
 992         spin_unlock_irqrestore(&vop->irq_lock, flags);
 993 }
 994
 995 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 996 {
 997         struct vop *vop = to_vop(crtc);
 998
 999         reinit_completion(&vop->wait_update_complete);
1000         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1001 }
1002
1003 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1004                                            struct drm_file *file_priv)
1005 {
1006         struct drm_device *drm = crtc->dev;
1007         struct vop *vop = to_vop(crtc);
1008         struct drm_pending_vblank_event *e;
1009         unsigned long flags;
1010
1011         spin_lock_irqsave(&drm->event_lock, flags);
1012         e = vop->event;
1013         if (e && e->base.file_priv == file_priv) {
1014                 vop->event = NULL;
1015
1016                 e->base.destroy(&e->base);
1017                 file_priv->event_space += sizeof(e->event);
1018         }
1019         spin_unlock_irqrestore(&drm->event_lock, flags);
1020 }
1021
1022 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1023         .enable_vblank = vop_crtc_enable_vblank,
1024         .disable_vblank = vop_crtc_disable_vblank,
1025         .wait_for_update = vop_crtc_wait_for_update,
1026         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1027 };
1028
1029 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1030                                 const struct drm_display_mode *mode,
1031                                 struct drm_display_mode *adjusted_mode)
1032 {
1033         struct vop *vop = to_vop(crtc);
1034
1035         adjusted_mode->clock =
1036                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1037
1038         return true;
1039 }
1040
1041 static void vop_crtc_enable(struct drm_crtc *crtc)
1042 {
1043         struct vop *vop = to_vop(crtc);
1044         const struct vop_data *vop_data = vop->data;
1045         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1046         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1047         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1048         u16 hdisplay = adjusted_mode->hdisplay;
1049         u16 htotal = adjusted_mode->htotal;
1050         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1051         u16 hact_end = hact_st + hdisplay;
1052         u16 vdisplay = adjusted_mode->vdisplay;
1053         u16 vtotal = adjusted_mode->vtotal;
1054         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1055         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1056         u16 vact_end = vact_st + vdisplay;
1057         uint32_t val;
1058
1059         vop_enable(crtc);
1060         /*
1061          * If dclk rate is zero, mean that scanout is stop,
1062          * we don't need wait any more.
1063          */
1064         if (clk_get_rate(vop->dclk)) {
1065                 /*
1066                  * Rk3288 vop timing register is immediately, when configure
1067                  * display timing on display time, may cause tearing.
1068                  *
1069                  * Vop standby will take effect at end of current frame,
1070                  * if dsp hold valid irq happen, it means standby complete.
1071                  *
1072                  * mode set:
1073                  *    standby and wait complete --> |----
1074                  *                                  | display time
1075                  *                                  |----
1076                  *                                  |---> dsp hold irq
1077                  *     configure display timing --> |
1078                  *         standby exit             |
1079                  *                                  | new frame start.
1080                  */
1081
1082                 reinit_completion(&vop->dsp_hold_completion);
1083                 vop_dsp_hold_valid_irq_enable(vop);
1084
1085                 spin_lock(&vop->reg_lock);
1086
1087                 VOP_CTRL_SET(vop, standby, 1);
1088
1089                 spin_unlock(&vop->reg_lock);
1090
1091                 wait_for_completion(&vop->dsp_hold_completion);
1092
1093                 vop_dsp_hold_valid_irq_disable(vop);
1094         }
1095
1096         val = 0x8;
1097         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1098         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1099         VOP_CTRL_SET(vop, pin_pol, val);
1100         switch (s->output_type) {
1101         case DRM_MODE_CONNECTOR_LVDS:
1102                 VOP_CTRL_SET(vop, rgb_en, 1);
1103                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1104                 break;
1105         case DRM_MODE_CONNECTOR_eDP:
1106                 VOP_CTRL_SET(vop, edp_en, 1);
1107                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1108                 break;
1109         case DRM_MODE_CONNECTOR_HDMIA:
1110                 VOP_CTRL_SET(vop, hdmi_en, 1);
1111                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1112                 break;
1113         case DRM_MODE_CONNECTOR_DSI:
1114                 VOP_CTRL_SET(vop, mipi_en, 1);
1115                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1116                 break;
1117         default:
1118                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1119         }
1120
1121         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1122             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1123                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1124
1125         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1126
1127         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1128         val = hact_st << 16;
1129         val |= hact_end;
1130         VOP_CTRL_SET(vop, hact_st_end, val);
1131         VOP_CTRL_SET(vop, hpost_st_end, val);
1132
1133         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1134         val = vact_st << 16;
1135         val |= vact_end;
1136         VOP_CTRL_SET(vop, vact_st_end, val);
1137         VOP_CTRL_SET(vop, vpost_st_end, val);
1138
1139         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1140
1141         VOP_CTRL_SET(vop, standby, 0);
1142 }
1143
1144 static int vop_zpos_cmp(const void *a, const void *b)
1145 {
1146         struct vop_zpos *pa = (struct vop_zpos *)a;
1147         struct vop_zpos *pb = (struct vop_zpos *)b;
1148
1149         return pa->zpos - pb->zpos;
1150 }
1151
1152 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1153                                  struct drm_crtc_state *crtc_state)
1154 {
1155         struct drm_atomic_state *state = crtc_state->state;
1156         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1157         struct vop *vop = to_vop(crtc);
1158         const struct vop_data *vop_data = vop->data;
1159         struct drm_plane *plane;
1160         struct drm_plane_state *pstate;
1161         struct vop_plane_state *plane_state;
1162         struct vop_zpos *pzpos;
1163         int dsp_layer_sel = 0;
1164         int i, j, cnt = 0, ret = 0;
1165
1166         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1167         if (!pzpos)
1168                 return -ENOMEM;
1169
1170         for (i = 0; i < vop_data->win_size; i++) {
1171                 const struct vop_win_data *win_data = &vop_data->win[i];
1172                 struct vop_win *win;
1173
1174                 if (!win_data->phy)
1175                         continue;
1176
1177                 for (j = 0; j < vop->num_wins; j++) {
1178                         win = &vop->win[j];
1179
1180                         if (win->win_id == i && !win->area_id)
1181                                 break;
1182                 }
1183                 if (WARN_ON(j >= vop->num_wins)) {
1184                         ret = -EINVAL;
1185                         goto err_free_pzpos;
1186                 }
1187
1188                 plane = &win->base;
1189                 pstate = state->plane_states[drm_plane_index(plane)];
1190                 /*
1191                  * plane might not have changed, in which case take
1192                  * current state:
1193                  */
1194                 if (!pstate)
1195                         pstate = plane->state;
1196                 plane_state = to_vop_plane_state(pstate);
1197                 pzpos[cnt].zpos = plane_state->zpos;
1198                 pzpos[cnt++].win_id = win->win_id;
1199         }
1200
1201         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1202
1203         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1204                 const struct vop_win_data *win_data = &vop_data->win[i];
1205                 int shift = i * 2;
1206
1207                 if (win_data->phy) {
1208                         struct vop_zpos *zpos = &pzpos[cnt++];
1209
1210                         dsp_layer_sel |= zpos->win_id << shift;
1211                 } else {
1212                         dsp_layer_sel |= i << shift;
1213                 }
1214         }
1215
1216         s->dsp_layer_sel = dsp_layer_sel;
1217
1218 err_free_pzpos:
1219         kfree(pzpos);
1220         return ret;
1221 }
1222
1223 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1224                                   struct drm_crtc_state *old_crtc_state)
1225 {
1226         struct rockchip_crtc_state *s =
1227                         to_rockchip_crtc_state(crtc->state);
1228         struct vop *vop = to_vop(crtc);
1229
1230         if (WARN_ON(!vop->is_enabled))
1231                 return;
1232
1233         spin_lock(&vop->reg_lock);
1234
1235         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1236         vop_cfg_done(vop);
1237
1238         spin_unlock(&vop->reg_lock);
1239 }
1240
1241 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1242                                   struct drm_crtc_state *old_crtc_state)
1243 {
1244         struct vop *vop = to_vop(crtc);
1245
1246         if (crtc->state->event) {
1247                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1248
1249                 vop->event = crtc->state->event;
1250                 crtc->state->event = NULL;
1251         }
1252 }
1253
1254 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1255         .enable = vop_crtc_enable,
1256         .disable = vop_crtc_disable,
1257         .mode_fixup = vop_crtc_mode_fixup,
1258         .atomic_check = vop_crtc_atomic_check,
1259         .atomic_flush = vop_crtc_atomic_flush,
1260         .atomic_begin = vop_crtc_atomic_begin,
1261 };
1262
1263 static void vop_crtc_destroy(struct drm_crtc *crtc)
1264 {
1265         drm_crtc_cleanup(crtc);
1266 }
1267
1268 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1269 {
1270         struct rockchip_crtc_state *rockchip_state;
1271
1272         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1273         if (!rockchip_state)
1274                 return NULL;
1275
1276         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1277         return &rockchip_state->base;
1278 }
1279
1280 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1281                                    struct drm_crtc_state *state)
1282 {
1283         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1284
1285         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1286         kfree(s);
1287 }
1288
1289 static const struct drm_crtc_funcs vop_crtc_funcs = {
1290         .set_config = drm_atomic_helper_set_config,
1291         .page_flip = drm_atomic_helper_page_flip,
1292         .destroy = vop_crtc_destroy,
1293         .reset = drm_atomic_helper_crtc_reset,
1294         .atomic_duplicate_state = vop_crtc_duplicate_state,
1295         .atomic_destroy_state = vop_crtc_destroy_state,
1296 };
1297
1298 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1299 {
1300         struct drm_plane *plane = &vop_win->base;
1301         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1302         dma_addr_t yrgb_mst;
1303
1304         if (!state->enable)
1305                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1306
1307         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1308
1309         return yrgb_mst == state->yrgb_mst;
1310 }
1311
1312 static void vop_handle_vblank(struct vop *vop)
1313 {
1314         struct drm_device *drm = vop->drm_dev;
1315         struct drm_crtc *crtc = &vop->crtc;
1316         unsigned long flags;
1317         int i;
1318
1319         for (i = 0; i < vop->num_wins; i++) {
1320                 if (!vop_win_pending_is_complete(&vop->win[i]))
1321                         return;
1322         }
1323
1324         if (vop->event) {
1325                 spin_lock_irqsave(&drm->event_lock, flags);
1326
1327                 drm_crtc_send_vblank_event(crtc, vop->event);
1328                 drm_crtc_vblank_put(crtc);
1329                 vop->event = NULL;
1330
1331                 spin_unlock_irqrestore(&drm->event_lock, flags);
1332         }
1333         if (!completion_done(&vop->wait_update_complete))
1334                 complete(&vop->wait_update_complete);
1335 }
1336
1337 static irqreturn_t vop_isr(int irq, void *data)
1338 {
1339         struct vop *vop = data;
1340         struct drm_crtc *crtc = &vop->crtc;
1341         uint32_t active_irqs;
1342         unsigned long flags;
1343         int ret = IRQ_NONE;
1344
1345         /*
1346          * interrupt register has interrupt status, enable and clear bits, we
1347          * must hold irq_lock to avoid a race with enable/disable_vblank().
1348         */
1349         spin_lock_irqsave(&vop->irq_lock, flags);
1350
1351         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1352         /* Clear all active interrupt sources */
1353         if (active_irqs)
1354                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1355
1356         spin_unlock_irqrestore(&vop->irq_lock, flags);
1357
1358         /* This is expected for vop iommu irqs, since the irq is shared */
1359         if (!active_irqs)
1360                 return IRQ_NONE;
1361
1362         if (active_irqs & DSP_HOLD_VALID_INTR) {
1363                 complete(&vop->dsp_hold_completion);
1364                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1365                 ret = IRQ_HANDLED;
1366         }
1367
1368         if (active_irqs & FS_INTR) {
1369                 drm_crtc_handle_vblank(crtc);
1370                 vop_handle_vblank(vop);
1371                 active_irqs &= ~FS_INTR;
1372                 ret = IRQ_HANDLED;
1373         }
1374
1375         /* Unhandled irqs are spurious. */
1376         if (active_irqs)
1377                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1378
1379         return ret;
1380 }
1381
1382 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1383                           unsigned long possible_crtcs)
1384 {
1385         struct drm_plane *share = NULL;
1386         unsigned int rotations = 0;
1387         struct drm_property *prop;
1388         int ret;
1389
1390         if (win->parent)
1391                 share = &win->parent->base;
1392
1393         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1394                                    possible_crtcs, &vop_plane_funcs,
1395                                    win->data_formats, win->nformats, win->type);
1396         if (ret) {
1397                 DRM_ERROR("failed to initialize plane\n");
1398                 return ret;
1399         }
1400         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1401         drm_object_attach_property(&win->base.base,
1402                                    vop->plane_zpos_prop, win->win_id);
1403
1404         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1405                 rotations |= BIT(DRM_REFLECT_X);
1406
1407         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1408                 rotations |= BIT(DRM_REFLECT_Y);
1409
1410         if (rotations) {
1411                 rotations |= BIT(DRM_ROTATE_0);
1412                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1413                                                          rotations);
1414                 if (!prop) {
1415                         DRM_ERROR("failed to create zpos property\n");
1416                         return -EINVAL;
1417                 }
1418                 drm_object_attach_property(&win->base.base, prop,
1419                                            BIT(DRM_ROTATE_0));
1420                 win->rotation_prop = prop;
1421         }
1422
1423         return 0;
1424 }
1425
1426 static int vop_create_crtc(struct vop *vop)
1427 {
1428         struct device *dev = vop->dev;
1429         struct drm_device *drm_dev = vop->drm_dev;
1430         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1431         struct drm_crtc *crtc = &vop->crtc;
1432         struct device_node *port;
1433         int ret;
1434         int i;
1435
1436         /*
1437          * Create drm_plane for primary and cursor planes first, since we need
1438          * to pass them to drm_crtc_init_with_planes, which sets the
1439          * "possible_crtcs" to the newly initialized crtc.
1440          */
1441         for (i = 0; i < vop->num_wins; i++) {
1442                 struct vop_win *win = &vop->win[i];
1443
1444                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1445                     win->type != DRM_PLANE_TYPE_CURSOR)
1446                         continue;
1447
1448                 ret = vop_plane_init(vop, win, 0);
1449                 if (ret)
1450                         goto err_cleanup_planes;
1451
1452                 plane = &win->base;
1453                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1454                         primary = plane;
1455                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1456                         cursor = plane;
1457
1458         }
1459
1460         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1461                                         &vop_crtc_funcs, NULL);
1462         if (ret)
1463                 goto err_cleanup_planes;
1464
1465         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1466
1467         /*
1468          * Create drm_planes for overlay windows with possible_crtcs restricted
1469          * to the newly created crtc.
1470          */
1471         for (i = 0; i < vop->num_wins; i++) {
1472                 struct vop_win *win = &vop->win[i];
1473                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1474
1475                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1476                         continue;
1477
1478                 ret = vop_plane_init(vop, win, possible_crtcs);
1479                 if (ret)
1480                         goto err_cleanup_crtc;
1481         }
1482
1483         port = of_get_child_by_name(dev->of_node, "port");
1484         if (!port) {
1485                 DRM_ERROR("no port node found in %s\n",
1486                           dev->of_node->full_name);
1487                 ret = -ENOENT;
1488                 goto err_cleanup_crtc;
1489         }
1490
1491         init_completion(&vop->dsp_hold_completion);
1492         init_completion(&vop->wait_update_complete);
1493         crtc->port = port;
1494         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1495
1496         return 0;
1497
1498 err_cleanup_crtc:
1499         drm_crtc_cleanup(crtc);
1500 err_cleanup_planes:
1501         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1502                                  head)
1503                 drm_plane_cleanup(plane);
1504         return ret;
1505 }
1506
1507 static void vop_destroy_crtc(struct vop *vop)
1508 {
1509         struct drm_crtc *crtc = &vop->crtc;
1510         struct drm_device *drm_dev = vop->drm_dev;
1511         struct drm_plane *plane, *tmp;
1512
1513         rockchip_unregister_crtc_funcs(crtc);
1514         of_node_put(crtc->port);
1515
1516         /*
1517          * We need to cleanup the planes now.  Why?
1518          *
1519          * The planes are "&vop->win[i].base".  That means the memory is
1520          * all part of the big "struct vop" chunk of memory.  That memory
1521          * was devm allocated and associated with this component.  We need to
1522          * free it ourselves before vop_unbind() finishes.
1523          */
1524         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1525                                  head)
1526                 vop_plane_destroy(plane);
1527
1528         /*
1529          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1530          * references the CRTC.
1531          */
1532         drm_crtc_cleanup(crtc);
1533 }
1534
1535 /*
1536  * Initialize the vop->win array elements.
1537  */
1538 static int vop_win_init(struct vop *vop)
1539 {
1540         const struct vop_data *vop_data = vop->data;
1541         unsigned int i, j;
1542         unsigned int num_wins = 0;
1543         struct drm_property *prop;
1544
1545         for (i = 0; i < vop_data->win_size; i++) {
1546                 struct vop_win *vop_win = &vop->win[num_wins];
1547                 const struct vop_win_data *win_data = &vop_data->win[i];
1548
1549                 if (!win_data->phy)
1550                         continue;
1551
1552                 vop_win->phy = win_data->phy;
1553                 vop_win->offset = win_data->base;
1554                 vop_win->type = win_data->type;
1555                 vop_win->data_formats = win_data->phy->data_formats;
1556                 vop_win->nformats = win_data->phy->nformats;
1557                 vop_win->vop = vop;
1558                 vop_win->win_id = i;
1559                 vop_win->area_id = 0;
1560                 num_wins++;
1561
1562                 for (j = 0; j < win_data->area_size; j++) {
1563                         struct vop_win *vop_area = &vop->win[num_wins];
1564                         const struct vop_win_phy *area = win_data->area[j];
1565
1566                         vop_area->parent = vop_win;
1567                         vop_area->offset = vop_win->offset;
1568                         vop_area->phy = area;
1569                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1570                         vop_area->data_formats = vop_win->data_formats;
1571                         vop_area->nformats = vop_win->nformats;
1572                         vop_area->vop = vop;
1573                         vop_area->win_id = i;
1574                         vop_area->area_id = j;
1575                         num_wins++;
1576                 }
1577         }
1578
1579         vop->num_wins = num_wins;
1580
1581         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1582                                          "ZPOS", 0, vop->data->win_size);
1583         if (!prop) {
1584                 DRM_ERROR("failed to create zpos property\n");
1585                 return -EINVAL;
1586         }
1587         vop->plane_zpos_prop = prop;
1588
1589         return 0;
1590 }
1591
1592 static int vop_bind(struct device *dev, struct device *master, void *data)
1593 {
1594         struct platform_device *pdev = to_platform_device(dev);
1595         const struct vop_data *vop_data;
1596         struct drm_device *drm_dev = data;
1597         struct vop *vop;
1598         struct resource *res;
1599         size_t alloc_size;
1600         int ret, irq, i;
1601         int num_wins = 0;
1602
1603         vop_data = of_device_get_match_data(dev);
1604         if (!vop_data)
1605                 return -ENODEV;
1606
1607         for (i = 0; i < vop_data->win_size; i++) {
1608                 const struct vop_win_data *win_data = &vop_data->win[i];
1609
1610                 num_wins += win_data->area_size + 1;
1611         }
1612
1613         /* Allocate vop struct and its vop_win array */
1614         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1615         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1616         if (!vop)
1617                 return -ENOMEM;
1618
1619         vop->dev = dev;
1620         vop->data = vop_data;
1621         vop->drm_dev = drm_dev;
1622         vop->num_wins = num_wins;
1623         dev_set_drvdata(dev, vop);
1624
1625         ret = vop_win_init(vop);
1626         if (ret)
1627                 return ret;
1628
1629         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1630         vop->len = resource_size(res);
1631         vop->regs = devm_ioremap_resource(dev, res);
1632         if (IS_ERR(vop->regs))
1633                 return PTR_ERR(vop->regs);
1634
1635         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1636         if (!vop->regsbak)
1637                 return -ENOMEM;
1638
1639         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1640         if (IS_ERR(vop->hclk)) {
1641                 dev_err(vop->dev, "failed to get hclk source\n");
1642                 return PTR_ERR(vop->hclk);
1643         }
1644         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1645         if (IS_ERR(vop->aclk)) {
1646                 dev_err(vop->dev, "failed to get aclk source\n");
1647                 return PTR_ERR(vop->aclk);
1648         }
1649         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1650         if (IS_ERR(vop->dclk)) {
1651                 dev_err(vop->dev, "failed to get dclk source\n");
1652                 return PTR_ERR(vop->dclk);
1653         }
1654
1655         irq = platform_get_irq(pdev, 0);
1656         if (irq < 0) {
1657                 dev_err(dev, "cannot find irq for vop\n");
1658                 return irq;
1659         }
1660         vop->irq = (unsigned int)irq;
1661
1662         spin_lock_init(&vop->reg_lock);
1663         spin_lock_init(&vop->irq_lock);
1664
1665         mutex_init(&vop->vsync_mutex);
1666
1667         ret = devm_request_irq(dev, vop->irq, vop_isr,
1668                                IRQF_SHARED, dev_name(dev), vop);
1669         if (ret)
1670                 return ret;
1671
1672         /* IRQ is initially disabled; it gets enabled in power_on */
1673         disable_irq(vop->irq);
1674
1675         ret = vop_create_crtc(vop);
1676         if (ret)
1677                 return ret;
1678
1679         pm_runtime_enable(&pdev->dev);
1680         return 0;
1681 }
1682
1683 static void vop_unbind(struct device *dev, struct device *master, void *data)
1684 {
1685         struct vop *vop = dev_get_drvdata(dev);
1686
1687         pm_runtime_disable(dev);
1688         vop_destroy_crtc(vop);
1689 }
1690
1691 const struct component_ops vop_component_ops = {
1692         .bind = vop_bind,
1693         .unbind = vop_unbind,
1694 };
1695 EXPORT_SYMBOL_GPL(vop_component_ops);