2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/pm_runtime.h>
17 #include <drm/drm_of.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_edid.h>
21 #include <drm/drm_encoder_slave.h>
22 #include <drm/bridge/dw_hdmi.h>
24 #include "rockchip_drm_drv.h"
25 #include "rockchip_drm_vop.h"
27 #define RK3288_GRF_SOC_CON6 0x025C
28 #define RK3288_HDMI_LCDC_SEL BIT(4)
29 #define RK3399_GRF_SOC_CON20 0x6250
30 #define RK3399_HDMI_LCDC_SEL BIT(6)
32 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
34 struct rockchip_hdmi {
36 struct regmap *regmap;
37 struct drm_encoder encoder;
38 enum dw_hdmi_devtype dev_type;
43 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
46 * There are some rates that would be ranged for better clock jitter at
47 * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
48 * to the clock is aglined to KHz in struct drm_display_mode, this would
49 * bring some inaccurate error if we still run the compute_n math, so
50 * let's just code an const table for it until we can actually get the
53 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
54 /* 25176471 for 25.175 MHz = 428000000 / 17. */
55 { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
56 /* 57290323 for 57.284 MHz */
57 { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
58 /* 74437500 for 74.44 MHz = 297750000 / 4 */
59 { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
60 /* 118666667 for 118.68 MHz */
61 { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
62 /* 121714286 for 121.75 MHz */
63 { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
64 /* 136800000 for 136.75 MHz */
65 { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
67 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
70 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
158 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
159 /* pixelclk bpp8 bpp10 bpp12 */
161 600000000, { 0x0000, 0x0000, 0x0000 },
163 ~0UL, { 0x0000, 0x0000, 0x0000},
167 static struct dw_hdmi_phy_config rockchip_phy_config[] = {
168 /*pixelclk symbol term vlev*/
169 { 74250000, 0x8009, 0x0004, 0x0272},
170 { 165000000, 0x802b, 0x0004, 0x0209},
171 { 297000000, 0x8039, 0x0005, 0x028d},
172 { 594000000, 0x8039, 0x0000, 0x019d},
173 { ~0UL, 0x0000, 0x0000, 0x0000}
176 static int rockchip_hdmi_update_phy_table(struct rockchip_hdmi *hdmi,
182 if (phy_table_size > ARRAY_SIZE(rockchip_phy_config)) {
183 dev_err(hdmi->dev, "phy table array number is out of range\n");
187 for (i = 0; i < phy_table_size; i++) {
188 if (config[i * 4] != 0)
189 rockchip_phy_config[i].mpixelclock = (u64)config[i * 4];
191 rockchip_phy_config[i].mpixelclock = ~0UL;
192 rockchip_phy_config[i].term = (u16)config[i * 4 + 1];
193 rockchip_phy_config[i].sym_ctr = (u16)config[i * 4 + 2];
194 rockchip_phy_config[i].vlev_ctr = (u16)config[i * 4 + 3];
200 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
202 struct device_node *np = hdmi->dev->of_node;
203 int ret, val, phy_table_size;
206 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
207 if (IS_ERR(hdmi->regmap)) {
208 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
209 return PTR_ERR(hdmi->regmap);
212 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
213 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
214 hdmi->vpll_clk = NULL;
215 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
216 return -EPROBE_DEFER;
217 } else if (IS_ERR(hdmi->vpll_clk)) {
218 dev_err(hdmi->dev, "failed to get grf clock\n");
219 return PTR_ERR(hdmi->vpll_clk);
222 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
223 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
224 hdmi->grf_clk = NULL;
225 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
226 return -EPROBE_DEFER;
227 } else if (IS_ERR(hdmi->grf_clk)) {
228 dev_err(hdmi->dev, "failed to get grf clock\n");
229 return PTR_ERR(hdmi->grf_clk);
232 ret = clk_prepare_enable(hdmi->vpll_clk);
234 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
238 if (of_get_property(np, "rockchip,phy-table", &val)) {
239 phy_config = kmalloc(val, GFP_KERNEL);
241 /* use default table when kmalloc failed. */
242 dev_err(hdmi->dev, "kmalloc phy table failed\n");
246 phy_table_size = val / 16;
247 of_property_read_u32_array(np, "rockchip,phy_table",
248 phy_config, val / sizeof(u32));
249 ret = rockchip_hdmi_update_phy_table(hdmi, phy_config,
257 dev_dbg(hdmi->dev, "use default hdmi phy table\n");
263 static enum drm_mode_status
264 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
265 struct drm_display_mode *mode)
267 struct drm_encoder *encoder = connector->encoder;
268 enum drm_mode_status status = MODE_OK;
269 struct drm_device *dev = connector->dev;
270 struct rockchip_drm_private *priv = dev->dev_private;
271 struct drm_crtc *crtc;
274 * Pixel clocks we support are always < 2GHz and so fit in an
275 * int. We should make sure source rate does too so we don't get
276 * overflow when we multiply by 1000.
278 if (mode->clock > INT_MAX / 1000)
282 const struct drm_connector_helper_funcs *funcs;
284 funcs = connector->helper_private;
285 if (funcs->atomic_best_encoder)
286 encoder = funcs->atomic_best_encoder(connector,
289 encoder = funcs->best_encoder(connector);
292 if (!encoder || !encoder->possible_crtcs)
295 * ensure all drm display mode can work, if someone want support more
296 * resolutions, please limit the possible_crtc, only connect to
299 drm_for_each_crtc(crtc, connector->dev) {
300 int pipe = drm_crtc_index(crtc);
301 const struct rockchip_crtc_funcs *funcs =
302 priv->crtc_funcs[pipe];
304 if (!(encoder->possible_crtcs & drm_crtc_mask(crtc)))
306 if (!funcs || !funcs->mode_valid)
309 status = funcs->mode_valid(crtc, mode,
310 DRM_MODE_CONNECTOR_HDMIA);
311 if (status != MODE_OK)
318 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
319 .destroy = drm_encoder_cleanup,
322 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
326 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
328 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
329 struct drm_crtc *crtc = encoder->crtc;
330 u32 lcdsel_grf_reg, lcdsel_mask;
335 if (WARN_ON(!crtc || !crtc->state))
338 clk_set_rate(hdmi->vpll_clk,
339 crtc->state->adjusted_mode.crtc_clock * 1000);
341 switch (hdmi->dev_type) {
343 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
344 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
347 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
348 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
354 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
356 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
358 val = HIWORD_UPDATE(0, lcdsel_mask);
360 ret = clk_prepare_enable(hdmi->grf_clk);
362 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
366 regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
367 dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
368 (mux) ? "LIT" : "BIG");
370 clk_disable_unprepare(hdmi->grf_clk);
374 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
375 struct drm_crtc_state *crtc_state,
376 struct drm_connector_state *conn_state)
378 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
380 if (crtc_state->mode.flags & DRM_MODE_FLAG_420_MASK) {
381 s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
382 s->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
384 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
385 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
387 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
392 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
393 .enable = dw_hdmi_rockchip_encoder_enable,
394 .disable = dw_hdmi_rockchip_encoder_disable,
395 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
398 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
399 .mode_valid = dw_hdmi_rockchip_mode_valid,
400 .mpll_cfg = rockchip_mpll_cfg,
401 .cur_ctr = rockchip_cur_ctr,
402 .phy_config = rockchip_phy_config,
403 .dev_type = RK3288_HDMI,
404 .tmds_n_table = rockchip_werid_tmds_n_table,
407 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
408 .mode_valid = dw_hdmi_rockchip_mode_valid,
409 .mpll_cfg = rockchip_mpll_cfg,
410 .cur_ctr = rockchip_cur_ctr,
411 .phy_config = rockchip_phy_config,
412 .dev_type = RK3399_HDMI,
415 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
416 { .compatible = "rockchip,rk3288-dw-hdmi",
417 .data = &rk3288_hdmi_drv_data
419 { .compatible = "rockchip,rk3399-dw-hdmi",
420 .data = &rk3399_hdmi_drv_data
424 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
426 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
429 struct platform_device *pdev = to_platform_device(dev);
430 const struct dw_hdmi_plat_data *plat_data;
431 const struct of_device_id *match;
432 struct drm_device *drm = data;
433 struct drm_encoder *encoder;
434 struct rockchip_hdmi *hdmi;
435 struct resource *iores;
439 if (!pdev->dev.of_node)
442 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
446 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
447 plat_data = match->data;
448 hdmi->dev = &pdev->dev;
449 hdmi->dev_type = plat_data->dev_type;
450 encoder = &hdmi->encoder;
452 irq = platform_get_irq(pdev, 0);
456 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
460 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
462 * If we failed to find the CRTC(s) which this encoder is
463 * supposed to be connected to, it's because the CRTC has
464 * not been registered yet. Defer probing, and hope that
465 * the required CRTC is added later.
467 if (encoder->possible_crtcs == 0)
468 return -EPROBE_DEFER;
470 ret = rockchip_hdmi_parse_dt(hdmi);
472 dev_err(hdmi->dev, "Unable to parse OF data\n");
476 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
477 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
478 DRM_MODE_ENCODER_TMDS, NULL);
480 ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
483 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
484 * which would have called the encoder cleanup. Do it manually.
487 drm_encoder_cleanup(encoder);
492 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
495 return dw_hdmi_unbind(dev, master, data);
498 static const struct component_ops dw_hdmi_rockchip_ops = {
499 .bind = dw_hdmi_rockchip_bind,
500 .unbind = dw_hdmi_rockchip_unbind,
503 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
505 pm_runtime_enable(&pdev->dev);
506 pm_runtime_get_sync(&pdev->dev);
508 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
511 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
513 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
514 pm_runtime_disable(&pdev->dev);
519 static int dw_hdmi_rockchip_suspend(struct device *dev)
521 dw_hdmi_suspend(dev);
522 pm_runtime_put_sync(dev);
527 static int dw_hdmi_rockchip_resume(struct device *dev)
529 pm_runtime_get_sync(dev);
535 static const struct dev_pm_ops dw_hdmi_pm_ops = {
536 SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend,
537 dw_hdmi_rockchip_resume)
540 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
541 .probe = dw_hdmi_rockchip_probe,
542 .remove = dw_hdmi_rockchip_remove,
544 .name = "dwhdmi-rockchip",
545 .of_match_table = dw_hdmi_rockchip_dt_ids,
546 .pm = &dw_hdmi_pm_ops,
550 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
552 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
553 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
554 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
555 MODULE_LICENSE("GPL");
556 MODULE_ALIAS("platform:dwhdmi-rockchip");