drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include <drm/drm_of.h>
  18 #include <drm/drmP.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_edid.h>
  21 #include <drm/drm_encoder_slave.h>
  22 #include <drm/bridge/dw_hdmi.h>
  23
  24 #include "rockchip_drm_drv.h"
  25 #include "rockchip_drm_vop.h"
  26
  27 #define RK3288_GRF_SOC_CON6             0x025C
  28 #define RK3288_HDMI_LCDC_SEL            BIT(4)
  29 #define RK3399_GRF_SOC_CON20            0x6250
  30 #define RK3399_HDMI_LCDC_SEL            BIT(6)
  31
  32 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  33
  34 struct rockchip_hdmi {
  35         struct device *dev;
  36         struct regmap *regmap;
  37         struct drm_encoder encoder;
  38         enum dw_hdmi_devtype dev_type;
  39         struct clk *vpll_clk;
  40         struct clk *grf_clk;
  41 };
  42
  43 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  44
  45 /*
  46  * There are some rates that would be ranged for better clock jitter at
  47  * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
  48  * to the clock is aglined to KHz in struct drm_display_mode, this would
  49  * bring some inaccurate error if we still run the compute_n math, so
  50  * let's just code an const table for it until we can actually get the
  51  * right clock rate.
  52  */
  53 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
  54         /* 25176471 for 25.175 MHz = 428000000 / 17. */
  55         { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
  56         /* 57290323 for 57.284 MHz */
  57         { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
  58         /* 74437500 for 74.44 MHz = 297750000 / 4 */
  59         { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
  60         /* 118666667 for 118.68 MHz */
  61         { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
  62         /* 121714286 for 121.75 MHz */
  63         { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
  64         /* 136800000 for 136.75 MHz */
  65         { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  66         /* End of table */
  67         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
  68 };
  69
  70 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  71         {
  72                 30666000, {
  73                         { 0x00b3, 0x0000 },
  74                         { 0x2153, 0x0000 },
  75                         { 0x40f3, 0x0000 },
  76                 },
  77         },  {
  78                 36800000, {
  79                         { 0x00b3, 0x0000 },
  80                         { 0x2153, 0x0000 },
  81                         { 0x40a2, 0x0001 },
  82                 },
  83         },  {
  84                 46000000, {
  85                         { 0x00b3, 0x0000 },
  86                         { 0x2142, 0x0001 },
  87                         { 0x40a2, 0x0001 },
  88                 },
  89         },  {
  90                 61333000, {
  91                         { 0x0072, 0x0001 },
  92                         { 0x2142, 0x0001 },
  93                         { 0x40a2, 0x0001 },
  94                 },
  95         },  {
  96                 73600000, {
  97                         { 0x0072, 0x0001 },
  98                         { 0x2142, 0x0001 },
  99                         { 0x4061, 0x0002 },
 100                 },
 101         },  {
 102                 92000000, {
 103                         { 0x0072, 0x0001 },
 104                         { 0x2145, 0x0002 },
 105                         { 0x4061, 0x0002 },
 106                 },
 107         },  {
 108                 122666000, {
 109                         { 0x0051, 0x0002 },
 110                         { 0x2145, 0x0002 },
 111                         { 0x4061, 0x0002 },
 112                 },
 113         },  {
 114                 147200000, {
 115                         { 0x0051, 0x0002 },
 116                         { 0x2145, 0x0002 },
 117                         { 0x4064, 0x0003 },
 118                 },
 119         },  {
 120                 184000000, {
 121                         { 0x0051, 0x0002 },
 122                         { 0x214c, 0x0003 },
 123                         { 0x4064, 0x0003 },
 124                 },
 125         },  {
 126                 226666000, {
 127                         { 0x0040, 0x0003 },
 128                         { 0x214c, 0x0003 },
 129                         { 0x4064, 0x0003 },
 130                 },
 131         },  {
 132                 272000000, {
 133                         { 0x0040, 0x0003 },
 134                         { 0x214c, 0x0003 },
 135                         { 0x5a64, 0x0003 },
 136                 },
 137         },  {
 138                 340000000, {
 139                         { 0x0040, 0x0003 },
 140                         { 0x3b4c, 0x0003 },
 141                         { 0x5a64, 0x0003 },
 142                 },
 143         },  {
 144                 600000000, {
 145                         { 0x1a40, 0x0003 },
 146                         { 0x3b4c, 0x0003 },
 147                         { 0x5a64, 0x0003 },
 148                 },
 149         },  {
 150                 ~0UL, {
 151                         { 0x0000, 0x0000 },
 152                         { 0x0000, 0x0000 },
 153                         { 0x0000, 0x0000 },
 154                 },
 155         }
 156 };
 157
 158 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 159         /*      pixelclk    bpp8    bpp10   bpp12 */
 160         {
 161                 600000000, { 0x0000, 0x0000, 0x0000 },
 162         },  {
 163                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 164         }
 165 };
 166
 167 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 168         /*pixelclk   symbol   term   vlev*/
 169         { 74250000,  0x8009, 0x0004, 0x0272},
 170         { 165000000, 0x802b, 0x0004, 0x0209},
 171         { 297000000, 0x8039, 0x0005, 0x028d},
 172         { 594000000, 0x8039, 0x0000, 0x019d},
 173         { ~0UL,      0x0000, 0x0000, 0x0000}
 174 };
 175
 176 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 177 {
 178         struct device_node *np = hdmi->dev->of_node;
 179         int ret;
 180
 181         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 182         if (IS_ERR(hdmi->regmap)) {
 183                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 184                 return PTR_ERR(hdmi->regmap);
 185         }
 186
 187         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
 188         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
 189                 hdmi->vpll_clk = NULL;
 190         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
 191                 return -EPROBE_DEFER;
 192         } else if (IS_ERR(hdmi->vpll_clk)) {
 193                 dev_err(hdmi->dev, "failed to get grf clock\n");
 194                 return PTR_ERR(hdmi->vpll_clk);
 195         }
 196
 197         hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
 198         if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
 199                 hdmi->grf_clk = NULL;
 200         } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
 201                 return -EPROBE_DEFER;
 202         } else if (IS_ERR(hdmi->grf_clk)) {
 203                 dev_err(hdmi->dev, "failed to get grf clock\n");
 204                 return PTR_ERR(hdmi->grf_clk);
 205         }
 206
 207         ret = clk_prepare_enable(hdmi->vpll_clk);
 208         if (ret) {
 209                 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
 210                 return ret;
 211         }
 212
 213         return 0;
 214 }
 215
 216 static enum drm_mode_status
 217 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 218                             struct drm_display_mode *mode)
 219 {
 220         struct drm_encoder *encoder = connector->encoder;
 221         enum drm_mode_status status = MODE_OK;
 222         struct drm_device *dev = connector->dev;
 223         struct rockchip_drm_private *priv = dev->dev_private;
 224         struct drm_crtc *crtc;
 225
 226         /*
 227          * Pixel clocks we support are always < 2GHz and so fit in an
 228          * int.  We should make sure source rate does too so we don't get
 229          * overflow when we multiply by 1000.
 230          */
 231         if (mode->clock > INT_MAX / 1000)
 232                 return MODE_BAD;
 233
 234         if (!encoder) {
 235                 const struct drm_connector_helper_funcs *funcs;
 236
 237                 funcs = connector->helper_private;
 238                 if (funcs->atomic_best_encoder)
 239                         encoder = funcs->atomic_best_encoder(connector,
 240                                                              connector->state);
 241                 else
 242                         encoder = funcs->best_encoder(connector);
 243         }
 244
 245         if (!encoder || !encoder->possible_crtcs)
 246                 return MODE_BAD;
 247         /*
 248          * ensure all drm display mode can work, if someone want support more
 249          * resolutions, please limit the possible_crtc, only connect to
 250          * needed crtc.
 251          */
 252         drm_for_each_crtc(crtc, connector->dev) {
 253                 int pipe = drm_crtc_index(crtc);
 254                 const struct rockchip_crtc_funcs *funcs =
 255                                                 priv->crtc_funcs[pipe];
 256
 257                 if (!(encoder->possible_crtcs & drm_crtc_mask(crtc)))
 258                         continue;
 259                 if (!funcs || !funcs->mode_valid)
 260                         continue;
 261
 262                 status = funcs->mode_valid(crtc, mode,
 263                                            DRM_MODE_CONNECTOR_HDMIA);
 264                 if (status != MODE_OK)
 265                         return status;
 266         }
 267
 268         return status;
 269 }
 270
 271 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 272         .destroy = drm_encoder_cleanup,
 273 };
 274
 275 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 276 {
 277 }
 278
 279 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 280 {
 281         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 282         struct drm_crtc *crtc = encoder->crtc;
 283         u32 lcdsel_grf_reg, lcdsel_mask;
 284         u32 val;
 285         int mux;
 286         int ret;
 287
 288         if (WARN_ON(!crtc || !crtc->state))
 289                 return;
 290
 291         clk_set_rate(hdmi->vpll_clk,
 292                      crtc->state->adjusted_mode.crtc_clock * 1000);
 293
 294         switch (hdmi->dev_type) {
 295         case RK3288_HDMI:
 296                 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
 297                 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
 298                 break;
 299         case RK3399_HDMI:
 300                 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
 301                 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
 302                 break;
 303         default:
 304                 return;
 305         };
 306
 307         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 308         if (mux)
 309                 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
 310         else
 311                 val = HIWORD_UPDATE(0, lcdsel_mask);
 312
 313         ret = clk_prepare_enable(hdmi->grf_clk);
 314         if (ret < 0) {
 315                 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
 316                 return;
 317         }
 318
 319         regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
 320         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 321                 (mux) ? "LIT" : "BIG");
 322
 323         clk_disable_unprepare(hdmi->grf_clk);
 324 }
 325
 326 static int
 327 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 328                                       struct drm_crtc_state *crtc_state,
 329                                       struct drm_connector_state *conn_state)
 330 {
 331         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 332
 333         if (crtc_state->mode.flags & DRM_MODE_FLAG_420_MASK) {
 334                 s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
 335                 s->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
 336         } else {
 337                 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 338                 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 339         }
 340         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 341
 342         return 0;
 343 }
 344
 345 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 346         .enable     = dw_hdmi_rockchip_encoder_enable,
 347         .disable    = dw_hdmi_rockchip_encoder_disable,
 348         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 349 };
 350
 351 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
 352         .mode_valid = dw_hdmi_rockchip_mode_valid,
 353         .mpll_cfg   = rockchip_mpll_cfg,
 354         .cur_ctr    = rockchip_cur_ctr,
 355         .phy_config = rockchip_phy_config,
 356         .dev_type   = RK3288_HDMI,
 357         .tmds_n_table = rockchip_werid_tmds_n_table,
 358 };
 359
 360 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 361         .mode_valid = dw_hdmi_rockchip_mode_valid,
 362         .mpll_cfg   = rockchip_mpll_cfg,
 363         .cur_ctr    = rockchip_cur_ctr,
 364         .phy_config = rockchip_phy_config,
 365         .dev_type   = RK3399_HDMI,
 366 };
 367
 368 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 369         { .compatible = "rockchip,rk3288-dw-hdmi",
 370           .data = &rk3288_hdmi_drv_data
 371         },
 372         { .compatible = "rockchip,rk3399-dw-hdmi",
 373           .data = &rk3399_hdmi_drv_data
 374         },
 375         {},
 376 };
 377 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 378
 379 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 380                                  void *data)
 381 {
 382         struct platform_device *pdev = to_platform_device(dev);
 383         const struct dw_hdmi_plat_data *plat_data;
 384         const struct of_device_id *match;
 385         struct drm_device *drm = data;
 386         struct drm_encoder *encoder;
 387         struct rockchip_hdmi *hdmi;
 388         struct resource *iores;
 389         int irq;
 390         int ret;
 391
 392         if (!pdev->dev.of_node)
 393                 return -ENODEV;
 394
 395         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 396         if (!hdmi)
 397                 return -ENOMEM;
 398
 399         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 400         plat_data = match->data;
 401         hdmi->dev = &pdev->dev;
 402         hdmi->dev_type = plat_data->dev_type;
 403         encoder = &hdmi->encoder;
 404
 405         irq = platform_get_irq(pdev, 0);
 406         if (irq < 0)
 407                 return irq;
 408
 409         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 410         if (!iores)
 411                 return -ENXIO;
 412
 413         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 414         /*
 415          * If we failed to find the CRTC(s) which this encoder is
 416          * supposed to be connected to, it's because the CRTC has
 417          * not been registered yet.  Defer probing, and hope that
 418          * the required CRTC is added later.
 419          */
 420         if (encoder->possible_crtcs == 0)
 421                 return -EPROBE_DEFER;
 422
 423         ret = rockchip_hdmi_parse_dt(hdmi);
 424         if (ret) {
 425                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 426                 return ret;
 427         }
 428
 429         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 430         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 431                          DRM_MODE_ENCODER_TMDS, NULL);
 432
 433         ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
 434
 435         /*
 436          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 437          * which would have called the encoder cleanup.  Do it manually.
 438          */
 439         if (ret)
 440                 drm_encoder_cleanup(encoder);
 441
 442         return ret;
 443 }
 444
 445 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 446                                     void *data)
 447 {
 448         return dw_hdmi_unbind(dev, master, data);
 449 }
 450
 451 static const struct component_ops dw_hdmi_rockchip_ops = {
 452         .bind   = dw_hdmi_rockchip_bind,
 453         .unbind = dw_hdmi_rockchip_unbind,
 454 };
 455
 456 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 457 {
 458         pm_runtime_enable(&pdev->dev);
 459         pm_runtime_get_sync(&pdev->dev);
 460
 461         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 462 }
 463
 464 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 465 {
 466         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 467         pm_runtime_disable(&pdev->dev);
 468
 469         return 0;
 470 }
 471
 472 static int dw_hdmi_rockchip_suspend(struct device *dev)
 473 {
 474         dw_hdmi_suspend(dev);
 475         pm_runtime_put_sync(dev);
 476
 477         return 0;
 478 }
 479
 480 static int dw_hdmi_rockchip_resume(struct device *dev)
 481 {
 482         pm_runtime_get_sync(dev);
 483         dw_hdmi_resume(dev);
 484
 485         return  0;
 486 }
 487
 488 static const struct dev_pm_ops dw_hdmi_pm_ops = {
 489         SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend,
 490                                 dw_hdmi_rockchip_resume)
 491 };
 492
 493 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 494         .probe  = dw_hdmi_rockchip_probe,
 495         .remove = dw_hdmi_rockchip_remove,
 496         .driver = {
 497                 .name = "dwhdmi-rockchip",
 498                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 499                 .pm = &dw_hdmi_pm_ops,
 500         },
 501 };
 502
 503 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
 504
 505 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
 506 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
 507 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
 508 MODULE_LICENSE("GPL");
 509 MODULE_ALIAS("platform:dwhdmi-rockchip");