drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_crtc.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drmP.h>
  25 #include <video/mipi_display.h>
  26
  27 #include "rockchip_drm_drv.h"
  28 #include "rockchip_drm_vop.h"
  29
  30 #define DRIVER_NAME    "dw-mipi-dsi"
  31
  32 #define RK3288_GRF_SOC_CON6             0x025c
  33 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  34 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  35
  36 #define RK3399_GRF_SOC_CON19            0x6250
  37 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  38 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  39
  40 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  41 #define RK3399_GRF_SOC_CON22            0x6258
  42 #define RK3399_GRF_DSI_MODE             0xffff0000
  43
  44 #define DSI_VERSION                     0x00
  45 #define DSI_PWR_UP                      0x04
  46 #define RESET                           0
  47 #define POWERUP                         BIT(0)
  48
  49 #define DSI_CLKMGR_CFG                  0x08
  50 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  51 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  52
  53 #define DSI_DPI_VCID                    0x0c
  54 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  55
  56 #define DSI_DPI_COLOR_CODING            0x10
  57 #define EN18_LOOSELY                    BIT(8)
  58 #define DPI_COLOR_CODING_16BIT_1        0x0
  59 #define DPI_COLOR_CODING_16BIT_2        0x1
  60 #define DPI_COLOR_CODING_16BIT_3        0x2
  61 #define DPI_COLOR_CODING_18BIT_1        0x3
  62 #define DPI_COLOR_CODING_18BIT_2        0x4
  63 #define DPI_COLOR_CODING_24BIT          0x5
  64
  65 #define DSI_DPI_CFG_POL                 0x14
  66 #define COLORM_ACTIVE_LOW               BIT(4)
  67 #define SHUTD_ACTIVE_LOW                BIT(3)
  68 #define HSYNC_ACTIVE_LOW                BIT(2)
  69 #define VSYNC_ACTIVE_LOW                BIT(1)
  70 #define DATAEN_ACTIVE_LOW               BIT(0)
  71
  72 #define DSI_DPI_LP_CMD_TIM              0x18
  73 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  74 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  75
  76 #define DSI_DBI_CFG                     0x20
  77 #define DSI_DBI_CMDSIZE                 0x28
  78
  79 #define DSI_PCKHDL_CFG                  0x2c
  80 #define EN_CRC_RX                       BIT(4)
  81 #define EN_ECC_RX                       BIT(3)
  82 #define EN_BTA                          BIT(2)
  83 #define EN_EOTP_RX                      BIT(1)
  84 #define EN_EOTP_TX                      BIT(0)
  85
  86 #define DSI_MODE_CFG                    0x34
  87 #define ENABLE_VIDEO_MODE               0
  88 #define ENABLE_CMD_MODE                 BIT(0)
  89
  90 #define DSI_VID_MODE_CFG                0x38
  91 #define FRAME_BTA_ACK                   BIT(14)
  92 #define ENABLE_LOW_POWER                (0x3f << 8)
  93 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  94 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
  95 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
  96 #define VID_MODE_TYPE_BURST             0x2
  97
  98 #define DSI_VID_PKT_SIZE                0x3c
  99 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 100 #define VID_PKT_MAX_SIZE                0x3fff
 101
 102 #define DSI_VID_NUM_CHUMKS              0x40
 103 #define DSI_VID_NULL_PKT_SIZE           0x44
 104 #define DSI_VID_HSA_TIME                0x48
 105 #define DSI_VID_HBP_TIME                0x4c
 106 #define DSI_VID_HLINE_TIME              0x50
 107 #define DSI_VID_VSA_LINES               0x54
 108 #define DSI_VID_VBP_LINES               0x58
 109 #define DSI_VID_VFP_LINES               0x5c
 110 #define DSI_VID_VACTIVE_LINES           0x60
 111 #define DSI_CMD_MODE_CFG                0x68
 112 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 113 #define DCS_LW_TX_LP                    BIT(19)
 114 #define DCS_SR_0P_TX_LP                 BIT(18)
 115 #define DCS_SW_1P_TX_LP                 BIT(17)
 116 #define DCS_SW_0P_TX_LP                 BIT(16)
 117 #define GEN_LW_TX_LP                    BIT(14)
 118 #define GEN_SR_2P_TX_LP                 BIT(13)
 119 #define GEN_SR_1P_TX_LP                 BIT(12)
 120 #define GEN_SR_0P_TX_LP                 BIT(11)
 121 #define GEN_SW_2P_TX_LP                 BIT(10)
 122 #define GEN_SW_1P_TX_LP                 BIT(9)
 123 #define GEN_SW_0P_TX_LP                 BIT(8)
 124 #define EN_ACK_RQST                     BIT(1)
 125 #define EN_TEAR_FX                      BIT(0)
 126
 127 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 128                                          DCS_LW_TX_LP | \
 129                                          DCS_SR_0P_TX_LP | \
 130                                          DCS_SW_1P_TX_LP | \
 131                                          DCS_SW_0P_TX_LP | \
 132                                          GEN_LW_TX_LP | \
 133                                          GEN_SR_2P_TX_LP | \
 134                                          GEN_SR_1P_TX_LP | \
 135                                          GEN_SR_0P_TX_LP | \
 136                                          GEN_SW_2P_TX_LP | \
 137                                          GEN_SW_1P_TX_LP | \
 138                                          GEN_SW_0P_TX_LP)
 139
 140 #define DSI_GEN_HDR                     0x6c
 141 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 142 #define GEN_HDATA_MASK                  (0xffff << 8)
 143 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 144 #define GEN_HTYPE_MASK                  0xff
 145
 146 #define DSI_GEN_PLD_DATA                0x70
 147
 148 #define DSI_CMD_PKT_STATUS              0x74
 149 #define GEN_CMD_EMPTY                   BIT(0)
 150 #define GEN_CMD_FULL                    BIT(1)
 151 #define GEN_PLD_W_EMPTY                 BIT(2)
 152 #define GEN_PLD_W_FULL                  BIT(3)
 153 #define GEN_PLD_R_EMPTY                 BIT(4)
 154 #define GEN_PLD_R_FULL                  BIT(5)
 155 #define GEN_RD_CMD_BUSY                 BIT(6)
 156
 157 #define DSI_TO_CNT_CFG                  0x78
 158 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 159 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 160
 161 #define DSI_BTA_TO_CNT                  0x8c
 162 #define DSI_LPCLK_CTRL                  0x94
 163 #define AUTO_CLKLANE_CTRL               BIT(1)
 164 #define PHY_TXREQUESTCLKHS              BIT(0)
 165
 166 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 167 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 168 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 169
 170 #define DSI_PHY_TMR_CFG                 0x9c
 171 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 172 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 173 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 174
 175 #define DSI_PHY_RSTZ                    0xa0
 176 #define PHY_DISFORCEPLL                 0
 177 #define PHY_ENFORCEPLL                  BIT(3)
 178 #define PHY_DISABLECLK                  0
 179 #define PHY_ENABLECLK                   BIT(2)
 180 #define PHY_RSTZ                        0
 181 #define PHY_UNRSTZ                      BIT(1)
 182 #define PHY_SHUTDOWNZ                   0
 183 #define PHY_UNSHUTDOWNZ                 BIT(0)
 184
 185 #define DSI_PHY_IF_CFG                  0xa4
 186 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 187 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 188
 189 #define DSI_PHY_STATUS                  0xb0
 190 #define LOCK                            BIT(0)
 191 #define STOP_STATE_CLK_LANE             BIT(2)
 192
 193 #define DSI_PHY_TST_CTRL0               0xb4
 194 #define PHY_TESTCLK                     BIT(1)
 195 #define PHY_UNTESTCLK                   0
 196 #define PHY_TESTCLR                     BIT(0)
 197 #define PHY_UNTESTCLR                   0
 198
 199 #define DSI_PHY_TST_CTRL1               0xb8
 200 #define PHY_TESTEN                      BIT(16)
 201 #define PHY_UNTESTEN                    0
 202 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 203 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 204
 205 #define DSI_INT_ST0                     0xbc
 206 #define DSI_INT_ST1                     0xc0
 207 #define DSI_INT_MSK0                    0xc4
 208 #define DSI_INT_MSK1                    0xc8
 209
 210 #define PHY_STATUS_TIMEOUT_US           10000
 211 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 212
 213 #define BYPASS_VCO_RANGE        BIT(7)
 214 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 215 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 216 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 217 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 218 #define REF_BIAS_CUR_SEL        BIT(0)
 219
 220 #define CP_CURRENT_3MA          BIT(3)
 221 #define CP_PROGRAM_EN           BIT(7)
 222 #define LPF_PROGRAM_EN          BIT(6)
 223 #define LPF_RESISTORS_20_KOHM   0
 224
 225 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 226
 227 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 228 #define LOW_PROGRAM_EN          0
 229 #define HIGH_PROGRAM_EN         BIT(7)
 230 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 231 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 232 #define PLL_LOOP_DIV_EN         BIT(5)
 233 #define PLL_INPUT_DIV_EN        BIT(4)
 234
 235 #define POWER_CONTROL           BIT(6)
 236 #define INTERNAL_REG_CURRENT    BIT(3)
 237 #define BIAS_BLOCK_ON           BIT(2)
 238 #define BANDGAP_ON              BIT(0)
 239
 240 #define TER_RESISTOR_HIGH       BIT(7)
 241 #define TER_RESISTOR_LOW        0
 242 #define LEVEL_SHIFTERS_ON       BIT(6)
 243 #define TER_CAL_DONE            BIT(5)
 244 #define SETRD_MAX               (0x7 << 2)
 245 #define POWER_MANAGE            BIT(1)
 246 #define TER_RESISTORS_ON        BIT(0)
 247
 248 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 249 #define BANDGAP_SEL(val)        ((val) & 0x7)
 250 #define TLP_PROGRAM_EN          BIT(7)
 251 #define THS_PRE_PROGRAM_EN      BIT(7)
 252 #define THS_ZERO_PROGRAM_EN     BIT(6)
 253
 254 enum {
 255         BANDGAP_97_07,
 256         BANDGAP_98_05,
 257         BANDGAP_99_02,
 258         BANDGAP_100_00,
 259         BANDGAP_93_17,
 260         BANDGAP_94_15,
 261         BANDGAP_95_12,
 262         BANDGAP_96_10,
 263 };
 264
 265 enum {
 266         BIASEXTR_87_1,
 267         BIASEXTR_91_5,
 268         BIASEXTR_95_9,
 269         BIASEXTR_100,
 270         BIASEXTR_105_94,
 271         BIASEXTR_111_88,
 272         BIASEXTR_118_8,
 273         BIASEXTR_127_7,
 274 };
 275
 276 struct dw_mipi_dsi_plat_data {
 277         u32 dsi0_en_bit;
 278         u32 dsi1_en_bit;
 279         u32 grf_switch_reg;
 280         u32 grf_dsi0_mode;
 281         u32 grf_dsi0_mode_reg;
 282         unsigned int max_data_lanes;
 283         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 284                                            struct drm_display_mode *mode);
 285 };
 286
 287 struct dw_mipi_dsi {
 288         struct drm_encoder encoder;
 289         struct drm_connector connector;
 290         struct mipi_dsi_host dsi_host;
 291         struct drm_panel *panel;
 292         struct device *dev;
 293         struct regmap *grf_regmap;
 294         void __iomem *base;
 295
 296         struct clk *pllref_clk;
 297         struct clk *pclk;
 298         struct clk *phy_cfg_clk;
 299
 300         int dpms_mode;
 301         unsigned int lane_mbps; /* per lane */
 302         u32 channel;
 303         u32 lanes;
 304         u32 format;
 305         u16 input_div;
 306         u16 feedback_div;
 307         struct drm_display_mode *mode;
 308
 309         const struct dw_mipi_dsi_plat_data *pdata;
 310 };
 311
 312 enum dw_mipi_dsi_mode {
 313         DW_MIPI_DSI_CMD_MODE,
 314         DW_MIPI_DSI_VID_MODE,
 315 };
 316
 317 struct dphy_pll_testdin_map {
 318         unsigned int max_mbps;
 319         u8 testdin;
 320 };
 321
 322 /* The table is based on 27MHz DPHY pll reference clock. */
 323 static const struct dphy_pll_testdin_map dptdin_map[] = {
 324         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 325         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 326         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 327         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 328         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 329         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 330         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 331         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 332         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 333         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 334 };
 335
 336 static int max_mbps_to_testdin(unsigned int max_mbps)
 337 {
 338         int i;
 339
 340         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 341                 if (dptdin_map[i].max_mbps > max_mbps)
 342                         return dptdin_map[i].testdin;
 343
 344         return -EINVAL;
 345 }
 346
 347 /*
 348  * The controller should generate 2 frames before
 349  * preparing the peripheral.
 350  */
 351 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 352 {
 353         int refresh, two_frames;
 354
 355         refresh = drm_mode_vrefresh(dsi->mode);
 356         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 357         msleep(two_frames);
 358 }
 359
 360 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 361 {
 362         return container_of(host, struct dw_mipi_dsi, dsi_host);
 363 }
 364
 365 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 366 {
 367         return container_of(con, struct dw_mipi_dsi, connector);
 368 }
 369
 370 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 371 {
 372         return container_of(encoder, struct dw_mipi_dsi, encoder);
 373 }
 374 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 375 {
 376         writel(val, dsi->base + reg);
 377 }
 378
 379 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 380 {
 381         return readl(dsi->base + reg);
 382 }
 383
 384 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 385                                  u8 test_data)
 386 {
 387         /*
 388          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 389          * is latched internally as the current test code. Test data is
 390          * programmed internally by rising edge on TESTCLK.
 391          */
 392         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 393
 394         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 395                                           PHY_TESTDIN(test_code));
 396
 397         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 398
 399         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 400                                           PHY_TESTDIN(test_data));
 401
 402         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 403 }
 404
 405 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 406 {
 407         int ret, testdin, vco, val;
 408
 409         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 410
 411         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 412         if (testdin < 0) {
 413                 dev_err(dsi->dev,
 414                         "failed to get testdin for %dmbps lane clock\n",
 415                         dsi->lane_mbps);
 416                 return testdin;
 417         }
 418
 419         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 420
 421         if (!IS_ERR(dsi->phy_cfg_clk)) {
 422                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 423                 if (ret) {
 424                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 425                         return ret;
 426                 }
 427         }
 428
 429         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 430                                          VCO_RANGE_CON_SEL(vco) |
 431                                          VCO_IN_CAP_CON_LOW |
 432                                          REF_BIAS_CUR_SEL);
 433
 434         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 435         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 436                                          LPF_RESISTORS_20_KOHM);
 437
 438         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 439
 440         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 441         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 442         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 443                                          LOW_PROGRAM_EN);
 444         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 445                                          HIGH_PROGRAM_EN);
 446
 447         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 448                                          BIAS_BLOCK_ON | BANDGAP_ON);
 449
 450         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 451                                          SETRD_MAX | TER_RESISTORS_ON);
 452         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 453                                          SETRD_MAX | POWER_MANAGE |
 454                                          TER_RESISTORS_ON);
 455
 456         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 457                                          BIASEXTR_SEL(BIASEXTR_127_7));
 458         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 459                                          BANDGAP_SEL(BANDGAP_96_10));
 460
 461         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 462         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 463         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 464
 465         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 466                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 467
 468
 469         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 470                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 471         if (ret < 0) {
 472                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 473                 goto phy_init_end;
 474         }
 475
 476         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 477                                  val, val & STOP_STATE_CLK_LANE, 1000,
 478                                  PHY_STATUS_TIMEOUT_US);
 479         if (ret < 0)
 480                 dev_err(dsi->dev,
 481                         "failed to wait for phy clk lane stop state\n");
 482
 483 phy_init_end:
 484         if (!IS_ERR(dsi->phy_cfg_clk))
 485                 clk_disable_unprepare(dsi->phy_cfg_clk);
 486
 487         return ret;
 488 }
 489
 490 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 491 {
 492         unsigned int i, pre;
 493         unsigned long mpclk, pllref, tmp;
 494         unsigned int m = 1, n = 1, target_mbps = 1000;
 495         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 496         int bpp;
 497
 498         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 499         if (bpp < 0) {
 500                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 501                         dsi->format);
 502                 return bpp;
 503         }
 504
 505         mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
 506         if (mpclk) {
 507                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 508                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 509                 if (tmp < max_mbps)
 510                         target_mbps = tmp;
 511                 else
 512                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 513         }
 514
 515         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 516         tmp = pllref;
 517
 518         for (i = 1; i < 6; i++) {
 519                 pre = pllref / i;
 520                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 521                         tmp = target_mbps % pre;
 522                         n = i;
 523                         m = target_mbps / pre;
 524                 }
 525                 if (tmp == 0)
 526                         break;
 527         }
 528
 529         dsi->lane_mbps = pllref / n * m;
 530         dsi->input_div = n;
 531         dsi->feedback_div = m;
 532
 533         return 0;
 534 }
 535
 536 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 537                                    struct mipi_dsi_device *device)
 538 {
 539         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 540
 541         if (device->lanes > dsi->pdata->max_data_lanes) {
 542                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 543                                 device->lanes);
 544                 return -EINVAL;
 545         }
 546
 547         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
 548             !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
 549                 dev_err(dsi->dev, "device mode is unsupported\n");
 550                 return -EINVAL;
 551         }
 552
 553         dsi->lanes = device->lanes;
 554         dsi->channel = device->channel;
 555         dsi->format = device->format;
 556         dsi->panel = of_drm_find_panel(device->dev.of_node);
 557         if (!dsi->panel) {
 558                 DRM_ERROR("failed to find panel\n");
 559                 return -ENODEV;
 560         }
 561
 562         return 0;
 563 }
 564
 565 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 566                                    struct mipi_dsi_device *device)
 567 {
 568         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 569
 570         if (dsi->panel)
 571                 drm_panel_detach(dsi->panel);
 572
 573         dsi->panel = NULL;
 574         return 0;
 575 }
 576
 577 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 578 {
 579         int ret;
 580         int sts = 0;
 581
 582         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 583                                  sts, !(sts & GEN_CMD_FULL), 1000,
 584                                  CMD_PKT_STATUS_TIMEOUT_US);
 585
 586         if (ret < 0) {
 587                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 588                 return ret;
 589         }
 590
 591         dsi_write(dsi, DSI_GEN_HDR, val);
 592
 593         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 594                                  sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 595                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 596
 597         if (ret < 0) {
 598                 dev_err(dsi->dev, "failed to write command FIFO\n");
 599                 return ret;
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
 606                                    const struct mipi_dsi_msg *msg)
 607 {
 608         const u16 *tx_buf = msg->tx_buf;
 609         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 610
 611         if (msg->tx_len > 2) {
 612                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 613                         msg->tx_len);
 614                 return -EINVAL;
 615         }
 616
 617         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 618 }
 619
 620 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
 621                                   const struct mipi_dsi_msg *msg)
 622 {
 623         const u32 *tx_buf = msg->tx_buf;
 624         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 625         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 626         u32 remainder = 0;
 627         u32 sts = 0;
 628
 629         if (msg->tx_len < 3) {
 630                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 631                         msg->tx_len);
 632                 return -EINVAL;
 633         }
 634
 635         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 636                 if (len < pld_data_bytes) {
 637                         memcpy(&remainder, tx_buf, len);
 638                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 639                         len = 0;
 640                 } else {
 641                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 642                         tx_buf++;
 643                         len -= pld_data_bytes;
 644                 }
 645
 646                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 647                                          sts, !(sts & GEN_PLD_W_FULL), 1000,
 648                                          CMD_PKT_STATUS_TIMEOUT_US);
 649                 if (ret < 0) {
 650                         dev_err(dsi->dev,
 651                                 "failed to get available write payload FIFO\n");
 652                         return ret;
 653                 }
 654         }
 655
 656         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 657 }
 658
 659 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 660                                          const struct mipi_dsi_msg *msg)
 661 {
 662         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 663         int ret;
 664
 665         switch (msg->type) {
 666         case MIPI_DSI_DCS_SHORT_WRITE:
 667         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 668         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 669         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 670         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 671         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 672                 ret = dw_mipi_dsi_short_write(dsi, msg);
 673                 break;
 674         case MIPI_DSI_DCS_LONG_WRITE:
 675         case MIPI_DSI_GENERIC_LONG_WRITE:
 676                 ret = dw_mipi_dsi_long_write(dsi, msg);
 677                 break;
 678         default:
 679                 dev_err(dsi->dev, "unsupported message type\n");
 680                 ret = -EINVAL;
 681         }
 682
 683         return ret;
 684 }
 685
 686 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 687         .attach = dw_mipi_dsi_host_attach,
 688         .detach = dw_mipi_dsi_host_detach,
 689         .transfer = dw_mipi_dsi_host_transfer,
 690 };
 691
 692 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 693 {
 694         u32 val;
 695
 696         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 697
 698         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 699 }
 700
 701 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 702                                  enum dw_mipi_dsi_mode mode)
 703 {
 704         if (mode == DW_MIPI_DSI_CMD_MODE) {
 705                 dsi_write(dsi, DSI_PWR_UP, RESET);
 706                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 707                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 708         } else {
 709                 dsi_write(dsi, DSI_PWR_UP, RESET);
 710                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 711                 dw_mipi_dsi_video_mode_config(dsi);
 712                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 713         }
 714 }
 715
 716 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 717 {
 718         dsi_write(dsi, DSI_PWR_UP, RESET);
 719         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 720 }
 721
 722 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 723 {
 724         dsi_write(dsi, DSI_PWR_UP, RESET);
 725         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 726                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 727         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 728                   TX_ESC_CLK_DIVIDSION(7));
 729         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 730 }
 731
 732 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 733                                    struct drm_display_mode *mode)
 734 {
 735         u32 val = 0, color = 0;
 736
 737         switch (dsi->format) {
 738         case MIPI_DSI_FMT_RGB888:
 739                 color = DPI_COLOR_CODING_24BIT;
 740                 break;
 741         case MIPI_DSI_FMT_RGB666:
 742                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 743                 break;
 744         case MIPI_DSI_FMT_RGB666_PACKED:
 745                 color = DPI_COLOR_CODING_18BIT_1;
 746                 break;
 747         case MIPI_DSI_FMT_RGB565:
 748                 color = DPI_COLOR_CODING_16BIT_1;
 749                 break;
 750         }
 751
 752         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 753                 val |= VSYNC_ACTIVE_LOW;
 754         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 755                 val |= HSYNC_ACTIVE_LOW;
 756
 757         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 758         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 759         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 760         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 761                   | INVACT_LPCMD_TIME(4));
 762 }
 763
 764 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 765 {
 766         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 767 }
 768
 769 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 770                                             struct drm_display_mode *mode)
 771 {
 772         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 773 }
 774
 775 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 776 {
 777         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 778         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 779         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 780         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 781 }
 782
 783 /* Get lane byte clock cycles. */
 784 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 785                                            u32 hcomponent)
 786 {
 787         u32 frac, lbcc;
 788
 789         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 790
 791         frac = lbcc % dsi->mode->clock;
 792         lbcc = lbcc / dsi->mode->clock;
 793         if (frac)
 794                 lbcc++;
 795
 796         return lbcc;
 797 }
 798
 799 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 800 {
 801         u32 htotal, hsa, hbp, lbcc;
 802         struct drm_display_mode *mode = dsi->mode;
 803
 804         htotal = mode->htotal;
 805         hsa = mode->hsync_end - mode->hsync_start;
 806         hbp = mode->htotal - mode->hsync_end;
 807
 808         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 809         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 810
 811         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 812         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 813
 814         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 815         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 816 }
 817
 818 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 819 {
 820         u32 vactive, vsa, vfp, vbp;
 821         struct drm_display_mode *mode = dsi->mode;
 822
 823         vactive = mode->vdisplay;
 824         vsa = mode->vsync_end - mode->vsync_start;
 825         vfp = mode->vsync_start - mode->vdisplay;
 826         vbp = mode->vtotal - mode->vsync_end;
 827
 828         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 829         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 830         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 831         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 832 }
 833
 834 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 835 {
 836         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 837                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 838
 839         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 840                   | PHY_CLKLP2HS_TIME(0x40));
 841 }
 842
 843 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 844 {
 845         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 846                   N_LANES(dsi->lanes));
 847 }
 848
 849 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 850 {
 851         dsi_read(dsi, DSI_INT_ST0);
 852         dsi_read(dsi, DSI_INT_ST1);
 853         dsi_write(dsi, DSI_INT_MSK0, 0);
 854         dsi_write(dsi, DSI_INT_MSK1, 0);
 855 }
 856
 857 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 858                                         struct drm_display_mode *mode,
 859                                         struct drm_display_mode *adjusted_mode)
 860 {
 861         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 862         int ret;
 863
 864         if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
 865                 return;
 866
 867         dsi->mode = adjusted_mode;
 868
 869         ret = dw_mipi_dsi_get_lane_bps(dsi);
 870         if (ret < 0)
 871                 return;
 872
 873         if (clk_prepare_enable(dsi->pclk)) {
 874                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 875                 return;
 876         }
 877
 878         pm_runtime_get_sync(dsi->dev);
 879
 880         dw_mipi_dsi_init(dsi);
 881         dw_mipi_dsi_dpi_config(dsi, mode);
 882         dw_mipi_dsi_packet_handler_config(dsi);
 883         dw_mipi_dsi_video_mode_config(dsi);
 884         dw_mipi_dsi_video_packet_config(dsi, mode);
 885         dw_mipi_dsi_command_mode_config(dsi);
 886         dw_mipi_dsi_line_timer_config(dsi);
 887         dw_mipi_dsi_vertical_timing_config(dsi);
 888         dw_mipi_dsi_dphy_timing_config(dsi);
 889         dw_mipi_dsi_dphy_interface_config(dsi);
 890         dw_mipi_dsi_clear_err(dsi);
 891         if (drm_panel_prepare(dsi->panel))
 892                 dev_err(dsi->dev, "failed to prepare panel\n");
 893
 894         clk_disable_unprepare(dsi->pclk);
 895 }
 896
 897 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 898 {
 899         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 900
 901         if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
 902                 return;
 903
 904         drm_panel_disable(dsi->panel);
 905
 906         if (clk_prepare_enable(dsi->pclk)) {
 907                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 908                 return;
 909         }
 910
 911         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 912         drm_panel_unprepare(dsi->panel);
 913         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 914
 915         /*
 916          * This is necessary to make sure the peripheral will be driven
 917          * normally when the display is enabled again later.
 918          */
 919         msleep(120);
 920
 921         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 922         dw_mipi_dsi_disable(dsi);
 923         pm_runtime_put(dsi->dev);
 924         clk_disable_unprepare(dsi->pclk);
 925         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
 926 }
 927
 928 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 929                                         const struct drm_display_mode *mode,
 930                                         struct drm_display_mode *adjusted_mode)
 931 {
 932         return true;
 933 }
 934
 935 static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
 936 {
 937         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 938         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 939         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 940         u32 val;
 941
 942         if (clk_prepare_enable(dsi->pclk)) {
 943                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 944                 return;
 945         }
 946
 947         if (pdata->grf_dsi0_mode_reg)
 948                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 949                              pdata->grf_dsi0_mode);
 950
 951         dw_mipi_dsi_phy_init(dsi);
 952         dw_mipi_dsi_wait_for_two_frames(dsi);
 953
 954         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 955         drm_panel_enable(dsi->panel);
 956
 957         clk_disable_unprepare(dsi->pclk);
 958
 959         if (mux)
 960                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 961         else
 962                 val = pdata->dsi0_en_bit << 16;
 963
 964         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 965         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 966         dsi->dpms_mode = DRM_MODE_DPMS_ON;
 967 }
 968
 969 static int
 970 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 971                                  struct drm_crtc_state *crtc_state,
 972                                  struct drm_connector_state *conn_state)
 973 {
 974         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 975         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 976
 977         switch (dsi->format) {
 978         case MIPI_DSI_FMT_RGB888:
 979                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 980                 break;
 981         case MIPI_DSI_FMT_RGB666:
 982                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 983                 break;
 984         case MIPI_DSI_FMT_RGB565:
 985                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 986                 break;
 987         default:
 988                 WARN_ON(1);
 989                 return -EINVAL;
 990         }
 991
 992         s->output_type = DRM_MODE_CONNECTOR_DSI;
 993
 994         return 0;
 995 }
 996
 997 static struct drm_encoder_helper_funcs
 998 dw_mipi_dsi_encoder_helper_funcs = {
 999         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1000         .commit = dw_mipi_dsi_encoder_commit,
1001         .mode_set = dw_mipi_dsi_encoder_mode_set,
1002         .disable = dw_mipi_dsi_encoder_disable,
1003         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1004 };
1005
1006 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1007         .destroy = drm_encoder_cleanup,
1008 };
1009
1010 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1011 {
1012         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1013
1014         return drm_panel_get_modes(dsi->panel);
1015 }
1016
1017 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1018                                         struct drm_connector *connector,
1019                                         struct drm_display_mode *mode)
1020 {
1021         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1022
1023         enum drm_mode_status mode_status = MODE_OK;
1024
1025         if (dsi->pdata->mode_valid)
1026                 mode_status = dsi->pdata->mode_valid(connector, mode);
1027
1028         return mode_status;
1029 }
1030
1031 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1032                                         struct drm_connector *connector)
1033 {
1034         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1035
1036         return &dsi->encoder;
1037 }
1038
1039 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1040         .get_modes = dw_mipi_dsi_connector_get_modes,
1041         .mode_valid = dw_mipi_dsi_mode_valid,
1042         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1043 };
1044
1045 static enum drm_connector_status
1046 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1047 {
1048         return connector_status_connected;
1049 }
1050
1051 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1052 {
1053         drm_connector_unregister(connector);
1054         drm_connector_cleanup(connector);
1055 }
1056
1057 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1058         .dpms = drm_atomic_helper_connector_dpms,
1059         .fill_modes = drm_helper_probe_single_connector_modes,
1060         .detect = dw_mipi_dsi_detect,
1061         .destroy = dw_mipi_dsi_drm_connector_destroy,
1062         .reset = drm_atomic_helper_connector_reset,
1063         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1064         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1065 };
1066
1067 static int dw_mipi_dsi_register(struct drm_device *drm,
1068                                       struct dw_mipi_dsi *dsi)
1069 {
1070         struct drm_encoder *encoder = &dsi->encoder;
1071         struct drm_connector *connector = &dsi->connector;
1072         struct device *dev = dsi->dev;
1073         int ret;
1074
1075         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1076                                                              dev->of_node);
1077         /*
1078          * If we failed to find the CRTC(s) which this encoder is
1079          * supposed to be connected to, it's because the CRTC has
1080          * not been registered yet.  Defer probing, and hope that
1081          * the required CRTC is added later.
1082          */
1083         if (encoder->possible_crtcs == 0)
1084                 return -EPROBE_DEFER;
1085
1086         drm_encoder_helper_add(&dsi->encoder,
1087                                &dw_mipi_dsi_encoder_helper_funcs);
1088         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1089                          DRM_MODE_ENCODER_DSI, NULL);
1090         if (ret) {
1091                 dev_err(dev, "Failed to initialize encoder with drm\n");
1092                 return ret;
1093         }
1094
1095         drm_connector_helper_add(connector,
1096                         &dw_mipi_dsi_connector_helper_funcs);
1097
1098         drm_connector_init(drm, &dsi->connector,
1099                            &dw_mipi_dsi_atomic_connector_funcs,
1100                            DRM_MODE_CONNECTOR_DSI);
1101
1102         drm_panel_attach(dsi->panel, &dsi->connector);
1103
1104         dsi->connector.port = dev->of_node;
1105
1106         drm_mode_connector_attach_encoder(connector, encoder);
1107
1108         return 0;
1109 }
1110
1111 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1112 {
1113         struct device_node *np = dsi->dev->of_node;
1114
1115         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1116         if (IS_ERR(dsi->grf_regmap)) {
1117                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1118                 return PTR_ERR(dsi->grf_regmap);
1119         }
1120
1121         return 0;
1122 }
1123
1124 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1125         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1126         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1127         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1128         .max_data_lanes = 4,
1129 };
1130
1131 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1132         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1133         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1134         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1135         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1136         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1137         .max_data_lanes = 4,
1138 };
1139
1140 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1141         {
1142          .compatible = "rockchip,rk3288-mipi-dsi",
1143          .data = &rk3288_mipi_dsi_drv_data,
1144         },{
1145          .compatible = "rockchip,rk3399-mipi-dsi",
1146          .data = &rk3399_mipi_dsi_drv_data,
1147         },
1148         { /* sentinel */ }
1149 };
1150 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1151
1152 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1153                              void *data)
1154 {
1155         struct platform_device *pdev = to_platform_device(dev);
1156         struct drm_device *drm = data;
1157         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1158         struct resource *res;
1159         int ret;
1160
1161         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
1162
1163         if (!dsi->panel)
1164                 return -EPROBE_DEFER;
1165
1166         ret = rockchip_mipi_parse_dt(dsi);
1167         if (ret)
1168                 return ret;
1169
1170         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171         if (!res)
1172                 return -ENODEV;
1173
1174         dsi->base = devm_ioremap_resource(dev, res);
1175         if (IS_ERR(dsi->base))
1176                 return PTR_ERR(dsi->base);
1177
1178         dsi->pllref_clk = devm_clk_get(dev, "ref");
1179         if (IS_ERR(dsi->pllref_clk)) {
1180                 ret = PTR_ERR(dsi->pllref_clk);
1181                 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1182                 return ret;
1183         }
1184
1185         dsi->pclk = devm_clk_get(dev, "pclk");
1186         if (IS_ERR(dsi->pclk)) {
1187                 ret = PTR_ERR(dsi->pclk);
1188                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1189                 return ret;
1190         }
1191
1192         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1193         if (IS_ERR(dsi->phy_cfg_clk))
1194                 dev_dbg(dev, "have not phy_cfg_clk\n");
1195
1196         ret = clk_prepare_enable(dsi->pllref_clk);
1197         if (ret) {
1198                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1199                 return ret;
1200         }
1201
1202         ret = dw_mipi_dsi_register(drm, dsi);
1203         if (ret) {
1204                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1205                 goto err_pllref;
1206         }
1207
1208         dev_set_drvdata(dev, dsi);
1209
1210         pm_runtime_enable(dev);
1211
1212         return 0;
1213
1214 err_pllref:
1215         clk_disable_unprepare(dsi->pllref_clk);
1216         return ret;
1217 }
1218
1219 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1220         void *data)
1221 {
1222         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1223
1224         pm_runtime_disable(dev);
1225         clk_disable_unprepare(dsi->pllref_clk);
1226 }
1227
1228 static const struct component_ops dw_mipi_dsi_ops = {
1229         .bind   = dw_mipi_dsi_bind,
1230         .unbind = dw_mipi_dsi_unbind,
1231 };
1232
1233 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1234 {
1235         struct device *dev = &pdev->dev;
1236         const struct of_device_id *of_id =
1237                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1238         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1239         struct dw_mipi_dsi *dsi;
1240         int ret;
1241
1242         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1243         if (!dsi)
1244                 return -ENOMEM;
1245
1246         dsi->dev = dev;
1247         dsi->pdata = pdata;
1248         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1249         dsi->dsi_host.dev = &pdev->dev;
1250
1251         ret = mipi_dsi_host_register(&dsi->dsi_host);
1252         if (ret)
1253                 return ret;
1254
1255         platform_set_drvdata(pdev, dsi);
1256         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1257         if (ret)
1258                 mipi_dsi_host_unregister(&dsi->dsi_host);
1259
1260         return ret;
1261 }
1262
1263 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1264 {
1265         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1266
1267         if (dsi)
1268                 mipi_dsi_host_unregister(&dsi->dsi_host);
1269         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1270         return 0;
1271 }
1272
1273 static struct platform_driver dw_mipi_dsi_driver = {
1274         .probe          = dw_mipi_dsi_probe,
1275         .remove         = dw_mipi_dsi_remove,
1276         .driver         = {
1277                 .of_match_table = dw_mipi_dsi_dt_ids,
1278                 .name   = DRIVER_NAME,
1279         },
1280 };
1281 module_platform_driver(dw_mipi_dsi_driver);
1282
1283 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1284 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1285 MODULE_LICENSE("GPL");
1286 MODULE_ALIAS("platform:" DRIVER_NAME);