drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_crtc.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drmP.h>
  25 #include <video/mipi_display.h>
  26
  27 #include "rockchip_drm_drv.h"
  28 #include "rockchip_drm_vop.h"
  29
  30 #define DRIVER_NAME    "dw-mipi-dsi"
  31
  32 #define RK3288_GRF_SOC_CON6             0x025c
  33 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  34 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  35
  36 #define RK3399_GRF_SOC_CON19            0x6250
  37 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  38 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  39
  40 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  41 #define RK3399_GRF_SOC_CON22            0x6258
  42 #define RK3399_GRF_DSI_MODE             0xffff0000
  43
  44 #define DSI_VERSION                     0x00
  45 #define DSI_PWR_UP                      0x04
  46 #define RESET                           0
  47 #define POWERUP                         BIT(0)
  48
  49 #define DSI_CLKMGR_CFG                  0x08
  50 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  51 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  52
  53 #define DSI_DPI_VCID                    0x0c
  54 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  55
  56 #define DSI_DPI_COLOR_CODING            0x10
  57 #define EN18_LOOSELY                    BIT(8)
  58 #define DPI_COLOR_CODING_16BIT_1        0x0
  59 #define DPI_COLOR_CODING_16BIT_2        0x1
  60 #define DPI_COLOR_CODING_16BIT_3        0x2
  61 #define DPI_COLOR_CODING_18BIT_1        0x3
  62 #define DPI_COLOR_CODING_18BIT_2        0x4
  63 #define DPI_COLOR_CODING_24BIT          0x5
  64
  65 #define DSI_DPI_CFG_POL                 0x14
  66 #define COLORM_ACTIVE_LOW               BIT(4)
  67 #define SHUTD_ACTIVE_LOW                BIT(3)
  68 #define HSYNC_ACTIVE_LOW                BIT(2)
  69 #define VSYNC_ACTIVE_LOW                BIT(1)
  70 #define DATAEN_ACTIVE_LOW               BIT(0)
  71
  72 #define DSI_DPI_LP_CMD_TIM              0x18
  73 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  74 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  75
  76 #define DSI_DBI_CFG                     0x20
  77 #define DSI_DBI_CMDSIZE                 0x28
  78
  79 #define DSI_PCKHDL_CFG                  0x2c
  80 #define EN_CRC_RX                       BIT(4)
  81 #define EN_ECC_RX                       BIT(3)
  82 #define EN_BTA                          BIT(2)
  83 #define EN_EOTP_RX                      BIT(1)
  84 #define EN_EOTP_TX                      BIT(0)
  85
  86 #define DSI_MODE_CFG                    0x34
  87 #define ENABLE_VIDEO_MODE               0
  88 #define ENABLE_CMD_MODE                 BIT(0)
  89
  90 #define DSI_VID_MODE_CFG                0x38
  91 #define FRAME_BTA_ACK                   BIT(14)
  92 #define ENABLE_LOW_POWER                (0x3f << 8)
  93 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  94 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
  95 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
  96 #define VID_MODE_TYPE_BURST             0x2
  97
  98 #define DSI_VID_PKT_SIZE                0x3c
  99 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 100 #define VID_PKT_MAX_SIZE                0x3fff
 101
 102 #define DSI_VID_NUM_CHUMKS              0x40
 103 #define DSI_VID_NULL_PKT_SIZE           0x44
 104 #define DSI_VID_HSA_TIME                0x48
 105 #define DSI_VID_HBP_TIME                0x4c
 106 #define DSI_VID_HLINE_TIME              0x50
 107 #define DSI_VID_VSA_LINES               0x54
 108 #define DSI_VID_VBP_LINES               0x58
 109 #define DSI_VID_VFP_LINES               0x5c
 110 #define DSI_VID_VACTIVE_LINES           0x60
 111 #define DSI_CMD_MODE_CFG                0x68
 112 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 113 #define DCS_LW_TX_LP                    BIT(19)
 114 #define DCS_SR_0P_TX_LP                 BIT(18)
 115 #define DCS_SW_1P_TX_LP                 BIT(17)
 116 #define DCS_SW_0P_TX_LP                 BIT(16)
 117 #define GEN_LW_TX_LP                    BIT(14)
 118 #define GEN_SR_2P_TX_LP                 BIT(13)
 119 #define GEN_SR_1P_TX_LP                 BIT(12)
 120 #define GEN_SR_0P_TX_LP                 BIT(11)
 121 #define GEN_SW_2P_TX_LP                 BIT(10)
 122 #define GEN_SW_1P_TX_LP                 BIT(9)
 123 #define GEN_SW_0P_TX_LP                 BIT(8)
 124 #define EN_ACK_RQST                     BIT(1)
 125 #define EN_TEAR_FX                      BIT(0)
 126
 127 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 128                                          DCS_LW_TX_LP | \
 129                                          DCS_SR_0P_TX_LP | \
 130                                          DCS_SW_1P_TX_LP | \
 131                                          DCS_SW_0P_TX_LP | \
 132                                          GEN_LW_TX_LP | \
 133                                          GEN_SR_2P_TX_LP | \
 134                                          GEN_SR_1P_TX_LP | \
 135                                          GEN_SR_0P_TX_LP | \
 136                                          GEN_SW_2P_TX_LP | \
 137                                          GEN_SW_1P_TX_LP | \
 138                                          GEN_SW_0P_TX_LP)
 139
 140 #define DSI_GEN_HDR                     0x6c
 141 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 142 #define GEN_HDATA_MASK                  (0xffff << 8)
 143 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 144 #define GEN_HTYPE_MASK                  0xff
 145
 146 #define DSI_GEN_PLD_DATA                0x70
 147
 148 #define DSI_CMD_PKT_STATUS              0x74
 149 #define GEN_CMD_EMPTY                   BIT(0)
 150 #define GEN_CMD_FULL                    BIT(1)
 151 #define GEN_PLD_W_EMPTY                 BIT(2)
 152 #define GEN_PLD_W_FULL                  BIT(3)
 153 #define GEN_PLD_R_EMPTY                 BIT(4)
 154 #define GEN_PLD_R_FULL                  BIT(5)
 155 #define GEN_RD_CMD_BUSY                 BIT(6)
 156
 157 #define DSI_TO_CNT_CFG                  0x78
 158 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 159 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 160
 161 #define DSI_BTA_TO_CNT                  0x8c
 162 #define DSI_LPCLK_CTRL                  0x94
 163 #define AUTO_CLKLANE_CTRL               BIT(1)
 164 #define PHY_TXREQUESTCLKHS              BIT(0)
 165
 166 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 167 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 168 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 169
 170 #define DSI_PHY_TMR_CFG                 0x9c
 171 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 172 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 173 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 174
 175 #define DSI_PHY_RSTZ                    0xa0
 176 #define PHY_DISFORCEPLL                 0
 177 #define PHY_ENFORCEPLL                  BIT(3)
 178 #define PHY_DISABLECLK                  0
 179 #define PHY_ENABLECLK                   BIT(2)
 180 #define PHY_RSTZ                        0
 181 #define PHY_UNRSTZ                      BIT(1)
 182 #define PHY_SHUTDOWNZ                   0
 183 #define PHY_UNSHUTDOWNZ                 BIT(0)
 184
 185 #define DSI_PHY_IF_CFG                  0xa4
 186 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 187 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 188
 189 #define DSI_PHY_STATUS                  0xb0
 190 #define LOCK                            BIT(0)
 191 #define STOP_STATE_CLK_LANE             BIT(2)
 192
 193 #define DSI_PHY_TST_CTRL0               0xb4
 194 #define PHY_TESTCLK                     BIT(1)
 195 #define PHY_UNTESTCLK                   0
 196 #define PHY_TESTCLR                     BIT(0)
 197 #define PHY_UNTESTCLR                   0
 198
 199 #define DSI_PHY_TST_CTRL1               0xb8
 200 #define PHY_TESTEN                      BIT(16)
 201 #define PHY_UNTESTEN                    0
 202 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 203 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 204
 205 #define DSI_INT_ST0                     0xbc
 206 #define DSI_INT_ST1                     0xc0
 207 #define DSI_INT_MSK0                    0xc4
 208 #define DSI_INT_MSK1                    0xc8
 209
 210 #define PHY_STATUS_TIMEOUT_US           10000
 211 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 212
 213 #define BYPASS_VCO_RANGE        BIT(7)
 214 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 215 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 216 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 217 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 218 #define REF_BIAS_CUR_SEL        BIT(0)
 219
 220 #define CP_CURRENT_3MA          BIT(3)
 221 #define CP_PROGRAM_EN           BIT(7)
 222 #define LPF_PROGRAM_EN          BIT(6)
 223 #define LPF_RESISTORS_20_KOHM   0
 224
 225 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 226
 227 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 228 #define LOW_PROGRAM_EN          0
 229 #define HIGH_PROGRAM_EN         BIT(7)
 230 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 231 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 232 #define PLL_LOOP_DIV_EN         BIT(5)
 233 #define PLL_INPUT_DIV_EN        BIT(4)
 234
 235 #define POWER_CONTROL           BIT(6)
 236 #define INTERNAL_REG_CURRENT    BIT(3)
 237 #define BIAS_BLOCK_ON           BIT(2)
 238 #define BANDGAP_ON              BIT(0)
 239
 240 #define TER_RESISTOR_HIGH       BIT(7)
 241 #define TER_RESISTOR_LOW        0
 242 #define LEVEL_SHIFTERS_ON       BIT(6)
 243 #define TER_CAL_DONE            BIT(5)
 244 #define SETRD_MAX               (0x7 << 2)
 245 #define POWER_MANAGE            BIT(1)
 246 #define TER_RESISTORS_ON        BIT(0)
 247
 248 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 249 #define BANDGAP_SEL(val)        ((val) & 0x7)
 250 #define TLP_PROGRAM_EN          BIT(7)
 251 #define THS_PRE_PROGRAM_EN      BIT(7)
 252 #define THS_ZERO_PROGRAM_EN     BIT(6)
 253
 254 enum {
 255         BANDGAP_97_07,
 256         BANDGAP_98_05,
 257         BANDGAP_99_02,
 258         BANDGAP_100_00,
 259         BANDGAP_93_17,
 260         BANDGAP_94_15,
 261         BANDGAP_95_12,
 262         BANDGAP_96_10,
 263 };
 264
 265 enum {
 266         BIASEXTR_87_1,
 267         BIASEXTR_91_5,
 268         BIASEXTR_95_9,
 269         BIASEXTR_100,
 270         BIASEXTR_105_94,
 271         BIASEXTR_111_88,
 272         BIASEXTR_118_8,
 273         BIASEXTR_127_7,
 274 };
 275
 276 struct dw_mipi_dsi_plat_data {
 277         u32 dsi0_en_bit;
 278         u32 dsi1_en_bit;
 279         u32 grf_switch_reg;
 280         u32 grf_dsi0_mode;
 281         u32 grf_dsi0_mode_reg;
 282         unsigned int max_data_lanes;
 283         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 284                                            struct drm_display_mode *mode);
 285 };
 286
 287 struct dw_mipi_dsi {
 288         struct drm_encoder encoder;
 289         struct drm_connector connector;
 290         struct mipi_dsi_host dsi_host;
 291         struct drm_panel *panel;
 292         struct device *dev;
 293         struct regmap *grf_regmap;
 294         void __iomem *base;
 295
 296         struct clk *pllref_clk;
 297         struct clk *pclk;
 298         struct clk *phy_cfg_clk;
 299
 300         unsigned int lane_mbps; /* per lane */
 301         u32 channel;
 302         u32 lanes;
 303         u32 format;
 304         u16 input_div;
 305         u16 feedback_div;
 306         struct drm_display_mode mode;
 307
 308         const struct dw_mipi_dsi_plat_data *pdata;
 309 };
 310
 311 enum dw_mipi_dsi_mode {
 312         DW_MIPI_DSI_CMD_MODE,
 313         DW_MIPI_DSI_VID_MODE,
 314 };
 315
 316 struct dphy_pll_testdin_map {
 317         unsigned int max_mbps;
 318         u8 testdin;
 319 };
 320
 321 /* The table is based on 27MHz DPHY pll reference clock. */
 322 static const struct dphy_pll_testdin_map dptdin_map[] = {
 323         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 324         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 325         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 326         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 327         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 328         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 329         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 330         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 331         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 332         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 333 };
 334
 335 static int max_mbps_to_testdin(unsigned int max_mbps)
 336 {
 337         int i;
 338
 339         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 340                 if (dptdin_map[i].max_mbps > max_mbps)
 341                         return dptdin_map[i].testdin;
 342
 343         return -EINVAL;
 344 }
 345
 346 /*
 347  * The controller should generate 2 frames before
 348  * preparing the peripheral.
 349  */
 350 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 351 {
 352         int refresh, two_frames;
 353
 354         refresh = drm_mode_vrefresh(&dsi->mode);
 355         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 356         msleep(two_frames);
 357 }
 358
 359 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 360 {
 361         return container_of(host, struct dw_mipi_dsi, dsi_host);
 362 }
 363
 364 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 365 {
 366         return container_of(con, struct dw_mipi_dsi, connector);
 367 }
 368
 369 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 370 {
 371         return container_of(encoder, struct dw_mipi_dsi, encoder);
 372 }
 373 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 374 {
 375         writel(val, dsi->base + reg);
 376 }
 377
 378 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 379 {
 380         return readl(dsi->base + reg);
 381 }
 382
 383 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 384                                  u8 test_data)
 385 {
 386         /*
 387          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 388          * is latched internally as the current test code. Test data is
 389          * programmed internally by rising edge on TESTCLK.
 390          */
 391         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 392
 393         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 394                                           PHY_TESTDIN(test_code));
 395
 396         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 397
 398         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 399                                           PHY_TESTDIN(test_data));
 400
 401         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 402 }
 403
 404 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 405 {
 406         int ret, testdin, vco, val;
 407
 408         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 409
 410         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 411         if (testdin < 0) {
 412                 dev_err(dsi->dev,
 413                         "failed to get testdin for %dmbps lane clock\n",
 414                         dsi->lane_mbps);
 415                 return testdin;
 416         }
 417
 418         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 419
 420         if (!IS_ERR(dsi->phy_cfg_clk)) {
 421                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 422                 if (ret) {
 423                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 424                         return ret;
 425                 }
 426         }
 427
 428         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 429                                          VCO_RANGE_CON_SEL(vco) |
 430                                          VCO_IN_CAP_CON_LOW |
 431                                          REF_BIAS_CUR_SEL);
 432
 433         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 434         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 435                                          LPF_RESISTORS_20_KOHM);
 436
 437         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 438
 439         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 440         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 441         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 442                                          LOW_PROGRAM_EN);
 443         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 444                                          HIGH_PROGRAM_EN);
 445
 446         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 447                                          BIAS_BLOCK_ON | BANDGAP_ON);
 448
 449         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 450                                          SETRD_MAX | TER_RESISTORS_ON);
 451         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 452                                          SETRD_MAX | POWER_MANAGE |
 453                                          TER_RESISTORS_ON);
 454
 455         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 456                                          BIASEXTR_SEL(BIASEXTR_127_7));
 457         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 458                                          BANDGAP_SEL(BANDGAP_96_10));
 459
 460         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 461         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 462         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 463
 464         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 465                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 466
 467
 468         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 469                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 470         if (ret < 0) {
 471                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 472                 goto phy_init_end;
 473         }
 474
 475         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 476                                  val, val & STOP_STATE_CLK_LANE, 1000,
 477                                  PHY_STATUS_TIMEOUT_US);
 478         if (ret < 0)
 479                 dev_err(dsi->dev,
 480                         "failed to wait for phy clk lane stop state\n");
 481
 482 phy_init_end:
 483         if (!IS_ERR(dsi->phy_cfg_clk))
 484                 clk_disable_unprepare(dsi->phy_cfg_clk);
 485
 486         return ret;
 487 }
 488
 489 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 490 {
 491         unsigned int i, pre;
 492         unsigned long mpclk, pllref, tmp;
 493         unsigned int m = 1, n = 1, target_mbps = 1000;
 494         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 495         int bpp;
 496
 497         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 498         if (bpp < 0) {
 499                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 500                         dsi->format);
 501                 return bpp;
 502         }
 503
 504         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 505         if (mpclk) {
 506                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 507                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 508                 if (tmp < max_mbps)
 509                         target_mbps = tmp;
 510                 else
 511                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 512         }
 513
 514         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 515         tmp = pllref;
 516
 517         for (i = 1; i < 6; i++) {
 518                 pre = pllref / i;
 519                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 520                         tmp = target_mbps % pre;
 521                         n = i;
 522                         m = target_mbps / pre;
 523                 }
 524                 if (tmp == 0)
 525                         break;
 526         }
 527
 528         dsi->lane_mbps = pllref / n * m;
 529         dsi->input_div = n;
 530         dsi->feedback_div = m;
 531
 532         return 0;
 533 }
 534
 535 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 536                                    struct mipi_dsi_device *device)
 537 {
 538         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 539
 540         if (device->lanes > dsi->pdata->max_data_lanes) {
 541                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 542                                 device->lanes);
 543                 return -EINVAL;
 544         }
 545
 546         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
 547             !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
 548                 dev_err(dsi->dev, "device mode is unsupported\n");
 549                 return -EINVAL;
 550         }
 551
 552         dsi->lanes = device->lanes;
 553         dsi->channel = device->channel;
 554         dsi->format = device->format;
 555         dsi->panel = of_drm_find_panel(device->dev.of_node);
 556         if (!dsi->panel) {
 557                 DRM_ERROR("failed to find panel\n");
 558                 return -ENODEV;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 565                                    struct mipi_dsi_device *device)
 566 {
 567         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 568
 569         if (dsi->panel)
 570                 drm_panel_detach(dsi->panel);
 571
 572         dsi->panel = NULL;
 573         return 0;
 574 }
 575
 576 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 577 {
 578         int ret;
 579         int sts = 0;
 580
 581         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 582                                  sts, !(sts & GEN_CMD_FULL), 1000,
 583                                  CMD_PKT_STATUS_TIMEOUT_US);
 584
 585         if (ret < 0) {
 586                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 587                 return ret;
 588         }
 589
 590         dsi_write(dsi, DSI_GEN_HDR, val);
 591
 592         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 593                                  sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 594                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 595
 596         if (ret < 0) {
 597                 dev_err(dsi->dev, "failed to write command FIFO\n");
 598                 return ret;
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
 605                                    const struct mipi_dsi_msg *msg)
 606 {
 607         const u16 *tx_buf = msg->tx_buf;
 608         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 609
 610         if (msg->tx_len > 2) {
 611                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 612                         msg->tx_len);
 613                 return -EINVAL;
 614         }
 615
 616         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 617 }
 618
 619 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
 620                                   const struct mipi_dsi_msg *msg)
 621 {
 622         const u32 *tx_buf = msg->tx_buf;
 623         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 624         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 625         u32 remainder = 0;
 626         u32 sts = 0;
 627
 628         if (msg->tx_len < 3) {
 629                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 630                         msg->tx_len);
 631                 return -EINVAL;
 632         }
 633
 634         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 635                 if (len < pld_data_bytes) {
 636                         memcpy(&remainder, tx_buf, len);
 637                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 638                         len = 0;
 639                 } else {
 640                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 641                         tx_buf++;
 642                         len -= pld_data_bytes;
 643                 }
 644
 645                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 646                                          sts, !(sts & GEN_PLD_W_FULL), 1000,
 647                                          CMD_PKT_STATUS_TIMEOUT_US);
 648                 if (ret < 0) {
 649                         dev_err(dsi->dev,
 650                                 "failed to get available write payload FIFO\n");
 651                         return ret;
 652                 }
 653         }
 654
 655         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 656 }
 657
 658 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 659                                          const struct mipi_dsi_msg *msg)
 660 {
 661         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 662         int ret;
 663
 664         switch (msg->type) {
 665         case MIPI_DSI_DCS_SHORT_WRITE:
 666         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 667         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 668         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 669         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 670         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 671                 ret = dw_mipi_dsi_short_write(dsi, msg);
 672                 break;
 673         case MIPI_DSI_DCS_LONG_WRITE:
 674         case MIPI_DSI_GENERIC_LONG_WRITE:
 675                 ret = dw_mipi_dsi_long_write(dsi, msg);
 676                 break;
 677         default:
 678                 dev_err(dsi->dev, "unsupported message type\n");
 679                 ret = -EINVAL;
 680         }
 681
 682         return ret;
 683 }
 684
 685 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 686         .attach = dw_mipi_dsi_host_attach,
 687         .detach = dw_mipi_dsi_host_detach,
 688         .transfer = dw_mipi_dsi_host_transfer,
 689 };
 690
 691 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 692 {
 693         u32 val;
 694
 695         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 696
 697         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 698 }
 699
 700 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 701                                  enum dw_mipi_dsi_mode mode)
 702 {
 703         if (mode == DW_MIPI_DSI_CMD_MODE) {
 704                 dsi_write(dsi, DSI_PWR_UP, RESET);
 705                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 706                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 707         } else {
 708                 dsi_write(dsi, DSI_PWR_UP, RESET);
 709                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 710                 dw_mipi_dsi_video_mode_config(dsi);
 711                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 712         }
 713 }
 714
 715 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 716 {
 717         dsi_write(dsi, DSI_PWR_UP, RESET);
 718         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 719 }
 720
 721 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 722 {
 723         dsi_write(dsi, DSI_PWR_UP, RESET);
 724         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 725                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 726         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 727                   TX_ESC_CLK_DIVIDSION(7));
 728         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 729 }
 730
 731 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 732                                    struct drm_display_mode *mode)
 733 {
 734         u32 val = 0, color = 0;
 735
 736         switch (dsi->format) {
 737         case MIPI_DSI_FMT_RGB888:
 738                 color = DPI_COLOR_CODING_24BIT;
 739                 break;
 740         case MIPI_DSI_FMT_RGB666:
 741                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 742                 break;
 743         case MIPI_DSI_FMT_RGB666_PACKED:
 744                 color = DPI_COLOR_CODING_18BIT_1;
 745                 break;
 746         case MIPI_DSI_FMT_RGB565:
 747                 color = DPI_COLOR_CODING_16BIT_1;
 748                 break;
 749         }
 750
 751         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 752                 val |= VSYNC_ACTIVE_LOW;
 753         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 754                 val |= HSYNC_ACTIVE_LOW;
 755
 756         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 757         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 758         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 759         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 760                   | INVACT_LPCMD_TIME(4));
 761 }
 762
 763 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 764 {
 765         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 766 }
 767
 768 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 769                                             struct drm_display_mode *mode)
 770 {
 771         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 772 }
 773
 774 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 775 {
 776         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 777         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 778         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 779         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 780 }
 781
 782 /* Get lane byte clock cycles. */
 783 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 784                                            u32 hcomponent)
 785 {
 786         u32 frac, lbcc;
 787
 788         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 789
 790         frac = lbcc % dsi->mode.clock;
 791         lbcc = lbcc / dsi->mode.clock;
 792         if (frac)
 793                 lbcc++;
 794
 795         return lbcc;
 796 }
 797
 798 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 799 {
 800         u32 htotal, hsa, hbp, lbcc;
 801         struct drm_display_mode *mode = &dsi->mode;
 802
 803         htotal = mode->htotal;
 804         hsa = mode->hsync_end - mode->hsync_start;
 805         hbp = mode->htotal - mode->hsync_end;
 806
 807         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 808         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 809
 810         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 811         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 812
 813         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 814         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 815 }
 816
 817 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 818 {
 819         u32 vactive, vsa, vfp, vbp;
 820         struct drm_display_mode *mode = &dsi->mode;
 821
 822         vactive = mode->vdisplay;
 823         vsa = mode->vsync_end - mode->vsync_start;
 824         vfp = mode->vsync_start - mode->vdisplay;
 825         vbp = mode->vtotal - mode->vsync_end;
 826
 827         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 828         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 829         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 830         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 831 }
 832
 833 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 834 {
 835         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 836                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 837
 838         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 839                   | PHY_CLKLP2HS_TIME(0x40));
 840 }
 841
 842 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 843 {
 844         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 845                   N_LANES(dsi->lanes));
 846 }
 847
 848 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 849 {
 850         dsi_read(dsi, DSI_INT_ST0);
 851         dsi_read(dsi, DSI_INT_ST1);
 852         dsi_write(dsi, DSI_INT_MSK0, 0);
 853         dsi_write(dsi, DSI_INT_MSK1, 0);
 854 }
 855
 856 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 857                                         struct drm_display_mode *mode,
 858                                         struct drm_display_mode *adjusted_mode)
 859 {
 860         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 861
 862         drm_mode_copy(&dsi->mode, adjusted_mode);
 863 }
 864
 865 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 866 {
 867         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 868
 869         drm_panel_disable(dsi->panel);
 870
 871         if (clk_prepare_enable(dsi->pclk)) {
 872                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 873                 return;
 874         }
 875
 876         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 877         drm_panel_unprepare(dsi->panel);
 878         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 879
 880         /*
 881          * This is necessary to make sure the peripheral will be driven
 882          * normally when the display is enabled again later.
 883          */
 884         msleep(120);
 885
 886         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 887         dw_mipi_dsi_disable(dsi);
 888         pm_runtime_put(dsi->dev);
 889         clk_disable_unprepare(dsi->pclk);
 890 }
 891
 892 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 893                                         const struct drm_display_mode *mode,
 894                                         struct drm_display_mode *adjusted_mode)
 895 {
 896         return true;
 897 }
 898
 899 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 900 {
 901         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 902         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 903         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 904         int ret;
 905         u32 val;
 906
 907         if (clk_prepare_enable(dsi->pclk)) {
 908                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 909                 return;
 910         }
 911
 912         ret = dw_mipi_dsi_get_lane_bps(dsi);
 913         if (ret < 0)
 914                 return;
 915
 916         pm_runtime_get_sync(dsi->dev);
 917
 918         dw_mipi_dsi_init(dsi);
 919         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 920         dw_mipi_dsi_packet_handler_config(dsi);
 921         dw_mipi_dsi_video_mode_config(dsi);
 922         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 923         dw_mipi_dsi_command_mode_config(dsi);
 924         dw_mipi_dsi_line_timer_config(dsi);
 925         dw_mipi_dsi_vertical_timing_config(dsi);
 926         dw_mipi_dsi_dphy_timing_config(dsi);
 927         dw_mipi_dsi_dphy_interface_config(dsi);
 928         dw_mipi_dsi_clear_err(dsi);
 929         if (drm_panel_prepare(dsi->panel))
 930                 dev_err(dsi->dev, "failed to prepare panel\n");
 931
 932         if (pdata->grf_dsi0_mode_reg)
 933                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 934                              pdata->grf_dsi0_mode);
 935
 936         dw_mipi_dsi_phy_init(dsi);
 937         dw_mipi_dsi_wait_for_two_frames(dsi);
 938
 939         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 940         drm_panel_enable(dsi->panel);
 941
 942         clk_disable_unprepare(dsi->pclk);
 943
 944         if (mux)
 945                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 946         else
 947                 val = pdata->dsi0_en_bit << 16;
 948
 949         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 950         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 951 }
 952
 953 static int
 954 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 955                                  struct drm_crtc_state *crtc_state,
 956                                  struct drm_connector_state *conn_state)
 957 {
 958         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 959         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 960         struct drm_connector *connector = conn_state->connector;
 961         struct drm_display_info *info = &connector->display_info;
 962
 963         switch (dsi->format) {
 964         case MIPI_DSI_FMT_RGB888:
 965                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 966                 break;
 967         case MIPI_DSI_FMT_RGB666:
 968                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 969                 break;
 970         case MIPI_DSI_FMT_RGB565:
 971                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 972                 break;
 973         default:
 974                 WARN_ON(1);
 975                 return -EINVAL;
 976         }
 977
 978         s->output_type = DRM_MODE_CONNECTOR_DSI;
 979         if (info->num_bus_formats)
 980                 s->bus_format = info->bus_formats[0];
 981
 982         return 0;
 983 }
 984
 985 static struct drm_encoder_helper_funcs
 986 dw_mipi_dsi_encoder_helper_funcs = {
 987         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
 988         .mode_set = dw_mipi_dsi_encoder_mode_set,
 989         .enable = dw_mipi_dsi_encoder_enable,
 990         .disable = dw_mipi_dsi_encoder_disable,
 991         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 992 };
 993
 994 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
 995         .destroy = drm_encoder_cleanup,
 996 };
 997
 998 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
 999 {
1000         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1001
1002         return drm_panel_get_modes(dsi->panel);
1003 }
1004
1005 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1006                                         struct drm_connector *connector,
1007                                         struct drm_display_mode *mode)
1008 {
1009         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1010
1011         enum drm_mode_status mode_status = MODE_OK;
1012
1013         if (dsi->pdata->mode_valid)
1014                 mode_status = dsi->pdata->mode_valid(connector, mode);
1015
1016         return mode_status;
1017 }
1018
1019 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1020                                         struct drm_connector *connector)
1021 {
1022         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1023
1024         return &dsi->encoder;
1025 }
1026
1027 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1028         .get_modes = dw_mipi_dsi_connector_get_modes,
1029         .mode_valid = dw_mipi_dsi_mode_valid,
1030         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1031 };
1032
1033 static enum drm_connector_status
1034 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1035 {
1036         return connector_status_connected;
1037 }
1038
1039 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1040 {
1041         drm_connector_unregister(connector);
1042         drm_connector_cleanup(connector);
1043 }
1044
1045 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1046         .dpms = drm_atomic_helper_connector_dpms,
1047         .fill_modes = drm_helper_probe_single_connector_modes,
1048         .detect = dw_mipi_dsi_detect,
1049         .destroy = dw_mipi_dsi_drm_connector_destroy,
1050         .reset = drm_atomic_helper_connector_reset,
1051         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1052         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1053 };
1054
1055 static int dw_mipi_dsi_register(struct drm_device *drm,
1056                                       struct dw_mipi_dsi *dsi)
1057 {
1058         struct drm_encoder *encoder = &dsi->encoder;
1059         struct drm_connector *connector = &dsi->connector;
1060         struct device *dev = dsi->dev;
1061         int ret;
1062
1063         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1064                                                              dev->of_node);
1065         /*
1066          * If we failed to find the CRTC(s) which this encoder is
1067          * supposed to be connected to, it's because the CRTC has
1068          * not been registered yet.  Defer probing, and hope that
1069          * the required CRTC is added later.
1070          */
1071         if (encoder->possible_crtcs == 0)
1072                 return -EPROBE_DEFER;
1073
1074         drm_encoder_helper_add(&dsi->encoder,
1075                                &dw_mipi_dsi_encoder_helper_funcs);
1076         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1077                          DRM_MODE_ENCODER_DSI, NULL);
1078         if (ret) {
1079                 dev_err(dev, "Failed to initialize encoder with drm\n");
1080                 return ret;
1081         }
1082
1083         drm_connector_helper_add(connector,
1084                         &dw_mipi_dsi_connector_helper_funcs);
1085
1086         drm_connector_init(drm, &dsi->connector,
1087                            &dw_mipi_dsi_atomic_connector_funcs,
1088                            DRM_MODE_CONNECTOR_DSI);
1089
1090         drm_panel_attach(dsi->panel, &dsi->connector);
1091
1092         dsi->connector.port = dev->of_node;
1093
1094         drm_mode_connector_attach_encoder(connector, encoder);
1095
1096         return 0;
1097 }
1098
1099 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1100 {
1101         struct device_node *np = dsi->dev->of_node;
1102
1103         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1104         if (IS_ERR(dsi->grf_regmap)) {
1105                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1106                 return PTR_ERR(dsi->grf_regmap);
1107         }
1108
1109         return 0;
1110 }
1111
1112 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1113         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1114         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1115         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1116         .max_data_lanes = 4,
1117 };
1118
1119 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1120         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1121         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1122         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1123         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1124         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1125         .max_data_lanes = 4,
1126 };
1127
1128 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1129         {
1130          .compatible = "rockchip,rk3288-mipi-dsi",
1131          .data = &rk3288_mipi_dsi_drv_data,
1132         },{
1133          .compatible = "rockchip,rk3399-mipi-dsi",
1134          .data = &rk3399_mipi_dsi_drv_data,
1135         },
1136         { /* sentinel */ }
1137 };
1138 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1139
1140 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1141                              void *data)
1142 {
1143         struct platform_device *pdev = to_platform_device(dev);
1144         struct drm_device *drm = data;
1145         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1146         struct resource *res;
1147         int ret;
1148
1149         if (!dsi->panel)
1150                 return -EPROBE_DEFER;
1151
1152         ret = rockchip_mipi_parse_dt(dsi);
1153         if (ret)
1154                 return ret;
1155
1156         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1157         if (!res)
1158                 return -ENODEV;
1159
1160         dsi->base = devm_ioremap_resource(dev, res);
1161         if (IS_ERR(dsi->base))
1162                 return PTR_ERR(dsi->base);
1163
1164         dsi->pllref_clk = devm_clk_get(dev, "ref");
1165         if (IS_ERR(dsi->pllref_clk)) {
1166                 ret = PTR_ERR(dsi->pllref_clk);
1167                 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1168                 return ret;
1169         }
1170
1171         dsi->pclk = devm_clk_get(dev, "pclk");
1172         if (IS_ERR(dsi->pclk)) {
1173                 ret = PTR_ERR(dsi->pclk);
1174                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1175                 return ret;
1176         }
1177
1178         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1179         if (IS_ERR(dsi->phy_cfg_clk))
1180                 dev_dbg(dev, "have not phy_cfg_clk\n");
1181
1182         ret = clk_prepare_enable(dsi->pllref_clk);
1183         if (ret) {
1184                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1185                 return ret;
1186         }
1187
1188         ret = dw_mipi_dsi_register(drm, dsi);
1189         if (ret) {
1190                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1191                 goto err_pllref;
1192         }
1193
1194         dev_set_drvdata(dev, dsi);
1195
1196         pm_runtime_enable(dev);
1197
1198         return 0;
1199
1200 err_pllref:
1201         clk_disable_unprepare(dsi->pllref_clk);
1202         return ret;
1203 }
1204
1205 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1206         void *data)
1207 {
1208         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1209
1210         pm_runtime_disable(dev);
1211         clk_disable_unprepare(dsi->pllref_clk);
1212 }
1213
1214 static const struct component_ops dw_mipi_dsi_ops = {
1215         .bind   = dw_mipi_dsi_bind,
1216         .unbind = dw_mipi_dsi_unbind,
1217 };
1218
1219 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1220 {
1221         struct device *dev = &pdev->dev;
1222         const struct of_device_id *of_id =
1223                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1224         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1225         struct dw_mipi_dsi *dsi;
1226         int ret;
1227
1228         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1229         if (!dsi)
1230                 return -ENOMEM;
1231
1232         dsi->dev = dev;
1233         dsi->pdata = pdata;
1234         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1235         dsi->dsi_host.dev = &pdev->dev;
1236
1237         ret = mipi_dsi_host_register(&dsi->dsi_host);
1238         if (ret)
1239                 return ret;
1240
1241         platform_set_drvdata(pdev, dsi);
1242         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1243         if (ret)
1244                 mipi_dsi_host_unregister(&dsi->dsi_host);
1245
1246         return ret;
1247 }
1248
1249 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1250 {
1251         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1252
1253         if (dsi)
1254                 mipi_dsi_host_unregister(&dsi->dsi_host);
1255         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1256         return 0;
1257 }
1258
1259 static struct platform_driver dw_mipi_dsi_driver = {
1260         .probe          = dw_mipi_dsi_probe,
1261         .remove         = dw_mipi_dsi_remove,
1262         .driver         = {
1263                 .of_match_table = dw_mipi_dsi_dt_ids,
1264                 .name   = DRIVER_NAME,
1265         },
1266 };
1267 module_platform_driver(dw_mipi_dsi_driver);
1268
1269 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1270 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1271 MODULE_LICENSE("GPL");
1272 MODULE_ALIAS("platform:" DRIVER_NAME);