drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_mipi_dsi.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_panel.h>
  23 #include <drm/drmP.h>
  24 #include <video/mipi_display.h>
  25
  26 #include "rockchip_drm_drv.h"
  27 #include "rockchip_drm_vop.h"
  28
  29 #define DRIVER_NAME    "dw-mipi-dsi"
  30
  31 #define RK3288_GRF_SOC_CON6             0x025c
  32 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  33 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  34
  35 #define RK3399_GRF_SOC_CON19            0x6250
  36 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  37 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  38
  39 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  40 #define RK3399_GRF_SOC_CON22            0x6258
  41 #define RK3399_GRF_DSI_MODE             0xffff0000
  42
  43 #define DSI_VERSION                     0x00
  44 #define DSI_PWR_UP                      0x04
  45 #define RESET                           0
  46 #define POWERUP                         BIT(0)
  47
  48 #define DSI_CLKMGR_CFG                  0x08
  49 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  50 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  51
  52 #define DSI_DPI_VCID                    0x0c
  53 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  54
  55 #define DSI_DPI_COLOR_CODING            0x10
  56 #define EN18_LOOSELY                    BIT(8)
  57 #define DPI_COLOR_CODING_16BIT_1        0x0
  58 #define DPI_COLOR_CODING_16BIT_2        0x1
  59 #define DPI_COLOR_CODING_16BIT_3        0x2
  60 #define DPI_COLOR_CODING_18BIT_1        0x3
  61 #define DPI_COLOR_CODING_18BIT_2        0x4
  62 #define DPI_COLOR_CODING_24BIT          0x5
  63
  64 #define DSI_DPI_CFG_POL                 0x14
  65 #define COLORM_ACTIVE_LOW               BIT(4)
  66 #define SHUTD_ACTIVE_LOW                BIT(3)
  67 #define HSYNC_ACTIVE_LOW                BIT(2)
  68 #define VSYNC_ACTIVE_LOW                BIT(1)
  69 #define DATAEN_ACTIVE_LOW               BIT(0)
  70
  71 #define DSI_DPI_LP_CMD_TIM              0x18
  72 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  73 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  74
  75 #define DSI_DBI_CFG                     0x20
  76 #define DSI_DBI_CMDSIZE                 0x28
  77
  78 #define DSI_PCKHDL_CFG                  0x2c
  79 #define EN_CRC_RX                       BIT(4)
  80 #define EN_ECC_RX                       BIT(3)
  81 #define EN_BTA                          BIT(2)
  82 #define EN_EOTP_RX                      BIT(1)
  83 #define EN_EOTP_TX                      BIT(0)
  84
  85 #define DSI_MODE_CFG                    0x34
  86 #define ENABLE_VIDEO_MODE               0
  87 #define ENABLE_CMD_MODE                 BIT(0)
  88
  89 #define DSI_VID_MODE_CFG                0x38
  90 #define FRAME_BTA_ACK                   BIT(14)
  91 #define ENABLE_LOW_POWER                (0x3f << 8)
  92 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  93 #define VID_MODE_TYPE_BURST_SYNC_PULSES         0x2
  94 #define VID_MODE_TYPE_MASK                      0x3
  95
  96 #define DSI_VID_PKT_SIZE                0x3c
  97 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
  98 #define VID_PKT_MAX_SIZE                0x3fff
  99
 100 #define DSI_VID_HSA_TIME                0x48
 101 #define DSI_VID_HBP_TIME                0x4c
 102 #define DSI_VID_HLINE_TIME              0x50
 103 #define DSI_VID_VSA_LINES               0x54
 104 #define DSI_VID_VBP_LINES               0x58
 105 #define DSI_VID_VFP_LINES               0x5c
 106 #define DSI_VID_VACTIVE_LINES           0x60
 107 #define DSI_CMD_MODE_CFG                0x68
 108 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 109 #define DCS_LW_TX_LP                    BIT(19)
 110 #define DCS_SR_0P_TX_LP                 BIT(18)
 111 #define DCS_SW_1P_TX_LP                 BIT(17)
 112 #define DCS_SW_0P_TX_LP                 BIT(16)
 113 #define GEN_LW_TX_LP                    BIT(14)
 114 #define GEN_SR_2P_TX_LP                 BIT(13)
 115 #define GEN_SR_1P_TX_LP                 BIT(12)
 116 #define GEN_SR_0P_TX_LP                 BIT(11)
 117 #define GEN_SW_2P_TX_LP                 BIT(10)
 118 #define GEN_SW_1P_TX_LP                 BIT(9)
 119 #define GEN_SW_0P_TX_LP                 BIT(8)
 120 #define EN_ACK_RQST                     BIT(1)
 121 #define EN_TEAR_FX                      BIT(0)
 122
 123 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 124                                          DCS_LW_TX_LP | \
 125                                          DCS_SR_0P_TX_LP | \
 126                                          DCS_SW_1P_TX_LP | \
 127                                          DCS_SW_0P_TX_LP | \
 128                                          GEN_LW_TX_LP | \
 129                                          GEN_SR_2P_TX_LP | \
 130                                          GEN_SR_1P_TX_LP | \
 131                                          GEN_SR_0P_TX_LP | \
 132                                          GEN_SW_2P_TX_LP | \
 133                                          GEN_SW_1P_TX_LP | \
 134                                          GEN_SW_0P_TX_LP)
 135
 136 #define DSI_GEN_HDR                     0x6c
 137 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 138 #define GEN_HDATA_MASK                  (0xffff << 8)
 139 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 140 #define GEN_HTYPE_MASK                  0xff
 141
 142 #define DSI_GEN_PLD_DATA                0x70
 143
 144 #define DSI_CMD_PKT_STATUS              0x74
 145 #define GEN_CMD_EMPTY                   BIT(0)
 146 #define GEN_CMD_FULL                    BIT(1)
 147 #define GEN_PLD_W_EMPTY                 BIT(2)
 148 #define GEN_PLD_W_FULL                  BIT(3)
 149 #define GEN_PLD_R_EMPTY                 BIT(4)
 150 #define GEN_PLD_R_FULL                  BIT(5)
 151 #define GEN_RD_CMD_BUSY                 BIT(6)
 152
 153 #define DSI_TO_CNT_CFG                  0x78
 154 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 155 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 156
 157 #define DSI_BTA_TO_CNT                  0x8c
 158 #define DSI_LPCLK_CTRL                  0x94
 159 #define AUTO_CLKLANE_CTRL               BIT(1)
 160 #define PHY_TXREQUESTCLKHS              BIT(0)
 161
 162 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 163 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 164 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 165
 166 #define DSI_PHY_TMR_CFG                 0x9c
 167 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 168 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 169 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 170
 171 #define DSI_PHY_RSTZ                    0xa0
 172 #define PHY_DISFORCEPLL                 0
 173 #define PHY_ENFORCEPLL                  BIT(3)
 174 #define PHY_DISABLECLK                  0
 175 #define PHY_ENABLECLK                   BIT(2)
 176 #define PHY_RSTZ                        0
 177 #define PHY_UNRSTZ                      BIT(1)
 178 #define PHY_SHUTDOWNZ                   0
 179 #define PHY_UNSHUTDOWNZ                 BIT(0)
 180
 181 #define DSI_PHY_IF_CFG                  0xa4
 182 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 183 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 184
 185 #define DSI_PHY_STATUS                  0xb0
 186 #define LOCK                            BIT(0)
 187 #define STOP_STATE_CLK_LANE             BIT(2)
 188
 189 #define DSI_PHY_TST_CTRL0               0xb4
 190 #define PHY_TESTCLK                     BIT(1)
 191 #define PHY_UNTESTCLK                   0
 192 #define PHY_TESTCLR                     BIT(0)
 193 #define PHY_UNTESTCLR                   0
 194
 195 #define DSI_PHY_TST_CTRL1               0xb8
 196 #define PHY_TESTEN                      BIT(16)
 197 #define PHY_UNTESTEN                    0
 198 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 199 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 200
 201 #define DSI_INT_ST0                     0xbc
 202 #define DSI_INT_ST1                     0xc0
 203 #define DSI_INT_MSK0                    0xc4
 204 #define DSI_INT_MSK1                    0xc8
 205
 206 #define PHY_STATUS_TIMEOUT_US           10000
 207 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 208
 209 #define BYPASS_VCO_RANGE        BIT(7)
 210 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 211 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 212 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 213 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 214 #define REF_BIAS_CUR_SEL        BIT(0)
 215
 216 #define CP_CURRENT_3MA          BIT(3)
 217 #define CP_PROGRAM_EN           BIT(7)
 218 #define LPF_PROGRAM_EN          BIT(6)
 219 #define LPF_RESISTORS_20_KOHM   0
 220
 221 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 222
 223 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 224 #define LOW_PROGRAM_EN          0
 225 #define HIGH_PROGRAM_EN         BIT(7)
 226 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 227 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 228 #define PLL_LOOP_DIV_EN         BIT(5)
 229 #define PLL_INPUT_DIV_EN        BIT(4)
 230
 231 #define POWER_CONTROL           BIT(6)
 232 #define INTERNAL_REG_CURRENT    BIT(3)
 233 #define BIAS_BLOCK_ON           BIT(2)
 234 #define BANDGAP_ON              BIT(0)
 235
 236 #define TER_RESISTOR_HIGH       BIT(7)
 237 #define TER_RESISTOR_LOW        0
 238 #define LEVEL_SHIFTERS_ON       BIT(6)
 239 #define TER_CAL_DONE            BIT(5)
 240 #define SETRD_MAX               (0x7 << 2)
 241 #define POWER_MANAGE            BIT(1)
 242 #define TER_RESISTORS_ON        BIT(0)
 243
 244 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 245 #define BANDGAP_SEL(val)        ((val) & 0x7)
 246 #define TLP_PROGRAM_EN          BIT(7)
 247 #define THS_PRE_PROGRAM_EN      BIT(7)
 248 #define THS_ZERO_PROGRAM_EN     BIT(6)
 249
 250 enum {
 251         BANDGAP_97_07,
 252         BANDGAP_98_05,
 253         BANDGAP_99_02,
 254         BANDGAP_100_00,
 255         BANDGAP_93_17,
 256         BANDGAP_94_15,
 257         BANDGAP_95_12,
 258         BANDGAP_96_10,
 259 };
 260
 261 enum {
 262         BIASEXTR_87_1,
 263         BIASEXTR_91_5,
 264         BIASEXTR_95_9,
 265         BIASEXTR_100,
 266         BIASEXTR_105_94,
 267         BIASEXTR_111_88,
 268         BIASEXTR_118_8,
 269         BIASEXTR_127_7,
 270 };
 271
 272 struct dw_mipi_dsi_plat_data {
 273         u32 dsi0_en_bit;
 274         u32 dsi1_en_bit;
 275         u32 grf_switch_reg;
 276         u32 grf_dsi0_mode;
 277         u32 grf_dsi0_mode_reg;
 278         unsigned int max_data_lanes;
 279         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 280                                            struct drm_display_mode *mode);
 281 };
 282
 283 struct dw_mipi_dsi {
 284         struct drm_encoder encoder;
 285         struct drm_connector connector;
 286         struct mipi_dsi_host dsi_host;
 287         struct drm_panel *panel;
 288         struct device *dev;
 289         struct regmap *grf_regmap;
 290         void __iomem *base;
 291
 292         struct clk *pllref_clk;
 293         struct clk *pclk;
 294         struct clk *phy_cfg_clk;
 295
 296         unsigned int lane_mbps; /* per lane */
 297         u32 channel;
 298         u32 lanes;
 299         u32 format;
 300         u16 input_div;
 301         u16 feedback_div;
 302         struct drm_display_mode *mode;
 303
 304         const struct dw_mipi_dsi_plat_data *pdata;
 305 };
 306
 307 enum dw_mipi_dsi_mode {
 308         DW_MIPI_DSI_CMD_MODE,
 309         DW_MIPI_DSI_VID_MODE,
 310 };
 311
 312 struct dphy_pll_testdin_map {
 313         unsigned int max_mbps;
 314         u8 testdin;
 315 };
 316
 317 /* The table is based on 27MHz DPHY pll reference clock. */
 318 static const struct dphy_pll_testdin_map dptdin_map[] = {
 319         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 320         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 321         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 322         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 323         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 324         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 325         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 326         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 327         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 328         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 329 };
 330
 331 static int max_mbps_to_testdin(unsigned int max_mbps)
 332 {
 333         int i;
 334
 335         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 336                 if (dptdin_map[i].max_mbps > max_mbps)
 337                         return dptdin_map[i].testdin;
 338
 339         return -EINVAL;
 340 }
 341
 342 /*
 343  * The controller should generate 2 frames before
 344  * preparing the peripheral.
 345  */
 346 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 347 {
 348         int refresh, two_frames;
 349
 350         refresh = drm_mode_vrefresh(dsi->mode);
 351         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 352         msleep(two_frames);
 353 }
 354
 355 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 356 {
 357         return container_of(host, struct dw_mipi_dsi, dsi_host);
 358 }
 359
 360 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 361 {
 362         return container_of(con, struct dw_mipi_dsi, connector);
 363 }
 364
 365 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 366 {
 367         return container_of(encoder, struct dw_mipi_dsi, encoder);
 368 }
 369 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 370 {
 371         writel(val, dsi->base + reg);
 372 }
 373
 374 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 375 {
 376         return readl(dsi->base + reg);
 377 }
 378
 379 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 380                                  u8 test_data)
 381 {
 382         /*
 383          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 384          * is latched internally as the current test code. Test data is
 385          * programmed internally by rising edge on TESTCLK.
 386          */
 387         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 388
 389         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 390                                           PHY_TESTDIN(test_code));
 391
 392         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 393
 394         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 395                                           PHY_TESTDIN(test_data));
 396
 397         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 398 }
 399
 400 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 401 {
 402         int ret, testdin, vco, val;
 403
 404         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 405
 406         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 407         if (testdin < 0) {
 408                 dev_err(dsi->dev,
 409                         "failed to get testdin for %dmbps lane clock\n",
 410                         dsi->lane_mbps);
 411                 return testdin;
 412         }
 413
 414         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 415
 416         if (!IS_ERR(dsi->phy_cfg_clk)) {
 417                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 418                 if (ret) {
 419                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 420                         return ret;
 421                 }
 422         }
 423
 424         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 425                                          VCO_RANGE_CON_SEL(vco) |
 426                                          VCO_IN_CAP_CON_LOW |
 427                                          REF_BIAS_CUR_SEL);
 428
 429         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 430         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 431                                          LPF_RESISTORS_20_KOHM);
 432
 433         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 434
 435         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 436         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 437         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 438                                          LOW_PROGRAM_EN);
 439         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 440                                          HIGH_PROGRAM_EN);
 441
 442         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 443                                          BIAS_BLOCK_ON | BANDGAP_ON);
 444
 445         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 446                                          SETRD_MAX | TER_RESISTORS_ON);
 447         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 448                                          SETRD_MAX | POWER_MANAGE |
 449                                          TER_RESISTORS_ON);
 450
 451         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 452                                          BIASEXTR_SEL(BIASEXTR_127_7));
 453         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 454                                          BANDGAP_SEL(BANDGAP_96_10));
 455
 456         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 457         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
 458         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 459
 460         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 461                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 462
 463
 464         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 465                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 466         if (ret < 0) {
 467                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 468                 goto phy_init_end;
 469         }
 470
 471         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 472                                  val, val & STOP_STATE_CLK_LANE, 1000,
 473                                  PHY_STATUS_TIMEOUT_US);
 474         if (ret < 0)
 475                 dev_err(dsi->dev,
 476                         "failed to wait for phy clk lane stop state\n");
 477
 478 phy_init_end:
 479         if (!IS_ERR(dsi->phy_cfg_clk))
 480                 clk_disable_unprepare(dsi->phy_cfg_clk);
 481
 482         return ret;
 483 }
 484
 485 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 486 {
 487         unsigned int i, pre;
 488         unsigned long mpclk, pllref, tmp;
 489         unsigned int m = 1, n = 1, target_mbps = 1000;
 490         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 491         int bpp;
 492
 493         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 494         if (bpp < 0) {
 495                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 496                         dsi->format);
 497                 return bpp;
 498         }
 499
 500         mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
 501         if (mpclk) {
 502                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 503                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 504                 if (tmp < max_mbps)
 505                         target_mbps = tmp;
 506                 else
 507                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 508         }
 509
 510         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 511         tmp = pllref;
 512
 513         for (i = 1; i < 6; i++) {
 514                 pre = pllref / i;
 515                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 516                         tmp = target_mbps % pre;
 517                         n = i;
 518                         m = target_mbps / pre;
 519                 }
 520                 if (tmp == 0)
 521                         break;
 522         }
 523
 524         dsi->lane_mbps = pllref / n * m;
 525         dsi->input_div = n;
 526         dsi->feedback_div = m;
 527
 528         return 0;
 529 }
 530
 531 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 532                                    struct mipi_dsi_device *device)
 533 {
 534         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 535
 536         if (device->lanes > dsi->pdata->max_data_lanes) {
 537                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 538                                 device->lanes);
 539                 return -EINVAL;
 540         }
 541
 542         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
 543             !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
 544                 dev_err(dsi->dev, "device mode is unsupported\n");
 545                 return -EINVAL;
 546         }
 547
 548         dsi->lanes = device->lanes;
 549         dsi->channel = device->channel;
 550         dsi->format = device->format;
 551         dsi->panel = of_drm_find_panel(device->dev.of_node);
 552         if (dsi->panel)
 553                 return drm_panel_attach(dsi->panel, &dsi->connector);
 554
 555         return -EINVAL;
 556 }
 557
 558 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 559                                    struct mipi_dsi_device *device)
 560 {
 561         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 562
 563         drm_panel_detach(dsi->panel);
 564
 565         return 0;
 566 }
 567
 568 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 569 {
 570         int ret;
 571
 572         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 573                                  val, !(val & GEN_CMD_FULL), 1000,
 574                                  CMD_PKT_STATUS_TIMEOUT_US);
 575         if (ret < 0) {
 576                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 577                 return ret;
 578         }
 579
 580         dsi_write(dsi, DSI_GEN_HDR, val);
 581
 582         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 583                                  val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 584                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 585         if (ret < 0) {
 586                 dev_err(dsi->dev, "failed to write command FIFO\n");
 587                 return ret;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
 594                                        const struct mipi_dsi_msg *msg)
 595 {
 596         const u16 *tx_buf = msg->tx_buf;
 597         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 598
 599         if (msg->tx_len > 2) {
 600                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 601                         msg->tx_len);
 602                 return -EINVAL;
 603         }
 604
 605         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 606 }
 607
 608 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 609                                       const struct mipi_dsi_msg *msg)
 610 {
 611         const u32 *tx_buf = msg->tx_buf;
 612         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 613         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 614         u32 remainder = 0;
 615
 616         if (msg->tx_len < 3) {
 617                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 618                         msg->tx_len);
 619                 return -EINVAL;
 620         }
 621
 622         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 623                 if (len < pld_data_bytes) {
 624                         memcpy(&remainder, tx_buf, len);
 625                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 626                         len = 0;
 627                 } else {
 628                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 629                         tx_buf++;
 630                         len -= pld_data_bytes;
 631                 }
 632
 633                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 634                                          val, !(val & GEN_PLD_W_FULL), 1000,
 635                                          CMD_PKT_STATUS_TIMEOUT_US);
 636                 if (ret < 0) {
 637                         dev_err(dsi->dev,
 638                                 "failed to get available write payload FIFO\n");
 639                         return ret;
 640                 }
 641         }
 642
 643         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 644 }
 645
 646 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 647                                          const struct mipi_dsi_msg *msg)
 648 {
 649         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 650         int ret;
 651
 652         switch (msg->type) {
 653         case MIPI_DSI_DCS_SHORT_WRITE:
 654         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 655         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 656                 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
 657                 break;
 658         case MIPI_DSI_DCS_LONG_WRITE:
 659                 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
 660                 break;
 661         default:
 662                 dev_err(dsi->dev, "unsupported message type\n");
 663                 ret = -EINVAL;
 664         }
 665
 666         return ret;
 667 }
 668
 669 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 670         .attach = dw_mipi_dsi_host_attach,
 671         .detach = dw_mipi_dsi_host_detach,
 672         .transfer = dw_mipi_dsi_host_transfer,
 673 };
 674
 675 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 676 {
 677         u32 val;
 678
 679         val = VID_MODE_TYPE_BURST_SYNC_PULSES | ENABLE_LOW_POWER;
 680
 681         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 682 }
 683
 684 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 685                                  enum dw_mipi_dsi_mode mode)
 686 {
 687         if (mode == DW_MIPI_DSI_CMD_MODE) {
 688                 dsi_write(dsi, DSI_PWR_UP, RESET);
 689                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 690                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 691         } else {
 692                 dsi_write(dsi, DSI_PWR_UP, RESET);
 693                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 694                 dw_mipi_dsi_video_mode_config(dsi);
 695                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 696         }
 697 }
 698
 699 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 700 {
 701         dsi_write(dsi, DSI_PWR_UP, RESET);
 702         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 703 }
 704
 705 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 706 {
 707         dsi_write(dsi, DSI_PWR_UP, RESET);
 708         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 709                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 710         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 711                   TX_ESC_CLK_DIVIDSION(7));
 712         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 713 }
 714
 715 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 716                                    struct drm_display_mode *mode)
 717 {
 718         u32 val = 0, color = 0;
 719
 720         switch (dsi->format) {
 721         case MIPI_DSI_FMT_RGB888:
 722                 color = DPI_COLOR_CODING_24BIT;
 723                 break;
 724         case MIPI_DSI_FMT_RGB666:
 725                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 726                 break;
 727         case MIPI_DSI_FMT_RGB666_PACKED:
 728                 color = DPI_COLOR_CODING_18BIT_1;
 729                 break;
 730         case MIPI_DSI_FMT_RGB565:
 731                 color = DPI_COLOR_CODING_16BIT_1;
 732                 break;
 733         }
 734
 735         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 736                 val |= VSYNC_ACTIVE_LOW;
 737         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 738                 val |= HSYNC_ACTIVE_LOW;
 739
 740         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 741         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 742         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 743         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 744                   | INVACT_LPCMD_TIME(4));
 745 }
 746
 747 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 748 {
 749         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 750 }
 751
 752 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 753                                             struct drm_display_mode *mode)
 754 {
 755         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 756 }
 757
 758 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 759 {
 760         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 761         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 762         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 763         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 764 }
 765
 766 /* Get lane byte clock cycles. */
 767 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 768                                            u32 hcomponent)
 769 {
 770         u32 frac, lbcc;
 771
 772         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 773
 774         frac = lbcc % dsi->mode->clock;
 775         lbcc = lbcc / dsi->mode->clock;
 776         if (frac)
 777                 lbcc++;
 778
 779         return lbcc;
 780 }
 781
 782 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 783 {
 784         u32 htotal, hsa, hbp, lbcc;
 785         struct drm_display_mode *mode = dsi->mode;
 786
 787         htotal = mode->htotal;
 788         hsa = mode->hsync_end - mode->hsync_start;
 789         hbp = mode->htotal - mode->hsync_end;
 790
 791         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 792         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 793
 794         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 795         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 796
 797         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 798         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 799 }
 800
 801 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 802 {
 803         u32 vactive, vsa, vfp, vbp;
 804         struct drm_display_mode *mode = dsi->mode;
 805
 806         vactive = mode->vdisplay;
 807         vsa = mode->vsync_end - mode->vsync_start;
 808         vfp = mode->vsync_start - mode->vdisplay;
 809         vbp = mode->vtotal - mode->vsync_end;
 810
 811         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 812         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 813         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 814         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 815 }
 816
 817 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 818 {
 819         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 820                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 821
 822         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 823                   | PHY_CLKLP2HS_TIME(0x40));
 824 }
 825
 826 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 827 {
 828         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 829                   N_LANES(dsi->lanes));
 830 }
 831
 832 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 833 {
 834         dsi_read(dsi, DSI_INT_ST0);
 835         dsi_read(dsi, DSI_INT_ST1);
 836         dsi_write(dsi, DSI_INT_MSK0, 0);
 837         dsi_write(dsi, DSI_INT_MSK1, 0);
 838 }
 839
 840 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 841                                         struct drm_display_mode *mode,
 842                                         struct drm_display_mode *adjusted_mode)
 843 {
 844         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 845         int ret;
 846
 847         dsi->mode = adjusted_mode;
 848
 849         ret = dw_mipi_dsi_get_lane_bps(dsi);
 850         if (ret < 0)
 851                 return;
 852
 853         if (clk_prepare_enable(dsi->pclk)) {
 854                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 855                 return;
 856         }
 857
 858         dw_mipi_dsi_init(dsi);
 859         dw_mipi_dsi_dpi_config(dsi, mode);
 860         dw_mipi_dsi_packet_handler_config(dsi);
 861         dw_mipi_dsi_video_mode_config(dsi);
 862         dw_mipi_dsi_video_packet_config(dsi, mode);
 863         dw_mipi_dsi_command_mode_config(dsi);
 864         dw_mipi_dsi_line_timer_config(dsi);
 865         dw_mipi_dsi_vertical_timing_config(dsi);
 866         dw_mipi_dsi_dphy_timing_config(dsi);
 867         dw_mipi_dsi_dphy_interface_config(dsi);
 868         dw_mipi_dsi_clear_err(dsi);
 869         if (drm_panel_prepare(dsi->panel))
 870                 dev_err(dsi->dev, "failed to prepare panel\n");
 871
 872         clk_disable_unprepare(dsi->pclk);
 873 }
 874
 875 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 876 {
 877         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 878
 879         drm_panel_disable(dsi->panel);
 880
 881         if (clk_prepare_enable(dsi->pclk)) {
 882                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 883                 return;
 884         }
 885
 886         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 887         drm_panel_unprepare(dsi->panel);
 888         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 889
 890         /*
 891          * This is necessary to make sure the peripheral will be driven
 892          * normally when the display is enabled again later.
 893          */
 894         msleep(120);
 895
 896         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 897         dw_mipi_dsi_disable(dsi);
 898         clk_disable_unprepare(dsi->pclk);
 899 }
 900
 901 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 902                                         const struct drm_display_mode *mode,
 903                                         struct drm_display_mode *adjusted_mode)
 904 {
 905         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 906
 907         switch (dsi->format) {
 908         case MIPI_DSI_FMT_RGB888:
 909                 adjusted_mode->private_flags = ROCKCHIP_DSP_MODE(DSI, P888);
 910                 break;
 911         case MIPI_DSI_FMT_RGB666:
 912                 adjusted_mode->private_flags = ROCKCHIP_DSP_MODE(DSI, P666);
 913                 break;
 914         case MIPI_DSI_FMT_RGB565:
 915                 adjusted_mode->private_flags = ROCKCHIP_DSP_MODE(DSI, P565);
 916                 break;
 917         default:
 918                 WARN_ON(1);
 919                 return false;
 920         }
 921
 922         return true;
 923 }
 924
 925 static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
 926 {
 927         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 928         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 929         int mux  = rockchip_drm_encoder_get_mux_id(dsi->dev->of_node, encoder);
 930         u32 val;
 931
 932         if (clk_prepare_enable(dsi->pclk)) {
 933                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 934                 return;
 935         }
 936
 937         if (pdata->grf_dsi0_mode_reg)
 938                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 939                              pdata->grf_dsi0_mode);
 940
 941         dw_mipi_dsi_phy_init(dsi);
 942         dw_mipi_dsi_wait_for_two_frames(dsi);
 943
 944         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 945         drm_panel_enable(dsi->panel);
 946
 947         clk_disable_unprepare(dsi->pclk);
 948
 949         if (mux)
 950                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 951         else
 952                 val = pdata->dsi0_en_bit << 16;
 953
 954         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 955         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 956 }
 957
 958 static struct drm_encoder_helper_funcs
 959 dw_mipi_dsi_encoder_helper_funcs = {
 960         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
 961         .commit = dw_mipi_dsi_encoder_commit,
 962         .mode_set = dw_mipi_dsi_encoder_mode_set,
 963         .disable = dw_mipi_dsi_encoder_disable,
 964 };
 965
 966 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
 967         .destroy = drm_encoder_cleanup,
 968 };
 969
 970 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
 971 {
 972         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
 973
 974         return drm_panel_get_modes(dsi->panel);
 975 }
 976
 977 static enum drm_mode_status dw_mipi_dsi_mode_valid(
 978                                         struct drm_connector *connector,
 979                                         struct drm_display_mode *mode)
 980 {
 981         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
 982
 983         enum drm_mode_status mode_status = MODE_OK;
 984
 985         if (dsi->pdata->mode_valid)
 986                 mode_status = dsi->pdata->mode_valid(connector, mode);
 987
 988         return mode_status;
 989 }
 990
 991 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
 992                                         struct drm_connector *connector)
 993 {
 994         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
 995
 996         return &dsi->encoder;
 997 }
 998
 999 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1000         .get_modes = dw_mipi_dsi_connector_get_modes,
1001         .mode_valid = dw_mipi_dsi_mode_valid,
1002         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1003 };
1004
1005 static enum drm_connector_status
1006 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1007 {
1008         return connector_status_connected;
1009 }
1010
1011 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1012 {
1013         drm_connector_unregister(connector);
1014         drm_connector_cleanup(connector);
1015 }
1016
1017 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1018         .dpms = drm_atomic_helper_connector_dpms,
1019         .fill_modes = drm_helper_probe_single_connector_modes,
1020         .detect = dw_mipi_dsi_detect,
1021         .destroy = dw_mipi_dsi_drm_connector_destroy,
1022         .reset = drm_atomic_helper_connector_reset,
1023         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1024         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1025 };
1026
1027 static int dw_mipi_dsi_register(struct drm_device *drm,
1028                                       struct dw_mipi_dsi *dsi)
1029 {
1030         struct drm_encoder *encoder = &dsi->encoder;
1031         struct drm_connector *connector = &dsi->connector;
1032         struct device *dev = dsi->dev;
1033         int ret;
1034
1035         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1036                                                              dev->of_node);
1037         /*
1038          * If we failed to find the CRTC(s) which this encoder is
1039          * supposed to be connected to, it's because the CRTC has
1040          * not been registered yet.  Defer probing, and hope that
1041          * the required CRTC is added later.
1042          */
1043         if (encoder->possible_crtcs == 0)
1044                 return -EPROBE_DEFER;
1045
1046         drm_encoder_helper_add(&dsi->encoder,
1047                                &dw_mipi_dsi_encoder_helper_funcs);
1048         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1049                          DRM_MODE_ENCODER_DSI, NULL);
1050         if (ret) {
1051                 dev_err(dev, "Failed to initialize encoder with drm\n");
1052                 return ret;
1053         }
1054
1055         drm_connector_helper_add(connector,
1056                         &dw_mipi_dsi_connector_helper_funcs);
1057
1058         drm_connector_init(drm, &dsi->connector,
1059                            &dw_mipi_dsi_atomic_connector_funcs,
1060                            DRM_MODE_CONNECTOR_DSI);
1061
1062         drm_mode_connector_attach_encoder(connector, encoder);
1063
1064         return 0;
1065 }
1066
1067 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1068 {
1069         struct device_node *np = dsi->dev->of_node;
1070
1071         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1072         if (IS_ERR(dsi->grf_regmap)) {
1073                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1074                 return PTR_ERR(dsi->grf_regmap);
1075         }
1076
1077         return 0;
1078 }
1079
1080 static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
1081                                         struct drm_connector *connector,
1082                                         struct drm_display_mode *mode)
1083 {
1084         /*
1085          * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
1086          * register is 11-bit.
1087          */
1088         if (mode->hdisplay > 0x7ff)
1089                 return MODE_BAD_HVALUE;
1090
1091         /*
1092          * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
1093          * register is 11-bit.
1094          */
1095         if (mode->vdisplay > 0x7ff)
1096                 return MODE_BAD_VVALUE;
1097
1098         return MODE_OK;
1099 }
1100
1101 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1102         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1103         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1104         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1105         .max_data_lanes = 4,
1106         .mode_valid = rk3288_mipi_dsi_mode_valid,
1107 };
1108
1109 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1110         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1111         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1112         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1113         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1114         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1115         .max_data_lanes = 4,
1116         .mode_valid = rk3288_mipi_dsi_mode_valid,
1117 };
1118
1119 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1120         {
1121          .compatible = "rockchip,rk3288-mipi-dsi",
1122          .data = &rk3288_mipi_dsi_drv_data,
1123         },{
1124          .compatible = "rockchip,rk3399-mipi-dsi",
1125          .data = &rk3399_mipi_dsi_drv_data,
1126         },
1127         { /* sentinel */ }
1128 };
1129 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1130
1131 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1132                              void *data)
1133 {
1134         const struct of_device_id *of_id =
1135                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1136         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1137         struct platform_device *pdev = to_platform_device(dev);
1138         struct drm_device *drm = data;
1139         struct dw_mipi_dsi *dsi;
1140         struct resource *res;
1141         int ret;
1142
1143         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1144         if (!dsi)
1145                 return -ENOMEM;
1146
1147         dsi->dev = dev;
1148         dsi->pdata = pdata;
1149
1150         ret = rockchip_mipi_parse_dt(dsi);
1151         if (ret)
1152                 return ret;
1153
1154         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1155         if (!res)
1156                 return -ENODEV;
1157
1158         dsi->base = devm_ioremap_resource(dev, res);
1159         if (IS_ERR(dsi->base))
1160                 return PTR_ERR(dsi->base);
1161
1162         dsi->pllref_clk = devm_clk_get(dev, "ref");
1163         if (IS_ERR(dsi->pllref_clk)) {
1164                 ret = PTR_ERR(dsi->pllref_clk);
1165                 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1166                 return ret;
1167         }
1168
1169         dsi->pclk = devm_clk_get(dev, "pclk");
1170         if (IS_ERR(dsi->pclk)) {
1171                 ret = PTR_ERR(dsi->pclk);
1172                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1173                 return ret;
1174         }
1175
1176         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1177         if (IS_ERR(dsi->phy_cfg_clk))
1178                 dev_dbg(dev, "have not phy_cfg_clk\n");
1179
1180         ret = clk_prepare_enable(dsi->pllref_clk);
1181         if (ret) {
1182                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1183                 return ret;
1184         }
1185
1186         ret = dw_mipi_dsi_register(drm, dsi);
1187         if (ret) {
1188                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1189                 goto err_pllref;
1190         }
1191
1192         dev_set_drvdata(dev, dsi);
1193
1194         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1195         dsi->dsi_host.dev = dev;
1196         return mipi_dsi_host_register(&dsi->dsi_host);
1197
1198 err_pllref:
1199         clk_disable_unprepare(dsi->pllref_clk);
1200         return ret;
1201 }
1202
1203 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1204         void *data)
1205 {
1206         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1207
1208         mipi_dsi_host_unregister(&dsi->dsi_host);
1209         clk_disable_unprepare(dsi->pllref_clk);
1210 }
1211
1212 static const struct component_ops dw_mipi_dsi_ops = {
1213         .bind   = dw_mipi_dsi_bind,
1214         .unbind = dw_mipi_dsi_unbind,
1215 };
1216
1217 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1218 {
1219         return component_add(&pdev->dev, &dw_mipi_dsi_ops);
1220 }
1221
1222 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1223 {
1224         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1225         return 0;
1226 }
1227
1228 static struct platform_driver dw_mipi_dsi_driver = {
1229         .probe          = dw_mipi_dsi_probe,
1230         .remove         = dw_mipi_dsi_remove,
1231         .driver         = {
1232                 .of_match_table = dw_mipi_dsi_dt_ids,
1233                 .name   = DRIVER_NAME,
1234         },
1235 };
1236 module_platform_driver(dw_mipi_dsi_driver);
1237
1238 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1239 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1240 MODULE_LICENSE("GPL");
1241 MODULE_ALIAS("platform:" DRIVER_NAME);