drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3288_GRF_SOC_CON9             0x0268
  40
  41 #define RK3288_GRF_SOC_CON14            0x027c
  42 #define RK3288_TXRX_BASEDIR             BIT(15)
  43 #define RK3288_TXRX_MASTERSLAVEZ        BIT(14)
  44 #define RK3288_TXRX_CLKEN               BIT(12)
  45
  46 #define RK3366_GRF_SOC_CON0             0x0400
  47 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  48
  49 #define RK3399_GRF_SOC_CON19            0x6250
  50 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  51 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  52
  53 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  54 #define RK3399_GRF_SOC_CON22            0x6258
  55 #define RK3399_GRF_DSI_MODE             0xffff0000
  56
  57 #define DSI_VERSION                     0x00
  58 #define DSI_PWR_UP                      0x04
  59 #define RESET                           0
  60 #define POWERUP                         BIT(0)
  61
  62 #define DSI_CLKMGR_CFG                  0x08
  63 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  64 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  65
  66 #define DSI_DPI_VCID                    0x0c
  67 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  68
  69 #define DSI_DPI_COLOR_CODING            0x10
  70 #define EN18_LOOSELY                    BIT(8)
  71 #define DPI_COLOR_CODING_16BIT_1        0x0
  72 #define DPI_COLOR_CODING_16BIT_2        0x1
  73 #define DPI_COLOR_CODING_16BIT_3        0x2
  74 #define DPI_COLOR_CODING_18BIT_1        0x3
  75 #define DPI_COLOR_CODING_18BIT_2        0x4
  76 #define DPI_COLOR_CODING_24BIT          0x5
  77
  78 #define DSI_DPI_CFG_POL                 0x14
  79 #define COLORM_ACTIVE_LOW               BIT(4)
  80 #define SHUTD_ACTIVE_LOW                BIT(3)
  81 #define HSYNC_ACTIVE_LOW                BIT(2)
  82 #define VSYNC_ACTIVE_LOW                BIT(1)
  83 #define DATAEN_ACTIVE_LOW               BIT(0)
  84
  85 #define DSI_DPI_LP_CMD_TIM              0x18
  86 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  87 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  88
  89 #define DSI_DBI_CFG                     0x20
  90 #define DSI_DBI_CMDSIZE                 0x28
  91
  92 #define DSI_PCKHDL_CFG                  0x2c
  93 #define EN_CRC_RX                       BIT(4)
  94 #define EN_ECC_RX                       BIT(3)
  95 #define EN_BTA                          BIT(2)
  96 #define EN_EOTP_RX                      BIT(1)
  97 #define EN_EOTP_TX                      BIT(0)
  98
  99 #define DSI_MODE_CFG                    0x34
 100 #define ENABLE_VIDEO_MODE               0
 101 #define ENABLE_CMD_MODE                 BIT(0)
 102
 103 #define DSI_VID_MODE_CFG                0x38
 104 #define VPG_EN                          BIT(16)
 105 #define FRAME_BTA_ACK                   BIT(14)
 106 #define LP_HFP_EN                       BIT(13)
 107 #define LP_HBP_EN                       BIT(12)
 108 #define ENABLE_LOW_POWER                (0xf << 8)
 109 #define ENABLE_LOW_POWER_MASK           (0xf << 8)
 110 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 111 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 112 #define VID_MODE_TYPE_BURST             0x2
 113
 114 #define DSI_VID_PKT_SIZE                0x3c
 115 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 116 #define VID_PKT_MAX_SIZE                0x3fff
 117
 118 #define DSI_VID_NUM_CHUMKS              0x40
 119 #define DSI_VID_NULL_PKT_SIZE           0x44
 120 #define DSI_VID_HSA_TIME                0x48
 121 #define DSI_VID_HBP_TIME                0x4c
 122 #define DSI_VID_HLINE_TIME              0x50
 123 #define DSI_VID_VSA_LINES               0x54
 124 #define DSI_VID_VBP_LINES               0x58
 125 #define DSI_VID_VFP_LINES               0x5c
 126 #define DSI_VID_VACTIVE_LINES           0x60
 127 #define DSI_CMD_MODE_CFG                0x68
 128 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 129 #define DCS_LW_TX_LP                    BIT(19)
 130 #define DCS_SR_0P_TX_LP                 BIT(18)
 131 #define DCS_SW_1P_TX_LP                 BIT(17)
 132 #define DCS_SW_0P_TX_LP                 BIT(16)
 133 #define GEN_LW_TX_LP                    BIT(14)
 134 #define GEN_SR_2P_TX_LP                 BIT(13)
 135 #define GEN_SR_1P_TX_LP                 BIT(12)
 136 #define GEN_SR_0P_TX_LP                 BIT(11)
 137 #define GEN_SW_2P_TX_LP                 BIT(10)
 138 #define GEN_SW_1P_TX_LP                 BIT(9)
 139 #define GEN_SW_0P_TX_LP                 BIT(8)
 140 #define EN_ACK_RQST                     BIT(1)
 141 #define EN_TEAR_FX                      BIT(0)
 142
 143 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 144                                          DCS_LW_TX_LP | \
 145                                          DCS_SR_0P_TX_LP | \
 146                                          DCS_SW_1P_TX_LP | \
 147                                          DCS_SW_0P_TX_LP | \
 148                                          GEN_LW_TX_LP | \
 149                                          GEN_SR_2P_TX_LP | \
 150                                          GEN_SR_1P_TX_LP | \
 151                                          GEN_SR_0P_TX_LP | \
 152                                          GEN_SW_2P_TX_LP | \
 153                                          GEN_SW_1P_TX_LP | \
 154                                          GEN_SW_0P_TX_LP)
 155
 156 #define DSI_GEN_HDR                     0x6c
 157 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 158 #define GEN_HDATA_MASK                  (0xffff << 8)
 159 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 160 #define GEN_HTYPE_MASK                  0xff
 161
 162 #define DSI_GEN_PLD_DATA                0x70
 163
 164 #define DSI_CMD_PKT_STATUS              0x74
 165 #define GEN_CMD_EMPTY                   BIT(0)
 166 #define GEN_CMD_FULL                    BIT(1)
 167 #define GEN_PLD_W_EMPTY                 BIT(2)
 168 #define GEN_PLD_W_FULL                  BIT(3)
 169 #define GEN_PLD_R_EMPTY                 BIT(4)
 170 #define GEN_PLD_R_FULL                  BIT(5)
 171 #define GEN_RD_CMD_BUSY                 BIT(6)
 172
 173 #define DSI_TO_CNT_CFG                  0x78
 174 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 175 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 176
 177 #define DSI_BTA_TO_CNT                  0x8c
 178 #define DSI_LPCLK_CTRL                  0x94
 179 #define AUTO_CLKLANE_CTRL               BIT(1)
 180 #define PHY_TXREQUESTCLKHS              BIT(0)
 181
 182 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 183 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 184 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 185
 186 #define DSI_PHY_TMR_CFG                 0x9c
 187 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 188 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 189 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 190
 191 #define DSI_PHY_RSTZ                    0xa0
 192 #define PHY_DISFORCEPLL                 0
 193 #define PHY_ENFORCEPLL                  BIT(3)
 194 #define PHY_DISABLECLK                  0
 195 #define PHY_ENABLECLK                   BIT(2)
 196 #define PHY_RSTZ                        0
 197 #define PHY_UNRSTZ                      BIT(1)
 198 #define PHY_SHUTDOWNZ                   0
 199 #define PHY_UNSHUTDOWNZ                 BIT(0)
 200
 201 #define DSI_PHY_IF_CFG                  0xa4
 202 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 203 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 204
 205 #define DSI_PHY_STATUS                  0xb0
 206 #define LOCK                            BIT(0)
 207 #define STOP_STATE_CLK_LANE             BIT(2)
 208
 209 #define DSI_PHY_TST_CTRL0               0xb4
 210 #define PHY_TESTCLK                     BIT(1)
 211 #define PHY_UNTESTCLK                   0
 212 #define PHY_TESTCLR                     BIT(0)
 213 #define PHY_UNTESTCLR                   0
 214
 215 #define DSI_PHY_TST_CTRL1               0xb8
 216 #define PHY_TESTEN                      BIT(16)
 217 #define PHY_UNTESTEN                    0
 218 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 219 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 220
 221 #define DSI_INT_ST0                     0xbc
 222 #define DSI_INT_ST1                     0xc0
 223 #define DSI_INT_MSK0                    0xc4
 224 #define DSI_INT_MSK1                    0xc8
 225
 226 #define PHY_STATUS_TIMEOUT_US           10000
 227 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 228
 229 #define BYPASS_VCO_RANGE        BIT(7)
 230 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 231 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 232 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 233 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 234 #define REF_BIAS_CUR_SEL        BIT(0)
 235
 236 #define CP_CURRENT_3MA          BIT(3)
 237 #define CP_PROGRAM_EN           BIT(7)
 238 #define LPF_PROGRAM_EN          BIT(6)
 239 #define LPF_RESISTORS_20_KOHM   0
 240
 241 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 242
 243 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 244 #define LOW_PROGRAM_EN          0
 245 #define HIGH_PROGRAM_EN         BIT(7)
 246 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 247 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 248 #define PLL_LOOP_DIV_EN         BIT(5)
 249 #define PLL_INPUT_DIV_EN        BIT(4)
 250
 251 #define POWER_CONTROL           BIT(6)
 252 #define INTERNAL_REG_CURRENT    BIT(3)
 253 #define BIAS_BLOCK_ON           BIT(2)
 254 #define BANDGAP_ON              BIT(0)
 255
 256 #define TER_RESISTOR_HIGH       BIT(7)
 257 #define TER_RESISTOR_LOW        0
 258 #define LEVEL_SHIFTERS_ON       BIT(6)
 259 #define TER_CAL_DONE            BIT(5)
 260 #define SETRD_MAX               (0x7 << 2)
 261 #define POWER_MANAGE            BIT(1)
 262 #define TER_RESISTORS_ON        BIT(0)
 263
 264 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 265 #define BANDGAP_SEL(val)        ((val) & 0x7)
 266 #define TLP_PROGRAM_EN          BIT(7)
 267 #define THS_PRE_PROGRAM_EN      BIT(7)
 268 #define THS_ZERO_PROGRAM_EN     BIT(6)
 269
 270 enum {
 271         BANDGAP_97_07,
 272         BANDGAP_98_05,
 273         BANDGAP_99_02,
 274         BANDGAP_100_00,
 275         BANDGAP_93_17,
 276         BANDGAP_94_15,
 277         BANDGAP_95_12,
 278         BANDGAP_96_10,
 279 };
 280
 281 enum {
 282         BIASEXTR_87_1,
 283         BIASEXTR_91_5,
 284         BIASEXTR_95_9,
 285         BIASEXTR_100,
 286         BIASEXTR_105_94,
 287         BIASEXTR_111_88,
 288         BIASEXTR_118_8,
 289         BIASEXTR_127_7,
 290 };
 291
 292 struct dw_mipi_dsi_plat_data {
 293         u32 dsi0_en_bit;
 294         u32 dsi1_en_bit;
 295         u32 grf_switch_reg;
 296         u32 grf_dsi0_mode;
 297         u32 grf_dsi0_mode_reg;
 298         u32 dsi1_basedir;
 299         u32 dsi1_masterslavez;
 300         u32 grf_dsi1_cfg_reg;
 301         unsigned int max_data_lanes;
 302         u32 max_bit_rate_per_lane;
 303         bool has_vop_sel;
 304         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 305                                            struct drm_display_mode *mode);
 306 };
 307
 308 struct mipi_dphy {
 309         /* SNPS PHY */
 310         struct clk *cfg_clk;
 311         struct clk *ref_clk;
 312         u16 input_div;
 313         u16 feedback_div;
 314
 315         /* Non-SNPS PHY */
 316         struct phy *phy;
 317         struct clk *hs_clk;
 318 };
 319
 320 struct dw_mipi_dsi {
 321         struct drm_encoder encoder;
 322         struct drm_connector connector;
 323         struct mipi_dsi_host dsi_host;
 324         struct mipi_dphy dphy;
 325         struct drm_panel *panel;
 326         struct device *dev;
 327         struct regmap *grf_regmap;
 328         struct reset_control *rst;
 329         void __iomem *base;
 330         struct clk *pclk;
 331
 332         /* dual-channel */
 333         struct dw_mipi_dsi *master;
 334         struct dw_mipi_dsi *slave;
 335         struct device_node *panel_node;
 336         int id;
 337
 338         unsigned long mode_flags;
 339         unsigned int lane_mbps; /* per lane */
 340         u32 channel;
 341         u32 lanes;
 342         u32 format;
 343         struct drm_display_mode mode;
 344
 345         const struct dw_mipi_dsi_plat_data *pdata;
 346 };
 347
 348 enum dw_mipi_dsi_mode {
 349         DSI_COMMAND_MODE,
 350         DSI_VIDEO_MODE,
 351 };
 352
 353 struct dphy_pll_testdin_map {
 354         unsigned int max_mbps;
 355         u8 testdin;
 356 };
 357
 358 /* The table is based on 27MHz DPHY pll reference clock. */
 359 static const struct dphy_pll_testdin_map dptdin_map[] = {
 360         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 361         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 362         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 363         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 364         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 365         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 366         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 367         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 368         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 369         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 370 };
 371
 372 static int max_mbps_to_testdin(unsigned int max_mbps)
 373 {
 374         int i;
 375
 376         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 377                 if (dptdin_map[i].max_mbps > max_mbps)
 378                         return dptdin_map[i].testdin;
 379
 380         return -EINVAL;
 381 }
 382
 383 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 384 {
 385         return container_of(host, struct dw_mipi_dsi, dsi_host);
 386 }
 387
 388 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 389 {
 390         return container_of(con, struct dw_mipi_dsi, connector);
 391 }
 392
 393 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 394 {
 395         return container_of(encoder, struct dw_mipi_dsi, encoder);
 396 }
 397 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 398 {
 399         writel(val, dsi->base + reg);
 400 }
 401
 402 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 403 {
 404         return readl(dsi->base + reg);
 405 }
 406
 407 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 408 {
 409         u32 sts;
 410         int ret;
 411
 412         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 413                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 414                                  CMD_PKT_STATUS_TIMEOUT_US);
 415         if (ret < 0) {
 416                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 417                 return ret;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 424 {
 425         u32 sts;
 426         int ret;
 427
 428         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 429                                  sts, !(sts & GEN_CMD_FULL), 10,
 430                                  CMD_PKT_STATUS_TIMEOUT_US);
 431         if (ret < 0) {
 432                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 433                 return ret;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 440 {
 441         u32 sts;
 442         u32 mask;
 443         int ret;
 444
 445         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 446         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 447                                  sts, (sts & mask) == mask, 10,
 448                                  CMD_PKT_STATUS_TIMEOUT_US);
 449         if (ret < 0) {
 450                 dev_err(dsi->dev, "generic write fifo is full\n");
 451                 return ret;
 452         }
 453
 454         return 0;
 455 }
 456
 457 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 458                                  u8 test_data)
 459 {
 460         /*
 461          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 462          * is latched internally as the current test code. Test data is
 463          * programmed internally by rising edge on TESTCLK.
 464          */
 465         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 466
 467         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 468                                           PHY_TESTDIN(test_code));
 469
 470         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 471
 472         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 473                                           PHY_TESTDIN(test_data));
 474
 475         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 476 }
 477
 478 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 479 {
 480         int ret, testdin, vco, val;
 481
 482         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 483
 484         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 485         if (testdin < 0) {
 486                 dev_err(dsi->dev,
 487                         "failed to get testdin for %dmbps lane clock\n",
 488                         dsi->lane_mbps);
 489                 return testdin;
 490         }
 491
 492         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 493
 494         if (!IS_ERR(dsi->dphy.cfg_clk)) {
 495                 ret = clk_prepare_enable(dsi->dphy.cfg_clk);
 496                 if (ret) {
 497                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 498                         return ret;
 499                 }
 500         }
 501
 502         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 503                                          VCO_RANGE_CON_SEL(vco) |
 504                                          VCO_IN_CAP_CON_LOW |
 505                                          REF_BIAS_CUR_SEL);
 506
 507         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 508         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 509                                          LPF_RESISTORS_20_KOHM);
 510
 511         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 512
 513         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
 514         val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
 515         dw_mipi_dsi_phy_write(dsi, 0x18, val);
 516         val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
 517         dw_mipi_dsi_phy_write(dsi, 0x18, val);
 518         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 519
 520         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 521                                          BIAS_BLOCK_ON | BANDGAP_ON);
 522
 523         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 524                                          SETRD_MAX | TER_RESISTORS_ON);
 525         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 526                                          SETRD_MAX | POWER_MANAGE |
 527                                          TER_RESISTORS_ON);
 528
 529         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 530                                          BIASEXTR_SEL(BIASEXTR_127_7));
 531         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 532                                          BANDGAP_SEL(BANDGAP_96_10));
 533
 534         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 535         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 536         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 537
 538         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 539                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 540
 541         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 542                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 543         if (ret < 0) {
 544                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 545                 goto phy_init_end;
 546         }
 547
 548         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 549                                  val, val & STOP_STATE_CLK_LANE, 1000,
 550                                  PHY_STATUS_TIMEOUT_US);
 551         if (ret < 0)
 552                 dev_err(dsi->dev,
 553                         "failed to wait for phy clk lane stop state\n");
 554
 555 phy_init_end:
 556         if (!IS_ERR(dsi->dphy.cfg_clk))
 557                 clk_disable_unprepare(dsi->dphy.cfg_clk);
 558
 559         return ret;
 560 }
 561
 562 static unsigned long rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
 563 {
 564         int bpp;
 565         unsigned long mpclk, tmp;
 566         unsigned long target_mbps = 1000;
 567         unsigned int value;
 568         struct device_node *np = dsi->dev->of_node;
 569         unsigned int max_mbps;
 570         int lanes;
 571
 572         /* optional override of the desired bandwidth */
 573         if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
 574                 return value;
 575
 576         max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
 577
 578         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 579         if (bpp < 0) {
 580                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 581                         dsi->format);
 582                 bpp = 24;
 583         }
 584
 585         lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
 586
 587         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 588         if (mpclk) {
 589                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 590                 tmp = mpclk * (bpp / lanes) * 10 / 9;
 591                 if (tmp < max_mbps)
 592                         target_mbps = tmp;
 593                 else
 594                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 595         }
 596
 597         return target_mbps;
 598 }
 599
 600 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 601 {
 602         unsigned int i, pre;
 603         unsigned long pllref, tmp;
 604         unsigned int m = 1, n = 1;
 605         unsigned long target_mbps;
 606
 607         if (dsi->master)
 608                 return 0;
 609
 610         target_mbps = rockchip_dsi_calc_bandwidth(dsi);
 611
 612         pllref = DIV_ROUND_UP(clk_get_rate(dsi->dphy.ref_clk), USEC_PER_SEC);
 613         tmp = pllref;
 614
 615         for (i = 1; i < 6; i++) {
 616                 pre = pllref / i;
 617                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 618                         tmp = target_mbps % pre;
 619                         n = i;
 620                         m = target_mbps / pre;
 621                 }
 622                 if (tmp == 0)
 623                         break;
 624         }
 625
 626         dsi->lane_mbps = pllref / n * m;
 627         dsi->dphy.input_div = n;
 628         dsi->dphy.feedback_div = m;
 629         if (dsi->slave) {
 630                 dsi->slave->lane_mbps = dsi->lane_mbps;
 631                 dsi->slave->dphy.input_div = n;
 632                 dsi->slave->dphy.feedback_div = m;
 633         }
 634
 635         return 0;
 636 }
 637
 638 static void rockchip_dsi_set_hs_clk(struct dw_mipi_dsi *dsi)
 639 {
 640         int ret;
 641         unsigned long target_mbps;
 642         unsigned long bw, rate;
 643
 644         target_mbps = rockchip_dsi_calc_bandwidth(dsi);
 645         bw = target_mbps * USEC_PER_SEC;
 646
 647         rate = clk_round_rate(dsi->dphy.hs_clk, bw);
 648         ret = clk_set_rate(dsi->dphy.hs_clk, rate);
 649         if (ret)
 650                 dev_err(dsi->dev, "failed to set hs clock rate: %lu\n",
 651                         rate);
 652
 653         clk_prepare_enable(dsi->dphy.hs_clk);
 654
 655         dsi->lane_mbps = rate / USEC_PER_SEC;
 656 }
 657
 658 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 659                                    struct mipi_dsi_device *device)
 660 {
 661         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 662         int lanes;
 663
 664         if (dsi->master)
 665                 return 0;
 666
 667         lanes = dsi->slave ? device->lanes / 2 : device->lanes;
 668
 669         if (lanes > dsi->pdata->max_data_lanes) {
 670                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 671                                 lanes);
 672                 return -EINVAL;
 673         }
 674
 675         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 676                 dev_err(dsi->dev, "device mode is unsupported\n");
 677                 return -EINVAL;
 678         }
 679
 680         dsi->lanes = lanes;
 681         dsi->channel = device->channel;
 682         dsi->format = device->format;
 683         dsi->mode_flags = device->mode_flags;
 684
 685         if (dsi->slave) {
 686                 dsi->slave->lanes = lanes;
 687                 dsi->slave->channel = device->channel;
 688                 dsi->slave->format = device->format;
 689                 dsi->slave->mode_flags = device->mode_flags;
 690         }
 691
 692         dsi->panel = of_drm_find_panel(device->dev.of_node);
 693         if (!dsi->panel) {
 694                 DRM_ERROR("failed to find panel\n");
 695                 return -ENODEV;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 702                                    struct mipi_dsi_device *device)
 703 {
 704         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 705
 706         if (dsi->panel)
 707                 drm_panel_detach(dsi->panel);
 708
 709         dsi->panel = NULL;
 710         return 0;
 711 }
 712
 713 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 714 {
 715         if (flags & MIPI_DSI_MSG_USE_LPM) {
 716                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 717                 dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 718         } else {
 719                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 720                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 721         }
 722 }
 723
 724 static ssize_t rockchip_dsi_send_packet(struct dw_mipi_dsi *dsi,
 725                                         const struct mipi_dsi_msg *msg)
 726 {
 727         struct mipi_dsi_packet packet;
 728         int ret;
 729         int val;
 730         int len = msg->tx_len;
 731
 732         /* create a packet to the DSI protocol */
 733         ret = mipi_dsi_create_packet(&packet, msg);
 734         if (ret) {
 735                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 736                 return ret;
 737         }
 738
 739         rockchip_set_transfer_mode(dsi, msg->flags);
 740
 741         /* Send payload,  */
 742         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 743                 /*
 744                  * Alternatively, you can always keep the FIFO
 745                  * nearly full by monitoring the FIFO state until
 746                  * it is not full, and then writea single word of data.
 747                  * This solution is more resource consuming
 748                  * but it simultaneously avoids FIFO starvation,
 749                  * making it possible to use FIFO sizes smaller than
 750                  * the amount of data of the longest packet to be written.
 751                  */
 752                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 753                 if (ret)
 754                         return ret;
 755
 756                 if (packet.payload_length < 4) {
 757                         /* send residu payload */
 758                         val = 0;
 759                         memcpy(&val, packet.payload, packet.payload_length);
 760                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 761                         packet.payload_length = 0;
 762                 } else {
 763                         val = get_unaligned_le32(packet.payload);
 764                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 765                         packet.payload += 4;
 766                         packet.payload_length -= 4;
 767                 }
 768         }
 769
 770         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 771         if (ret)
 772                 return ret;
 773
 774         /* Send packet header */
 775         val = get_unaligned_le32(packet.header);
 776         dsi_write(dsi, DSI_GEN_HDR, val);
 777
 778         ret = rockchip_wait_write_fifo_empty(dsi);
 779         if (ret)
 780                 return ret;
 781
 782         if (dsi->slave)
 783                 rockchip_dsi_send_packet(dsi->slave, msg);
 784
 785         return len;
 786 }
 787
 788 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 789                                          const struct mipi_dsi_msg *msg)
 790 {
 791         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 792
 793         return rockchip_dsi_send_packet(dsi, msg);
 794 }
 795
 796 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 797         .attach = dw_mipi_dsi_host_attach,
 798         .detach = dw_mipi_dsi_host_detach,
 799         .transfer = dw_mipi_dsi_host_transfer,
 800 };
 801
 802 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 803 {
 804         u32 val;
 805
 806         val = LP_HFP_EN | ENABLE_LOW_POWER;
 807
 808         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 809                 val |= VID_MODE_TYPE_BURST;
 810         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 811                 val |= VID_MODE_TYPE_BURST_SYNC_PULSES;
 812         else
 813                 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS;
 814
 815         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 816 }
 817
 818 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 819                                  enum dw_mipi_dsi_mode mode)
 820 {
 821         if (mode == DSI_COMMAND_MODE)
 822                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 823         else
 824                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 825 }
 826
 827 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 828 {
 829         u32 esc_clk_div;
 830
 831         dsi_write(dsi, DSI_PWR_UP, RESET);
 832         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 833                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 834
 835         /* The maximum value of the escape clock frequency is 20MHz */
 836         esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
 837         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 838                   TX_ESC_CLK_DIVIDSION(esc_clk_div));
 839 }
 840
 841 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 842                                    struct drm_display_mode *mode)
 843 {
 844         u32 val = 0, color = 0;
 845
 846         switch (dsi->format) {
 847         case MIPI_DSI_FMT_RGB888:
 848                 color = DPI_COLOR_CODING_24BIT;
 849                 break;
 850         case MIPI_DSI_FMT_RGB666:
 851                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 852                 break;
 853         case MIPI_DSI_FMT_RGB666_PACKED:
 854                 color = DPI_COLOR_CODING_18BIT_1;
 855                 break;
 856         case MIPI_DSI_FMT_RGB565:
 857                 color = DPI_COLOR_CODING_16BIT_1;
 858                 break;
 859         }
 860
 861         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 862                 val |= VSYNC_ACTIVE_LOW;
 863         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 864                 val |= HSYNC_ACTIVE_LOW;
 865
 866         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 867         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 868         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 869         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 870                   | INVACT_LPCMD_TIME(4));
 871 }
 872
 873 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 874 {
 875         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 876 }
 877
 878 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 879                                             struct drm_display_mode *mode)
 880 {
 881         int pkt_size;
 882
 883         if (dsi->slave || dsi->master)
 884                 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2 + 4);
 885         else
 886                 pkt_size = VID_PKT_SIZE(mode->hdisplay);
 887
 888         dsi_write(dsi, DSI_VID_PKT_SIZE, pkt_size);
 889 }
 890
 891 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 892 {
 893         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 894         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 895 }
 896
 897 /* Get lane byte clock cycles. */
 898 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 899                                            u32 hcomponent)
 900 {
 901         u32 lbcc;
 902
 903         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 904
 905         if (dsi->mode.clock == 0) {
 906                 dev_err(dsi->dev, "dsi mode clock is 0!\n");
 907                 return 0;
 908         }
 909
 910         return DIV_ROUND_CLOSEST_ULL(lbcc, dsi->mode.clock);
 911 }
 912
 913 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 914 {
 915         u32 htotal, hsa, hbp, lbcc;
 916         struct drm_display_mode *mode = &dsi->mode;
 917
 918         htotal = mode->htotal;
 919         hsa = mode->hsync_end - mode->hsync_start;
 920         hbp = mode->htotal - mode->hsync_end;
 921
 922         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 923         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 924
 925         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 926         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 927
 928         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 929         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 930 }
 931
 932 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 933 {
 934         u32 vactive, vsa, vfp, vbp;
 935         struct drm_display_mode *mode = &dsi->mode;
 936
 937         vactive = mode->vdisplay;
 938         vsa = mode->vsync_end - mode->vsync_start;
 939         vfp = mode->vsync_start - mode->vdisplay;
 940         vbp = mode->vtotal - mode->vsync_end;
 941
 942         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 943         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 944         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 945         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 946 }
 947
 948 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 949 {
 950         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 951                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 952
 953         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 954                   | PHY_CLKLP2HS_TIME(0x40));
 955 }
 956
 957 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 958 {
 959         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 960                   N_LANES(dsi->lanes));
 961 }
 962
 963 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 964 {
 965         dsi_read(dsi, DSI_INT_ST0);
 966         dsi_read(dsi, DSI_INT_ST1);
 967         dsi_write(dsi, DSI_INT_MSK0, 0);
 968         dsi_write(dsi, DSI_INT_MSK1, 0);
 969 }
 970
 971 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 972                                         struct drm_display_mode *mode,
 973                                         struct drm_display_mode *adjusted_mode)
 974 {
 975         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 976
 977         drm_mode_copy(&dsi->mode, adjusted_mode);
 978
 979         if (dsi->slave)
 980                 drm_mode_copy(&dsi->slave->mode, adjusted_mode);
 981 }
 982
 983 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
 984 {
 985         if (clk_prepare_enable(dsi->pclk)) {
 986                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 987                 return;
 988         }
 989
 990         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 991
 992         if (dsi->slave)
 993                 rockchip_dsi_pre_disable(dsi->slave);
 994 }
 995
 996 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
 997 {
 998         /* host */
 999         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
1000         dsi_write(dsi, DSI_PWR_UP, RESET);
1001
1002         /* phy */
1003         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
1004         if (dsi->dphy.phy) {
1005                 clk_disable_unprepare(dsi->dphy.hs_clk);
1006                 phy_power_off(dsi->dphy.phy);
1007         }
1008
1009         pm_runtime_put(dsi->dev);
1010         clk_disable_unprepare(dsi->pclk);
1011
1012         if (dsi->slave)
1013                 rockchip_dsi_disable(dsi->slave);
1014 }
1015
1016 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
1017 {
1018         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1019
1020         if (dsi->panel)
1021                 drm_panel_disable(dsi->panel);
1022
1023         rockchip_dsi_pre_disable(dsi);
1024
1025         if (dsi->panel)
1026                 drm_panel_unprepare(dsi->panel);
1027
1028         rockchip_dsi_disable(dsi);
1029 }
1030
1031 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
1032                                         const struct drm_display_mode *mode,
1033                                         struct drm_display_mode *adjusted_mode)
1034 {
1035         return true;
1036 }
1037
1038 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
1039 {
1040         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
1041         int val = 0;
1042
1043         if (dsi->slave) {
1044                 if (vop_id)
1045                         val = pdata->dsi0_en_bit |
1046                               (pdata->dsi0_en_bit << 16) |
1047                               pdata->dsi1_en_bit |
1048                               (pdata->dsi1_en_bit << 16);
1049                 else
1050                         val = (pdata->dsi0_en_bit << 16) |
1051                               (pdata->dsi1_en_bit << 16);
1052
1053                 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1054                 val = pdata->dsi1_masterslavez |
1055                       (pdata->dsi1_masterslavez << 16) |
1056                       (pdata->dsi1_basedir << 16);
1057                 regmap_write(dsi->grf_regmap, pdata->grf_dsi1_cfg_reg, val);
1058         } else {
1059                 if (vop_id)
1060                         val = pdata->dsi0_en_bit |
1061                               (pdata->dsi0_en_bit << 16);
1062                 else
1063                         val = pdata->dsi0_en_bit << 16;
1064
1065                 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1066         }
1067
1068         dev_info(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
1069 }
1070
1071 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
1072 {
1073         if (clk_prepare_enable(dsi->pclk)) {
1074                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
1075                 return;
1076         }
1077
1078         if (clk_prepare_enable(dsi->dphy.ref_clk)) {
1079                 dev_err(dsi->dev, "Failed to enable pllref_clk\n");
1080                 return;
1081         }
1082
1083         pm_runtime_get_sync(dsi->dev);
1084
1085         if (dsi->rst) {
1086                 /* MIPI DSI APB software reset request. */
1087                 reset_control_assert(dsi->rst);
1088                 udelay(10);
1089                 reset_control_deassert(dsi->rst);
1090                 udelay(10);
1091         }
1092
1093         if (dsi->dphy.phy) {
1094                 rockchip_dsi_set_hs_clk(dsi);
1095                 phy_power_on(dsi->dphy.phy);
1096         } else {
1097                 dw_mipi_dsi_get_lane_bps(dsi);
1098         }
1099
1100         dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
1101                  dsi->lane_mbps, dsi->lanes);
1102 }
1103
1104 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
1105 {
1106         dw_mipi_dsi_init(dsi);
1107         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
1108         dw_mipi_dsi_packet_handler_config(dsi);
1109         dw_mipi_dsi_video_mode_config(dsi);
1110         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
1111         dw_mipi_dsi_command_mode_config(dsi);
1112         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
1113         dw_mipi_dsi_line_timer_config(dsi);
1114         dw_mipi_dsi_vertical_timing_config(dsi);
1115         dw_mipi_dsi_dphy_timing_config(dsi);
1116         dw_mipi_dsi_dphy_interface_config(dsi);
1117         dw_mipi_dsi_clear_err(dsi);
1118 }
1119
1120 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
1121 {
1122         rockchip_dsi_pre_init(dsi);
1123         rockchip_dsi_host_init(dsi);
1124         dw_mipi_dsi_phy_init(dsi);
1125
1126         if (dsi->slave)
1127                 rockchip_dsi_init(dsi->slave);
1128 }
1129
1130 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
1131 {
1132         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
1133         dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
1134         clk_disable_unprepare(dsi->dphy.ref_clk);
1135         clk_disable_unprepare(dsi->pclk);
1136
1137         if (dsi->slave)
1138                 rockchip_dsi_enable(dsi->slave);
1139 }
1140
1141 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
1142 {
1143         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1144         int vop_id;
1145
1146         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
1147
1148         rockchip_dsi_grf_config(dsi, vop_id);
1149         rockchip_dsi_init(dsi);
1150
1151         if (dsi->panel)
1152                 drm_panel_prepare(dsi->panel);
1153
1154         rockchip_dsi_enable(dsi);
1155
1156         if (dsi->panel)
1157                 drm_panel_enable(dsi->panel);
1158 }
1159
1160 static int
1161 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1162                                  struct drm_crtc_state *crtc_state,
1163                                  struct drm_connector_state *conn_state)
1164 {
1165         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1166         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1167         struct drm_connector *connector = conn_state->connector;
1168         struct drm_display_info *info = &connector->display_info;
1169
1170         switch (dsi->format) {
1171         case MIPI_DSI_FMT_RGB888:
1172                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1173                 break;
1174         case MIPI_DSI_FMT_RGB666:
1175                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1176                 break;
1177         case MIPI_DSI_FMT_RGB565:
1178                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1179                 break;
1180         default:
1181                 WARN_ON(1);
1182                 return -EINVAL;
1183         }
1184
1185         s->output_type = DRM_MODE_CONNECTOR_DSI;
1186         if (info->num_bus_formats)
1187                 s->bus_format = info->bus_formats[0];
1188
1189         if (dsi->slave)
1190                 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL;
1191
1192         return 0;
1193 }
1194
1195 static struct drm_encoder_helper_funcs
1196 dw_mipi_dsi_encoder_helper_funcs = {
1197         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1198         .mode_set = dw_mipi_dsi_encoder_mode_set,
1199         .enable = dw_mipi_dsi_encoder_enable,
1200         .disable = dw_mipi_dsi_encoder_disable,
1201         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1202 };
1203
1204 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1205         .destroy = drm_encoder_cleanup,
1206 };
1207
1208 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1209 {
1210         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1211
1212         return drm_panel_get_modes(dsi->panel);
1213 }
1214
1215 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1216                                         struct drm_connector *connector,
1217                                         struct drm_display_mode *mode)
1218 {
1219         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1220
1221         enum drm_mode_status mode_status = MODE_OK;
1222
1223         if (dsi->pdata->mode_valid)
1224                 mode_status = dsi->pdata->mode_valid(connector, mode);
1225
1226         return mode_status;
1227 }
1228
1229 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1230                                         struct drm_connector *connector)
1231 {
1232         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1233
1234         return &dsi->encoder;
1235 }
1236
1237 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1238 {
1239         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1240
1241         if (dsi->panel)
1242                 drm_panel_loader_protect(dsi->panel, on);
1243         if (on)
1244                 pm_runtime_get_sync(dsi->dev);
1245         else
1246                 pm_runtime_put(dsi->dev);
1247
1248         return 0;
1249 }
1250
1251 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1252         .loader_protect = dw_mipi_loader_protect,
1253         .get_modes = dw_mipi_dsi_connector_get_modes,
1254         .mode_valid = dw_mipi_dsi_mode_valid,
1255         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1256 };
1257
1258 static enum drm_connector_status
1259 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1260 {
1261         return connector_status_connected;
1262 }
1263
1264 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1265 {
1266         drm_connector_unregister(connector);
1267         drm_connector_cleanup(connector);
1268 }
1269
1270 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1271         .dpms = drm_atomic_helper_connector_dpms,
1272         .fill_modes = drm_helper_probe_single_connector_modes,
1273         .detect = dw_mipi_dsi_detect,
1274         .destroy = dw_mipi_dsi_drm_connector_destroy,
1275         .reset = drm_atomic_helper_connector_reset,
1276         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1277         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1278 };
1279
1280 static int rockchip_dsi_dual_channel_probe(struct dw_mipi_dsi *dsi)
1281 {
1282         struct device_node *np;
1283         struct platform_device *secondary;
1284
1285         np = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0);
1286         if (np) {
1287                 secondary = of_find_device_by_node(np);
1288                 dsi->slave = platform_get_drvdata(secondary);
1289                 of_node_put(np);
1290
1291                 if (!dsi->slave)
1292                         return -EPROBE_DEFER;
1293
1294                 dsi->slave->master = dsi;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int dw_mipi_dsi_register(struct drm_device *drm,
1301                                       struct dw_mipi_dsi *dsi)
1302 {
1303         struct drm_encoder *encoder = &dsi->encoder;
1304         struct drm_connector *connector = &dsi->connector;
1305         struct device *dev = dsi->dev;
1306         int ret;
1307
1308         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1309                                                              dev->of_node);
1310         /*
1311          * If we failed to find the CRTC(s) which this encoder is
1312          * supposed to be connected to, it's because the CRTC has
1313          * not been registered yet.  Defer probing, and hope that
1314          * the required CRTC is added later.
1315          */
1316         if (encoder->possible_crtcs == 0)
1317                 return -EPROBE_DEFER;
1318
1319         drm_encoder_helper_add(&dsi->encoder,
1320                                &dw_mipi_dsi_encoder_helper_funcs);
1321         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1322                          DRM_MODE_ENCODER_DSI, NULL);
1323         if (ret) {
1324                 dev_err(dev, "Failed to initialize encoder with drm\n");
1325                 return ret;
1326         }
1327
1328         drm_connector_helper_add(connector,
1329                         &dw_mipi_dsi_connector_helper_funcs);
1330
1331         drm_connector_init(drm, &dsi->connector,
1332                            &dw_mipi_dsi_atomic_connector_funcs,
1333                            DRM_MODE_CONNECTOR_DSI);
1334
1335         drm_panel_attach(dsi->panel, &dsi->connector);
1336
1337         dsi->connector.port = dev->of_node;
1338
1339         drm_mode_connector_attach_encoder(connector, encoder);
1340
1341         return 0;
1342 }
1343
1344 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1345         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1346         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1347         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1348         .dsi1_basedir = RK3288_TXRX_BASEDIR,
1349         .dsi1_masterslavez = RK3288_TXRX_MASTERSLAVEZ,
1350         .grf_dsi1_cfg_reg = RK3288_GRF_SOC_CON14,
1351         .max_data_lanes = 4,
1352         .max_bit_rate_per_lane = 1500000000,
1353         .has_vop_sel = true,
1354 };
1355
1356 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1357         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1358         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1359         .max_data_lanes = 4,
1360         .max_bit_rate_per_lane = 1000000000,
1361         .has_vop_sel = true,
1362 };
1363
1364 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1365         .max_data_lanes = 4,
1366         .max_bit_rate_per_lane = 1000000000,
1367 };
1368
1369 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1370         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1371         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1372         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1373         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1374         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1375         .max_data_lanes = 4,
1376         .max_bit_rate_per_lane = 1500000000,
1377         .has_vop_sel = true,
1378 };
1379
1380 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1381         {
1382          .compatible = "rockchip,rk3288-mipi-dsi",
1383          .data = &rk3288_mipi_dsi_drv_data,
1384         }, {
1385          .compatible = "rockchip,rk3366-mipi-dsi",
1386          .data = &rk3366_mipi_dsi_drv_data,
1387         }, {
1388          .compatible = "rockchip,rk3368-mipi-dsi",
1389          .data = &rk3368_mipi_dsi_drv_data,
1390         }, {
1391          .compatible = "rockchip,rk3399-mipi-dsi",
1392          .data = &rk3399_mipi_dsi_drv_data,
1393         },
1394         { /* sentinel */ }
1395 };
1396 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1397
1398 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1399                              void *data)
1400 {
1401         struct drm_device *drm = data;
1402         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1403         int ret;
1404
1405         ret = rockchip_dsi_dual_channel_probe(dsi);
1406         if (ret)
1407                 return ret;
1408
1409         if (dsi->master)
1410                 return 0;
1411
1412         if (!dsi->panel)
1413                 return -EPROBE_DEFER;
1414
1415         ret = dw_mipi_dsi_register(drm, dsi);
1416         if (ret) {
1417                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1418                 return ret;
1419         }
1420
1421         dev_set_drvdata(dev, dsi);
1422
1423         pm_runtime_enable(dev);
1424         if (dsi->slave)
1425                 pm_runtime_enable(dsi->slave->dev);
1426
1427         return ret;
1428 }
1429
1430 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1431         void *data)
1432 {
1433         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1434
1435         pm_runtime_disable(dev);
1436         if (dsi->slave)
1437                 pm_runtime_disable(dsi->slave->dev);
1438 }
1439
1440 static const struct component_ops dw_mipi_dsi_ops = {
1441         .bind   = dw_mipi_dsi_bind,
1442         .unbind = dw_mipi_dsi_unbind,
1443 };
1444
1445 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
1446 {
1447         struct device *dev = dsi->dev;
1448
1449         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1450         if (IS_ERR(dsi->rst)) {
1451                 dev_info(dev, "no reset control specified\n");
1452                 dsi->rst = NULL;
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int rockchip_dsi_grf_regmap(struct dw_mipi_dsi *dsi)
1459 {
1460         struct device_node *np = dsi->dev->of_node;
1461
1462         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1463         if (IS_ERR(dsi->grf_regmap)) {
1464                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1465                 return PTR_ERR(dsi->grf_regmap);
1466         }
1467
1468         return 0;
1469 }
1470
1471 static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
1472 {
1473         struct device *dev = dsi->dev;
1474         int ret;
1475
1476         dsi->pclk = devm_clk_get(dev, "pclk");
1477         if (IS_ERR(dsi->pclk)) {
1478                 ret = PTR_ERR(dsi->pclk);
1479                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1480                 return ret;
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
1487 {
1488         struct device *dev = dsi->dev;
1489         int ret;
1490
1491         dsi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");
1492         if (IS_ERR(dsi->dphy.phy)) {
1493                 ret = PTR_ERR(dsi->dphy.phy);
1494                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1495                 return ret;
1496         }
1497
1498         if (dsi->dphy.phy) {
1499                 dev_dbg(dev, "Use Non-SNPS PHY\n");
1500
1501                 dsi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");
1502                 if (IS_ERR(dsi->dphy.hs_clk)) {
1503                         dev_err(dev, "failed to get PHY high-speed clock\n");
1504                         return PTR_ERR(dsi->dphy.hs_clk);
1505                 }
1506         } else {
1507                 dev_dbg(dev, "Use SNPS PHY\n");
1508
1509                 dsi->dphy.ref_clk = devm_clk_get(dev, "ref");
1510                 if (IS_ERR(dsi->dphy.ref_clk)) {
1511                         dev_err(dev, "failed to get PHY reference clock\n");
1512                         return PTR_ERR(dsi->dphy.ref_clk);
1513                 }
1514
1515                 /* Check if cfg_clk provided */
1516                 dsi->dphy.cfg_clk = devm_clk_get(dev, "phy_cfg");
1517                 if (IS_ERR(dsi->dphy.cfg_clk)) {
1518                         if (PTR_ERR(dsi->dphy.cfg_clk) != -ENOENT) {
1519                                 dev_err(dev, "failed to get PHY config clk\n");
1520                                 return PTR_ERR(dsi->dphy.cfg_clk);
1521                         }
1522
1523                         /* Otherwise mark the cfg_clk pointer to NULL */
1524                         dsi->dphy.cfg_clk = NULL;
1525                 }
1526         }
1527
1528         return 0;
1529 }
1530
1531 static int rockchip_dsi_ioremap_resource(struct platform_device *pdev,
1532                                          struct dw_mipi_dsi *dsi)
1533 {
1534         struct device *dev = &pdev->dev;
1535         struct resource *res;
1536
1537         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1538         if (!res)
1539                 return -ENODEV;
1540
1541         dsi->base = devm_ioremap_resource(dev, res);
1542         if (IS_ERR(dsi->base))
1543                 return PTR_ERR(dsi->base);
1544
1545         return 0;
1546 }
1547
1548 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1549 {
1550         struct device *dev = &pdev->dev;
1551         const struct of_device_id *of_id =
1552                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1553         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1554         struct dw_mipi_dsi *dsi;
1555         struct device_node *np = dev->of_node;
1556         int ret;
1557         int dsi_id;
1558
1559         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1560         if (!dsi)
1561                 return -ENOMEM;
1562
1563         dsi_id = of_alias_get_id(np, "dsi");
1564         if (dsi_id < 0)
1565                 dsi_id = 0;
1566
1567         dsi->id = dsi_id;
1568         dsi->dev = dev;
1569         dsi->pdata = pdata;
1570
1571         rockchip_dsi_ioremap_resource(pdev, dsi);
1572         rockchip_dsi_clk_get(dsi);
1573         rockchip_dsi_dphy_parse(dsi);
1574         rockchip_dsi_grf_regmap(dsi);
1575         rockchip_dsi_get_reset_handle(dsi);
1576
1577         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1578         dsi->dsi_host.dev = &pdev->dev;
1579
1580         ret = mipi_dsi_host_register(&dsi->dsi_host);
1581         if (ret)
1582                 return ret;
1583
1584         platform_set_drvdata(pdev, dsi);
1585         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1586         if (ret)
1587                 mipi_dsi_host_unregister(&dsi->dsi_host);
1588
1589         return ret;
1590 }
1591
1592 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1593 {
1594         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1595
1596         if (dsi)
1597                 mipi_dsi_host_unregister(&dsi->dsi_host);
1598         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1599         return 0;
1600 }
1601
1602 static struct platform_driver dw_mipi_dsi_driver = {
1603         .probe          = dw_mipi_dsi_probe,
1604         .remove         = dw_mipi_dsi_remove,
1605         .driver         = {
1606                 .of_match_table = dw_mipi_dsi_dt_ids,
1607                 .name   = DRIVER_NAME,
1608         },
1609 };
1610 module_platform_driver(dw_mipi_dsi_driver);
1611
1612 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1613 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1614 MODULE_LICENSE("GPL");
1615 MODULE_ALIAS("platform:" DRIVER_NAME);