drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3366_GRF_SOC_CON0             0x0400
  40 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  41
  42 #define RK3399_GRF_SOC_CON19            0x6250
  43 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  44 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  45
  46 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  47 #define RK3399_GRF_SOC_CON22            0x6258
  48 #define RK3399_GRF_DSI_MODE             0xffff0000
  49
  50 #define DSI_VERSION                     0x00
  51 #define DSI_PWR_UP                      0x04
  52 #define RESET                           0
  53 #define POWERUP                         BIT(0)
  54
  55 #define DSI_CLKMGR_CFG                  0x08
  56 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  57 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  58
  59 #define DSI_DPI_VCID                    0x0c
  60 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  61
  62 #define DSI_DPI_COLOR_CODING            0x10
  63 #define EN18_LOOSELY                    BIT(8)
  64 #define DPI_COLOR_CODING_16BIT_1        0x0
  65 #define DPI_COLOR_CODING_16BIT_2        0x1
  66 #define DPI_COLOR_CODING_16BIT_3        0x2
  67 #define DPI_COLOR_CODING_18BIT_1        0x3
  68 #define DPI_COLOR_CODING_18BIT_2        0x4
  69 #define DPI_COLOR_CODING_24BIT          0x5
  70
  71 #define DSI_DPI_CFG_POL                 0x14
  72 #define COLORM_ACTIVE_LOW               BIT(4)
  73 #define SHUTD_ACTIVE_LOW                BIT(3)
  74 #define HSYNC_ACTIVE_LOW                BIT(2)
  75 #define VSYNC_ACTIVE_LOW                BIT(1)
  76 #define DATAEN_ACTIVE_LOW               BIT(0)
  77
  78 #define DSI_DPI_LP_CMD_TIM              0x18
  79 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  80 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  81
  82 #define DSI_DBI_CFG                     0x20
  83 #define DSI_DBI_CMDSIZE                 0x28
  84
  85 #define DSI_PCKHDL_CFG                  0x2c
  86 #define EN_CRC_RX                       BIT(4)
  87 #define EN_ECC_RX                       BIT(3)
  88 #define EN_BTA                          BIT(2)
  89 #define EN_EOTP_RX                      BIT(1)
  90 #define EN_EOTP_TX                      BIT(0)
  91
  92 #define DSI_MODE_CFG                    0x34
  93 #define ENABLE_VIDEO_MODE               0
  94 #define ENABLE_CMD_MODE                 BIT(0)
  95
  96 #define DSI_VID_MODE_CFG                0x38
  97 #define FRAME_BTA_ACK                   BIT(14)
  98 #define ENABLE_LOW_POWER                (0x3f << 8)
  99 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
 100 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 101 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 102 #define VID_MODE_TYPE_BURST             0x2
 103
 104 #define DSI_VID_PKT_SIZE                0x3c
 105 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 106 #define VID_PKT_MAX_SIZE                0x3fff
 107
 108 #define DSI_VID_NUM_CHUMKS              0x40
 109 #define DSI_VID_NULL_PKT_SIZE           0x44
 110 #define DSI_VID_HSA_TIME                0x48
 111 #define DSI_VID_HBP_TIME                0x4c
 112 #define DSI_VID_HLINE_TIME              0x50
 113 #define DSI_VID_VSA_LINES               0x54
 114 #define DSI_VID_VBP_LINES               0x58
 115 #define DSI_VID_VFP_LINES               0x5c
 116 #define DSI_VID_VACTIVE_LINES           0x60
 117 #define DSI_CMD_MODE_CFG                0x68
 118 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 119 #define DCS_LW_TX_LP                    BIT(19)
 120 #define DCS_SR_0P_TX_LP                 BIT(18)
 121 #define DCS_SW_1P_TX_LP                 BIT(17)
 122 #define DCS_SW_0P_TX_LP                 BIT(16)
 123 #define GEN_LW_TX_LP                    BIT(14)
 124 #define GEN_SR_2P_TX_LP                 BIT(13)
 125 #define GEN_SR_1P_TX_LP                 BIT(12)
 126 #define GEN_SR_0P_TX_LP                 BIT(11)
 127 #define GEN_SW_2P_TX_LP                 BIT(10)
 128 #define GEN_SW_1P_TX_LP                 BIT(9)
 129 #define GEN_SW_0P_TX_LP                 BIT(8)
 130 #define EN_ACK_RQST                     BIT(1)
 131 #define EN_TEAR_FX                      BIT(0)
 132
 133 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 134                                          DCS_LW_TX_LP | \
 135                                          DCS_SR_0P_TX_LP | \
 136                                          DCS_SW_1P_TX_LP | \
 137                                          DCS_SW_0P_TX_LP | \
 138                                          GEN_LW_TX_LP | \
 139                                          GEN_SR_2P_TX_LP | \
 140                                          GEN_SR_1P_TX_LP | \
 141                                          GEN_SR_0P_TX_LP | \
 142                                          GEN_SW_2P_TX_LP | \
 143                                          GEN_SW_1P_TX_LP | \
 144                                          GEN_SW_0P_TX_LP)
 145
 146 #define DSI_GEN_HDR                     0x6c
 147 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 148 #define GEN_HDATA_MASK                  (0xffff << 8)
 149 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 150 #define GEN_HTYPE_MASK                  0xff
 151
 152 #define DSI_GEN_PLD_DATA                0x70
 153
 154 #define DSI_CMD_PKT_STATUS              0x74
 155 #define GEN_CMD_EMPTY                   BIT(0)
 156 #define GEN_CMD_FULL                    BIT(1)
 157 #define GEN_PLD_W_EMPTY                 BIT(2)
 158 #define GEN_PLD_W_FULL                  BIT(3)
 159 #define GEN_PLD_R_EMPTY                 BIT(4)
 160 #define GEN_PLD_R_FULL                  BIT(5)
 161 #define GEN_RD_CMD_BUSY                 BIT(6)
 162
 163 #define DSI_TO_CNT_CFG                  0x78
 164 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 165 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 166
 167 #define DSI_BTA_TO_CNT                  0x8c
 168 #define DSI_LPCLK_CTRL                  0x94
 169 #define AUTO_CLKLANE_CTRL               BIT(1)
 170 #define PHY_TXREQUESTCLKHS              BIT(0)
 171
 172 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 173 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 174 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 175
 176 #define DSI_PHY_TMR_CFG                 0x9c
 177 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 178 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 179 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 180
 181 #define DSI_PHY_RSTZ                    0xa0
 182 #define PHY_DISFORCEPLL                 0
 183 #define PHY_ENFORCEPLL                  BIT(3)
 184 #define PHY_DISABLECLK                  0
 185 #define PHY_ENABLECLK                   BIT(2)
 186 #define PHY_RSTZ                        0
 187 #define PHY_UNRSTZ                      BIT(1)
 188 #define PHY_SHUTDOWNZ                   0
 189 #define PHY_UNSHUTDOWNZ                 BIT(0)
 190
 191 #define DSI_PHY_IF_CFG                  0xa4
 192 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 193 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 194
 195 #define DSI_PHY_STATUS                  0xb0
 196 #define LOCK                            BIT(0)
 197 #define STOP_STATE_CLK_LANE             BIT(2)
 198
 199 #define DSI_PHY_TST_CTRL0               0xb4
 200 #define PHY_TESTCLK                     BIT(1)
 201 #define PHY_UNTESTCLK                   0
 202 #define PHY_TESTCLR                     BIT(0)
 203 #define PHY_UNTESTCLR                   0
 204
 205 #define DSI_PHY_TST_CTRL1               0xb8
 206 #define PHY_TESTEN                      BIT(16)
 207 #define PHY_UNTESTEN                    0
 208 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 209 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 210
 211 #define DSI_INT_ST0                     0xbc
 212 #define DSI_INT_ST1                     0xc0
 213 #define DSI_INT_MSK0                    0xc4
 214 #define DSI_INT_MSK1                    0xc8
 215
 216 #define PHY_STATUS_TIMEOUT_US           10000
 217 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 218
 219 #define BYPASS_VCO_RANGE        BIT(7)
 220 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 221 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 222 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 223 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 224 #define REF_BIAS_CUR_SEL        BIT(0)
 225
 226 #define CP_CURRENT_3MA          BIT(3)
 227 #define CP_PROGRAM_EN           BIT(7)
 228 #define LPF_PROGRAM_EN          BIT(6)
 229 #define LPF_RESISTORS_20_KOHM   0
 230
 231 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 232
 233 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 234 #define LOW_PROGRAM_EN          0
 235 #define HIGH_PROGRAM_EN         BIT(7)
 236 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 237 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 238 #define PLL_LOOP_DIV_EN         BIT(5)
 239 #define PLL_INPUT_DIV_EN        BIT(4)
 240
 241 #define POWER_CONTROL           BIT(6)
 242 #define INTERNAL_REG_CURRENT    BIT(3)
 243 #define BIAS_BLOCK_ON           BIT(2)
 244 #define BANDGAP_ON              BIT(0)
 245
 246 #define TER_RESISTOR_HIGH       BIT(7)
 247 #define TER_RESISTOR_LOW        0
 248 #define LEVEL_SHIFTERS_ON       BIT(6)
 249 #define TER_CAL_DONE            BIT(5)
 250 #define SETRD_MAX               (0x7 << 2)
 251 #define POWER_MANAGE            BIT(1)
 252 #define TER_RESISTORS_ON        BIT(0)
 253
 254 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 255 #define BANDGAP_SEL(val)        ((val) & 0x7)
 256 #define TLP_PROGRAM_EN          BIT(7)
 257 #define THS_PRE_PROGRAM_EN      BIT(7)
 258 #define THS_ZERO_PROGRAM_EN     BIT(6)
 259
 260 enum {
 261         BANDGAP_97_07,
 262         BANDGAP_98_05,
 263         BANDGAP_99_02,
 264         BANDGAP_100_00,
 265         BANDGAP_93_17,
 266         BANDGAP_94_15,
 267         BANDGAP_95_12,
 268         BANDGAP_96_10,
 269 };
 270
 271 enum {
 272         BIASEXTR_87_1,
 273         BIASEXTR_91_5,
 274         BIASEXTR_95_9,
 275         BIASEXTR_100,
 276         BIASEXTR_105_94,
 277         BIASEXTR_111_88,
 278         BIASEXTR_118_8,
 279         BIASEXTR_127_7,
 280 };
 281
 282 struct dw_mipi_dsi_plat_data {
 283         u32 dsi0_en_bit;
 284         u32 dsi1_en_bit;
 285         u32 grf_switch_reg;
 286         u32 grf_dsi0_mode;
 287         u32 grf_dsi0_mode_reg;
 288         unsigned int max_data_lanes;
 289         u32 max_bit_rate_per_lane;
 290         bool has_vop_sel;
 291         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 292                                            struct drm_display_mode *mode);
 293 };
 294
 295 struct dw_mipi_dsi {
 296         struct drm_encoder encoder;
 297         struct drm_connector connector;
 298         struct mipi_dsi_host dsi_host;
 299         struct phy *phy;
 300         struct drm_panel *panel;
 301         struct device *dev;
 302         struct regmap *grf_regmap;
 303         struct reset_control *rst;
 304         void __iomem *base;
 305
 306         struct clk *pllref_clk;
 307         struct clk *pclk;
 308         struct clk *phy_cfg_clk;
 309
 310         unsigned int lane_mbps; /* per lane */
 311         u32 channel;
 312         u32 lanes;
 313         u32 format;
 314         u16 input_div;
 315         u16 feedback_div;
 316         struct drm_display_mode mode;
 317
 318         const struct dw_mipi_dsi_plat_data *pdata;
 319 };
 320
 321 enum dw_mipi_dsi_mode {
 322         DW_MIPI_DSI_CMD_MODE,
 323         DW_MIPI_DSI_VID_MODE,
 324 };
 325
 326 struct dphy_pll_testdin_map {
 327         unsigned int max_mbps;
 328         u8 testdin;
 329 };
 330
 331 /* The table is based on 27MHz DPHY pll reference clock. */
 332 static const struct dphy_pll_testdin_map dptdin_map[] = {
 333         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 334         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 335         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 336         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 337         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 338         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 339         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 340         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 341         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 342         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 343 };
 344
 345 static int max_mbps_to_testdin(unsigned int max_mbps)
 346 {
 347         int i;
 348
 349         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 350                 if (dptdin_map[i].max_mbps > max_mbps)
 351                         return dptdin_map[i].testdin;
 352
 353         return -EINVAL;
 354 }
 355
 356 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 357 {
 358         return container_of(host, struct dw_mipi_dsi, dsi_host);
 359 }
 360
 361 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 362 {
 363         return container_of(con, struct dw_mipi_dsi, connector);
 364 }
 365
 366 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 367 {
 368         return container_of(encoder, struct dw_mipi_dsi, encoder);
 369 }
 370 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 371 {
 372         writel(val, dsi->base + reg);
 373 }
 374
 375 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 376 {
 377         return readl(dsi->base + reg);
 378 }
 379
 380 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 381 {
 382         u32 sts;
 383         int ret;
 384
 385         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 386                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 387                                  CMD_PKT_STATUS_TIMEOUT_US);
 388         if (ret < 0) {
 389                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 390                 return ret;
 391         }
 392
 393         return 0;
 394 }
 395
 396 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 397 {
 398         u32 sts;
 399         int ret;
 400
 401         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 402                                  sts, !(sts & GEN_CMD_FULL), 10,
 403                                  CMD_PKT_STATUS_TIMEOUT_US);
 404         if (ret < 0) {
 405                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 406                 return ret;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 413 {
 414         u32 sts;
 415         u32 mask;
 416         int ret;
 417
 418         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 419         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 420                                  sts, (sts & mask) == mask, 10,
 421                                  CMD_PKT_STATUS_TIMEOUT_US);
 422         if (ret < 0) {
 423                 dev_err(dsi->dev, "generic write fifo is full\n");
 424                 return ret;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 431                                  u8 test_data)
 432 {
 433         /*
 434          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 435          * is latched internally as the current test code. Test data is
 436          * programmed internally by rising edge on TESTCLK.
 437          */
 438         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 439
 440         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 441                                           PHY_TESTDIN(test_code));
 442
 443         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 444
 445         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 446                                           PHY_TESTDIN(test_data));
 447
 448         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 449 }
 450
 451 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 452 {
 453         int ret, testdin, vco, val;
 454
 455         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 456
 457         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 458         if (testdin < 0) {
 459                 dev_err(dsi->dev,
 460                         "failed to get testdin for %dmbps lane clock\n",
 461                         dsi->lane_mbps);
 462                 return testdin;
 463         }
 464
 465         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 466
 467         if (!IS_ERR(dsi->phy_cfg_clk)) {
 468                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 469                 if (ret) {
 470                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 471                         return ret;
 472                 }
 473         }
 474
 475         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 476                                          VCO_RANGE_CON_SEL(vco) |
 477                                          VCO_IN_CAP_CON_LOW |
 478                                          REF_BIAS_CUR_SEL);
 479
 480         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 481         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 482                                          LPF_RESISTORS_20_KOHM);
 483
 484         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 485
 486         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 487         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 488         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 489                                          LOW_PROGRAM_EN);
 490         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 491                                          HIGH_PROGRAM_EN);
 492
 493         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 494                                          BIAS_BLOCK_ON | BANDGAP_ON);
 495
 496         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 497                                          SETRD_MAX | TER_RESISTORS_ON);
 498         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 499                                          SETRD_MAX | POWER_MANAGE |
 500                                          TER_RESISTORS_ON);
 501
 502         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 503                                          BIASEXTR_SEL(BIASEXTR_127_7));
 504         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 505                                          BANDGAP_SEL(BANDGAP_96_10));
 506
 507         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 508         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 509         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 510
 511         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 512                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 513
 514
 515         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 516                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 517         if (ret < 0) {
 518                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 519                 goto phy_init_end;
 520         }
 521
 522         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 523                                  val, val & STOP_STATE_CLK_LANE, 1000,
 524                                  PHY_STATUS_TIMEOUT_US);
 525         if (ret < 0)
 526                 dev_err(dsi->dev,
 527                         "failed to wait for phy clk lane stop state\n");
 528
 529 phy_init_end:
 530         if (!IS_ERR(dsi->phy_cfg_clk))
 531                 clk_disable_unprepare(dsi->phy_cfg_clk);
 532
 533         return ret;
 534 }
 535
 536 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 537 {
 538         unsigned int i, pre;
 539         unsigned long mpclk, pllref, tmp;
 540         unsigned int m = 1, n = 1, target_mbps = 1000;
 541         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 542         int bpp;
 543
 544         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 545         if (bpp < 0) {
 546                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 547                         dsi->format);
 548                 return bpp;
 549         }
 550
 551         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 552         if (mpclk) {
 553                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 554                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 555                 if (tmp < max_mbps)
 556                         target_mbps = tmp;
 557                 else
 558                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 559         }
 560
 561         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 562         tmp = pllref;
 563
 564         for (i = 1; i < 6; i++) {
 565                 pre = pllref / i;
 566                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 567                         tmp = target_mbps % pre;
 568                         n = i;
 569                         m = target_mbps / pre;
 570                 }
 571                 if (tmp == 0)
 572                         break;
 573         }
 574
 575         dsi->lane_mbps = pllref / n * m;
 576         dsi->input_div = n;
 577         dsi->feedback_div = m;
 578
 579         return 0;
 580 }
 581
 582 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 583                                    struct mipi_dsi_device *device)
 584 {
 585         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 586
 587         if (device->lanes > dsi->pdata->max_data_lanes) {
 588                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 589                                 device->lanes);
 590                 return -EINVAL;
 591         }
 592
 593         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 594                 dev_err(dsi->dev, "device mode is unsupported\n");
 595                 return -EINVAL;
 596         }
 597
 598         dsi->lanes = device->lanes;
 599         dsi->channel = device->channel;
 600         dsi->format = device->format;
 601         dsi->panel = of_drm_find_panel(device->dev.of_node);
 602         if (!dsi->panel) {
 603                 DRM_ERROR("failed to find panel\n");
 604                 return -ENODEV;
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 611                                    struct mipi_dsi_device *device)
 612 {
 613         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 614
 615         if (dsi->panel)
 616                 drm_panel_detach(dsi->panel);
 617
 618         dsi->panel = NULL;
 619         return 0;
 620 }
 621
 622 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 623 {
 624         if (flags & MIPI_DSI_MSG_USE_LPM)
 625                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 626         else
 627                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 628 }
 629
 630 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 631                                          const struct mipi_dsi_msg *msg)
 632 {
 633         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 634         struct mipi_dsi_packet packet;
 635         int ret;
 636         int val;
 637         int len = msg->tx_len;
 638
 639         /* create a packet to the DSI protocol */
 640         ret = mipi_dsi_create_packet(&packet, msg);
 641         if (ret) {
 642                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 643                 return ret;
 644         }
 645
 646         rockchip_set_transfer_mode(dsi, msg->flags);
 647
 648         /* Send payload,  */
 649         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 650                 /*
 651                  * Alternatively, you can always keep the FIFO
 652                  * nearly full by monitoring the FIFO state until
 653                  * it is not full, and then writea single word of data.
 654                  * This solution is more resource consuming
 655                  * but it simultaneously avoids FIFO starvation,
 656                  * making it possible to use FIFO sizes smaller than
 657                  * the amount of data of the longest packet to be written.
 658                  */
 659                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 660                 if (ret)
 661                         return ret;
 662
 663                 if (packet.payload_length < 4) {
 664                         /* send residu payload */
 665                         val = 0;
 666                         memcpy(&val, packet.payload, packet.payload_length);
 667                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 668                         packet.payload_length = 0;
 669                 } else {
 670                         val = get_unaligned_le32(packet.payload);
 671                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 672                         packet.payload += 4;
 673                         packet.payload_length -= 4;
 674                 }
 675         }
 676
 677         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 678         if (ret)
 679                 return ret;
 680
 681         /* Send packet header */
 682         val = get_unaligned_le32(packet.header);
 683         dsi_write(dsi, DSI_GEN_HDR, val);
 684
 685         ret = rockchip_wait_write_fifo_empty(dsi);
 686         if (ret)
 687                 return ret;
 688
 689         return len;
 690 }
 691
 692 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 693         .attach = dw_mipi_dsi_host_attach,
 694         .detach = dw_mipi_dsi_host_detach,
 695         .transfer = dw_mipi_dsi_host_transfer,
 696 };
 697
 698 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 699 {
 700         u32 val;
 701
 702         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 703
 704         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 705 }
 706
 707 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 708                                  enum dw_mipi_dsi_mode mode)
 709 {
 710         if (mode == DW_MIPI_DSI_CMD_MODE) {
 711                 dsi_write(dsi, DSI_PWR_UP, RESET);
 712                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 713                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 714         } else {
 715                 dsi_write(dsi, DSI_PWR_UP, RESET);
 716                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 717                 dw_mipi_dsi_video_mode_config(dsi);
 718                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 719         }
 720 }
 721
 722 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 723 {
 724         dsi_write(dsi, DSI_PWR_UP, RESET);
 725         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 726                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 727         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 728                   TX_ESC_CLK_DIVIDSION(7));
 729         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 730 }
 731
 732 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 733                                    struct drm_display_mode *mode)
 734 {
 735         u32 val = 0, color = 0;
 736
 737         switch (dsi->format) {
 738         case MIPI_DSI_FMT_RGB888:
 739                 color = DPI_COLOR_CODING_24BIT;
 740                 break;
 741         case MIPI_DSI_FMT_RGB666:
 742                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 743                 break;
 744         case MIPI_DSI_FMT_RGB666_PACKED:
 745                 color = DPI_COLOR_CODING_18BIT_1;
 746                 break;
 747         case MIPI_DSI_FMT_RGB565:
 748                 color = DPI_COLOR_CODING_16BIT_1;
 749                 break;
 750         }
 751
 752         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 753                 val |= VSYNC_ACTIVE_LOW;
 754         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 755                 val |= HSYNC_ACTIVE_LOW;
 756
 757         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 758         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 759         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 760         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 761                   | INVACT_LPCMD_TIME(4));
 762 }
 763
 764 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 765 {
 766         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 767 }
 768
 769 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 770                                             struct drm_display_mode *mode)
 771 {
 772         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 773 }
 774
 775 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 776 {
 777         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 778         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 779         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 780 }
 781
 782 /* Get lane byte clock cycles. */
 783 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 784                                            u32 hcomponent)
 785 {
 786         u32 frac, lbcc;
 787
 788         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 789
 790         frac = lbcc % dsi->mode.clock;
 791         lbcc = lbcc / dsi->mode.clock;
 792         if (frac)
 793                 lbcc++;
 794
 795         return lbcc;
 796 }
 797
 798 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 799 {
 800         u32 htotal, hsa, hbp, lbcc;
 801         struct drm_display_mode *mode = &dsi->mode;
 802
 803         htotal = mode->htotal;
 804         hsa = mode->hsync_end - mode->hsync_start;
 805         hbp = mode->htotal - mode->hsync_end;
 806
 807         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 808         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 809
 810         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 811         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 812
 813         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 814         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 815 }
 816
 817 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 818 {
 819         u32 vactive, vsa, vfp, vbp;
 820         struct drm_display_mode *mode = &dsi->mode;
 821
 822         vactive = mode->vdisplay;
 823         vsa = mode->vsync_end - mode->vsync_start;
 824         vfp = mode->vsync_start - mode->vdisplay;
 825         vbp = mode->vtotal - mode->vsync_end;
 826
 827         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 828         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 829         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 830         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 831 }
 832
 833 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 834 {
 835         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 836                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 837
 838         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 839                   | PHY_CLKLP2HS_TIME(0x40));
 840 }
 841
 842 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 843 {
 844         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 845                   N_LANES(dsi->lanes));
 846 }
 847
 848 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 849 {
 850         dsi_read(dsi, DSI_INT_ST0);
 851         dsi_read(dsi, DSI_INT_ST1);
 852         dsi_write(dsi, DSI_INT_MSK0, 0);
 853         dsi_write(dsi, DSI_INT_MSK1, 0);
 854 }
 855
 856 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 857                                         struct drm_display_mode *mode,
 858                                         struct drm_display_mode *adjusted_mode)
 859 {
 860         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 861
 862         drm_mode_copy(&dsi->mode, adjusted_mode);
 863 }
 864
 865 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
 866 {
 867         if (clk_prepare_enable(dsi->pclk)) {
 868                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 869                 return;
 870         }
 871
 872         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 873 }
 874
 875 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
 876 {
 877         /* host */
 878         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 879         dsi_write(dsi, DSI_PWR_UP, RESET);
 880
 881         /* phy */
 882         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 883         if (dsi->phy)
 884                 phy_power_off(dsi->phy);
 885
 886         pm_runtime_put(dsi->dev);
 887         clk_disable_unprepare(dsi->pclk);
 888 }
 889
 890 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 891 {
 892         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 893
 894         if (dsi->panel)
 895                 drm_panel_disable(dsi->panel);
 896
 897         rockchip_dsi_pre_disable(dsi);
 898
 899         if (dsi->panel)
 900                 drm_panel_unprepare(dsi->panel);
 901
 902         rockchip_dsi_disable(dsi);
 903 }
 904
 905 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 906                                         const struct drm_display_mode *mode,
 907                                         struct drm_display_mode *adjusted_mode)
 908 {
 909         return true;
 910 }
 911
 912 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
 913 {
 914         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 915         int val = 0;
 916
 917         if (vop_id)
 918                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 919         else
 920                 val = pdata->dsi0_en_bit << 16;
 921
 922         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 923
 924         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
 925 }
 926
 927 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
 928 {
 929         if (clk_prepare_enable(dsi->pclk)) {
 930                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 931                 return;
 932         }
 933
 934         pm_runtime_get_sync(dsi->dev);
 935
 936         if (dsi->rst) {
 937                 /* MIPI DSI APB software reset request. */
 938                 reset_control_assert(dsi->rst);
 939                 udelay(10);
 940                 reset_control_deassert(dsi->rst);
 941                 udelay(10);
 942         }
 943
 944         if (dsi->phy) {
 945                 phy_power_on(dsi->phy);
 946
 947                 /*
 948                  * If using the third party PHY, we get the lane
 949                  * rate information from PHY.
 950                  */
 951                 dsi->lane_mbps = phy_get_bus_width(dsi->phy);
 952         } else {
 953                 dw_mipi_dsi_get_lane_bps(dsi);
 954         }
 955 }
 956
 957 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
 958 {
 959         dw_mipi_dsi_init(dsi);
 960         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 961         dw_mipi_dsi_packet_handler_config(dsi);
 962         dw_mipi_dsi_video_mode_config(dsi);
 963         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 964         dw_mipi_dsi_command_mode_config(dsi);
 965         dw_mipi_dsi_line_timer_config(dsi);
 966         dw_mipi_dsi_vertical_timing_config(dsi);
 967         dw_mipi_dsi_dphy_timing_config(dsi);
 968         dw_mipi_dsi_dphy_interface_config(dsi);
 969         dw_mipi_dsi_clear_err(dsi);
 970 }
 971
 972 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
 973 {
 974         rockchip_dsi_pre_init(dsi);
 975         rockchip_dsi_host_init(dsi);
 976         dw_mipi_dsi_phy_init(dsi);
 977 }
 978
 979 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
 980 {
 981         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 982         clk_disable_unprepare(dsi->pclk);
 983 }
 984
 985 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 986 {
 987         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 988         int vop_id;
 989
 990         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 991
 992         rockchip_dsi_grf_config(dsi, vop_id);
 993         rockchip_dsi_init(dsi);
 994
 995         if (dsi->panel)
 996                 drm_panel_prepare(dsi->panel);
 997
 998         rockchip_dsi_enable(dsi);
 999
1000         if (dsi->panel)
1001                 drm_panel_enable(dsi->panel);
1002 }
1003
1004 static int
1005 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1006                                  struct drm_crtc_state *crtc_state,
1007                                  struct drm_connector_state *conn_state)
1008 {
1009         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1010         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1011         struct drm_connector *connector = conn_state->connector;
1012         struct drm_display_info *info = &connector->display_info;
1013
1014         switch (dsi->format) {
1015         case MIPI_DSI_FMT_RGB888:
1016                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1017                 break;
1018         case MIPI_DSI_FMT_RGB666:
1019                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1020                 break;
1021         case MIPI_DSI_FMT_RGB565:
1022                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1023                 break;
1024         default:
1025                 WARN_ON(1);
1026                 return -EINVAL;
1027         }
1028
1029         s->output_type = DRM_MODE_CONNECTOR_DSI;
1030         if (info->num_bus_formats)
1031                 s->bus_format = info->bus_formats[0];
1032
1033         return 0;
1034 }
1035
1036 static struct drm_encoder_helper_funcs
1037 dw_mipi_dsi_encoder_helper_funcs = {
1038         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1039         .mode_set = dw_mipi_dsi_encoder_mode_set,
1040         .enable = dw_mipi_dsi_encoder_enable,
1041         .disable = dw_mipi_dsi_encoder_disable,
1042         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1043 };
1044
1045 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1046         .destroy = drm_encoder_cleanup,
1047 };
1048
1049 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1050 {
1051         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1052
1053         return drm_panel_get_modes(dsi->panel);
1054 }
1055
1056 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1057                                         struct drm_connector *connector,
1058                                         struct drm_display_mode *mode)
1059 {
1060         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1061
1062         enum drm_mode_status mode_status = MODE_OK;
1063
1064         if (dsi->pdata->mode_valid)
1065                 mode_status = dsi->pdata->mode_valid(connector, mode);
1066
1067         return mode_status;
1068 }
1069
1070 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1071                                         struct drm_connector *connector)
1072 {
1073         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1074
1075         return &dsi->encoder;
1076 }
1077
1078 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1079 {
1080         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1081
1082         if (dsi->panel)
1083                 drm_panel_loader_protect(dsi->panel, on);
1084         if (on)
1085                 pm_runtime_get_sync(dsi->dev);
1086         else
1087                 pm_runtime_put(dsi->dev);
1088
1089         return 0;
1090 }
1091
1092 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1093         .loader_protect = dw_mipi_loader_protect,
1094         .get_modes = dw_mipi_dsi_connector_get_modes,
1095         .mode_valid = dw_mipi_dsi_mode_valid,
1096         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1097 };
1098
1099 static enum drm_connector_status
1100 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1101 {
1102         return connector_status_connected;
1103 }
1104
1105 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1106 {
1107         drm_connector_unregister(connector);
1108         drm_connector_cleanup(connector);
1109 }
1110
1111 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1112         .dpms = drm_atomic_helper_connector_dpms,
1113         .fill_modes = drm_helper_probe_single_connector_modes,
1114         .detect = dw_mipi_dsi_detect,
1115         .destroy = dw_mipi_dsi_drm_connector_destroy,
1116         .reset = drm_atomic_helper_connector_reset,
1117         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1118         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1119 };
1120
1121 static int dw_mipi_dsi_register(struct drm_device *drm,
1122                                       struct dw_mipi_dsi *dsi)
1123 {
1124         struct drm_encoder *encoder = &dsi->encoder;
1125         struct drm_connector *connector = &dsi->connector;
1126         struct device *dev = dsi->dev;
1127         int ret;
1128
1129         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1130                                                              dev->of_node);
1131         /*
1132          * If we failed to find the CRTC(s) which this encoder is
1133          * supposed to be connected to, it's because the CRTC has
1134          * not been registered yet.  Defer probing, and hope that
1135          * the required CRTC is added later.
1136          */
1137         if (encoder->possible_crtcs == 0)
1138                 return -EPROBE_DEFER;
1139
1140         drm_encoder_helper_add(&dsi->encoder,
1141                                &dw_mipi_dsi_encoder_helper_funcs);
1142         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1143                          DRM_MODE_ENCODER_DSI, NULL);
1144         if (ret) {
1145                 dev_err(dev, "Failed to initialize encoder with drm\n");
1146                 return ret;
1147         }
1148
1149         drm_connector_helper_add(connector,
1150                         &dw_mipi_dsi_connector_helper_funcs);
1151
1152         drm_connector_init(drm, &dsi->connector,
1153                            &dw_mipi_dsi_atomic_connector_funcs,
1154                            DRM_MODE_CONNECTOR_DSI);
1155
1156         drm_panel_attach(dsi->panel, &dsi->connector);
1157
1158         dsi->connector.port = dev->of_node;
1159
1160         drm_mode_connector_attach_encoder(connector, encoder);
1161
1162         return 0;
1163 }
1164
1165 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1166 {
1167         struct device_node *np = dsi->dev->of_node;
1168
1169         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1170         if (IS_ERR(dsi->grf_regmap)) {
1171                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1172                 return PTR_ERR(dsi->grf_regmap);
1173         }
1174
1175         return 0;
1176 }
1177
1178 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1179         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1180         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1181         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1182         .max_data_lanes = 4,
1183         .max_bit_rate_per_lane = 1500000000,
1184         .has_vop_sel = true,
1185 };
1186
1187 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1188         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1189         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1190         .max_data_lanes = 4,
1191         .max_bit_rate_per_lane = 1000000000,
1192         .has_vop_sel = true,
1193 };
1194
1195 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1196         .max_data_lanes = 4,
1197         .max_bit_rate_per_lane = 1000000000,
1198 };
1199
1200 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1201         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1202         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1203         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1204         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1205         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1206         .max_data_lanes = 4,
1207         .max_bit_rate_per_lane = 1500000000,
1208         .has_vop_sel = true,
1209 };
1210
1211 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1212         {
1213          .compatible = "rockchip,rk3288-mipi-dsi",
1214          .data = &rk3288_mipi_dsi_drv_data,
1215         }, {
1216          .compatible = "rockchip,rk3366-mipi-dsi",
1217          .data = &rk3366_mipi_dsi_drv_data,
1218         }, {
1219          .compatible = "rockchip,rk3368-mipi-dsi",
1220          .data = &rk3368_mipi_dsi_drv_data,
1221         }, {
1222          .compatible = "rockchip,rk3399-mipi-dsi",
1223          .data = &rk3399_mipi_dsi_drv_data,
1224         },
1225         { /* sentinel */ }
1226 };
1227 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1228
1229 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1230                              void *data)
1231 {
1232         struct platform_device *pdev = to_platform_device(dev);
1233         struct drm_device *drm = data;
1234         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1235         struct resource *res;
1236         int ret;
1237
1238         if (!dsi->panel)
1239                 return -EPROBE_DEFER;
1240
1241         ret = rockchip_mipi_parse_dt(dsi);
1242         if (ret)
1243                 return ret;
1244
1245         dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
1246         if (IS_ERR(dsi->phy)) {
1247                 ret = PTR_ERR(dsi->phy);
1248                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1249                 return ret;
1250         }
1251
1252         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1253         if (!res)
1254                 return -ENODEV;
1255
1256         dsi->base = devm_ioremap_resource(dev, res);
1257         if (IS_ERR(dsi->base))
1258                 return PTR_ERR(dsi->base);
1259
1260         dsi->pclk = devm_clk_get(dev, "pclk");
1261         if (IS_ERR(dsi->pclk)) {
1262                 ret = PTR_ERR(dsi->pclk);
1263                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1264                 return ret;
1265         }
1266
1267         /* optional */
1268         dsi->pllref_clk = devm_clk_get(dev, "ref");
1269         if (IS_ERR(dsi->pllref_clk)) {
1270                 dev_info(dev, "No PHY reference clock specified\n");
1271                 dsi->pllref_clk = NULL;
1272         }
1273
1274         /* optional */
1275         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1276         if (IS_ERR(dsi->phy_cfg_clk)) {
1277                 dev_info(dev, "No PHY APB clock specified\n");
1278                 dsi->phy_cfg_clk = NULL;
1279         }
1280
1281         ret = clk_prepare_enable(dsi->pllref_clk);
1282         if (ret) {
1283                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1284                 return ret;
1285         }
1286
1287         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1288         if (IS_ERR(dsi->rst)) {
1289                 dev_info(dev, "no reset control specified\n");
1290                 dsi->rst = NULL;
1291         }
1292
1293         ret = dw_mipi_dsi_register(drm, dsi);
1294         if (ret) {
1295                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1296                 goto err_pllref;
1297         }
1298
1299         dev_set_drvdata(dev, dsi);
1300
1301         pm_runtime_enable(dev);
1302
1303         return 0;
1304
1305 err_pllref:
1306         clk_disable_unprepare(dsi->pllref_clk);
1307         return ret;
1308 }
1309
1310 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1311         void *data)
1312 {
1313         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1314
1315         pm_runtime_disable(dev);
1316         clk_disable_unprepare(dsi->pllref_clk);
1317 }
1318
1319 static const struct component_ops dw_mipi_dsi_ops = {
1320         .bind   = dw_mipi_dsi_bind,
1321         .unbind = dw_mipi_dsi_unbind,
1322 };
1323
1324 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1325 {
1326         struct device *dev = &pdev->dev;
1327         const struct of_device_id *of_id =
1328                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1329         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1330         struct dw_mipi_dsi *dsi;
1331         int ret;
1332
1333         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1334         if (!dsi)
1335                 return -ENOMEM;
1336
1337         dsi->dev = dev;
1338         dsi->pdata = pdata;
1339         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1340         dsi->dsi_host.dev = &pdev->dev;
1341
1342         ret = mipi_dsi_host_register(&dsi->dsi_host);
1343         if (ret)
1344                 return ret;
1345
1346         platform_set_drvdata(pdev, dsi);
1347         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1348         if (ret)
1349                 mipi_dsi_host_unregister(&dsi->dsi_host);
1350
1351         return ret;
1352 }
1353
1354 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1355 {
1356         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1357
1358         if (dsi)
1359                 mipi_dsi_host_unregister(&dsi->dsi_host);
1360         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1361         return 0;
1362 }
1363
1364 static struct platform_driver dw_mipi_dsi_driver = {
1365         .probe          = dw_mipi_dsi_probe,
1366         .remove         = dw_mipi_dsi_remove,
1367         .driver         = {
1368                 .of_match_table = dw_mipi_dsi_dt_ids,
1369                 .name   = DRIVER_NAME,
1370         },
1371 };
1372 module_platform_driver(dw_mipi_dsi_driver);
1373
1374 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1375 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1376 MODULE_LICENSE("GPL");
1377 MODULE_ALIAS("platform:" DRIVER_NAME);