drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drmP.h>
  26 #include <video/mipi_display.h>
  27
  28 #include "rockchip_drm_drv.h"
  29 #include "rockchip_drm_vop.h"
  30
  31 #define DRIVER_NAME    "dw-mipi-dsi"
  32
  33 #define RK3288_GRF_SOC_CON6             0x025c
  34 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  35 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  36
  37 #define RK3399_GRF_SOC_CON19            0x6250
  38 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  39 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  40
  41 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  42 #define RK3399_GRF_SOC_CON22            0x6258
  43 #define RK3399_GRF_DSI_MODE             0xffff0000
  44
  45 #define DSI_VERSION                     0x00
  46 #define DSI_PWR_UP                      0x04
  47 #define RESET                           0
  48 #define POWERUP                         BIT(0)
  49
  50 #define DSI_CLKMGR_CFG                  0x08
  51 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  52 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  53
  54 #define DSI_DPI_VCID                    0x0c
  55 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  56
  57 #define DSI_DPI_COLOR_CODING            0x10
  58 #define EN18_LOOSELY                    BIT(8)
  59 #define DPI_COLOR_CODING_16BIT_1        0x0
  60 #define DPI_COLOR_CODING_16BIT_2        0x1
  61 #define DPI_COLOR_CODING_16BIT_3        0x2
  62 #define DPI_COLOR_CODING_18BIT_1        0x3
  63 #define DPI_COLOR_CODING_18BIT_2        0x4
  64 #define DPI_COLOR_CODING_24BIT          0x5
  65
  66 #define DSI_DPI_CFG_POL                 0x14
  67 #define COLORM_ACTIVE_LOW               BIT(4)
  68 #define SHUTD_ACTIVE_LOW                BIT(3)
  69 #define HSYNC_ACTIVE_LOW                BIT(2)
  70 #define VSYNC_ACTIVE_LOW                BIT(1)
  71 #define DATAEN_ACTIVE_LOW               BIT(0)
  72
  73 #define DSI_DPI_LP_CMD_TIM              0x18
  74 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  75 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  76
  77 #define DSI_DBI_CFG                     0x20
  78 #define DSI_DBI_CMDSIZE                 0x28
  79
  80 #define DSI_PCKHDL_CFG                  0x2c
  81 #define EN_CRC_RX                       BIT(4)
  82 #define EN_ECC_RX                       BIT(3)
  83 #define EN_BTA                          BIT(2)
  84 #define EN_EOTP_RX                      BIT(1)
  85 #define EN_EOTP_TX                      BIT(0)
  86
  87 #define DSI_MODE_CFG                    0x34
  88 #define ENABLE_VIDEO_MODE               0
  89 #define ENABLE_CMD_MODE                 BIT(0)
  90
  91 #define DSI_VID_MODE_CFG                0x38
  92 #define FRAME_BTA_ACK                   BIT(14)
  93 #define ENABLE_LOW_POWER                (0x3f << 8)
  94 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  95 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
  96 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
  97 #define VID_MODE_TYPE_BURST             0x2
  98
  99 #define DSI_VID_PKT_SIZE                0x3c
 100 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 101 #define VID_PKT_MAX_SIZE                0x3fff
 102
 103 #define DSI_VID_NUM_CHUMKS              0x40
 104 #define DSI_VID_NULL_PKT_SIZE           0x44
 105 #define DSI_VID_HSA_TIME                0x48
 106 #define DSI_VID_HBP_TIME                0x4c
 107 #define DSI_VID_HLINE_TIME              0x50
 108 #define DSI_VID_VSA_LINES               0x54
 109 #define DSI_VID_VBP_LINES               0x58
 110 #define DSI_VID_VFP_LINES               0x5c
 111 #define DSI_VID_VACTIVE_LINES           0x60
 112 #define DSI_CMD_MODE_CFG                0x68
 113 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 114 #define DCS_LW_TX_LP                    BIT(19)
 115 #define DCS_SR_0P_TX_LP                 BIT(18)
 116 #define DCS_SW_1P_TX_LP                 BIT(17)
 117 #define DCS_SW_0P_TX_LP                 BIT(16)
 118 #define GEN_LW_TX_LP                    BIT(14)
 119 #define GEN_SR_2P_TX_LP                 BIT(13)
 120 #define GEN_SR_1P_TX_LP                 BIT(12)
 121 #define GEN_SR_0P_TX_LP                 BIT(11)
 122 #define GEN_SW_2P_TX_LP                 BIT(10)
 123 #define GEN_SW_1P_TX_LP                 BIT(9)
 124 #define GEN_SW_0P_TX_LP                 BIT(8)
 125 #define EN_ACK_RQST                     BIT(1)
 126 #define EN_TEAR_FX                      BIT(0)
 127
 128 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 129                                          DCS_LW_TX_LP | \
 130                                          DCS_SR_0P_TX_LP | \
 131                                          DCS_SW_1P_TX_LP | \
 132                                          DCS_SW_0P_TX_LP | \
 133                                          GEN_LW_TX_LP | \
 134                                          GEN_SR_2P_TX_LP | \
 135                                          GEN_SR_1P_TX_LP | \
 136                                          GEN_SR_0P_TX_LP | \
 137                                          GEN_SW_2P_TX_LP | \
 138                                          GEN_SW_1P_TX_LP | \
 139                                          GEN_SW_0P_TX_LP)
 140
 141 #define DSI_GEN_HDR                     0x6c
 142 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 143 #define GEN_HDATA_MASK                  (0xffff << 8)
 144 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 145 #define GEN_HTYPE_MASK                  0xff
 146
 147 #define DSI_GEN_PLD_DATA                0x70
 148
 149 #define DSI_CMD_PKT_STATUS              0x74
 150 #define GEN_CMD_EMPTY                   BIT(0)
 151 #define GEN_CMD_FULL                    BIT(1)
 152 #define GEN_PLD_W_EMPTY                 BIT(2)
 153 #define GEN_PLD_W_FULL                  BIT(3)
 154 #define GEN_PLD_R_EMPTY                 BIT(4)
 155 #define GEN_PLD_R_FULL                  BIT(5)
 156 #define GEN_RD_CMD_BUSY                 BIT(6)
 157
 158 #define DSI_TO_CNT_CFG                  0x78
 159 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 160 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 161
 162 #define DSI_BTA_TO_CNT                  0x8c
 163 #define DSI_LPCLK_CTRL                  0x94
 164 #define AUTO_CLKLANE_CTRL               BIT(1)
 165 #define PHY_TXREQUESTCLKHS              BIT(0)
 166
 167 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 168 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 169 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 170
 171 #define DSI_PHY_TMR_CFG                 0x9c
 172 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 173 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 174 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 175
 176 #define DSI_PHY_RSTZ                    0xa0
 177 #define PHY_DISFORCEPLL                 0
 178 #define PHY_ENFORCEPLL                  BIT(3)
 179 #define PHY_DISABLECLK                  0
 180 #define PHY_ENABLECLK                   BIT(2)
 181 #define PHY_RSTZ                        0
 182 #define PHY_UNRSTZ                      BIT(1)
 183 #define PHY_SHUTDOWNZ                   0
 184 #define PHY_UNSHUTDOWNZ                 BIT(0)
 185
 186 #define DSI_PHY_IF_CFG                  0xa4
 187 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 188 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 189
 190 #define DSI_PHY_STATUS                  0xb0
 191 #define LOCK                            BIT(0)
 192 #define STOP_STATE_CLK_LANE             BIT(2)
 193
 194 #define DSI_PHY_TST_CTRL0               0xb4
 195 #define PHY_TESTCLK                     BIT(1)
 196 #define PHY_UNTESTCLK                   0
 197 #define PHY_TESTCLR                     BIT(0)
 198 #define PHY_UNTESTCLR                   0
 199
 200 #define DSI_PHY_TST_CTRL1               0xb8
 201 #define PHY_TESTEN                      BIT(16)
 202 #define PHY_UNTESTEN                    0
 203 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 204 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 205
 206 #define DSI_INT_ST0                     0xbc
 207 #define DSI_INT_ST1                     0xc0
 208 #define DSI_INT_MSK0                    0xc4
 209 #define DSI_INT_MSK1                    0xc8
 210
 211 #define PHY_STATUS_TIMEOUT_US           10000
 212 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 213
 214 #define BYPASS_VCO_RANGE        BIT(7)
 215 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 216 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 217 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 218 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 219 #define REF_BIAS_CUR_SEL        BIT(0)
 220
 221 #define CP_CURRENT_3MA          BIT(3)
 222 #define CP_PROGRAM_EN           BIT(7)
 223 #define LPF_PROGRAM_EN          BIT(6)
 224 #define LPF_RESISTORS_20_KOHM   0
 225
 226 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 227
 228 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 229 #define LOW_PROGRAM_EN          0
 230 #define HIGH_PROGRAM_EN         BIT(7)
 231 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 232 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 233 #define PLL_LOOP_DIV_EN         BIT(5)
 234 #define PLL_INPUT_DIV_EN        BIT(4)
 235
 236 #define POWER_CONTROL           BIT(6)
 237 #define INTERNAL_REG_CURRENT    BIT(3)
 238 #define BIAS_BLOCK_ON           BIT(2)
 239 #define BANDGAP_ON              BIT(0)
 240
 241 #define TER_RESISTOR_HIGH       BIT(7)
 242 #define TER_RESISTOR_LOW        0
 243 #define LEVEL_SHIFTERS_ON       BIT(6)
 244 #define TER_CAL_DONE            BIT(5)
 245 #define SETRD_MAX               (0x7 << 2)
 246 #define POWER_MANAGE            BIT(1)
 247 #define TER_RESISTORS_ON        BIT(0)
 248
 249 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 250 #define BANDGAP_SEL(val)        ((val) & 0x7)
 251 #define TLP_PROGRAM_EN          BIT(7)
 252 #define THS_PRE_PROGRAM_EN      BIT(7)
 253 #define THS_ZERO_PROGRAM_EN     BIT(6)
 254
 255 enum {
 256         BANDGAP_97_07,
 257         BANDGAP_98_05,
 258         BANDGAP_99_02,
 259         BANDGAP_100_00,
 260         BANDGAP_93_17,
 261         BANDGAP_94_15,
 262         BANDGAP_95_12,
 263         BANDGAP_96_10,
 264 };
 265
 266 enum {
 267         BIASEXTR_87_1,
 268         BIASEXTR_91_5,
 269         BIASEXTR_95_9,
 270         BIASEXTR_100,
 271         BIASEXTR_105_94,
 272         BIASEXTR_111_88,
 273         BIASEXTR_118_8,
 274         BIASEXTR_127_7,
 275 };
 276
 277 struct dw_mipi_dsi_plat_data {
 278         u32 dsi0_en_bit;
 279         u32 dsi1_en_bit;
 280         u32 grf_switch_reg;
 281         u32 grf_dsi0_mode;
 282         u32 grf_dsi0_mode_reg;
 283         unsigned int max_data_lanes;
 284         u32 max_bit_rate_per_lane;
 285         bool has_separate_phy;
 286         bool has_phy_pclk;
 287         bool has_phy_refclk;
 288         bool has_vop_sel;
 289         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 290                                            struct drm_display_mode *mode);
 291 };
 292
 293 struct dw_mipi_dsi {
 294         struct drm_encoder encoder;
 295         struct drm_connector connector;
 296         struct mipi_dsi_host dsi_host;
 297         struct phy *phy;
 298         struct drm_panel *panel;
 299         struct device *dev;
 300         struct regmap *grf_regmap;
 301         void __iomem *base;
 302
 303         struct clk *pllref_clk;
 304         struct clk *pclk;
 305         struct clk *phy_cfg_clk;
 306
 307         unsigned int lane_mbps; /* per lane */
 308         u32 channel;
 309         u32 lanes;
 310         u32 format;
 311         u16 input_div;
 312         u16 feedback_div;
 313         struct drm_display_mode mode;
 314
 315         const struct dw_mipi_dsi_plat_data *pdata;
 316 };
 317
 318 enum dw_mipi_dsi_mode {
 319         DW_MIPI_DSI_CMD_MODE,
 320         DW_MIPI_DSI_VID_MODE,
 321 };
 322
 323 struct dphy_pll_testdin_map {
 324         unsigned int max_mbps;
 325         u8 testdin;
 326 };
 327
 328 /* The table is based on 27MHz DPHY pll reference clock. */
 329 static const struct dphy_pll_testdin_map dptdin_map[] = {
 330         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 331         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 332         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 333         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 334         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 335         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 336         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 337         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 338         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 339         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 340 };
 341
 342 static int max_mbps_to_testdin(unsigned int max_mbps)
 343 {
 344         int i;
 345
 346         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 347                 if (dptdin_map[i].max_mbps > max_mbps)
 348                         return dptdin_map[i].testdin;
 349
 350         return -EINVAL;
 351 }
 352
 353 /*
 354  * The controller should generate 2 frames before
 355  * preparing the peripheral.
 356  */
 357 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 358 {
 359         int refresh, two_frames;
 360
 361         refresh = drm_mode_vrefresh(&dsi->mode);
 362         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 363         msleep(two_frames);
 364 }
 365
 366 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 367 {
 368         return container_of(host, struct dw_mipi_dsi, dsi_host);
 369 }
 370
 371 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 372 {
 373         return container_of(con, struct dw_mipi_dsi, connector);
 374 }
 375
 376 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 377 {
 378         return container_of(encoder, struct dw_mipi_dsi, encoder);
 379 }
 380 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 381 {
 382         writel(val, dsi->base + reg);
 383 }
 384
 385 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 386 {
 387         return readl(dsi->base + reg);
 388 }
 389
 390 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 391                                  u8 test_data)
 392 {
 393         /*
 394          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 395          * is latched internally as the current test code. Test data is
 396          * programmed internally by rising edge on TESTCLK.
 397          */
 398         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 399
 400         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 401                                           PHY_TESTDIN(test_code));
 402
 403         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 404
 405         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 406                                           PHY_TESTDIN(test_data));
 407
 408         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 409 }
 410
 411 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 412 {
 413         int ret, testdin, vco, val;
 414
 415         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 416
 417         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 418         if (testdin < 0) {
 419                 dev_err(dsi->dev,
 420                         "failed to get testdin for %dmbps lane clock\n",
 421                         dsi->lane_mbps);
 422                 return testdin;
 423         }
 424
 425         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 426
 427         if (!IS_ERR(dsi->phy_cfg_clk)) {
 428                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 429                 if (ret) {
 430                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 431                         return ret;
 432                 }
 433         }
 434
 435         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 436                                          VCO_RANGE_CON_SEL(vco) |
 437                                          VCO_IN_CAP_CON_LOW |
 438                                          REF_BIAS_CUR_SEL);
 439
 440         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 441         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 442                                          LPF_RESISTORS_20_KOHM);
 443
 444         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 445
 446         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 447         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 448         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 449                                          LOW_PROGRAM_EN);
 450         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 451                                          HIGH_PROGRAM_EN);
 452
 453         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 454                                          BIAS_BLOCK_ON | BANDGAP_ON);
 455
 456         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 457                                          SETRD_MAX | TER_RESISTORS_ON);
 458         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 459                                          SETRD_MAX | POWER_MANAGE |
 460                                          TER_RESISTORS_ON);
 461
 462         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 463                                          BIASEXTR_SEL(BIASEXTR_127_7));
 464         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 465                                          BANDGAP_SEL(BANDGAP_96_10));
 466
 467         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 468         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 469         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 470
 471         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 472                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 473
 474
 475         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 476                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 477         if (ret < 0) {
 478                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 479                 goto phy_init_end;
 480         }
 481
 482         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 483                                  val, val & STOP_STATE_CLK_LANE, 1000,
 484                                  PHY_STATUS_TIMEOUT_US);
 485         if (ret < 0)
 486                 dev_err(dsi->dev,
 487                         "failed to wait for phy clk lane stop state\n");
 488
 489 phy_init_end:
 490         if (!IS_ERR(dsi->phy_cfg_clk))
 491                 clk_disable_unprepare(dsi->phy_cfg_clk);
 492
 493         return ret;
 494 }
 495
 496 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 497 {
 498         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 499         unsigned int i, pre;
 500         unsigned long mpclk, pllref, tmp;
 501         unsigned int m = 1, n = 1, target_mbps = 1000;
 502         unsigned int max_mbps = pdata->max_bit_rate_per_lane / USEC_PER_SEC;
 503         int bpp;
 504
 505         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 506         if (bpp < 0) {
 507                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 508                         dsi->format);
 509                 return bpp;
 510         }
 511
 512         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 513         if (mpclk) {
 514                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 515                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 516                 if (tmp < max_mbps)
 517                         target_mbps = tmp;
 518                 else
 519                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 520         }
 521
 522         if (pdata->has_phy_refclk)
 523                 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk),
 524                                       USEC_PER_SEC);
 525         else
 526                 pllref = DIV_ROUND_UP(12000000, USEC_PER_SEC);
 527
 528         tmp = pllref;
 529
 530         for (i = 1; i < 6; i++) {
 531                 pre = pllref / i;
 532                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 533                         tmp = target_mbps % pre;
 534                         n = i;
 535                         m = target_mbps / pre;
 536                 }
 537                 if (tmp == 0)
 538                         break;
 539         }
 540
 541         dsi->lane_mbps = pllref / n * m;
 542         dsi->input_div = n;
 543         dsi->feedback_div = m;
 544
 545         return 0;
 546 }
 547
 548 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 549                                    struct mipi_dsi_device *device)
 550 {
 551         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 552
 553         if (device->lanes > dsi->pdata->max_data_lanes) {
 554                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 555                                 device->lanes);
 556                 return -EINVAL;
 557         }
 558
 559         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 560                 dev_err(dsi->dev, "device mode is unsupported\n");
 561                 return -EINVAL;
 562         }
 563
 564         dsi->lanes = device->lanes;
 565         dsi->channel = device->channel;
 566         dsi->format = device->format;
 567
 568         dsi->panel = of_drm_find_panel(device->dev.of_node);
 569         if (!dsi->panel) {
 570                 DRM_ERROR("failed to find panel\n");
 571                 return -ENODEV;
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 578                                    struct mipi_dsi_device *device)
 579 {
 580         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 581
 582         if (dsi->panel)
 583                 drm_panel_detach(dsi->panel);
 584
 585         dsi->panel = NULL;
 586         return 0;
 587 }
 588
 589 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 590 {
 591         int ret;
 592         int sts = 0;
 593
 594         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 595                                  sts, !(sts & GEN_CMD_FULL), 1000,
 596                                  CMD_PKT_STATUS_TIMEOUT_US);
 597
 598         if (ret < 0) {
 599                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 600                 return ret;
 601         }
 602
 603         dsi_write(dsi, DSI_GEN_HDR, val);
 604
 605         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 606                                  sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 607                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 608
 609         if (ret < 0) {
 610                 dev_err(dsi->dev, "failed to write command FIFO\n");
 611                 return ret;
 612         }
 613
 614         return 0;
 615 }
 616
 617 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
 618                                    const struct mipi_dsi_msg *msg)
 619 {
 620         const u16 *tx_buf = msg->tx_buf;
 621         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 622
 623         if (msg->tx_len > 2) {
 624                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 625                         msg->tx_len);
 626                 return -EINVAL;
 627         }
 628
 629         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 630 }
 631
 632 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
 633                                   const struct mipi_dsi_msg *msg)
 634 {
 635         const u32 *tx_buf = msg->tx_buf;
 636         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 637         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 638         u32 remainder = 0;
 639         u32 sts = 0;
 640
 641         if (msg->tx_len < 3) {
 642                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 643                         msg->tx_len);
 644                 return -EINVAL;
 645         }
 646
 647         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 648                 if (len < pld_data_bytes) {
 649                         memcpy(&remainder, tx_buf, len);
 650                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 651                         len = 0;
 652                 } else {
 653                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 654                         tx_buf++;
 655                         len -= pld_data_bytes;
 656                 }
 657
 658                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 659                                          sts, !(sts & GEN_PLD_W_FULL), 1000,
 660                                          CMD_PKT_STATUS_TIMEOUT_US);
 661                 if (ret < 0) {
 662                         dev_err(dsi->dev,
 663                                 "failed to get available write payload FIFO\n");
 664                         return ret;
 665                 }
 666         }
 667
 668         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 669 }
 670
 671 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 672                                          const struct mipi_dsi_msg *msg)
 673 {
 674         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 675         int ret;
 676
 677         switch (msg->type) {
 678         case MIPI_DSI_DCS_SHORT_WRITE:
 679         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 680         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 681         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 682         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 683         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 684                 ret = dw_mipi_dsi_short_write(dsi, msg);
 685                 break;
 686         case MIPI_DSI_DCS_LONG_WRITE:
 687         case MIPI_DSI_GENERIC_LONG_WRITE:
 688                 ret = dw_mipi_dsi_long_write(dsi, msg);
 689                 break;
 690         default:
 691                 dev_err(dsi->dev, "unsupported message type\n");
 692                 ret = -EINVAL;
 693         }
 694
 695         return ret;
 696 }
 697
 698 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 699         .attach = dw_mipi_dsi_host_attach,
 700         .detach = dw_mipi_dsi_host_detach,
 701         .transfer = dw_mipi_dsi_host_transfer,
 702 };
 703
 704 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 705 {
 706         u32 val;
 707
 708         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 709
 710         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 711 }
 712
 713 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 714                                  enum dw_mipi_dsi_mode mode)
 715 {
 716         if (mode == DW_MIPI_DSI_CMD_MODE) {
 717                 dsi_write(dsi, DSI_PWR_UP, RESET);
 718                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 719                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 720         } else {
 721                 dsi_write(dsi, DSI_PWR_UP, RESET);
 722                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 723                 dw_mipi_dsi_video_mode_config(dsi);
 724                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 725         }
 726 }
 727
 728 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 729 {
 730         dsi_write(dsi, DSI_PWR_UP, RESET);
 731         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 732 }
 733
 734 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 735 {
 736         dsi_write(dsi, DSI_PWR_UP, RESET);
 737         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 738                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 739         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 740                   TX_ESC_CLK_DIVIDSION(7));
 741         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 742 }
 743
 744 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 745                                    struct drm_display_mode *mode)
 746 {
 747         u32 val = 0, color = 0;
 748
 749         switch (dsi->format) {
 750         case MIPI_DSI_FMT_RGB888:
 751                 color = DPI_COLOR_CODING_24BIT;
 752                 break;
 753         case MIPI_DSI_FMT_RGB666:
 754                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 755                 break;
 756         case MIPI_DSI_FMT_RGB666_PACKED:
 757                 color = DPI_COLOR_CODING_18BIT_1;
 758                 break;
 759         case MIPI_DSI_FMT_RGB565:
 760                 color = DPI_COLOR_CODING_16BIT_1;
 761                 break;
 762         }
 763
 764         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 765                 val |= VSYNC_ACTIVE_LOW;
 766         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 767                 val |= HSYNC_ACTIVE_LOW;
 768
 769         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 770         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 771         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 772         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 773                   | INVACT_LPCMD_TIME(4));
 774 }
 775
 776 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 777 {
 778         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 779 }
 780
 781 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 782                                             struct drm_display_mode *mode)
 783 {
 784         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 785 }
 786
 787 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 788 {
 789         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 790         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 791         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 792         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 793 }
 794
 795 /* Get lane byte clock cycles. */
 796 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 797                                            u32 hcomponent)
 798 {
 799         u32 frac, lbcc;
 800
 801         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 802
 803         frac = lbcc % dsi->mode.clock;
 804         lbcc = lbcc / dsi->mode.clock;
 805         if (frac)
 806                 lbcc++;
 807
 808         return lbcc;
 809 }
 810
 811 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 812 {
 813         u32 htotal, hsa, hbp, lbcc;
 814         struct drm_display_mode *mode = &dsi->mode;
 815
 816         htotal = mode->htotal;
 817         hsa = mode->hsync_end - mode->hsync_start;
 818         hbp = mode->htotal - mode->hsync_end;
 819
 820         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 821         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 822
 823         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 824         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 825
 826         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 827         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 828 }
 829
 830 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 831 {
 832         u32 vactive, vsa, vfp, vbp;
 833         struct drm_display_mode *mode = &dsi->mode;
 834
 835         vactive = mode->vdisplay;
 836         vsa = mode->vsync_end - mode->vsync_start;
 837         vfp = mode->vsync_start - mode->vdisplay;
 838         vbp = mode->vtotal - mode->vsync_end;
 839
 840         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 841         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 842         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 843         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 844 }
 845
 846 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 847 {
 848         /*
 849          * HS-PREPARE: 40ns + 4 * UI ~ 85ns + 6 * UI
 850          * HS-EXIT: 100ns
 851          */
 852         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 853                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 854
 855         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 856                   | PHY_CLKLP2HS_TIME(0x40));
 857 }
 858
 859 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 860 {
 861         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 862                   N_LANES(dsi->lanes));
 863 }
 864
 865 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 866 {
 867         dsi_read(dsi, DSI_INT_ST0);
 868         dsi_read(dsi, DSI_INT_ST1);
 869         dsi_write(dsi, DSI_INT_MSK0, 0);
 870         dsi_write(dsi, DSI_INT_MSK1, 0);
 871 }
 872
 873 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 874                                         struct drm_display_mode *mode,
 875                                         struct drm_display_mode *adjusted_mode)
 876 {
 877         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 878
 879         drm_mode_copy(&dsi->mode, adjusted_mode);
 880 }
 881
 882 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 883 {
 884         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 885
 886         drm_panel_disable(dsi->panel);
 887
 888         if (clk_prepare_enable(dsi->pclk)) {
 889                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 890                 return;
 891         }
 892
 893         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 894         drm_panel_unprepare(dsi->panel);
 895         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 896
 897         /*
 898          * This is necessary to make sure the peripheral will be driven
 899          * normally when the display is enabled again later.
 900          */
 901         msleep(120);
 902
 903         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 904         dw_mipi_dsi_disable(dsi);
 905         phy_power_off(dsi->phy);
 906         pm_runtime_put(dsi->dev);
 907         clk_disable_unprepare(dsi->pclk);
 908 }
 909
 910 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 911                                         const struct drm_display_mode *mode,
 912                                         struct drm_display_mode *adjusted_mode)
 913 {
 914         return true;
 915 }
 916
 917 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 918 {
 919         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 920         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 921         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 922         int ret;
 923         u32 val;
 924
 925         if (clk_prepare_enable(dsi->pclk)) {
 926                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 927                 return;
 928         }
 929
 930         ret = dw_mipi_dsi_get_lane_bps(dsi);
 931         if (ret < 0)
 932                 return;
 933
 934         pm_runtime_get_sync(dsi->dev);
 935
 936         phy_power_on(dsi->phy);
 937         dw_mipi_dsi_init(dsi);
 938         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 939         dw_mipi_dsi_packet_handler_config(dsi);
 940         dw_mipi_dsi_video_mode_config(dsi);
 941         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 942         dw_mipi_dsi_command_mode_config(dsi);
 943         dw_mipi_dsi_line_timer_config(dsi);
 944         dw_mipi_dsi_vertical_timing_config(dsi);
 945         dw_mipi_dsi_dphy_timing_config(dsi);
 946         dw_mipi_dsi_dphy_interface_config(dsi);
 947         dw_mipi_dsi_clear_err(dsi);
 948         if (drm_panel_prepare(dsi->panel))
 949                 dev_err(dsi->dev, "failed to prepare panel\n");
 950
 951         if (pdata->grf_dsi0_mode_reg)
 952                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 953                              pdata->grf_dsi0_mode);
 954
 955         dw_mipi_dsi_phy_init(dsi);
 956         dw_mipi_dsi_wait_for_two_frames(dsi);
 957
 958         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 959         drm_panel_enable(dsi->panel);
 960
 961         clk_disable_unprepare(dsi->pclk);
 962
 963         if (!pdata->has_vop_sel)
 964                 return;
 965
 966         if (mux)
 967                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 968         else
 969                 val = pdata->dsi0_en_bit << 16;
 970
 971         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 972         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 973 }
 974
 975 static int
 976 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 977                                  struct drm_crtc_state *crtc_state,
 978                                  struct drm_connector_state *conn_state)
 979 {
 980         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 981         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 982         struct drm_connector *connector = conn_state->connector;
 983         struct drm_display_info *info = &connector->display_info;
 984
 985         switch (dsi->format) {
 986         case MIPI_DSI_FMT_RGB888:
 987                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 988                 break;
 989         case MIPI_DSI_FMT_RGB666:
 990                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 991                 break;
 992         case MIPI_DSI_FMT_RGB565:
 993                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 994                 break;
 995         default:
 996                 WARN_ON(1);
 997                 return -EINVAL;
 998         }
 999
1000         s->output_type = DRM_MODE_CONNECTOR_DSI;
1001         if (info->num_bus_formats)
1002                 s->bus_format = info->bus_formats[0];
1003
1004         return 0;
1005 }
1006
1007 static struct drm_encoder_helper_funcs
1008 dw_mipi_dsi_encoder_helper_funcs = {
1009         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1010         .mode_set = dw_mipi_dsi_encoder_mode_set,
1011         .enable = dw_mipi_dsi_encoder_enable,
1012         .disable = dw_mipi_dsi_encoder_disable,
1013         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1014 };
1015
1016 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1017         .destroy = drm_encoder_cleanup,
1018 };
1019
1020 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1021 {
1022         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1023
1024         return drm_panel_get_modes(dsi->panel);
1025 }
1026
1027 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1028                                         struct drm_connector *connector,
1029                                         struct drm_display_mode *mode)
1030 {
1031         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1032
1033         enum drm_mode_status mode_status = MODE_OK;
1034
1035         if (dsi->pdata->mode_valid)
1036                 mode_status = dsi->pdata->mode_valid(connector, mode);
1037
1038         return mode_status;
1039 }
1040
1041 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1042                                         struct drm_connector *connector)
1043 {
1044         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1045
1046         return &dsi->encoder;
1047 }
1048
1049 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1050         .get_modes = dw_mipi_dsi_connector_get_modes,
1051         .mode_valid = dw_mipi_dsi_mode_valid,
1052         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1053 };
1054
1055 static enum drm_connector_status
1056 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1057 {
1058         return connector_status_connected;
1059 }
1060
1061 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1062 {
1063         drm_connector_unregister(connector);
1064         drm_connector_cleanup(connector);
1065 }
1066
1067 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1068         .dpms = drm_atomic_helper_connector_dpms,
1069         .fill_modes = drm_helper_probe_single_connector_modes,
1070         .detect = dw_mipi_dsi_detect,
1071         .destroy = dw_mipi_dsi_drm_connector_destroy,
1072         .reset = drm_atomic_helper_connector_reset,
1073         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1074         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1075 };
1076
1077 static int dw_mipi_dsi_register(struct drm_device *drm,
1078                                       struct dw_mipi_dsi *dsi)
1079 {
1080         struct drm_encoder *encoder = &dsi->encoder;
1081         struct drm_connector *connector = &dsi->connector;
1082         struct device *dev = dsi->dev;
1083         int ret;
1084
1085         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1086                                                              dev->of_node);
1087         /*
1088          * If we failed to find the CRTC(s) which this encoder is
1089          * supposed to be connected to, it's because the CRTC has
1090          * not been registered yet.  Defer probing, and hope that
1091          * the required CRTC is added later.
1092          */
1093         if (encoder->possible_crtcs == 0)
1094                 return -EPROBE_DEFER;
1095
1096         drm_encoder_helper_add(&dsi->encoder,
1097                                &dw_mipi_dsi_encoder_helper_funcs);
1098         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1099                          DRM_MODE_ENCODER_DSI, NULL);
1100         if (ret) {
1101                 dev_err(dev, "Failed to initialize encoder with drm\n");
1102                 return ret;
1103         }
1104
1105         drm_connector_helper_add(connector,
1106                         &dw_mipi_dsi_connector_helper_funcs);
1107
1108         drm_connector_init(drm, &dsi->connector,
1109                            &dw_mipi_dsi_atomic_connector_funcs,
1110                            DRM_MODE_CONNECTOR_DSI);
1111
1112         drm_panel_attach(dsi->panel, &dsi->connector);
1113
1114         dsi->connector.port = dev->of_node;
1115
1116         drm_mode_connector_attach_encoder(connector, encoder);
1117
1118         return 0;
1119 }
1120
1121 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1122 {
1123         struct device_node *np = dsi->dev->of_node;
1124
1125         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1126         if (IS_ERR(dsi->grf_regmap)) {
1127                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1128                 return PTR_ERR(dsi->grf_regmap);
1129         }
1130
1131         return 0;
1132 }
1133
1134 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1135         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1136         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1137         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1138         .max_data_lanes = 4,
1139         .max_bit_rate_per_lane = 1500000000,
1140         .has_vop_sel = true,
1141         .has_phy_refclk = true,
1142         .has_phy_pclk = true,
1143 };
1144
1145 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1146         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1147         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1148         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1149         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1150         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1151         .max_data_lanes = 4,
1152         .max_bit_rate_per_lane = 1500000000,
1153         .has_vop_sel = true,
1154         .has_phy_refclk = true,
1155         .has_phy_pclk = true,
1156 };
1157
1158 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1159         .max_data_lanes = 4,
1160         .max_bit_rate_per_lane = 1000000000,
1161         .has_separate_phy = true,
1162 };
1163
1164 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1165         {
1166          .compatible = "rockchip,rk3288-mipi-dsi",
1167          .data = &rk3288_mipi_dsi_drv_data,
1168         },{
1169          .compatible = "rockchip,rk3399-mipi-dsi",
1170          .data = &rk3399_mipi_dsi_drv_data,
1171         }, {
1172          .compatible = "rockchip,rk3368-mipi-dsi",
1173          .data = &rk3368_mipi_dsi_drv_data,
1174         },
1175         { /* sentinel */ }
1176 };
1177 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1178
1179 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1180                              void *data)
1181 {
1182         struct platform_device *pdev = to_platform_device(dev);
1183         struct drm_device *drm = data;
1184         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1185         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
1186         struct resource *res;
1187         int ret;
1188
1189         if (!dsi->panel)
1190                 return -EPROBE_DEFER;
1191
1192         ret = rockchip_mipi_parse_dt(dsi);
1193         if (ret)
1194                 return ret;
1195
1196         if (pdata->has_separate_phy) {
1197                 dsi->phy = devm_phy_get(dev, "mipi_dphy");
1198                 if (IS_ERR(dsi->phy)) {
1199                         dev_err(dev, "failed to get mipi dphy\n");
1200                         return PTR_ERR(dsi->phy);
1201                 }
1202         }
1203
1204         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1205         if (!res)
1206                 return -ENODEV;
1207
1208         dsi->base = devm_ioremap_resource(dev, res);
1209         if (IS_ERR(dsi->base))
1210                 return PTR_ERR(dsi->base);
1211
1212         dsi->pclk = devm_clk_get(dev, "pclk");
1213         if (IS_ERR(dsi->pclk)) {
1214                 ret = PTR_ERR(dsi->pclk);
1215                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1216                 return ret;
1217         }
1218
1219         if (pdata->has_phy_refclk) {
1220                 dsi->pllref_clk = devm_clk_get(dev, "ref");
1221                 if (IS_ERR(dsi->pllref_clk)) {
1222                         ret = PTR_ERR(dsi->pllref_clk);
1223                         dev_err(dev, "failed to get pll ref clock: %d\n", ret);
1224                         return ret;
1225                 }
1226         }
1227
1228         if (pdata->has_phy_pclk) {
1229                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1230                 if (IS_ERR(dsi->phy_cfg_clk))
1231                         dev_dbg(dev, "have not phy_cfg_clk\n");
1232         }
1233
1234         ret = clk_prepare_enable(dsi->pllref_clk);
1235         if (ret) {
1236                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1237                 return ret;
1238         }
1239
1240         ret = dw_mipi_dsi_register(drm, dsi);
1241         if (ret) {
1242                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1243                 goto err_pllref;
1244         }
1245
1246         dev_set_drvdata(dev, dsi);
1247
1248         pm_runtime_enable(dev);
1249
1250         return 0;
1251
1252 err_pllref:
1253         clk_disable_unprepare(dsi->pllref_clk);
1254         return ret;
1255 }
1256
1257 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1258         void *data)
1259 {
1260         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1261
1262         pm_runtime_disable(dev);
1263         clk_disable_unprepare(dsi->pllref_clk);
1264 }
1265
1266 static const struct component_ops dw_mipi_dsi_ops = {
1267         .bind   = dw_mipi_dsi_bind,
1268         .unbind = dw_mipi_dsi_unbind,
1269 };
1270
1271 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1272 {
1273         struct device *dev = &pdev->dev;
1274         const struct of_device_id *of_id =
1275                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1276         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1277         struct dw_mipi_dsi *dsi;
1278         int ret;
1279
1280         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1281         if (!dsi)
1282                 return -ENOMEM;
1283
1284         dsi->dev = dev;
1285         dsi->pdata = pdata;
1286         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1287         dsi->dsi_host.dev = &pdev->dev;
1288
1289         ret = mipi_dsi_host_register(&dsi->dsi_host);
1290         if (ret)
1291                 return ret;
1292
1293         platform_set_drvdata(pdev, dsi);
1294         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1295         if (ret)
1296                 mipi_dsi_host_unregister(&dsi->dsi_host);
1297
1298         return ret;
1299 }
1300
1301 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1302 {
1303         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1304
1305         if (dsi)
1306                 mipi_dsi_host_unregister(&dsi->dsi_host);
1307         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1308         return 0;
1309 }
1310
1311 static struct platform_driver dw_mipi_dsi_driver = {
1312         .probe          = dw_mipi_dsi_probe,
1313         .remove         = dw_mipi_dsi_remove,
1314         .driver         = {
1315                 .of_match_table = dw_mipi_dsi_dt_ids,
1316                 .name   = DRIVER_NAME,
1317         },
1318 };
1319 module_platform_driver(dw_mipi_dsi_driver);
1320
1321 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1322 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1323 MODULE_LICENSE("GPL");
1324 MODULE_ALIAS("platform:" DRIVER_NAME);