drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 static const struct si_dte_data dte_data_tahiti_le =
 255 {
 256         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 257         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 258         0x5,
 259         0xAFC8,
 260         0x64,
 261         0x32,
 262         1,
 263         0,
 264         0x10,
 265         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 266         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 267         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 268         85,
 269         true
 270 };
 271
 272 static const struct si_dte_data dte_data_tahiti_pro =
 273 {
 274         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 275         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 276         5,
 277         45000,
 278         100,
 279         0xA,
 280         1,
 281         0,
 282         0x10,
 283         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 284         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 285         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 286         90,
 287         true
 288 };
 289
 290 static const struct si_dte_data dte_data_new_zealand =
 291 {
 292         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 293         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 294         0x5,
 295         0xAFC8,
 296         0x69,
 297         0x32,
 298         1,
 299         0,
 300         0x10,
 301         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 302         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 303         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 304         85,
 305         true
 306 };
 307
 308 static const struct si_dte_data dte_data_aruba_pro =
 309 {
 310         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 311         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 312         5,
 313         45000,
 314         100,
 315         0xA,
 316         1,
 317         0,
 318         0x10,
 319         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 320         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 321         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 322         90,
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_malta =
 327 {
 328         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 329         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 330         5,
 331         45000,
 332         100,
 333         0xA,
 334         1,
 335         0,
 336         0x10,
 337         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 338         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 339         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 340         90,
 341         true
 342 };
 343
 344 struct si_cac_config_reg cac_weights_pitcairn[] =
 345 {
 346         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 347         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 350         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 359         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 364         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 365         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 368         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 381         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 384         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 406         { 0xFFFFFFFF }
 407 };
 408
 409 static const struct si_cac_config_reg lcac_pitcairn[] =
 410 {
 411         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 412         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg cac_override_pitcairn[] =
 501 {
 502     { 0xFFFFFFFF }
 503 };
 504
 505 static const struct si_powertune_data powertune_data_pitcairn =
 506 {
 507         ((1 << 16) | 27027),
 508         5,
 509         0,
 510         6,
 511         100,
 512         {
 513                 51600000UL,
 514                 1800000UL,
 515                 7194395UL,
 516                 309631529UL,
 517                 -1270850L,
 518                 4513710L,
 519                 100
 520         },
 521         117830498UL,
 522         12,
 523         {
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0
 532         },
 533         true
 534 };
 535
 536 static const struct si_dte_data dte_data_pitcairn =
 537 {
 538         { 0, 0, 0, 0, 0 },
 539         { 0, 0, 0, 0, 0 },
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         0,
 551         false
 552 };
 553
 554 static const struct si_dte_data dte_data_curacao_xt =
 555 {
 556         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 557         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 558         5,
 559         45000,
 560         100,
 561         0xA,
 562         1,
 563         0,
 564         0x10,
 565         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 566         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 567         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 568         90,
 569         true
 570 };
 571
 572 static const struct si_dte_data dte_data_curacao_pro =
 573 {
 574         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 575         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 576         5,
 577         45000,
 578         100,
 579         0xA,
 580         1,
 581         0,
 582         0x10,
 583         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 584         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 585         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 586         90,
 587         true
 588 };
 589
 590 static const struct si_dte_data dte_data_neptune_xt =
 591 {
 592         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 593         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 594         5,
 595         45000,
 596         100,
 597         0xA,
 598         1,
 599         0,
 600         0x10,
 601         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 602         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 603         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 604         90,
 605         true
 606 };
 607
 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 609 {
 610         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 611         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 614         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 623         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 628         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 629         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 632         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 642         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 648         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 651         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 670         { 0xFFFFFFFF }
 671 };
 672
 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 674 {
 675         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 676         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 679         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 688         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 693         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 694         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 697         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 707         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 713         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 716         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 735         { 0xFFFFFFFF }
 736 };
 737
 738 static const struct si_cac_config_reg cac_weights_heathrow[] =
 739 {
 740         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 741         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 744         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 753         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 758         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 759         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 762         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 772         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 778         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 781         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 800         { 0xFFFFFFFF }
 801 };
 802
 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 804 {
 805         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 806         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 809         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 818         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 823         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 824         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 827         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 837         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 843         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 846         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 865         { 0xFFFFFFFF }
 866 };
 867
 868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 869 {
 870         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 871         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 874         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 883         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 888         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 889         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 892         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 902         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 908         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 911         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 930         { 0xFFFFFFFF }
 931 };
 932
 933 static const struct si_cac_config_reg lcac_cape_verde[] =
 934 {
 935         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 936         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0xFFFFFFFF }
 990 };
 991
 992 static const struct si_cac_config_reg cac_override_cape_verde[] =
 993 {
 994     { 0xFFFFFFFF }
 995 };
 996
 997 static const struct si_powertune_data powertune_data_cape_verde =
 998 {
 999         ((1 << 16) | 0x6993),
1000         5,
1001         0,
1002         7,
1003         105,
1004         {
1005                 0UL,
1006                 0UL,
1007                 7194395UL,
1008                 309631529UL,
1009                 -1270850L,
1010                 4513710L,
1011                 100
1012         },
1013         117830498UL,
1014         12,
1015         {
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0
1024         },
1025         true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030         { 0, 0, 0, 0, 0 },
1031         { 0, 0, 0, 0, 0 },
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         0,
1043         false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050         5,
1051         55000,
1052         0x69,
1053         0xA,
1054         1,
1055         0,
1056         0x3,
1057         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         90,
1061         true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068         5,
1069         55000,
1070         0x69,
1071         0xA,
1072         1,
1073         0,
1074         0x3,
1075         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         90,
1079         true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086         5,
1087         55000,
1088         0x69,
1089         0xA,
1090         1,
1091         0,
1092         0x3,
1093         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         90,
1097         true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162         { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227         { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292         { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357         { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422         { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521         { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526         ((1 << 16) | 0x6993),
1527         5,
1528         0,
1529         7,
1530         105,
1531         {
1532                 0UL,
1533                 0UL,
1534                 7194395UL,
1535                 309631529UL,
1536                 -1270850L,
1537                 4513710L,
1538                 100
1539         },
1540         117830498UL,
1541         12,
1542         {
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0
1551         },
1552         true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557         ((1 << 16) | 0x6993),
1558         5,
1559         0,
1560         7,
1561         105,
1562         {
1563                 0UL,
1564                 0UL,
1565                 7194395UL,
1566                 309631529UL,
1567                 -1270850L,
1568                 4513710L,
1569                 100
1570         },
1571         117830498UL,
1572         12,
1573         {
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0
1582         },
1583         true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588         { 0, 0, 0, 0, 0 },
1589         { 0, 0, 0, 0, 0 },
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         0,
1601         false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608         5,
1609         55000,
1610         105,
1611         0xA,
1612         1,
1613         0,
1614         0x10,
1615         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618         90,
1619         true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626         5,
1627         55000,
1628         105,
1629         0xA,
1630         1,
1631         0,
1632         0x10,
1633         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636         90,
1637         true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703         { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708         ((1 << 16) | 0x6993),
1709         5,
1710         0,
1711         9,
1712         105,
1713         {
1714                 0UL,
1715                 0UL,
1716                 7194395UL,
1717                 309631529UL,
1718                 -1270850L,
1719                 4513710L,
1720                 100
1721         },
1722         117830498UL,
1723         12,
1724         {
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0
1733         },
1734         true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746                                      const struct atom_voltage_table *table,
1747                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750                                     u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752                                       u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754                                          struct rv7xx_pl *pl,
1755                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757                                     u32 engine_clock,
1758                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765         struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767         return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773         s64 kt, kv, leakage_w, i_leakage, vddc;
1774         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775         s64 tmp;
1776
1777         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778         vddc = div64_s64(drm_int2fixp(v), 1000);
1779         temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785         t_ref = drm_int2fixp(coeff->t_ref);
1786
1787         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794         *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798                                              const struct ni_leakage_coeffients *coeff,
1799                                              u16 v,
1800                                              s32 t,
1801                                              u32 i_leakage,
1802                                              u32 *leakage)
1803 {
1804         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808                                                const u32 fixed_kt, u16 v,
1809                                                u32 ileakage, u32 *leakage)
1810 {
1811         s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814         vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822         *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826                                        const struct ni_leakage_coeffients *coeff,
1827                                        const u32 fixed_kt,
1828                                        u16 v,
1829                                        u32 i_leakage,
1830                                        u32 *leakage)
1831 {
1832         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837                                    struct si_dte_data *dte_data)
1838 {
1839         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841         u32 k = dte_data->k;
1842         u32 t_max = dte_data->max_t;
1843         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844         u32 t_0 = dte_data->t0;
1845         u32 i;
1846
1847         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848                 dte_data->tdep_count = 3;
1849
1850                 for (i = 0; i < k; i++) {
1851                         dte_data->r[i] =
1852                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853                                 (p_limit2  * (u32)100);
1854                 }
1855
1856                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859                         dte_data->tdep_r[i] = dte_data->r[4];
1860                 }
1861         } else {
1862                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863         }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869         struct si_power_info *si_pi = si_get_pi(rdev);
1870         bool update_dte_from_pl2 = false;
1871
1872         if (rdev->family == CHIP_TAHITI) {
1873                 si_pi->cac_weights = cac_weights_tahiti;
1874                 si_pi->lcac_config = lcac_tahiti;
1875                 si_pi->cac_override = cac_override_tahiti;
1876                 si_pi->powertune_data = &powertune_data_tahiti;
1877                 si_pi->dte_data = dte_data_tahiti;
1878
1879                 switch (rdev->pdev->device) {
1880                 case 0x6798:
1881                         si_pi->dte_data.enable_dte_by_default = true;
1882                         break;
1883                 case 0x6799:
1884                         si_pi->dte_data = dte_data_new_zealand;
1885                         break;
1886                 case 0x6790:
1887                 case 0x6791:
1888                 case 0x6792:
1889                 case 0x679E:
1890                         si_pi->dte_data = dte_data_aruba_pro;
1891                         update_dte_from_pl2 = true;
1892                         break;
1893                 case 0x679B:
1894                         si_pi->dte_data = dte_data_malta;
1895                         update_dte_from_pl2 = true;
1896                         break;
1897                 case 0x679A:
1898                         si_pi->dte_data = dte_data_tahiti_pro;
1899                         update_dte_from_pl2 = true;
1900                         break;
1901                 default:
1902                         if (si_pi->dte_data.enable_dte_by_default == true)
1903                                 DRM_ERROR("DTE is not enabled!\n");
1904                         break;
1905                 }
1906         } else if (rdev->family == CHIP_PITCAIRN) {
1907                 switch (rdev->pdev->device) {
1908                 case 0x6810:
1909                 case 0x6818:
1910                         si_pi->cac_weights = cac_weights_pitcairn;
1911                         si_pi->lcac_config = lcac_pitcairn;
1912                         si_pi->cac_override = cac_override_pitcairn;
1913                         si_pi->powertune_data = &powertune_data_pitcairn;
1914                         si_pi->dte_data = dte_data_curacao_xt;
1915                         update_dte_from_pl2 = true;
1916                         break;
1917                 case 0x6819:
1918                 case 0x6811:
1919                         si_pi->cac_weights = cac_weights_pitcairn;
1920                         si_pi->lcac_config = lcac_pitcairn;
1921                         si_pi->cac_override = cac_override_pitcairn;
1922                         si_pi->powertune_data = &powertune_data_pitcairn;
1923                         si_pi->dte_data = dte_data_curacao_pro;
1924                         update_dte_from_pl2 = true;
1925                         break;
1926                 case 0x6800:
1927                 case 0x6806:
1928                         si_pi->cac_weights = cac_weights_pitcairn;
1929                         si_pi->lcac_config = lcac_pitcairn;
1930                         si_pi->cac_override = cac_override_pitcairn;
1931                         si_pi->powertune_data = &powertune_data_pitcairn;
1932                         si_pi->dte_data = dte_data_neptune_xt;
1933                         update_dte_from_pl2 = true;
1934                         break;
1935                 default:
1936                         si_pi->cac_weights = cac_weights_pitcairn;
1937                         si_pi->lcac_config = lcac_pitcairn;
1938                         si_pi->cac_override = cac_override_pitcairn;
1939                         si_pi->powertune_data = &powertune_data_pitcairn;
1940                         si_pi->dte_data = dte_data_pitcairn;
1941                         break;
1942                 }
1943         } else if (rdev->family == CHIP_VERDE) {
1944                 si_pi->lcac_config = lcac_cape_verde;
1945                 si_pi->cac_override = cac_override_cape_verde;
1946                 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948                 switch (rdev->pdev->device) {
1949                 case 0x683B:
1950                 case 0x683F:
1951                 case 0x6829:
1952                 case 0x6835:
1953                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1954                         si_pi->dte_data = dte_data_cape_verde;
1955                         break;
1956                 case 0x682C:
1957                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1958                         si_pi->dte_data = dte_data_sun_xt;
1959                         break;
1960                 case 0x6825:
1961                 case 0x6827:
1962                         si_pi->cac_weights = cac_weights_heathrow;
1963                         si_pi->dte_data = dte_data_cape_verde;
1964                         break;
1965                 case 0x6824:
1966                 case 0x682D:
1967                         si_pi->cac_weights = cac_weights_chelsea_xt;
1968                         si_pi->dte_data = dte_data_cape_verde;
1969                         break;
1970                 case 0x682F:
1971                         si_pi->cac_weights = cac_weights_chelsea_pro;
1972                         si_pi->dte_data = dte_data_cape_verde;
1973                         break;
1974                 case 0x6820:
1975                         si_pi->cac_weights = cac_weights_heathrow;
1976                         si_pi->dte_data = dte_data_venus_xtx;
1977                         break;
1978                 case 0x6821:
1979                         si_pi->cac_weights = cac_weights_heathrow;
1980                         si_pi->dte_data = dte_data_venus_xt;
1981                         break;
1982                 case 0x6823:
1983                 case 0x682B:
1984                 case 0x6822:
1985                 case 0x682A:
1986                         si_pi->cac_weights = cac_weights_chelsea_pro;
1987                         si_pi->dte_data = dte_data_venus_pro;
1988                         break;
1989                 default:
1990                         si_pi->cac_weights = cac_weights_cape_verde;
1991                         si_pi->dte_data = dte_data_cape_verde;
1992                         break;
1993                 }
1994         } else if (rdev->family == CHIP_OLAND) {
1995                 switch (rdev->pdev->device) {
1996                 case 0x6601:
1997                 case 0x6621:
1998                 case 0x6603:
1999                 case 0x6605:
2000                         si_pi->cac_weights = cac_weights_mars_pro;
2001                         si_pi->lcac_config = lcac_mars_pro;
2002                         si_pi->cac_override = cac_override_oland;
2003                         si_pi->powertune_data = &powertune_data_mars_pro;
2004                         si_pi->dte_data = dte_data_mars_pro;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x6600:
2008                 case 0x6606:
2009                 case 0x6620:
2010                 case 0x6604:
2011                         si_pi->cac_weights = cac_weights_mars_xt;
2012                         si_pi->lcac_config = lcac_mars_pro;
2013                         si_pi->cac_override = cac_override_oland;
2014                         si_pi->powertune_data = &powertune_data_mars_pro;
2015                         si_pi->dte_data = dte_data_mars_pro;
2016                         update_dte_from_pl2 = true;
2017                         break;
2018                 case 0x6611:
2019                 case 0x6613:
2020                 case 0x6608:
2021                         si_pi->cac_weights = cac_weights_oland_pro;
2022                         si_pi->lcac_config = lcac_mars_pro;
2023                         si_pi->cac_override = cac_override_oland;
2024                         si_pi->powertune_data = &powertune_data_mars_pro;
2025                         si_pi->dte_data = dte_data_mars_pro;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6610:
2029                         si_pi->cac_weights = cac_weights_oland_xt;
2030                         si_pi->lcac_config = lcac_mars_pro;
2031                         si_pi->cac_override = cac_override_oland;
2032                         si_pi->powertune_data = &powertune_data_mars_pro;
2033                         si_pi->dte_data = dte_data_mars_pro;
2034                         update_dte_from_pl2 = true;
2035                         break;
2036                 default:
2037                         si_pi->cac_weights = cac_weights_oland;
2038                         si_pi->lcac_config = lcac_oland;
2039                         si_pi->cac_override = cac_override_oland;
2040                         si_pi->powertune_data = &powertune_data_oland;
2041                         si_pi->dte_data = dte_data_oland;
2042                         break;
2043                 }
2044         } else if (rdev->family == CHIP_HAINAN) {
2045                 si_pi->cac_weights = cac_weights_hainan;
2046                 si_pi->lcac_config = lcac_oland;
2047                 si_pi->cac_override = cac_override_oland;
2048                 si_pi->powertune_data = &powertune_data_hainan;
2049                 si_pi->dte_data = dte_data_sun_xt;
2050                 update_dte_from_pl2 = true;
2051         } else {
2052                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053                 return;
2054         }
2055
2056         ni_pi->enable_power_containment = false;
2057         ni_pi->enable_cac = false;
2058         ni_pi->enable_sq_ramping = false;
2059         si_pi->enable_dte = false;
2060
2061         if (si_pi->powertune_data->enable_powertune_by_default) {
2062                 ni_pi->enable_power_containment= true;
2063                 ni_pi->enable_cac = true;
2064                 if (si_pi->dte_data.enable_dte_by_default) {
2065                         si_pi->enable_dte = true;
2066                         if (update_dte_from_pl2)
2067                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069                 }
2070                 ni_pi->enable_sq_ramping = true;
2071         }
2072
2073         ni_pi->driver_calculate_cac_leakage = true;
2074         ni_pi->cac_configuration_required = true;
2075
2076         if (ni_pi->cac_configuration_required) {
2077                 ni_pi->support_cac_long_term_average = true;
2078                 si_pi->dyn_powertune_data.l2_lta_window_size =
2079                         si_pi->powertune_data->l2_lta_window_size_default;
2080                 si_pi->dyn_powertune_data.lts_truncate =
2081                         si_pi->powertune_data->lts_truncate_default;
2082         } else {
2083                 ni_pi->support_cac_long_term_average = false;
2084                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085                 si_pi->dyn_powertune_data.lts_truncate = 0;
2086         }
2087
2088         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 }
2090
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 {
2093         return 1;
2094 }
2095
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 {
2098         u32 xclk;
2099         u32 wintime;
2100         u32 cac_window;
2101         u32 cac_window_size;
2102
2103         xclk = radeon_get_xclk(rdev);
2104
2105         if (xclk == 0)
2106                 return 0;
2107
2108         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111         wintime = (cac_window_size * 100) / xclk;
2112
2113         return wintime;
2114 }
2115
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 {
2118         return power_in_watts;
2119 }
2120
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122                                             bool adjust_polarity,
2123                                             u32 tdp_adjustment,
2124                                             u32 *tdp_limit,
2125                                             u32 *near_tdp_limit)
2126 {
2127         u32 adjustment_delta, max_tdp_limit;
2128
2129         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130                 return -EINVAL;
2131
2132         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134         if (adjust_polarity) {
2135                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137         } else {
2138                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142                 else
2143                         *near_tdp_limit = 0;
2144         }
2145
2146         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147                 return -EINVAL;
2148         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149                 return -EINVAL;
2150
2151         return 0;
2152 }
2153
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155                                       struct radeon_ps *radeon_state)
2156 {
2157         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158         struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160         if (ni_pi->enable_power_containment) {
2161                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162                 PP_SIslands_PAPMParameters *papm_parm;
2163                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165                 u32 tdp_limit;
2166                 u32 near_tdp_limit;
2167                 int ret;
2168
2169                 if (scaling_factor == 0)
2170                         return -EINVAL;
2171
2172                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174                 ret = si_calculate_adjusted_tdp_limits(rdev,
2175                                                        false, /* ??? */
2176                                                        rdev->pm.dpm.tdp_adjustment,
2177                                                        &tdp_limit,
2178                                                        &near_tdp_limit);
2179                 if (ret)
2180                         return ret;
2181
2182                 smc_table->dpm2Params.TDPLimit =
2183                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184                 smc_table->dpm2Params.NearTDPLimit =
2185                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186                 smc_table->dpm2Params.SafePowerLimit =
2187                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189                 ret = si_copy_bytes_to_smc(rdev,
2190                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193                                            sizeof(u32) * 3,
2194                                            si_pi->sram_end);
2195                 if (ret)
2196                         return ret;
2197
2198                 if (si_pi->enable_ppm) {
2199                         papm_parm = &si_pi->papm_parm;
2200                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205                         papm_parm->PlatformPowerLimit = 0xffffffff;
2206                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209                                                    (u8 *)papm_parm,
2210                                                    sizeof(PP_SIslands_PAPMParameters),
2211                                                    si_pi->sram_end);
2212                         if (ret)
2213                                 return ret;
2214                 }
2215         }
2216         return 0;
2217 }
2218
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220                                         struct radeon_ps *radeon_state)
2221 {
2222         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223         struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225         if (ni_pi->enable_power_containment) {
2226                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228                 int ret;
2229
2230                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232                 smc_table->dpm2Params.NearTDPLimit =
2233                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234                 smc_table->dpm2Params.SafePowerLimit =
2235                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237                 ret = si_copy_bytes_to_smc(rdev,
2238                                            (si_pi->state_table_start +
2239                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242                                            sizeof(u32) * 2,
2243                                            si_pi->sram_end);
2244                 if (ret)
2245                         return ret;
2246         }
2247
2248         return 0;
2249 }
2250
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252                                                const u16 prev_std_vddc,
2253                                                const u16 curr_std_vddc)
2254 {
2255         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256         u64 prev_vddc = (u64)prev_std_vddc;
2257         u64 curr_vddc = (u64)curr_std_vddc;
2258         u64 pwr_efficiency_ratio, n, d;
2259
2260         if ((prev_vddc == 0) || (curr_vddc == 0))
2261                 return 0;
2262
2263         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264         d = prev_vddc * prev_vddc;
2265         pwr_efficiency_ratio = div64_u64(n, d);
2266
2267         if (pwr_efficiency_ratio > (u64)0xFFFF)
2268                 return 0;
2269
2270         return (u16)pwr_efficiency_ratio;
2271 }
2272
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274                                             struct radeon_ps *radeon_state)
2275 {
2276         struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279             radeon_state->vclk && radeon_state->dclk)
2280                 return true;
2281
2282         return false;
2283 }
2284
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286                                                 struct radeon_ps *radeon_state,
2287                                                 SISLANDS_SMC_SWSTATE *smc_state)
2288 {
2289         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291         struct ni_ps *state = ni_get_ps(radeon_state);
2292         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293         u32 prev_sclk;
2294         u32 max_sclk;
2295         u32 min_sclk;
2296         u16 prev_std_vddc;
2297         u16 curr_std_vddc;
2298         int i;
2299         u16 pwr_efficiency_ratio;
2300         u8 max_ps_percent;
2301         bool disable_uvd_power_tune;
2302         int ret;
2303
2304         if (ni_pi->enable_power_containment == false)
2305                 return 0;
2306
2307         if (state->performance_level_count == 0)
2308                 return -EINVAL;
2309
2310         if (smc_state->levelCount != state->performance_level_count)
2311                 return -EINVAL;
2312
2313         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315         smc_state->levels[0].dpm2.MaxPS = 0;
2316         smc_state->levels[0].dpm2.NearTDPDec = 0;
2317         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321         for (i = 1; i < state->performance_level_count; i++) {
2322                 prev_sclk = state->performance_levels[i-1].sclk;
2323                 max_sclk  = state->performance_levels[i].sclk;
2324                 if (i == 1)
2325                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326                 else
2327                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329                 if (prev_sclk > max_sclk)
2330                         return -EINVAL;
2331
2332                 if ((max_ps_percent == 0) ||
2333                     (prev_sclk == max_sclk) ||
2334                     disable_uvd_power_tune) {
2335                         min_sclk = max_sclk;
2336                 } else if (i == 1) {
2337                         min_sclk = prev_sclk;
2338                 } else {
2339                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340                 }
2341
2342                 if (min_sclk < state->performance_levels[0].sclk)
2343                         min_sclk = state->performance_levels[0].sclk;
2344
2345                 if (min_sclk == 0)
2346                         return -EINVAL;
2347
2348                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349                                                 state->performance_levels[i-1].vddc, &vddc);
2350                 if (ret)
2351                         return ret;
2352
2353                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354                 if (ret)
2355                         return ret;
2356
2357                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358                                                 state->performance_levels[i].vddc, &vddc);
2359                 if (ret)
2360                         return ret;
2361
2362                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363                 if (ret)
2364                         return ret;
2365
2366                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367                                                                            prev_std_vddc, curr_std_vddc);
2368
2369                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380                                          struct radeon_ps *radeon_state,
2381                                          SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384         struct ni_ps *state = ni_get_ps(radeon_state);
2385         u32 sq_power_throttle, sq_power_throttle2;
2386         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387         int i;
2388
2389         if (state->performance_level_count == 0)
2390                 return -EINVAL;
2391
2392         if (smc_state->levelCount != state->performance_level_count)
2393                 return -EINVAL;
2394
2395         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396                 return -EINVAL;
2397
2398         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399                 enable_sq_ramping = false;
2400
2401         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402                 enable_sq_ramping = false;
2403
2404         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405                 enable_sq_ramping = false;
2406
2407         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408                 enable_sq_ramping = false;
2409
2410         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411                 enable_sq_ramping = false;
2412
2413         for (i = 0; i < state->performance_level_count; i++) {
2414                 sq_power_throttle = 0;
2415                 sq_power_throttle2 = 0;
2416
2417                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418                     enable_sq_ramping) {
2419                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424                 } else {
2425                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427                 }
2428
2429                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437                                        struct radeon_ps *radeon_new_state,
2438                                        bool enable)
2439 {
2440         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441         PPSMC_Result smc_result;
2442         int ret = 0;
2443
2444         if (ni_pi->enable_power_containment) {
2445                 if (enable) {
2446                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448                                 if (smc_result != PPSMC_Result_OK) {
2449                                         ret = -EINVAL;
2450                                         ni_pi->pc_enabled = false;
2451                                 } else {
2452                                         ni_pi->pc_enabled = true;
2453                                 }
2454                         }
2455                 } else {
2456                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457                         if (smc_result != PPSMC_Result_OK)
2458                                 ret = -EINVAL;
2459                         ni_pi->pc_enabled = false;
2460                 }
2461         }
2462
2463         return ret;
2464 }
2465
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 {
2468         struct si_power_info *si_pi = si_get_pi(rdev);
2469         int ret = 0;
2470         struct si_dte_data *dte_data = &si_pi->dte_data;
2471         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472         u32 table_size;
2473         u8 tdep_count;
2474         u32 i;
2475
2476         if (dte_data == NULL)
2477                 si_pi->enable_dte = false;
2478
2479         if (si_pi->enable_dte == false)
2480                 return 0;
2481
2482         if (dte_data->k <= 0)
2483                 return -EINVAL;
2484
2485         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486         if (dte_tables == NULL) {
2487                 si_pi->enable_dte = false;
2488                 return -ENOMEM;
2489         }
2490
2491         table_size = dte_data->k;
2492
2493         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496         tdep_count = dte_data->tdep_count;
2497         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500         dte_tables->K = cpu_to_be32(table_size);
2501         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503         dte_tables->WindowSize = dte_data->window_size;
2504         dte_tables->temp_select = dte_data->temp_select;
2505         dte_tables->DTE_mode = dte_data->dte_mode;
2506         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508         if (tdep_count > 0)
2509                 table_size--;
2510
2511         for (i = 0; i < table_size; i++) {
2512                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2514         }
2515
2516         dte_tables->Tdep_count = tdep_count;
2517
2518         for (i = 0; i < (u32)tdep_count; i++) {
2519                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522         }
2523
2524         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526         kfree(dte_tables);
2527
2528         return ret;
2529 }
2530
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532                                           u16 *max, u16 *min)
2533 {
2534         struct si_power_info *si_pi = si_get_pi(rdev);
2535         struct radeon_cac_leakage_table *table =
2536                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537         u32 i;
2538         u32 v0_loadline;
2539
2540
2541         if (table == NULL)
2542                 return -EINVAL;
2543
2544         *max = 0;
2545         *min = 0xFFFF;
2546
2547         for (i = 0; i < table->count; i++) {
2548                 if (table->entries[i].vddc > *max)
2549                         *max = table->entries[i].vddc;
2550                 if (table->entries[i].vddc < *min)
2551                         *min = table->entries[i].vddc;
2552         }
2553
2554         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555                 return -EINVAL;
2556
2557         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559         if (v0_loadline > 0xFFFFUL)
2560                 return -EINVAL;
2561
2562         *min = (u16)v0_loadline;
2563
2564         if ((*min > *max) || (*max == 0) || (*min == 0))
2565                 return -EINVAL;
2566
2567         return 0;
2568 }
2569
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 {
2572         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 }
2575
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577                                      PP_SIslands_CacConfig *cac_tables,
2578                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579                                      u16 t0, u16 t_step)
2580 {
2581         struct si_power_info *si_pi = si_get_pi(rdev);
2582         u32 leakage;
2583         unsigned int i, j;
2584         s32 t;
2585         u32 smc_leakage;
2586         u32 scaling_factor;
2587         u16 voltage;
2588
2589         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592                 t = (1000 * (i * t_step + t0));
2593
2594                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595                         voltage = vddc_max - (vddc_step * j);
2596
2597                         si_calculate_leakage_for_v_and_t(rdev,
2598                                                          &si_pi->powertune_data->leakage_coefficients,
2599                                                          voltage,
2600                                                          t,
2601                                                          si_pi->dyn_powertune_data.cac_leakage,
2602                                                          &leakage);
2603
2604                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606                         if (smc_leakage > 0xFFFF)
2607                                 smc_leakage = 0xFFFF;
2608
2609                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610                                 cpu_to_be16((u16)smc_leakage);
2611                 }
2612         }
2613         return 0;
2614 }
2615
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617                                             PP_SIslands_CacConfig *cac_tables,
2618                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 {
2620         struct si_power_info *si_pi = si_get_pi(rdev);
2621         u32 leakage;
2622         unsigned int i, j;
2623         u32 smc_leakage;
2624         u32 scaling_factor;
2625         u16 voltage;
2626
2627         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630                 voltage = vddc_max - (vddc_step * j);
2631
2632                 si_calculate_leakage_for_v(rdev,
2633                                            &si_pi->powertune_data->leakage_coefficients,
2634                                            si_pi->powertune_data->fixed_kt,
2635                                            voltage,
2636                                            si_pi->dyn_powertune_data.cac_leakage,
2637                                            &leakage);
2638
2639                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641                 if (smc_leakage > 0xFFFF)
2642                         smc_leakage = 0xFFFF;
2643
2644                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646                                 cpu_to_be16((u16)smc_leakage);
2647         }
2648         return 0;
2649 }
2650
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 {
2653         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654         struct si_power_info *si_pi = si_get_pi(rdev);
2655         PP_SIslands_CacConfig *cac_tables = NULL;
2656         u16 vddc_max, vddc_min, vddc_step;
2657         u16 t0, t_step;
2658         u32 load_line_slope, reg;
2659         int ret = 0;
2660         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662         if (ni_pi->enable_cac == false)
2663                 return 0;
2664
2665         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666         if (!cac_tables)
2667                 return -ENOMEM;
2668
2669         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671         WREG32(CG_CAC_CTRL, reg);
2672
2673         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674         si_pi->dyn_powertune_data.dc_pwr_value =
2675                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682         if (ret)
2683                 goto done_free;
2684
2685         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687         t_step = 4;
2688         t0 = 60;
2689
2690         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692                                                 vddc_max, vddc_min, vddc_step,
2693                                                 t0, t_step);
2694         else
2695                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696                                                        vddc_max, vddc_min, vddc_step);
2697         if (ret)
2698                 goto done_free;
2699
2700         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709         cac_tables->calculation_repeats = cpu_to_be32(2);
2710         cac_tables->dc_cac = cpu_to_be32(0);
2711         cac_tables->log2_PG_LKG_SCALE = 12;
2712         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719         if (ret)
2720                 goto done_free;
2721
2722         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724 done_free:
2725         if (ret) {
2726                 ni_pi->enable_cac = false;
2727                 ni_pi->enable_power_containment = false;
2728         }
2729
2730         kfree(cac_tables);
2731
2732         return 0;
2733 }
2734
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736                                            const struct si_cac_config_reg *cac_config_regs)
2737 {
2738         const struct si_cac_config_reg *config_regs = cac_config_regs;
2739         u32 data = 0, offset;
2740
2741         if (!config_regs)
2742                 return -EINVAL;
2743
2744         while (config_regs->offset != 0xFFFFFFFF) {
2745                 switch (config_regs->type) {
2746                 case SISLANDS_CACCONFIG_CGIND:
2747                         offset = SMC_CG_IND_START + config_regs->offset;
2748                         if (offset < SMC_CG_IND_END)
2749                                 data = RREG32_SMC(offset);
2750                         break;
2751                 default:
2752                         data = RREG32(config_regs->offset << 2);
2753                         break;
2754                 }
2755
2756                 data &= ~config_regs->mask;
2757                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759                 switch (config_regs->type) {
2760                 case SISLANDS_CACCONFIG_CGIND:
2761                         offset = SMC_CG_IND_START + config_regs->offset;
2762                         if (offset < SMC_CG_IND_END)
2763                                 WREG32_SMC(offset, data);
2764                         break;
2765                 default:
2766                         WREG32(config_regs->offset << 2, data);
2767                         break;
2768                 }
2769                 config_regs++;
2770         }
2771         return 0;
2772 }
2773
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 {
2776         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777         struct si_power_info *si_pi = si_get_pi(rdev);
2778         int ret;
2779
2780         if ((ni_pi->enable_cac == false) ||
2781             (ni_pi->cac_configuration_required == false))
2782                 return 0;
2783
2784         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785         if (ret)
2786                 return ret;
2787         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788         if (ret)
2789                 return ret;
2790         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791         if (ret)
2792                 return ret;
2793
2794         return 0;
2795 }
2796
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798                              struct radeon_ps *radeon_new_state,
2799                              bool enable)
2800 {
2801         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802         struct si_power_info *si_pi = si_get_pi(rdev);
2803         PPSMC_Result smc_result;
2804         int ret = 0;
2805
2806         if (ni_pi->enable_cac) {
2807                 if (enable) {
2808                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809                                 if (ni_pi->support_cac_long_term_average) {
2810                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811                                         if (smc_result != PPSMC_Result_OK)
2812                                                 ni_pi->support_cac_long_term_average = false;
2813                                 }
2814
2815                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816                                 if (smc_result != PPSMC_Result_OK) {
2817                                         ret = -EINVAL;
2818                                         ni_pi->cac_enabled = false;
2819                                 } else {
2820                                         ni_pi->cac_enabled = true;
2821                                 }
2822
2823                                 if (si_pi->enable_dte) {
2824                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825                                         if (smc_result != PPSMC_Result_OK)
2826                                                 ret = -EINVAL;
2827                                 }
2828                         }
2829                 } else if (ni_pi->cac_enabled) {
2830                         if (si_pi->enable_dte)
2831                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835                         ni_pi->cac_enabled = false;
2836
2837                         if (ni_pi->support_cac_long_term_average)
2838                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839                 }
2840         }
2841         return ret;
2842 }
2843
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 {
2846         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847         struct si_power_info *si_pi = si_get_pi(rdev);
2848         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849         SISLANDS_SMC_SCLK_VALUE sclk_params;
2850         u32 fb_div, p_div;
2851         u32 clk_s, clk_v;
2852         u32 sclk = 0;
2853         int ret = 0;
2854         u32 tmp;
2855         int i;
2856
2857         if (si_pi->spll_table_start == 0)
2858                 return -EINVAL;
2859
2860         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861         if (spll_table == NULL)
2862                 return -ENOMEM;
2863
2864         for (i = 0; i < 256; i++) {
2865                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866                 if (ret)
2867                         break;
2868
2869                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874                 fb_div &= ~0x00001FFF;
2875                 fb_div >>= 1;
2876                 clk_v >>= 6;
2877
2878                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879                         ret = -EINVAL;
2880                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881                         ret = -EINVAL;
2882                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883                         ret = -EINVAL;
2884                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885                         ret = -EINVAL;
2886
2887                 if (ret)
2888                         break;
2889
2890                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892                 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896                 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898                 sclk += 512;
2899         }
2900
2901
2902         if (!ret)
2903                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905                                            si_pi->sram_end);
2906
2907         if (ret)
2908                 ni_pi->enable_power_containment = false;
2909
2910         kfree(spll_table);
2911
2912         return ret;
2913 }
2914
2915 struct si_dpm_quirk {
2916         u32 chip_vendor;
2917         u32 chip_device;
2918         u32 subsys_vendor;
2919         u32 subsys_device;
2920         u32 max_sclk;
2921         u32 max_mclk;
2922 };
2923
2924 /* cards with dpm stability problems */
2925 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2930         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2931         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2932         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2933         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2934         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2935         { 0, 0, 0, 0 },
2936 };
2937
2938 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2939                                                    u16 vce_voltage)
2940 {
2941         u16 highest_leakage = 0;
2942         struct si_power_info *si_pi = si_get_pi(rdev);
2943         int i;
2944
2945         for (i = 0; i < si_pi->leakage_voltage.count; i++){
2946                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2947                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2948         }
2949
2950         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2951                 return highest_leakage;
2952
2953         return vce_voltage;
2954 }
2955
2956 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2957                                     u32 evclk, u32 ecclk, u16 *voltage)
2958 {
2959         u32 i;
2960         int ret = -EINVAL;
2961         struct radeon_vce_clock_voltage_dependency_table *table =
2962                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2963
2964         if (((evclk == 0) && (ecclk == 0)) ||
2965             (table && (table->count == 0))) {
2966                 *voltage = 0;
2967                 return 0;
2968         }
2969
2970         for (i = 0; i < table->count; i++) {
2971                 if ((evclk <= table->entries[i].evclk) &&
2972                     (ecclk <= table->entries[i].ecclk)) {
2973                         *voltage = table->entries[i].v;
2974                         ret = 0;
2975                         break;
2976                 }
2977         }
2978
2979         /* if no match return the highest voltage */
2980         if (ret)
2981                 *voltage = table->entries[table->count - 1].v;
2982
2983         *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2984
2985         return ret;
2986 }
2987
2988 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2989                                         struct radeon_ps *rps)
2990 {
2991         struct ni_ps *ps = ni_get_ps(rps);
2992         struct radeon_clock_and_voltage_limits *max_limits;
2993         bool disable_mclk_switching = false;
2994         bool disable_sclk_switching = false;
2995         u32 mclk, sclk;
2996         u16 vddc, vddci, min_vce_voltage = 0;
2997         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2998         u32 max_sclk = 0, max_mclk = 0;
2999         int i;
3000         struct si_dpm_quirk *p = si_dpm_quirk_list;
3001
3002         /* limit all SI kickers */
3003         if (rdev->family == CHIP_PITCAIRN) {
3004                 if ((rdev->pdev->revision == 0x81) ||
3005                     (rdev->pdev->device == 0x6810) ||
3006                     (rdev->pdev->device == 0x6811) ||
3007                     (rdev->pdev->device == 0x6816) ||
3008                     (rdev->pdev->device == 0x6817) ||
3009                     (rdev->pdev->device == 0x6806))
3010                         max_mclk = 120000;
3011         } else if (rdev->family == CHIP_VERDE) {
3012                 if ((rdev->pdev->revision == 0x81) ||
3013                     (rdev->pdev->revision == 0x83) ||
3014                     (rdev->pdev->revision == 0x87) ||
3015                     (rdev->pdev->device == 0x6820) ||
3016                     (rdev->pdev->device == 0x6821) ||
3017                     (rdev->pdev->device == 0x6822) ||
3018                     (rdev->pdev->device == 0x6823) ||
3019                     (rdev->pdev->device == 0x682A) ||
3020                     (rdev->pdev->device == 0x682B)) {
3021                         max_sclk = 75000;
3022                         max_mclk = 80000;
3023                 }
3024         } else if (rdev->family == CHIP_OLAND) {
3025                 if ((rdev->pdev->revision == 0xC7) ||
3026                     (rdev->pdev->revision == 0x80) ||
3027                     (rdev->pdev->revision == 0x81) ||
3028                     (rdev->pdev->revision == 0x83) ||
3029                     (rdev->pdev->device == 0x6604) ||
3030                     (rdev->pdev->device == 0x6605)) {
3031                         max_sclk = 75000;
3032                         max_mclk = 80000;
3033                 }
3034         } else if (rdev->family == CHIP_HAINAN) {
3035                 if ((rdev->pdev->revision == 0x81) ||
3036                     (rdev->pdev->revision == 0x83) ||
3037                     (rdev->pdev->revision == 0xC3) ||
3038                     (rdev->pdev->device == 0x6664) ||
3039                     (rdev->pdev->device == 0x6665) ||
3040                     (rdev->pdev->device == 0x6667)) {
3041                         max_sclk = 75000;
3042                         max_mclk = 80000;
3043                 }
3044         }
3045         /* Apply dpm quirks */
3046         while (p && p->chip_device != 0) {
3047                 if (rdev->pdev->vendor == p->chip_vendor &&
3048                     rdev->pdev->device == p->chip_device &&
3049                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3050                     rdev->pdev->subsystem_device == p->subsys_device) {
3051                         max_sclk = p->max_sclk;
3052                         max_mclk = p->max_mclk;
3053                         break;
3054                 }
3055                 ++p;
3056         }
3057
3058         if (rps->vce_active) {
3059                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3060                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3061                 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3062                                          &min_vce_voltage);
3063         } else {
3064                 rps->evclk = 0;
3065                 rps->ecclk = 0;
3066         }
3067
3068         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3069             ni_dpm_vblank_too_short(rdev))
3070                 disable_mclk_switching = true;
3071
3072         if (rps->vclk || rps->dclk) {
3073                 disable_mclk_switching = true;
3074                 disable_sclk_switching = true;
3075         }
3076
3077         if (rdev->pm.dpm.ac_power)
3078                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3079         else
3080                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3081
3082         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3083                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3084                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3085         }
3086         if (rdev->pm.dpm.ac_power == false) {
3087                 for (i = 0; i < ps->performance_level_count; i++) {
3088                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3089                                 ps->performance_levels[i].mclk = max_limits->mclk;
3090                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3091                                 ps->performance_levels[i].sclk = max_limits->sclk;
3092                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3093                                 ps->performance_levels[i].vddc = max_limits->vddc;
3094                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3095                                 ps->performance_levels[i].vddci = max_limits->vddci;
3096                 }
3097         }
3098
3099         /* limit clocks to max supported clocks based on voltage dependency tables */
3100         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3101                                                         &max_sclk_vddc);
3102         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3103                                                         &max_mclk_vddci);
3104         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3105                                                         &max_mclk_vddc);
3106
3107         for (i = 0; i < ps->performance_level_count; i++) {
3108                 if (max_sclk_vddc) {
3109                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3110                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3111                 }
3112                 if (max_mclk_vddci) {
3113                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3114                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3115                 }
3116                 if (max_mclk_vddc) {
3117                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3118                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3119                 }
3120                 if (max_mclk) {
3121                         if (ps->performance_levels[i].mclk > max_mclk)
3122                                 ps->performance_levels[i].mclk = max_mclk;
3123                 }
3124                 if (max_sclk) {
3125                         if (ps->performance_levels[i].sclk > max_sclk)
3126                                 ps->performance_levels[i].sclk = max_sclk;
3127                 }
3128         }
3129
3130         /* XXX validate the min clocks required for display */
3131
3132         if (disable_mclk_switching) {
3133                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3134                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3135         } else {
3136                 mclk = ps->performance_levels[0].mclk;
3137                 vddci = ps->performance_levels[0].vddci;
3138         }
3139
3140         if (disable_sclk_switching) {
3141                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3142                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3143         } else {
3144                 sclk = ps->performance_levels[0].sclk;
3145                 vddc = ps->performance_levels[0].vddc;
3146         }
3147
3148         if (rps->vce_active) {
3149                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3150                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3151                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3152                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3153         }
3154
3155         /* adjusted low state */
3156         ps->performance_levels[0].sclk = sclk;
3157         ps->performance_levels[0].mclk = mclk;
3158         ps->performance_levels[0].vddc = vddc;
3159         ps->performance_levels[0].vddci = vddci;
3160
3161         if (disable_sclk_switching) {
3162                 sclk = ps->performance_levels[0].sclk;
3163                 for (i = 1; i < ps->performance_level_count; i++) {
3164                         if (sclk < ps->performance_levels[i].sclk)
3165                                 sclk = ps->performance_levels[i].sclk;
3166                 }
3167                 for (i = 0; i < ps->performance_level_count; i++) {
3168                         ps->performance_levels[i].sclk = sclk;
3169                         ps->performance_levels[i].vddc = vddc;
3170                 }
3171         } else {
3172                 for (i = 1; i < ps->performance_level_count; i++) {
3173                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3174                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3175                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3176                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3177                 }
3178         }
3179
3180         if (disable_mclk_switching) {
3181                 mclk = ps->performance_levels[0].mclk;
3182                 for (i = 1; i < ps->performance_level_count; i++) {
3183                         if (mclk < ps->performance_levels[i].mclk)
3184                                 mclk = ps->performance_levels[i].mclk;
3185                 }
3186                 for (i = 0; i < ps->performance_level_count; i++) {
3187                         ps->performance_levels[i].mclk = mclk;
3188                         ps->performance_levels[i].vddci = vddci;
3189                 }
3190         } else {
3191                 for (i = 1; i < ps->performance_level_count; i++) {
3192                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3193                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3194                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3195                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3196                 }
3197         }
3198
3199         for (i = 0; i < ps->performance_level_count; i++)
3200                 btc_adjust_clock_combinations(rdev, max_limits,
3201                                               &ps->performance_levels[i]);
3202
3203         for (i = 0; i < ps->performance_level_count; i++) {
3204                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3205                         ps->performance_levels[i].vddc = min_vce_voltage;
3206                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3207                                                    ps->performance_levels[i].sclk,
3208                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3209                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3210                                                    ps->performance_levels[i].mclk,
3211                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3212                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3213                                                    ps->performance_levels[i].mclk,
3214                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3215                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3216                                                    rdev->clock.current_dispclk,
3217                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3218         }
3219
3220         for (i = 0; i < ps->performance_level_count; i++) {
3221                 btc_apply_voltage_delta_rules(rdev,
3222                                               max_limits->vddc, max_limits->vddci,
3223                                               &ps->performance_levels[i].vddc,
3224                                               &ps->performance_levels[i].vddci);
3225         }
3226
3227         ps->dc_compatible = true;
3228         for (i = 0; i < ps->performance_level_count; i++) {
3229                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3230                         ps->dc_compatible = false;
3231         }
3232 }
3233
3234 #if 0
3235 static int si_read_smc_soft_register(struct radeon_device *rdev,
3236                                      u16 reg_offset, u32 *value)
3237 {
3238         struct si_power_info *si_pi = si_get_pi(rdev);
3239
3240         return si_read_smc_sram_dword(rdev,
3241                                       si_pi->soft_regs_start + reg_offset, value,
3242                                       si_pi->sram_end);
3243 }
3244 #endif
3245
3246 static int si_write_smc_soft_register(struct radeon_device *rdev,
3247                                       u16 reg_offset, u32 value)
3248 {
3249         struct si_power_info *si_pi = si_get_pi(rdev);
3250
3251         return si_write_smc_sram_dword(rdev,
3252                                        si_pi->soft_regs_start + reg_offset,
3253                                        value, si_pi->sram_end);
3254 }
3255
3256 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3257 {
3258         bool ret = false;
3259         u32 tmp, width, row, column, bank, density;
3260         bool is_memory_gddr5, is_special;
3261
3262         tmp = RREG32(MC_SEQ_MISC0);
3263         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3264         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3265                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3266
3267         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3268         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3269
3270         tmp = RREG32(MC_ARB_RAMCFG);
3271         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3272         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3273         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3274
3275         density = (1 << (row + column - 20 + bank)) * width;
3276
3277         if ((rdev->pdev->device == 0x6819) &&
3278             is_memory_gddr5 && is_special && (density == 0x400))
3279                 ret = true;
3280
3281         return ret;
3282 }
3283
3284 static void si_get_leakage_vddc(struct radeon_device *rdev)
3285 {
3286         struct si_power_info *si_pi = si_get_pi(rdev);
3287         u16 vddc, count = 0;
3288         int i, ret;
3289
3290         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3291                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3292
3293                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3294                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3295                         si_pi->leakage_voltage.entries[count].leakage_index =
3296                                 SISLANDS_LEAKAGE_INDEX0 + i;
3297                         count++;
3298                 }
3299         }
3300         si_pi->leakage_voltage.count = count;
3301 }
3302
3303 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3304                                                      u32 index, u16 *leakage_voltage)
3305 {
3306         struct si_power_info *si_pi = si_get_pi(rdev);
3307         int i;
3308
3309         if (leakage_voltage == NULL)
3310                 return -EINVAL;
3311
3312         if ((index & 0xff00) != 0xff00)
3313                 return -EINVAL;
3314
3315         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3316                 return -EINVAL;
3317
3318         if (index < SISLANDS_LEAKAGE_INDEX0)
3319                 return -EINVAL;
3320
3321         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3322                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3323                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3324                         return 0;
3325                 }
3326         }
3327         return -EAGAIN;
3328 }
3329
3330 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3331 {
3332         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3333         bool want_thermal_protection;
3334         enum radeon_dpm_event_src dpm_event_src;
3335
3336         switch (sources) {
3337         case 0:
3338         default:
3339                 want_thermal_protection = false;
3340                 break;
3341         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3342                 want_thermal_protection = true;
3343                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3344                 break;
3345         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3346                 want_thermal_protection = true;
3347                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3348                 break;
3349         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3350               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3351                 want_thermal_protection = true;
3352                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3353                 break;
3354         }
3355
3356         if (want_thermal_protection) {
3357                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3358                 if (pi->thermal_protection)
3359                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3360         } else {
3361                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3362         }
3363 }
3364
3365 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3366                                            enum radeon_dpm_auto_throttle_src source,
3367                                            bool enable)
3368 {
3369         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3370
3371         if (enable) {
3372                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3373                         pi->active_auto_throttle_sources |= 1 << source;
3374                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3375                 }
3376         } else {
3377                 if (pi->active_auto_throttle_sources & (1 << source)) {
3378                         pi->active_auto_throttle_sources &= ~(1 << source);
3379                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3380                 }
3381         }
3382 }
3383
3384 static void si_start_dpm(struct radeon_device *rdev)
3385 {
3386         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3387 }
3388
3389 static void si_stop_dpm(struct radeon_device *rdev)
3390 {
3391         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3392 }
3393
3394 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3395 {
3396         if (enable)
3397                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3398         else
3399                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3400
3401 }
3402
3403 #if 0
3404 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3405                                                u32 thermal_level)
3406 {
3407         PPSMC_Result ret;
3408
3409         if (thermal_level == 0) {
3410                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3411                 if (ret == PPSMC_Result_OK)
3412                         return 0;
3413                 else
3414                         return -EINVAL;
3415         }
3416         return 0;
3417 }
3418
3419 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3420 {
3421         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3422 }
3423 #endif
3424
3425 #if 0
3426 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3427 {
3428         if (ac_power)
3429                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3430                         0 : -EINVAL;
3431
3432         return 0;
3433 }
3434 #endif
3435
3436 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3437                                                       PPSMC_Msg msg, u32 parameter)
3438 {
3439         WREG32(SMC_SCRATCH0, parameter);
3440         return si_send_msg_to_smc(rdev, msg);
3441 }
3442
3443 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3444 {
3445         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3446                 return -EINVAL;
3447
3448         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3449                 0 : -EINVAL;
3450 }
3451
3452 int si_dpm_force_performance_level(struct radeon_device *rdev,
3453                                    enum radeon_dpm_forced_level level)
3454 {
3455         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3456         struct ni_ps *ps = ni_get_ps(rps);
3457         u32 levels = ps->performance_level_count;
3458
3459         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3460                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3461                         return -EINVAL;
3462
3463                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3464                         return -EINVAL;
3465         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3466                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3467                         return -EINVAL;
3468
3469                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3470                         return -EINVAL;
3471         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3472                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3473                         return -EINVAL;
3474
3475                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3476                         return -EINVAL;
3477         }
3478
3479         rdev->pm.dpm.forced_level = level;
3480
3481         return 0;
3482 }
3483
3484 #if 0
3485 static int si_set_boot_state(struct radeon_device *rdev)
3486 {
3487         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3488                 0 : -EINVAL;
3489 }
3490 #endif
3491
3492 static int si_set_sw_state(struct radeon_device *rdev)
3493 {
3494         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3495                 0 : -EINVAL;
3496 }
3497
3498 static int si_halt_smc(struct radeon_device *rdev)
3499 {
3500         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3501                 return -EINVAL;
3502
3503         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3504                 0 : -EINVAL;
3505 }
3506
3507 static int si_resume_smc(struct radeon_device *rdev)
3508 {
3509         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3510                 return -EINVAL;
3511
3512         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3513                 0 : -EINVAL;
3514 }
3515
3516 static void si_dpm_start_smc(struct radeon_device *rdev)
3517 {
3518         si_program_jump_on_start(rdev);
3519         si_start_smc(rdev);
3520         si_start_smc_clock(rdev);
3521 }
3522
3523 static void si_dpm_stop_smc(struct radeon_device *rdev)
3524 {
3525         si_reset_smc(rdev);
3526         si_stop_smc_clock(rdev);
3527 }
3528
3529 static int si_process_firmware_header(struct radeon_device *rdev)
3530 {
3531         struct si_power_info *si_pi = si_get_pi(rdev);
3532         u32 tmp;
3533         int ret;
3534
3535         ret = si_read_smc_sram_dword(rdev,
3536                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3537                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3538                                      &tmp, si_pi->sram_end);
3539         if (ret)
3540                 return ret;
3541
3542         si_pi->state_table_start = tmp;
3543
3544         ret = si_read_smc_sram_dword(rdev,
3545                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3546                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3547                                      &tmp, si_pi->sram_end);
3548         if (ret)
3549                 return ret;
3550
3551         si_pi->soft_regs_start = tmp;
3552
3553         ret = si_read_smc_sram_dword(rdev,
3554                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3555                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3556                                      &tmp, si_pi->sram_end);
3557         if (ret)
3558                 return ret;
3559
3560         si_pi->mc_reg_table_start = tmp;
3561
3562         ret = si_read_smc_sram_dword(rdev,
3563                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3564                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3565                                      &tmp, si_pi->sram_end);
3566         if (ret)
3567                 return ret;
3568
3569         si_pi->fan_table_start = tmp;
3570
3571         ret = si_read_smc_sram_dword(rdev,
3572                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3573                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3574                                      &tmp, si_pi->sram_end);
3575         if (ret)
3576                 return ret;
3577
3578         si_pi->arb_table_start = tmp;
3579
3580         ret = si_read_smc_sram_dword(rdev,
3581                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3582                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3583                                      &tmp, si_pi->sram_end);
3584         if (ret)
3585                 return ret;
3586
3587         si_pi->cac_table_start = tmp;
3588
3589         ret = si_read_smc_sram_dword(rdev,
3590                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3591                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3592                                      &tmp, si_pi->sram_end);
3593         if (ret)
3594                 return ret;
3595
3596         si_pi->dte_table_start = tmp;
3597
3598         ret = si_read_smc_sram_dword(rdev,
3599                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3600                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3601                                      &tmp, si_pi->sram_end);
3602         if (ret)
3603                 return ret;
3604
3605         si_pi->spll_table_start = tmp;
3606
3607         ret = si_read_smc_sram_dword(rdev,
3608                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3609                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3610                                      &tmp, si_pi->sram_end);
3611         if (ret)
3612                 return ret;
3613
3614         si_pi->papm_cfg_table_start = tmp;
3615
3616         return ret;
3617 }
3618
3619 static void si_read_clock_registers(struct radeon_device *rdev)
3620 {
3621         struct si_power_info *si_pi = si_get_pi(rdev);
3622
3623         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3624         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3625         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3626         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3627         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3628         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3629         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3630         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3631         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3632         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3633         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3634         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3635         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3636         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3637         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3638 }
3639
3640 static void si_enable_thermal_protection(struct radeon_device *rdev,
3641                                           bool enable)
3642 {
3643         if (enable)
3644                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3645         else
3646                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3647 }
3648
3649 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3650 {
3651         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3652 }
3653
3654 #if 0
3655 static int si_enter_ulp_state(struct radeon_device *rdev)
3656 {
3657         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3658
3659         udelay(25000);
3660
3661         return 0;
3662 }
3663
3664 static int si_exit_ulp_state(struct radeon_device *rdev)
3665 {
3666         int i;
3667
3668         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3669
3670         udelay(7000);
3671
3672         for (i = 0; i < rdev->usec_timeout; i++) {
3673                 if (RREG32(SMC_RESP_0) == 1)
3674                         break;
3675                 udelay(1000);
3676         }
3677
3678         return 0;
3679 }
3680 #endif
3681
3682 static int si_notify_smc_display_change(struct radeon_device *rdev,
3683                                      bool has_display)
3684 {
3685         PPSMC_Msg msg = has_display ?
3686                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3687
3688         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3689                 0 : -EINVAL;
3690 }
3691
3692 static void si_program_response_times(struct radeon_device *rdev)
3693 {
3694         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3695         u32 vddc_dly, acpi_dly, vbi_dly;
3696         u32 reference_clock;
3697
3698         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3699
3700         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3701         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3702
3703         if (voltage_response_time == 0)
3704                 voltage_response_time = 1000;
3705
3706         acpi_delay_time = 15000;
3707         vbi_time_out = 100000;
3708
3709         reference_clock = radeon_get_xclk(rdev);
3710
3711         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3712         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3713         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3714
3715         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3716         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3717         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3718         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3719 }
3720
3721 static void si_program_ds_registers(struct radeon_device *rdev)
3722 {
3723         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3724         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3725
3726         if (eg_pi->sclk_deep_sleep) {
3727                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3728                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3729                          ~AUTOSCALE_ON_SS_CLEAR);
3730         }
3731 }
3732
3733 static void si_program_display_gap(struct radeon_device *rdev)
3734 {
3735         u32 tmp, pipe;
3736         int i;
3737
3738         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3739         if (rdev->pm.dpm.new_active_crtc_count > 0)
3740                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3741         else
3742                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3743
3744         if (rdev->pm.dpm.new_active_crtc_count > 1)
3745                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3746         else
3747                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3748
3749         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3750
3751         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3752         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3753
3754         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3755             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3756                 /* find the first active crtc */
3757                 for (i = 0; i < rdev->num_crtc; i++) {
3758                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3759                                 break;
3760                 }
3761                 if (i == rdev->num_crtc)
3762                         pipe = 0;
3763                 else
3764                         pipe = i;
3765
3766                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3767                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3768                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3769         }
3770
3771         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3772          * This can be a problem on PowerXpress systems or if you want to use the card
3773          * for offscreen rendering or compute if there are no crtcs enabled.
3774          */
3775         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3776 }
3777
3778 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3779 {
3780         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3781
3782         if (enable) {
3783                 if (pi->sclk_ss)
3784                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3785         } else {
3786                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3787                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3788         }
3789 }
3790
3791 static void si_setup_bsp(struct radeon_device *rdev)
3792 {
3793         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3794         u32 xclk = radeon_get_xclk(rdev);
3795
3796         r600_calculate_u_and_p(pi->asi,
3797                                xclk,
3798                                16,
3799                                &pi->bsp,
3800                                &pi->bsu);
3801
3802         r600_calculate_u_and_p(pi->pasi,
3803                                xclk,
3804                                16,
3805                                &pi->pbsp,
3806                                &pi->pbsu);
3807
3808
3809         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3810         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3811
3812         WREG32(CG_BSP, pi->dsp);
3813 }
3814
3815 static void si_program_git(struct radeon_device *rdev)
3816 {
3817         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3818 }
3819
3820 static void si_program_tp(struct radeon_device *rdev)
3821 {
3822         int i;
3823         enum r600_td td = R600_TD_DFLT;
3824
3825         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3826                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3827
3828         if (td == R600_TD_AUTO)
3829                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3830         else
3831                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3832
3833         if (td == R600_TD_UP)
3834                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3835
3836         if (td == R600_TD_DOWN)
3837                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3838 }
3839
3840 static void si_program_tpp(struct radeon_device *rdev)
3841 {
3842         WREG32(CG_TPC, R600_TPC_DFLT);
3843 }
3844
3845 static void si_program_sstp(struct radeon_device *rdev)
3846 {
3847         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3848 }
3849
3850 static void si_enable_display_gap(struct radeon_device *rdev)
3851 {
3852         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3853
3854         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3855         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3856                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3857
3858         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3859         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3860                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3861         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3862 }
3863
3864 static void si_program_vc(struct radeon_device *rdev)
3865 {
3866         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3867
3868         WREG32(CG_FTV, pi->vrc);
3869 }
3870
3871 static void si_clear_vc(struct radeon_device *rdev)
3872 {
3873         WREG32(CG_FTV, 0);
3874 }
3875
3876 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3877 {
3878         u8 mc_para_index;
3879
3880         if (memory_clock < 10000)
3881                 mc_para_index = 0;
3882         else if (memory_clock >= 80000)
3883                 mc_para_index = 0x0f;
3884         else
3885                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3886         return mc_para_index;
3887 }
3888
3889 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3890 {
3891         u8 mc_para_index;
3892
3893         if (strobe_mode) {
3894                 if (memory_clock < 12500)
3895                         mc_para_index = 0x00;
3896                 else if (memory_clock > 47500)
3897                         mc_para_index = 0x0f;
3898                 else
3899                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3900         } else {
3901                 if (memory_clock < 65000)
3902                         mc_para_index = 0x00;
3903                 else if (memory_clock > 135000)
3904                         mc_para_index = 0x0f;
3905                 else
3906                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3907         }
3908         return mc_para_index;
3909 }
3910
3911 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3912 {
3913         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3914         bool strobe_mode = false;
3915         u8 result = 0;
3916
3917         if (mclk <= pi->mclk_strobe_mode_threshold)
3918                 strobe_mode = true;
3919
3920         if (pi->mem_gddr5)
3921                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3922         else
3923                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3924
3925         if (strobe_mode)
3926                 result |= SISLANDS_SMC_STROBE_ENABLE;
3927
3928         return result;
3929 }
3930
3931 static int si_upload_firmware(struct radeon_device *rdev)
3932 {
3933         struct si_power_info *si_pi = si_get_pi(rdev);
3934         int ret;
3935
3936         si_reset_smc(rdev);
3937         si_stop_smc_clock(rdev);
3938
3939         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3940
3941         return ret;
3942 }
3943
3944 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3945                                               const struct atom_voltage_table *table,
3946                                               const struct radeon_phase_shedding_limits_table *limits)
3947 {
3948         u32 data, num_bits, num_levels;
3949
3950         if ((table == NULL) || (limits == NULL))
3951                 return false;
3952
3953         data = table->mask_low;
3954
3955         num_bits = hweight32(data);
3956
3957         if (num_bits == 0)
3958                 return false;
3959
3960         num_levels = (1 << num_bits);
3961
3962         if (table->count != num_levels)
3963                 return false;
3964
3965         if (limits->count != (num_levels - 1))
3966                 return false;
3967
3968         return true;
3969 }
3970
3971 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3972                                               u32 max_voltage_steps,
3973                                               struct atom_voltage_table *voltage_table)
3974 {
3975         unsigned int i, diff;
3976
3977         if (voltage_table->count <= max_voltage_steps)
3978                 return;
3979
3980         diff = voltage_table->count - max_voltage_steps;
3981
3982         for (i= 0; i < max_voltage_steps; i++)
3983                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3984
3985         voltage_table->count = max_voltage_steps;
3986 }
3987
3988 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3989                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3990                                      struct atom_voltage_table *voltage_table)
3991 {
3992         u32 i;
3993
3994         if (voltage_dependency_table == NULL)
3995                 return -EINVAL;
3996
3997         voltage_table->mask_low = 0;
3998         voltage_table->phase_delay = 0;
3999
4000         voltage_table->count = voltage_dependency_table->count;
4001         for (i = 0; i < voltage_table->count; i++) {
4002                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4003                 voltage_table->entries[i].smio_low = 0;
4004         }
4005
4006         return 0;
4007 }
4008
4009 static int si_construct_voltage_tables(struct radeon_device *rdev)
4010 {
4011         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4012         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4013         struct si_power_info *si_pi = si_get_pi(rdev);
4014         int ret;
4015
4016         if (pi->voltage_control) {
4017                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4018                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4019                 if (ret)
4020                         return ret;
4021
4022                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4023                         si_trim_voltage_table_to_fit_state_table(rdev,
4024                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4025                                                                  &eg_pi->vddc_voltage_table);
4026         } else if (si_pi->voltage_control_svi2) {
4027                 ret = si_get_svi2_voltage_table(rdev,
4028                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4029                                                 &eg_pi->vddc_voltage_table);
4030                 if (ret)
4031                         return ret;
4032         } else {
4033                 return -EINVAL;
4034         }
4035
4036         if (eg_pi->vddci_control) {
4037                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
4038                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4039                 if (ret)
4040                         return ret;
4041
4042                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4043                         si_trim_voltage_table_to_fit_state_table(rdev,
4044                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4045                                                                  &eg_pi->vddci_voltage_table);
4046         }
4047         if (si_pi->vddci_control_svi2) {
4048                 ret = si_get_svi2_voltage_table(rdev,
4049                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4050                                                 &eg_pi->vddci_voltage_table);
4051                 if (ret)
4052                         return ret;
4053         }
4054
4055         if (pi->mvdd_control) {
4056                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4057                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4058
4059                 if (ret) {
4060                         pi->mvdd_control = false;
4061                         return ret;
4062                 }
4063
4064                 if (si_pi->mvdd_voltage_table.count == 0) {
4065                         pi->mvdd_control = false;
4066                         return -EINVAL;
4067                 }
4068
4069                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4070                         si_trim_voltage_table_to_fit_state_table(rdev,
4071                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4072                                                                  &si_pi->mvdd_voltage_table);
4073         }
4074
4075         if (si_pi->vddc_phase_shed_control) {
4076                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4077                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4078                 if (ret)
4079                         si_pi->vddc_phase_shed_control = false;
4080
4081                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4082                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4083                         si_pi->vddc_phase_shed_control = false;
4084         }
4085
4086         return 0;
4087 }
4088
4089 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4090                                           const struct atom_voltage_table *voltage_table,
4091                                           SISLANDS_SMC_STATETABLE *table)
4092 {
4093         unsigned int i;
4094
4095         for (i = 0; i < voltage_table->count; i++)
4096                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4097 }
4098
4099 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4100                                           SISLANDS_SMC_STATETABLE *table)
4101 {
4102         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4103         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4104         struct si_power_info *si_pi = si_get_pi(rdev);
4105         u8 i;
4106
4107         if (si_pi->voltage_control_svi2) {
4108                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4109                         si_pi->svc_gpio_id);
4110                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4111                         si_pi->svd_gpio_id);
4112                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4113                                            2);
4114         } else {
4115                 if (eg_pi->vddc_voltage_table.count) {
4116                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4117                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4118                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4119
4120                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4121                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4122                                         table->maxVDDCIndexInPPTable = i;
4123                                         break;
4124                                 }
4125                         }
4126                 }
4127
4128                 if (eg_pi->vddci_voltage_table.count) {
4129                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4130
4131                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4132                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4133                 }
4134
4135
4136                 if (si_pi->mvdd_voltage_table.count) {
4137                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4138
4139                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4140                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4141                 }
4142
4143                 if (si_pi->vddc_phase_shed_control) {
4144                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4145                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4146                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4147
4148                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4149                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4150
4151                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4152                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4153                         } else {
4154                                 si_pi->vddc_phase_shed_control = false;
4155                         }
4156                 }
4157         }
4158
4159         return 0;
4160 }
4161
4162 static int si_populate_voltage_value(struct radeon_device *rdev,
4163                                      const struct atom_voltage_table *table,
4164                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4165 {
4166         unsigned int i;
4167
4168         for (i = 0; i < table->count; i++) {
4169                 if (value <= table->entries[i].value) {
4170                         voltage->index = (u8)i;
4171                         voltage->value = cpu_to_be16(table->entries[i].value);
4172                         break;
4173                 }
4174         }
4175
4176         if (i >= table->count)
4177                 return -EINVAL;
4178
4179         return 0;
4180 }
4181
4182 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4183                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4184 {
4185         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4186         struct si_power_info *si_pi = si_get_pi(rdev);
4187
4188         if (pi->mvdd_control) {
4189                 if (mclk <= pi->mvdd_split_frequency)
4190                         voltage->index = 0;
4191                 else
4192                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4193
4194                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4195         }
4196         return 0;
4197 }
4198
4199 static int si_get_std_voltage_value(struct radeon_device *rdev,
4200                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4201                                     u16 *std_voltage)
4202 {
4203         u16 v_index;
4204         bool voltage_found = false;
4205         *std_voltage = be16_to_cpu(voltage->value);
4206
4207         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4208                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4209                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4210                                 return -EINVAL;
4211
4212                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4213                                 if (be16_to_cpu(voltage->value) ==
4214                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4215                                         voltage_found = true;
4216                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4217                                                 *std_voltage =
4218                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4219                                         else
4220                                                 *std_voltage =
4221                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4222                                         break;
4223                                 }
4224                         }
4225
4226                         if (!voltage_found) {
4227                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4228                                         if (be16_to_cpu(voltage->value) <=
4229                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4230                                                 voltage_found = true;
4231                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4232                                                         *std_voltage =
4233                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4234                                                 else
4235                                                         *std_voltage =
4236                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4237                                                 break;
4238                                         }
4239                                 }
4240                         }
4241                 } else {
4242                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4243                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4244                 }
4245         }
4246
4247         return 0;
4248 }
4249
4250 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4251                                          u16 value, u8 index,
4252                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4253 {
4254         voltage->index = index;
4255         voltage->value = cpu_to_be16(value);
4256
4257         return 0;
4258 }
4259
4260 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4261                                             const struct radeon_phase_shedding_limits_table *limits,
4262                                             u16 voltage, u32 sclk, u32 mclk,
4263                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4264 {
4265         unsigned int i;
4266
4267         for (i = 0; i < limits->count; i++) {
4268                 if ((voltage <= limits->entries[i].voltage) &&
4269                     (sclk <= limits->entries[i].sclk) &&
4270                     (mclk <= limits->entries[i].mclk))
4271                         break;
4272         }
4273
4274         smc_voltage->phase_settings = (u8)i;
4275
4276         return 0;
4277 }
4278
4279 static int si_init_arb_table_index(struct radeon_device *rdev)
4280 {
4281         struct si_power_info *si_pi = si_get_pi(rdev);
4282         u32 tmp;
4283         int ret;
4284
4285         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4286         if (ret)
4287                 return ret;
4288
4289         tmp &= 0x00FFFFFF;
4290         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4291
4292         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4293 }
4294
4295 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4296 {
4297         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4298 }
4299
4300 static int si_reset_to_default(struct radeon_device *rdev)
4301 {
4302         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4303                 0 : -EINVAL;
4304 }
4305
4306 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4307 {
4308         struct si_power_info *si_pi = si_get_pi(rdev);
4309         u32 tmp;
4310         int ret;
4311
4312         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4313                                      &tmp, si_pi->sram_end);
4314         if (ret)
4315                 return ret;
4316
4317         tmp = (tmp >> 24) & 0xff;
4318
4319         if (tmp == MC_CG_ARB_FREQ_F0)
4320                 return 0;
4321
4322         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4323 }
4324
4325 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4326                                             u32 engine_clock)
4327 {
4328         u32 dram_rows;
4329         u32 dram_refresh_rate;
4330         u32 mc_arb_rfsh_rate;
4331         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4332
4333         if (tmp >= 4)
4334                 dram_rows = 16384;
4335         else
4336                 dram_rows = 1 << (tmp + 10);
4337
4338         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4339         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4340
4341         return mc_arb_rfsh_rate;
4342 }
4343
4344 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4345                                                 struct rv7xx_pl *pl,
4346                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4347 {
4348         u32 dram_timing;
4349         u32 dram_timing2;
4350         u32 burst_time;
4351
4352         arb_regs->mc_arb_rfsh_rate =
4353                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4354
4355         radeon_atom_set_engine_dram_timings(rdev,
4356                                             pl->sclk,
4357                                             pl->mclk);
4358
4359         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4360         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4361         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4362
4363         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4364         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4365         arb_regs->mc_arb_burst_time = (u8)burst_time;
4366
4367         return 0;
4368 }
4369
4370 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4371                                                   struct radeon_ps *radeon_state,
4372                                                   unsigned int first_arb_set)
4373 {
4374         struct si_power_info *si_pi = si_get_pi(rdev);
4375         struct ni_ps *state = ni_get_ps(radeon_state);
4376         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4377         int i, ret = 0;
4378
4379         for (i = 0; i < state->performance_level_count; i++) {
4380                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4381                 if (ret)
4382                         break;
4383                 ret = si_copy_bytes_to_smc(rdev,
4384                                            si_pi->arb_table_start +
4385                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4386                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4387                                            (u8 *)&arb_regs,
4388                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4389                                            si_pi->sram_end);
4390                 if (ret)
4391                         break;
4392         }
4393
4394         return ret;
4395 }
4396
4397 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4398                                                struct radeon_ps *radeon_new_state)
4399 {
4400         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4401                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4402 }
4403
4404 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4405                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4406 {
4407         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4408         struct si_power_info *si_pi = si_get_pi(rdev);
4409
4410         if (pi->mvdd_control)
4411                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4412                                                  si_pi->mvdd_bootup_value, voltage);
4413
4414         return 0;
4415 }
4416
4417 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4418                                          struct radeon_ps *radeon_initial_state,
4419                                          SISLANDS_SMC_STATETABLE *table)
4420 {
4421         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4422         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4423         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4424         struct si_power_info *si_pi = si_get_pi(rdev);
4425         u32 reg;
4426         int ret;
4427
4428         table->initialState.levels[0].mclk.vDLL_CNTL =
4429                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4430         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4431                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4432         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4433                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4434         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4435                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4436         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4437                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4438         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4439                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4440         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4441                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4442         table->initialState.levels[0].mclk.vMPLL_SS =
4443                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4444         table->initialState.levels[0].mclk.vMPLL_SS2 =
4445                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4446
4447         table->initialState.levels[0].mclk.mclk_value =
4448                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4449
4450         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4451                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4452         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4453                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4454         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4455                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4456         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4457                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4458         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4459                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4460         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4461                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4462
4463         table->initialState.levels[0].sclk.sclk_value =
4464                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4465
4466         table->initialState.levels[0].arbRefreshState =
4467                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4468
4469         table->initialState.levels[0].ACIndex = 0;
4470
4471         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4472                                         initial_state->performance_levels[0].vddc,
4473                                         &table->initialState.levels[0].vddc);
4474
4475         if (!ret) {
4476                 u16 std_vddc;
4477
4478                 ret = si_get_std_voltage_value(rdev,
4479                                                &table->initialState.levels[0].vddc,
4480                                                &std_vddc);
4481                 if (!ret)
4482                         si_populate_std_voltage_value(rdev, std_vddc,
4483                                                       table->initialState.levels[0].vddc.index,
4484                                                       &table->initialState.levels[0].std_vddc);
4485         }
4486
4487         if (eg_pi->vddci_control)
4488                 si_populate_voltage_value(rdev,
4489                                           &eg_pi->vddci_voltage_table,
4490                                           initial_state->performance_levels[0].vddci,
4491                                           &table->initialState.levels[0].vddci);
4492
4493         if (si_pi->vddc_phase_shed_control)
4494                 si_populate_phase_shedding_value(rdev,
4495                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4496                                                  initial_state->performance_levels[0].vddc,
4497                                                  initial_state->performance_levels[0].sclk,
4498                                                  initial_state->performance_levels[0].mclk,
4499                                                  &table->initialState.levels[0].vddc);
4500
4501         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4502
4503         reg = CG_R(0xffff) | CG_L(0);
4504         table->initialState.levels[0].aT = cpu_to_be32(reg);
4505
4506         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4507
4508         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4509
4510         if (pi->mem_gddr5) {
4511                 table->initialState.levels[0].strobeMode =
4512                         si_get_strobe_mode_settings(rdev,
4513                                                     initial_state->performance_levels[0].mclk);
4514
4515                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4516                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4517                 else
4518                         table->initialState.levels[0].mcFlags =  0;
4519         }
4520
4521         table->initialState.levelCount = 1;
4522
4523         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4524
4525         table->initialState.levels[0].dpm2.MaxPS = 0;
4526         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4527         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4528         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4529         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4530
4531         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4532         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4533
4534         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4535         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4536
4537         return 0;
4538 }
4539
4540 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4541                                       SISLANDS_SMC_STATETABLE *table)
4542 {
4543         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4544         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4545         struct si_power_info *si_pi = si_get_pi(rdev);
4546         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4547         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4548         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4549         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4550         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4551         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4552         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4553         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4554         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4555         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4556         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4557         u32 reg;
4558         int ret;
4559
4560         table->ACPIState = table->initialState;
4561
4562         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4563
4564         if (pi->acpi_vddc) {
4565                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4566                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4567                 if (!ret) {
4568                         u16 std_vddc;
4569
4570                         ret = si_get_std_voltage_value(rdev,
4571                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4572                         if (!ret)
4573                                 si_populate_std_voltage_value(rdev, std_vddc,
4574                                                               table->ACPIState.levels[0].vddc.index,
4575                                                               &table->ACPIState.levels[0].std_vddc);
4576                 }
4577                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4578
4579                 if (si_pi->vddc_phase_shed_control) {
4580                         si_populate_phase_shedding_value(rdev,
4581                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4582                                                          pi->acpi_vddc,
4583                                                          0,
4584                                                          0,
4585                                                          &table->ACPIState.levels[0].vddc);
4586                 }
4587         } else {
4588                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4589                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4590                 if (!ret) {
4591                         u16 std_vddc;
4592
4593                         ret = si_get_std_voltage_value(rdev,
4594                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4595
4596                         if (!ret)
4597                                 si_populate_std_voltage_value(rdev, std_vddc,
4598                                                               table->ACPIState.levels[0].vddc.index,
4599                                                               &table->ACPIState.levels[0].std_vddc);
4600                 }
4601                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4602                                                                                     si_pi->sys_pcie_mask,
4603                                                                                     si_pi->boot_pcie_gen,
4604                                                                                     RADEON_PCIE_GEN1);
4605
4606                 if (si_pi->vddc_phase_shed_control)
4607                         si_populate_phase_shedding_value(rdev,
4608                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4609                                                          pi->min_vddc_in_table,
4610                                                          0,
4611                                                          0,
4612                                                          &table->ACPIState.levels[0].vddc);
4613         }
4614
4615         if (pi->acpi_vddc) {
4616                 if (eg_pi->acpi_vddci)
4617                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4618                                                   eg_pi->acpi_vddci,
4619                                                   &table->ACPIState.levels[0].vddci);
4620         }
4621
4622         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4623         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4624
4625         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4626
4627         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4628         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4629
4630         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4631                 cpu_to_be32(dll_cntl);
4632         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4633                 cpu_to_be32(mclk_pwrmgt_cntl);
4634         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4635                 cpu_to_be32(mpll_ad_func_cntl);
4636         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4637                 cpu_to_be32(mpll_dq_func_cntl);
4638         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4639                 cpu_to_be32(mpll_func_cntl);
4640         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4641                 cpu_to_be32(mpll_func_cntl_1);
4642         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4643                 cpu_to_be32(mpll_func_cntl_2);
4644         table->ACPIState.levels[0].mclk.vMPLL_SS =
4645                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4646         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4647                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4648
4649         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4650                 cpu_to_be32(spll_func_cntl);
4651         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4652                 cpu_to_be32(spll_func_cntl_2);
4653         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4654                 cpu_to_be32(spll_func_cntl_3);
4655         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4656                 cpu_to_be32(spll_func_cntl_4);
4657
4658         table->ACPIState.levels[0].mclk.mclk_value = 0;
4659         table->ACPIState.levels[0].sclk.sclk_value = 0;
4660
4661         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4662
4663         if (eg_pi->dynamic_ac_timing)
4664                 table->ACPIState.levels[0].ACIndex = 0;
4665
4666         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4667         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4668         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4669         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4670         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4671
4672         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4673         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4674
4675         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4676         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4677
4678         return 0;
4679 }
4680
4681 static int si_populate_ulv_state(struct radeon_device *rdev,
4682                                  SISLANDS_SMC_SWSTATE *state)
4683 {
4684         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4685         struct si_power_info *si_pi = si_get_pi(rdev);
4686         struct si_ulv_param *ulv = &si_pi->ulv;
4687         u32 sclk_in_sr = 1350; /* ??? */
4688         int ret;
4689
4690         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4691                                             &state->levels[0]);
4692         if (!ret) {
4693                 if (eg_pi->sclk_deep_sleep) {
4694                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4695                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4696                         else
4697                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4698                 }
4699                 if (ulv->one_pcie_lane_in_ulv)
4700                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4701                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4702                 state->levels[0].ACIndex = 1;
4703                 state->levels[0].std_vddc = state->levels[0].vddc;
4704                 state->levelCount = 1;
4705
4706                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4707         }
4708
4709         return ret;
4710 }
4711
4712 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4713 {
4714         struct si_power_info *si_pi = si_get_pi(rdev);
4715         struct si_ulv_param *ulv = &si_pi->ulv;
4716         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4717         int ret;
4718
4719         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4720                                                    &arb_regs);
4721         if (ret)
4722                 return ret;
4723
4724         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4725                                    ulv->volt_change_delay);
4726
4727         ret = si_copy_bytes_to_smc(rdev,
4728                                    si_pi->arb_table_start +
4729                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4730                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4731                                    (u8 *)&arb_regs,
4732                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4733                                    si_pi->sram_end);
4734
4735         return ret;
4736 }
4737
4738 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4739 {
4740         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4741
4742         pi->mvdd_split_frequency = 30000;
4743 }
4744
4745 static int si_init_smc_table(struct radeon_device *rdev)
4746 {
4747         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4748         struct si_power_info *si_pi = si_get_pi(rdev);
4749         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4750         const struct si_ulv_param *ulv = &si_pi->ulv;
4751         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4752         int ret;
4753         u32 lane_width;
4754         u32 vr_hot_gpio;
4755
4756         si_populate_smc_voltage_tables(rdev, table);
4757
4758         switch (rdev->pm.int_thermal_type) {
4759         case THERMAL_TYPE_SI:
4760         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4761                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4762                 break;
4763         case THERMAL_TYPE_NONE:
4764                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4765                 break;
4766         default:
4767                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4768                 break;
4769         }
4770
4771         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4772                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4773
4774         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4775                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4776                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4777         }
4778
4779         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4780                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4781
4782         if (pi->mem_gddr5)
4783                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4784
4785         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4786                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4787
4788         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4789                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4790                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4791                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4792                                            vr_hot_gpio);
4793         }
4794
4795         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4796         if (ret)
4797                 return ret;
4798
4799         ret = si_populate_smc_acpi_state(rdev, table);
4800         if (ret)
4801                 return ret;
4802
4803         table->driverState = table->initialState;
4804
4805         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4806                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4807         if (ret)
4808                 return ret;
4809
4810         if (ulv->supported && ulv->pl.vddc) {
4811                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4812                 if (ret)
4813                         return ret;
4814
4815                 ret = si_program_ulv_memory_timing_parameters(rdev);
4816                 if (ret)
4817                         return ret;
4818
4819                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4820                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4821
4822                 lane_width = radeon_get_pcie_lanes(rdev);
4823                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4824         } else {
4825                 table->ULVState = table->initialState;
4826         }
4827
4828         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4829                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4830                                     si_pi->sram_end);
4831 }
4832
4833 static int si_calculate_sclk_params(struct radeon_device *rdev,
4834                                     u32 engine_clock,
4835                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4836 {
4837         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4838         struct si_power_info *si_pi = si_get_pi(rdev);
4839         struct atom_clock_dividers dividers;
4840         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4841         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4842         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4843         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4844         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4845         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4846         u64 tmp;
4847         u32 reference_clock = rdev->clock.spll.reference_freq;
4848         u32 reference_divider;
4849         u32 fbdiv;
4850         int ret;
4851
4852         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4853                                              engine_clock, false, &dividers);
4854         if (ret)
4855                 return ret;
4856
4857         reference_divider = 1 + dividers.ref_div;
4858
4859         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4860         do_div(tmp, reference_clock);
4861         fbdiv = (u32) tmp;
4862
4863         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4864         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4865         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4866
4867         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4868         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4869
4870         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4871         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4872         spll_func_cntl_3 |= SPLL_DITHEN;
4873
4874         if (pi->sclk_ss) {
4875                 struct radeon_atom_ss ss;
4876                 u32 vco_freq = engine_clock * dividers.post_div;
4877
4878                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4879                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4880                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4881                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4882
4883                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4884                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4885                         cg_spll_spread_spectrum |= SSEN;
4886
4887                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4888                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4889                 }
4890         }
4891
4892         sclk->sclk_value = engine_clock;
4893         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4894         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4895         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4896         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4897         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4898         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4899
4900         return 0;
4901 }
4902
4903 static int si_populate_sclk_value(struct radeon_device *rdev,
4904                                   u32 engine_clock,
4905                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4906 {
4907         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4908         int ret;
4909
4910         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4911         if (!ret) {
4912                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4913                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4914                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4915                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4916                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4917                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4918                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4919         }
4920
4921         return ret;
4922 }
4923
4924 static int si_populate_mclk_value(struct radeon_device *rdev,
4925                                   u32 engine_clock,
4926                                   u32 memory_clock,
4927                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4928                                   bool strobe_mode,
4929                                   bool dll_state_on)
4930 {
4931         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4932         struct si_power_info *si_pi = si_get_pi(rdev);
4933         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4934         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4935         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4936         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4937         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4938         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4939         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4940         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4941         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4942         struct atom_mpll_param mpll_param;
4943         int ret;
4944
4945         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4946         if (ret)
4947                 return ret;
4948
4949         mpll_func_cntl &= ~BWCTRL_MASK;
4950         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4951
4952         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4953         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4954                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4955
4956         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4957         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4958
4959         if (pi->mem_gddr5) {
4960                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4961                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4962                         YCLK_POST_DIV(mpll_param.post_div);
4963         }
4964
4965         if (pi->mclk_ss) {
4966                 struct radeon_atom_ss ss;
4967                 u32 freq_nom;
4968                 u32 tmp;
4969                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4970
4971                 if (pi->mem_gddr5)
4972                         freq_nom = memory_clock * 4;
4973                 else
4974                         freq_nom = memory_clock * 2;
4975
4976                 tmp = freq_nom / reference_clock;
4977                 tmp = tmp * tmp;
4978                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4979                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4980                         u32 clks = reference_clock * 5 / ss.rate;
4981                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4982
4983                         mpll_ss1 &= ~CLKV_MASK;
4984                         mpll_ss1 |= CLKV(clkv);
4985
4986                         mpll_ss2 &= ~CLKS_MASK;
4987                         mpll_ss2 |= CLKS(clks);
4988                 }
4989         }
4990
4991         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4992         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4993
4994         if (dll_state_on)
4995                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4996         else
4997                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4998
4999         mclk->mclk_value = cpu_to_be32(memory_clock);
5000         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5001         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5002         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5003         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5004         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5005         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5006         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5007         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5008         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5009
5010         return 0;
5011 }
5012
5013 static void si_populate_smc_sp(struct radeon_device *rdev,
5014                                struct radeon_ps *radeon_state,
5015                                SISLANDS_SMC_SWSTATE *smc_state)
5016 {
5017         struct ni_ps *ps = ni_get_ps(radeon_state);
5018         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5019         int i;
5020
5021         for (i = 0; i < ps->performance_level_count - 1; i++)
5022                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5023
5024         smc_state->levels[ps->performance_level_count - 1].bSP =
5025                 cpu_to_be32(pi->psp);
5026 }
5027
5028 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
5029                                          struct rv7xx_pl *pl,
5030                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5031 {
5032         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5033         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5034         struct si_power_info *si_pi = si_get_pi(rdev);
5035         int ret;
5036         bool dll_state_on;
5037         u16 std_vddc;
5038         bool gmc_pg = false;
5039
5040         if (eg_pi->pcie_performance_request &&
5041             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5042                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5043         else
5044                 level->gen2PCIE = (u8)pl->pcie_gen;
5045
5046         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5047         if (ret)
5048                 return ret;
5049
5050         level->mcFlags =  0;
5051
5052         if (pi->mclk_stutter_mode_threshold &&
5053             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5054             !eg_pi->uvd_enabled &&
5055             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5056             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5057                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5058
5059                 if (gmc_pg)
5060                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5061         }
5062
5063         if (pi->mem_gddr5) {
5064                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5065                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5066
5067                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5068                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5069
5070                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5071
5072                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5073                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5074                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5075                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5076                         else
5077                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5078                 } else {
5079                         dll_state_on = false;
5080                 }
5081         } else {
5082                 level->strobeMode = si_get_strobe_mode_settings(rdev,
5083                                                                 pl->mclk);
5084
5085                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5086         }
5087
5088         ret = si_populate_mclk_value(rdev,
5089                                      pl->sclk,
5090                                      pl->mclk,
5091                                      &level->mclk,
5092                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5093         if (ret)
5094                 return ret;
5095
5096         ret = si_populate_voltage_value(rdev,
5097                                         &eg_pi->vddc_voltage_table,
5098                                         pl->vddc, &level->vddc);
5099         if (ret)
5100                 return ret;
5101
5102
5103         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5104         if (ret)
5105                 return ret;
5106
5107         ret = si_populate_std_voltage_value(rdev, std_vddc,
5108                                             level->vddc.index, &level->std_vddc);
5109         if (ret)
5110                 return ret;
5111
5112         if (eg_pi->vddci_control) {
5113                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5114                                                 pl->vddci, &level->vddci);
5115                 if (ret)
5116                         return ret;
5117         }
5118
5119         if (si_pi->vddc_phase_shed_control) {
5120                 ret = si_populate_phase_shedding_value(rdev,
5121                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5122                                                        pl->vddc,
5123                                                        pl->sclk,
5124                                                        pl->mclk,
5125                                                        &level->vddc);
5126                 if (ret)
5127                         return ret;
5128         }
5129
5130         level->MaxPoweredUpCU = si_pi->max_cu;
5131
5132         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5133
5134         return ret;
5135 }
5136
5137 static int si_populate_smc_t(struct radeon_device *rdev,
5138                              struct radeon_ps *radeon_state,
5139                              SISLANDS_SMC_SWSTATE *smc_state)
5140 {
5141         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5142         struct ni_ps *state = ni_get_ps(radeon_state);
5143         u32 a_t;
5144         u32 t_l, t_h;
5145         u32 high_bsp;
5146         int i, ret;
5147
5148         if (state->performance_level_count >= 9)
5149                 return -EINVAL;
5150
5151         if (state->performance_level_count < 2) {
5152                 a_t = CG_R(0xffff) | CG_L(0);
5153                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5154                 return 0;
5155         }
5156
5157         smc_state->levels[0].aT = cpu_to_be32(0);
5158
5159         for (i = 0; i <= state->performance_level_count - 2; i++) {
5160                 ret = r600_calculate_at(
5161                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5162                         100 * R600_AH_DFLT,
5163                         state->performance_levels[i + 1].sclk,
5164                         state->performance_levels[i].sclk,
5165                         &t_l,
5166                         &t_h);
5167
5168                 if (ret) {
5169                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5170                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5171                 }
5172
5173                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5174                 a_t |= CG_R(t_l * pi->bsp / 20000);
5175                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5176
5177                 high_bsp = (i == state->performance_level_count - 2) ?
5178                         pi->pbsp : pi->bsp;
5179                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5180                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5181         }
5182
5183         return 0;
5184 }
5185
5186 static int si_disable_ulv(struct radeon_device *rdev)
5187 {
5188         struct si_power_info *si_pi = si_get_pi(rdev);
5189         struct si_ulv_param *ulv = &si_pi->ulv;
5190
5191         if (ulv->supported)
5192                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5193                         0 : -EINVAL;
5194
5195         return 0;
5196 }
5197
5198 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5199                                        struct radeon_ps *radeon_state)
5200 {
5201         const struct si_power_info *si_pi = si_get_pi(rdev);
5202         const struct si_ulv_param *ulv = &si_pi->ulv;
5203         const struct ni_ps *state = ni_get_ps(radeon_state);
5204         int i;
5205
5206         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5207                 return false;
5208
5209         /* XXX validate against display requirements! */
5210
5211         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5212                 if (rdev->clock.current_dispclk <=
5213                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5214                         if (ulv->pl.vddc <
5215                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5216                                 return false;
5217                 }
5218         }
5219
5220         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5221                 return false;
5222
5223         return true;
5224 }
5225
5226 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5227                                                        struct radeon_ps *radeon_new_state)
5228 {
5229         const struct si_power_info *si_pi = si_get_pi(rdev);
5230         const struct si_ulv_param *ulv = &si_pi->ulv;
5231
5232         if (ulv->supported) {
5233                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5234                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5235                                 0 : -EINVAL;
5236         }
5237         return 0;
5238 }
5239
5240 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5241                                          struct radeon_ps *radeon_state,
5242                                          SISLANDS_SMC_SWSTATE *smc_state)
5243 {
5244         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5245         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5246         struct si_power_info *si_pi = si_get_pi(rdev);
5247         struct ni_ps *state = ni_get_ps(radeon_state);
5248         int i, ret;
5249         u32 threshold;
5250         u32 sclk_in_sr = 1350; /* ??? */
5251
5252         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5253                 return -EINVAL;
5254
5255         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5256
5257         if (radeon_state->vclk && radeon_state->dclk) {
5258                 eg_pi->uvd_enabled = true;
5259                 if (eg_pi->smu_uvd_hs)
5260                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5261         } else {
5262                 eg_pi->uvd_enabled = false;
5263         }
5264
5265         if (state->dc_compatible)
5266                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5267
5268         smc_state->levelCount = 0;
5269         for (i = 0; i < state->performance_level_count; i++) {
5270                 if (eg_pi->sclk_deep_sleep) {
5271                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5272                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5273                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5274                                 else
5275                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5276                         }
5277                 }
5278
5279                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5280                                                     &smc_state->levels[i]);
5281                 smc_state->levels[i].arbRefreshState =
5282                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5283
5284                 if (ret)
5285                         return ret;
5286
5287                 if (ni_pi->enable_power_containment)
5288                         smc_state->levels[i].displayWatermark =
5289                                 (state->performance_levels[i].sclk < threshold) ?
5290                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5291                 else
5292                         smc_state->levels[i].displayWatermark = (i < 2) ?
5293                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5294
5295                 if (eg_pi->dynamic_ac_timing)
5296                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5297                 else
5298                         smc_state->levels[i].ACIndex = 0;
5299
5300                 smc_state->levelCount++;
5301         }
5302
5303         si_write_smc_soft_register(rdev,
5304                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5305                                    threshold / 512);
5306
5307         si_populate_smc_sp(rdev, radeon_state, smc_state);
5308
5309         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5310         if (ret)
5311                 ni_pi->enable_power_containment = false;
5312
5313         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5314         if (ret)
5315                 ni_pi->enable_sq_ramping = false;
5316
5317         return si_populate_smc_t(rdev, radeon_state, smc_state);
5318 }
5319
5320 static int si_upload_sw_state(struct radeon_device *rdev,
5321                               struct radeon_ps *radeon_new_state)
5322 {
5323         struct si_power_info *si_pi = si_get_pi(rdev);
5324         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5325         int ret;
5326         u32 address = si_pi->state_table_start +
5327                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5328         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5329                 ((new_state->performance_level_count - 1) *
5330                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5331         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5332
5333         memset(smc_state, 0, state_size);
5334
5335         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5336         if (ret)
5337                 return ret;
5338
5339         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5340                                    state_size, si_pi->sram_end);
5341
5342         return ret;
5343 }
5344
5345 static int si_upload_ulv_state(struct radeon_device *rdev)
5346 {
5347         struct si_power_info *si_pi = si_get_pi(rdev);
5348         struct si_ulv_param *ulv = &si_pi->ulv;
5349         int ret = 0;
5350
5351         if (ulv->supported && ulv->pl.vddc) {
5352                 u32 address = si_pi->state_table_start +
5353                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5354                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5355                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5356
5357                 memset(smc_state, 0, state_size);
5358
5359                 ret = si_populate_ulv_state(rdev, smc_state);
5360                 if (!ret)
5361                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5362                                                    state_size, si_pi->sram_end);
5363         }
5364
5365         return ret;
5366 }
5367
5368 static int si_upload_smc_data(struct radeon_device *rdev)
5369 {
5370         struct radeon_crtc *radeon_crtc = NULL;
5371         int i;
5372
5373         if (rdev->pm.dpm.new_active_crtc_count == 0)
5374                 return 0;
5375
5376         for (i = 0; i < rdev->num_crtc; i++) {
5377                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5378                         radeon_crtc = rdev->mode_info.crtcs[i];
5379                         break;
5380                 }
5381         }
5382
5383         if (radeon_crtc == NULL)
5384                 return 0;
5385
5386         if (radeon_crtc->line_time <= 0)
5387                 return 0;
5388
5389         if (si_write_smc_soft_register(rdev,
5390                                        SI_SMC_SOFT_REGISTER_crtc_index,
5391                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5392                 return 0;
5393
5394         if (si_write_smc_soft_register(rdev,
5395                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5396                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5397                 return 0;
5398
5399         if (si_write_smc_soft_register(rdev,
5400                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5401                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5402                 return 0;
5403
5404         return 0;
5405 }
5406
5407 static int si_set_mc_special_registers(struct radeon_device *rdev,
5408                                        struct si_mc_reg_table *table)
5409 {
5410         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5411         u8 i, j, k;
5412         u32 temp_reg;
5413
5414         for (i = 0, j = table->last; i < table->last; i++) {
5415                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5416                         return -EINVAL;
5417                 switch (table->mc_reg_address[i].s1 << 2) {
5418                 case MC_SEQ_MISC1:
5419                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5420                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5421                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5422                         for (k = 0; k < table->num_entries; k++)
5423                                 table->mc_reg_table_entry[k].mc_data[j] =
5424                                         ((temp_reg & 0xffff0000)) |
5425                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5426                         j++;
5427                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5428                                 return -EINVAL;
5429
5430                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5431                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5432                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5433                         for (k = 0; k < table->num_entries; k++) {
5434                                 table->mc_reg_table_entry[k].mc_data[j] =
5435                                         (temp_reg & 0xffff0000) |
5436                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5437                                 if (!pi->mem_gddr5)
5438                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5439                         }
5440                         j++;
5441                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5442                                 return -EINVAL;
5443
5444                         if (!pi->mem_gddr5) {
5445                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5446                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5447                                 for (k = 0; k < table->num_entries; k++)
5448                                         table->mc_reg_table_entry[k].mc_data[j] =
5449                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5450                                 j++;
5451                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5452                                         return -EINVAL;
5453                         }
5454                         break;
5455                 case MC_SEQ_RESERVE_M:
5456                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5457                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5458                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5459                         for(k = 0; k < table->num_entries; k++)
5460                                 table->mc_reg_table_entry[k].mc_data[j] =
5461                                         (temp_reg & 0xffff0000) |
5462                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5463                         j++;
5464                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5465                                 return -EINVAL;
5466                         break;
5467                 default:
5468                         break;
5469                 }
5470         }
5471
5472         table->last = j;
5473
5474         return 0;
5475 }
5476
5477 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5478 {
5479         bool result = true;
5480
5481         switch (in_reg) {
5482         case  MC_SEQ_RAS_TIMING >> 2:
5483                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5484                 break;
5485         case MC_SEQ_CAS_TIMING >> 2:
5486                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5487                 break;
5488         case MC_SEQ_MISC_TIMING >> 2:
5489                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5490                 break;
5491         case MC_SEQ_MISC_TIMING2 >> 2:
5492                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5493                 break;
5494         case MC_SEQ_RD_CTL_D0 >> 2:
5495                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5496                 break;
5497         case MC_SEQ_RD_CTL_D1 >> 2:
5498                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5499                 break;
5500         case MC_SEQ_WR_CTL_D0 >> 2:
5501                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5502                 break;
5503         case MC_SEQ_WR_CTL_D1 >> 2:
5504                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5505                 break;
5506         case MC_PMG_CMD_EMRS >> 2:
5507                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5508                 break;
5509         case MC_PMG_CMD_MRS >> 2:
5510                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5511                 break;
5512         case MC_PMG_CMD_MRS1 >> 2:
5513                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5514                 break;
5515         case MC_SEQ_PMG_TIMING >> 2:
5516                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5517                 break;
5518         case MC_PMG_CMD_MRS2 >> 2:
5519                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5520                 break;
5521         case MC_SEQ_WR_CTL_2 >> 2:
5522                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5523                 break;
5524         default:
5525                 result = false;
5526                 break;
5527         }
5528
5529         return result;
5530 }
5531
5532 static void si_set_valid_flag(struct si_mc_reg_table *table)
5533 {
5534         u8 i, j;
5535
5536         for (i = 0; i < table->last; i++) {
5537                 for (j = 1; j < table->num_entries; j++) {
5538                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5539                                 table->valid_flag |= 1 << i;
5540                                 break;
5541                         }
5542                 }
5543         }
5544 }
5545
5546 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5547 {
5548         u32 i;
5549         u16 address;
5550
5551         for (i = 0; i < table->last; i++)
5552                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5553                         address : table->mc_reg_address[i].s1;
5554
5555 }
5556
5557 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5558                                       struct si_mc_reg_table *si_table)
5559 {
5560         u8 i, j;
5561
5562         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5563                 return -EINVAL;
5564         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5565                 return -EINVAL;
5566
5567         for (i = 0; i < table->last; i++)
5568                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5569         si_table->last = table->last;
5570
5571         for (i = 0; i < table->num_entries; i++) {
5572                 si_table->mc_reg_table_entry[i].mclk_max =
5573                         table->mc_reg_table_entry[i].mclk_max;
5574                 for (j = 0; j < table->last; j++) {
5575                         si_table->mc_reg_table_entry[i].mc_data[j] =
5576                                 table->mc_reg_table_entry[i].mc_data[j];
5577                 }
5578         }
5579         si_table->num_entries = table->num_entries;
5580
5581         return 0;
5582 }
5583
5584 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5585 {
5586         struct si_power_info *si_pi = si_get_pi(rdev);
5587         struct atom_mc_reg_table *table;
5588         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5589         u8 module_index = rv770_get_memory_module_index(rdev);
5590         int ret;
5591
5592         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5593         if (!table)
5594                 return -ENOMEM;
5595
5596         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5597         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5598         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5599         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5600         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5601         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5602         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5603         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5604         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5605         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5606         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5607         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5608         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5609         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5610
5611         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5612         if (ret)
5613                 goto init_mc_done;
5614
5615         ret = si_copy_vbios_mc_reg_table(table, si_table);
5616         if (ret)
5617                 goto init_mc_done;
5618
5619         si_set_s0_mc_reg_index(si_table);
5620
5621         ret = si_set_mc_special_registers(rdev, si_table);
5622         if (ret)
5623                 goto init_mc_done;
5624
5625         si_set_valid_flag(si_table);
5626
5627 init_mc_done:
5628         kfree(table);
5629
5630         return ret;
5631
5632 }
5633
5634 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5635                                          SMC_SIslands_MCRegisters *mc_reg_table)
5636 {
5637         struct si_power_info *si_pi = si_get_pi(rdev);
5638         u32 i, j;
5639
5640         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5641                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5642                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5643                                 break;
5644                         mc_reg_table->address[i].s0 =
5645                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5646                         mc_reg_table->address[i].s1 =
5647                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5648                         i++;
5649                 }
5650         }
5651         mc_reg_table->last = (u8)i;
5652 }
5653
5654 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5655                                     SMC_SIslands_MCRegisterSet *data,
5656                                     u32 num_entries, u32 valid_flag)
5657 {
5658         u32 i, j;
5659
5660         for(i = 0, j = 0; j < num_entries; j++) {
5661                 if (valid_flag & (1 << j)) {
5662                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5663                         i++;
5664                 }
5665         }
5666 }
5667
5668 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5669                                                  struct rv7xx_pl *pl,
5670                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5671 {
5672         struct si_power_info *si_pi = si_get_pi(rdev);
5673         u32 i = 0;
5674
5675         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5676                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5677                         break;
5678         }
5679
5680         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5681                 --i;
5682
5683         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5684                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5685                                 si_pi->mc_reg_table.valid_flag);
5686 }
5687
5688 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5689                                            struct radeon_ps *radeon_state,
5690                                            SMC_SIslands_MCRegisters *mc_reg_table)
5691 {
5692         struct ni_ps *state = ni_get_ps(radeon_state);
5693         int i;
5694
5695         for (i = 0; i < state->performance_level_count; i++) {
5696                 si_convert_mc_reg_table_entry_to_smc(rdev,
5697                                                      &state->performance_levels[i],
5698                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5699         }
5700 }
5701
5702 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5703                                     struct radeon_ps *radeon_boot_state)
5704 {
5705         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5706         struct si_power_info *si_pi = si_get_pi(rdev);
5707         struct si_ulv_param *ulv = &si_pi->ulv;
5708         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5709
5710         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5711
5712         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5713
5714         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5715
5716         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5717                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5718
5719         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5720                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5721                                 si_pi->mc_reg_table.last,
5722                                 si_pi->mc_reg_table.valid_flag);
5723
5724         if (ulv->supported && ulv->pl.vddc != 0)
5725                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5726                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5727         else
5728                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5729                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5730                                         si_pi->mc_reg_table.last,
5731                                         si_pi->mc_reg_table.valid_flag);
5732
5733         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5734
5735         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5736                                     (u8 *)smc_mc_reg_table,
5737                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5738 }
5739
5740 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5741                                   struct radeon_ps *radeon_new_state)
5742 {
5743         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5744         struct si_power_info *si_pi = si_get_pi(rdev);
5745         u32 address = si_pi->mc_reg_table_start +
5746                 offsetof(SMC_SIslands_MCRegisters,
5747                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5748         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5749
5750         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5751
5752         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5753
5754
5755         return si_copy_bytes_to_smc(rdev, address,
5756                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5757                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5758                                     si_pi->sram_end);
5759
5760 }
5761
5762 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5763 {
5764         if (enable)
5765                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5766         else
5767                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5768 }
5769
5770 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5771                                                       struct radeon_ps *radeon_state)
5772 {
5773         struct ni_ps *state = ni_get_ps(radeon_state);
5774         int i;
5775         u16 pcie_speed, max_speed = 0;
5776
5777         for (i = 0; i < state->performance_level_count; i++) {
5778                 pcie_speed = state->performance_levels[i].pcie_gen;
5779                 if (max_speed < pcie_speed)
5780                         max_speed = pcie_speed;
5781         }
5782         return max_speed;
5783 }
5784
5785 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5786 {
5787         u32 speed_cntl;
5788
5789         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5790         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5791
5792         return (u16)speed_cntl;
5793 }
5794
5795 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5796                                                              struct radeon_ps *radeon_new_state,
5797                                                              struct radeon_ps *radeon_current_state)
5798 {
5799         struct si_power_info *si_pi = si_get_pi(rdev);
5800         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5801         enum radeon_pcie_gen current_link_speed;
5802
5803         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5804                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5805         else
5806                 current_link_speed = si_pi->force_pcie_gen;
5807
5808         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5809         si_pi->pspp_notify_required = false;
5810         if (target_link_speed > current_link_speed) {
5811                 switch (target_link_speed) {
5812 #if defined(CONFIG_ACPI)
5813                 case RADEON_PCIE_GEN3:
5814                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5815                                 break;
5816                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5817                         if (current_link_speed == RADEON_PCIE_GEN2)
5818                                 break;
5819                 case RADEON_PCIE_GEN2:
5820                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5821                                 break;
5822 #endif
5823                 default:
5824                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5825                         break;
5826                 }
5827         } else {
5828                 if (target_link_speed < current_link_speed)
5829                         si_pi->pspp_notify_required = true;
5830         }
5831 }
5832
5833 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5834                                                            struct radeon_ps *radeon_new_state,
5835                                                            struct radeon_ps *radeon_current_state)
5836 {
5837         struct si_power_info *si_pi = si_get_pi(rdev);
5838         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5839         u8 request;
5840
5841         if (si_pi->pspp_notify_required) {
5842                 if (target_link_speed == RADEON_PCIE_GEN3)
5843                         request = PCIE_PERF_REQ_PECI_GEN3;
5844                 else if (target_link_speed == RADEON_PCIE_GEN2)
5845                         request = PCIE_PERF_REQ_PECI_GEN2;
5846                 else
5847                         request = PCIE_PERF_REQ_PECI_GEN1;
5848
5849                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5850                     (si_get_current_pcie_speed(rdev) > 0))
5851                         return;
5852
5853 #if defined(CONFIG_ACPI)
5854                 radeon_acpi_pcie_performance_request(rdev, request, false);
5855 #endif
5856         }
5857 }
5858
5859 #if 0
5860 static int si_ds_request(struct radeon_device *rdev,
5861                          bool ds_status_on, u32 count_write)
5862 {
5863         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5864
5865         if (eg_pi->sclk_deep_sleep) {
5866                 if (ds_status_on)
5867                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5868                                 PPSMC_Result_OK) ?
5869                                 0 : -EINVAL;
5870                 else
5871                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5872                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5873         }
5874         return 0;
5875 }
5876 #endif
5877
5878 static void si_set_max_cu_value(struct radeon_device *rdev)
5879 {
5880         struct si_power_info *si_pi = si_get_pi(rdev);
5881
5882         if (rdev->family == CHIP_VERDE) {
5883                 switch (rdev->pdev->device) {
5884                 case 0x6820:
5885                 case 0x6825:
5886                 case 0x6821:
5887                 case 0x6823:
5888                 case 0x6827:
5889                         si_pi->max_cu = 10;
5890                         break;
5891                 case 0x682D:
5892                 case 0x6824:
5893                 case 0x682F:
5894                 case 0x6826:
5895                         si_pi->max_cu = 8;
5896                         break;
5897                 case 0x6828:
5898                 case 0x6830:
5899                 case 0x6831:
5900                 case 0x6838:
5901                 case 0x6839:
5902                 case 0x683D:
5903                         si_pi->max_cu = 10;
5904                         break;
5905                 case 0x683B:
5906                 case 0x683F:
5907                 case 0x6829:
5908                         si_pi->max_cu = 8;
5909                         break;
5910                 default:
5911                         si_pi->max_cu = 0;
5912                         break;
5913                 }
5914         } else {
5915                 si_pi->max_cu = 0;
5916         }
5917 }
5918
5919 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5920                                                              struct radeon_clock_voltage_dependency_table *table)
5921 {
5922         u32 i;
5923         int j;
5924         u16 leakage_voltage;
5925
5926         if (table) {
5927                 for (i = 0; i < table->count; i++) {
5928                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5929                                                                           table->entries[i].v,
5930                                                                           &leakage_voltage)) {
5931                         case 0:
5932                                 table->entries[i].v = leakage_voltage;
5933                                 break;
5934                         case -EAGAIN:
5935                                 return -EINVAL;
5936                         case -EINVAL:
5937                         default:
5938                                 break;
5939                         }
5940                 }
5941
5942                 for (j = (table->count - 2); j >= 0; j--) {
5943                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5944                                 table->entries[j].v : table->entries[j + 1].v;
5945                 }
5946         }
5947         return 0;
5948 }
5949
5950 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5951 {
5952         int ret = 0;
5953
5954         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5955                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5956         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5957                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5958         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5959                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5960         return ret;
5961 }
5962
5963 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5964                                           struct radeon_ps *radeon_new_state,
5965                                           struct radeon_ps *radeon_current_state)
5966 {
5967         u32 lane_width;
5968         u32 new_lane_width =
5969                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5970         u32 current_lane_width =
5971                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5972
5973         if (new_lane_width != current_lane_width) {
5974                 radeon_set_pcie_lanes(rdev, new_lane_width);
5975                 lane_width = radeon_get_pcie_lanes(rdev);
5976                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5977         }
5978 }
5979
5980 static void si_set_vce_clock(struct radeon_device *rdev,
5981                              struct radeon_ps *new_rps,
5982                              struct radeon_ps *old_rps)
5983 {
5984         if ((old_rps->evclk != new_rps->evclk) ||
5985             (old_rps->ecclk != new_rps->ecclk)) {
5986                 /* turn the clocks on when encoding, off otherwise */
5987                 if (new_rps->evclk || new_rps->ecclk)
5988                         vce_v1_0_enable_mgcg(rdev, false);
5989                 else
5990                         vce_v1_0_enable_mgcg(rdev, true);
5991                 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5992         }
5993 }
5994
5995 void si_dpm_setup_asic(struct radeon_device *rdev)
5996 {
5997         int r;
5998
5999         r = si_mc_load_microcode(rdev);
6000         if (r)
6001                 DRM_ERROR("Failed to load MC firmware!\n");
6002         rv770_get_memory_type(rdev);
6003         si_read_clock_registers(rdev);
6004         si_enable_acpi_power_management(rdev);
6005 }
6006
6007 static int si_thermal_enable_alert(struct radeon_device *rdev,
6008                                    bool enable)
6009 {
6010         u32 thermal_int = RREG32(CG_THERMAL_INT);
6011
6012         if (enable) {
6013                 PPSMC_Result result;
6014
6015                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6016                 WREG32(CG_THERMAL_INT, thermal_int);
6017                 rdev->irq.dpm_thermal = false;
6018                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
6019                 if (result != PPSMC_Result_OK) {
6020                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6021                         return -EINVAL;
6022                 }
6023         } else {
6024                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6025                 WREG32(CG_THERMAL_INT, thermal_int);
6026                 rdev->irq.dpm_thermal = true;
6027         }
6028
6029         return 0;
6030 }
6031
6032 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6033                                             int min_temp, int max_temp)
6034 {
6035         int low_temp = 0 * 1000;
6036         int high_temp = 255 * 1000;
6037
6038         if (low_temp < min_temp)
6039                 low_temp = min_temp;
6040         if (high_temp > max_temp)
6041                 high_temp = max_temp;
6042         if (high_temp < low_temp) {
6043                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6044                 return -EINVAL;
6045         }
6046
6047         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6048         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6049         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6050
6051         rdev->pm.dpm.thermal.min_temp = low_temp;
6052         rdev->pm.dpm.thermal.max_temp = high_temp;
6053
6054         return 0;
6055 }
6056
6057 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6058 {
6059         struct si_power_info *si_pi = si_get_pi(rdev);
6060         u32 tmp;
6061
6062         if (si_pi->fan_ctrl_is_in_default_mode) {
6063                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6064                 si_pi->fan_ctrl_default_mode = tmp;
6065                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6066                 si_pi->t_min = tmp;
6067                 si_pi->fan_ctrl_is_in_default_mode = false;
6068         }
6069
6070         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6071         tmp |= TMIN(0);
6072         WREG32(CG_FDO_CTRL2, tmp);
6073
6074         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6075         tmp |= FDO_PWM_MODE(mode);
6076         WREG32(CG_FDO_CTRL2, tmp);
6077 }
6078
6079 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6080 {
6081         struct si_power_info *si_pi = si_get_pi(rdev);
6082         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6083         u32 duty100;
6084         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6085         u16 fdo_min, slope1, slope2;
6086         u32 reference_clock, tmp;
6087         int ret;
6088         u64 tmp64;
6089
6090         if (!si_pi->fan_table_start) {
6091                 rdev->pm.dpm.fan.ucode_fan_control = false;
6092                 return 0;
6093         }
6094
6095         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6096
6097         if (duty100 == 0) {
6098                 rdev->pm.dpm.fan.ucode_fan_control = false;
6099                 return 0;
6100         }
6101
6102         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6103         do_div(tmp64, 10000);
6104         fdo_min = (u16)tmp64;
6105
6106         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6107         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6108
6109         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6110         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6111
6112         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6113         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6114
6115         fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6116         fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6117         fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6118
6119         fan_table.slope1 = cpu_to_be16(slope1);
6120         fan_table.slope2 = cpu_to_be16(slope2);
6121
6122         fan_table.fdo_min = cpu_to_be16(fdo_min);
6123
6124         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6125
6126         fan_table.hys_up = cpu_to_be16(1);
6127
6128         fan_table.hys_slope = cpu_to_be16(1);
6129
6130         fan_table.temp_resp_lim = cpu_to_be16(5);
6131
6132         reference_clock = radeon_get_xclk(rdev);
6133
6134         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6135                                                 reference_clock) / 1600);
6136
6137         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6138
6139         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6140         fan_table.temp_src = (uint8_t)tmp;
6141
6142         ret = si_copy_bytes_to_smc(rdev,
6143                                    si_pi->fan_table_start,
6144                                    (u8 *)(&fan_table),
6145                                    sizeof(fan_table),
6146                                    si_pi->sram_end);
6147
6148         if (ret) {
6149                 DRM_ERROR("Failed to load fan table to the SMC.");
6150                 rdev->pm.dpm.fan.ucode_fan_control = false;
6151         }
6152
6153         return 0;
6154 }
6155
6156 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6157 {
6158         struct si_power_info *si_pi = si_get_pi(rdev);
6159         PPSMC_Result ret;
6160
6161         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6162         if (ret == PPSMC_Result_OK) {
6163                 si_pi->fan_is_controlled_by_smc = true;
6164                 return 0;
6165         } else {
6166                 return -EINVAL;
6167         }
6168 }
6169
6170 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6171 {
6172         struct si_power_info *si_pi = si_get_pi(rdev);
6173         PPSMC_Result ret;
6174
6175         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6176
6177         if (ret == PPSMC_Result_OK) {
6178                 si_pi->fan_is_controlled_by_smc = false;
6179                 return 0;
6180         } else {
6181                 return -EINVAL;
6182         }
6183 }
6184
6185 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6186                                       u32 *speed)
6187 {
6188         u32 duty, duty100;
6189         u64 tmp64;
6190
6191         if (rdev->pm.no_fan)
6192                 return -ENOENT;
6193
6194         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6195         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6196
6197         if (duty100 == 0)
6198                 return -EINVAL;
6199
6200         tmp64 = (u64)duty * 100;
6201         do_div(tmp64, duty100);
6202         *speed = (u32)tmp64;
6203
6204         if (*speed > 100)
6205                 *speed = 100;
6206
6207         return 0;
6208 }
6209
6210 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6211                                       u32 speed)
6212 {
6213         struct si_power_info *si_pi = si_get_pi(rdev);
6214         u32 tmp;
6215         u32 duty, duty100;
6216         u64 tmp64;
6217
6218         if (rdev->pm.no_fan)
6219                 return -ENOENT;
6220
6221         if (si_pi->fan_is_controlled_by_smc)
6222                 return -EINVAL;
6223
6224         if (speed > 100)
6225                 return -EINVAL;
6226
6227         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6228
6229         if (duty100 == 0)
6230                 return -EINVAL;
6231
6232         tmp64 = (u64)speed * duty100;
6233         do_div(tmp64, 100);
6234         duty = (u32)tmp64;
6235
6236         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6237         tmp |= FDO_STATIC_DUTY(duty);
6238         WREG32(CG_FDO_CTRL0, tmp);
6239
6240         return 0;
6241 }
6242
6243 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6244 {
6245         if (mode) {
6246                 /* stop auto-manage */
6247                 if (rdev->pm.dpm.fan.ucode_fan_control)
6248                         si_fan_ctrl_stop_smc_fan_control(rdev);
6249                 si_fan_ctrl_set_static_mode(rdev, mode);
6250         } else {
6251                 /* restart auto-manage */
6252                 if (rdev->pm.dpm.fan.ucode_fan_control)
6253                         si_thermal_start_smc_fan_control(rdev);
6254                 else
6255                         si_fan_ctrl_set_default_mode(rdev);
6256         }
6257 }
6258
6259 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6260 {
6261         struct si_power_info *si_pi = si_get_pi(rdev);
6262         u32 tmp;
6263
6264         if (si_pi->fan_is_controlled_by_smc)
6265                 return 0;
6266
6267         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6268         return (tmp >> FDO_PWM_MODE_SHIFT);
6269 }
6270
6271 #if 0
6272 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6273                                          u32 *speed)
6274 {
6275         u32 tach_period;
6276         u32 xclk = radeon_get_xclk(rdev);
6277
6278         if (rdev->pm.no_fan)
6279                 return -ENOENT;
6280
6281         if (rdev->pm.fan_pulses_per_revolution == 0)
6282                 return -ENOENT;
6283
6284         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6285         if (tach_period == 0)
6286                 return -ENOENT;
6287
6288         *speed = 60 * xclk * 10000 / tach_period;
6289
6290         return 0;
6291 }
6292
6293 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6294                                          u32 speed)
6295 {
6296         u32 tach_period, tmp;
6297         u32 xclk = radeon_get_xclk(rdev);
6298
6299         if (rdev->pm.no_fan)
6300                 return -ENOENT;
6301
6302         if (rdev->pm.fan_pulses_per_revolution == 0)
6303                 return -ENOENT;
6304
6305         if ((speed < rdev->pm.fan_min_rpm) ||
6306             (speed > rdev->pm.fan_max_rpm))
6307                 return -EINVAL;
6308
6309         if (rdev->pm.dpm.fan.ucode_fan_control)
6310                 si_fan_ctrl_stop_smc_fan_control(rdev);
6311
6312         tach_period = 60 * xclk * 10000 / (8 * speed);
6313         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6314         tmp |= TARGET_PERIOD(tach_period);
6315         WREG32(CG_TACH_CTRL, tmp);
6316
6317         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6318
6319         return 0;
6320 }
6321 #endif
6322
6323 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6324 {
6325         struct si_power_info *si_pi = si_get_pi(rdev);
6326         u32 tmp;
6327
6328         if (!si_pi->fan_ctrl_is_in_default_mode) {
6329                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6330                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6331                 WREG32(CG_FDO_CTRL2, tmp);
6332
6333                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6334                 tmp |= TMIN(si_pi->t_min);
6335                 WREG32(CG_FDO_CTRL2, tmp);
6336                 si_pi->fan_ctrl_is_in_default_mode = true;
6337         }
6338 }
6339
6340 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6341 {
6342         if (rdev->pm.dpm.fan.ucode_fan_control) {
6343                 si_fan_ctrl_start_smc_fan_control(rdev);
6344                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6345         }
6346 }
6347
6348 static void si_thermal_initialize(struct radeon_device *rdev)
6349 {
6350         u32 tmp;
6351
6352         if (rdev->pm.fan_pulses_per_revolution) {
6353                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6354                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6355                 WREG32(CG_TACH_CTRL, tmp);
6356         }
6357
6358         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6359         tmp |= TACH_PWM_RESP_RATE(0x28);
6360         WREG32(CG_FDO_CTRL2, tmp);
6361 }
6362
6363 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6364 {
6365         int ret;
6366
6367         si_thermal_initialize(rdev);
6368         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6369         if (ret)
6370                 return ret;
6371         ret = si_thermal_enable_alert(rdev, true);
6372         if (ret)
6373                 return ret;
6374         if (rdev->pm.dpm.fan.ucode_fan_control) {
6375                 ret = si_halt_smc(rdev);
6376                 if (ret)
6377                         return ret;
6378                 ret = si_thermal_setup_fan_table(rdev);
6379                 if (ret)
6380                         return ret;
6381                 ret = si_resume_smc(rdev);
6382                 if (ret)
6383                         return ret;
6384                 si_thermal_start_smc_fan_control(rdev);
6385         }
6386
6387         return 0;
6388 }
6389
6390 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6391 {
6392         if (!rdev->pm.no_fan) {
6393                 si_fan_ctrl_set_default_mode(rdev);
6394                 si_fan_ctrl_stop_smc_fan_control(rdev);
6395         }
6396 }
6397
6398 int si_dpm_enable(struct radeon_device *rdev)
6399 {
6400         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6401         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6402         struct si_power_info *si_pi = si_get_pi(rdev);
6403         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6404         int ret;
6405
6406         if (si_is_smc_running(rdev))
6407                 return -EINVAL;
6408         if (pi->voltage_control || si_pi->voltage_control_svi2)
6409                 si_enable_voltage_control(rdev, true);
6410         if (pi->mvdd_control)
6411                 si_get_mvdd_configuration(rdev);
6412         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6413                 ret = si_construct_voltage_tables(rdev);
6414                 if (ret) {
6415                         DRM_ERROR("si_construct_voltage_tables failed\n");
6416                         return ret;
6417                 }
6418         }
6419         if (eg_pi->dynamic_ac_timing) {
6420                 ret = si_initialize_mc_reg_table(rdev);
6421                 if (ret)
6422                         eg_pi->dynamic_ac_timing = false;
6423         }
6424         if (pi->dynamic_ss)
6425                 si_enable_spread_spectrum(rdev, true);
6426         if (pi->thermal_protection)
6427                 si_enable_thermal_protection(rdev, true);
6428         si_setup_bsp(rdev);
6429         si_program_git(rdev);
6430         si_program_tp(rdev);
6431         si_program_tpp(rdev);
6432         si_program_sstp(rdev);
6433         si_enable_display_gap(rdev);
6434         si_program_vc(rdev);
6435         ret = si_upload_firmware(rdev);
6436         if (ret) {
6437                 DRM_ERROR("si_upload_firmware failed\n");
6438                 return ret;
6439         }
6440         ret = si_process_firmware_header(rdev);
6441         if (ret) {
6442                 DRM_ERROR("si_process_firmware_header failed\n");
6443                 return ret;
6444         }
6445         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6446         if (ret) {
6447                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6448                 return ret;
6449         }
6450         ret = si_init_smc_table(rdev);
6451         if (ret) {
6452                 DRM_ERROR("si_init_smc_table failed\n");
6453                 return ret;
6454         }
6455         ret = si_init_smc_spll_table(rdev);
6456         if (ret) {
6457                 DRM_ERROR("si_init_smc_spll_table failed\n");
6458                 return ret;
6459         }
6460         ret = si_init_arb_table_index(rdev);
6461         if (ret) {
6462                 DRM_ERROR("si_init_arb_table_index failed\n");
6463                 return ret;
6464         }
6465         if (eg_pi->dynamic_ac_timing) {
6466                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6467                 if (ret) {
6468                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6469                         return ret;
6470                 }
6471         }
6472         ret = si_initialize_smc_cac_tables(rdev);
6473         if (ret) {
6474                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6475                 return ret;
6476         }
6477         ret = si_initialize_hardware_cac_manager(rdev);
6478         if (ret) {
6479                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6480                 return ret;
6481         }
6482         ret = si_initialize_smc_dte_tables(rdev);
6483         if (ret) {
6484                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6485                 return ret;
6486         }
6487         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6488         if (ret) {
6489                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6490                 return ret;
6491         }
6492         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6493         if (ret) {
6494                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6495                 return ret;
6496         }
6497         si_program_response_times(rdev);
6498         si_program_ds_registers(rdev);
6499         si_dpm_start_smc(rdev);
6500         ret = si_notify_smc_display_change(rdev, false);
6501         if (ret) {
6502                 DRM_ERROR("si_notify_smc_display_change failed\n");
6503                 return ret;
6504         }
6505         si_enable_sclk_control(rdev, true);
6506         si_start_dpm(rdev);
6507
6508         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6509
6510         si_thermal_start_thermal_controller(rdev);
6511
6512         ni_update_current_ps(rdev, boot_ps);
6513
6514         return 0;
6515 }
6516
6517 static int si_set_temperature_range(struct radeon_device *rdev)
6518 {
6519         int ret;
6520
6521         ret = si_thermal_enable_alert(rdev, false);
6522         if (ret)
6523                 return ret;
6524         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6525         if (ret)
6526                 return ret;
6527         ret = si_thermal_enable_alert(rdev, true);
6528         if (ret)
6529                 return ret;
6530
6531         return ret;
6532 }
6533
6534 int si_dpm_late_enable(struct radeon_device *rdev)
6535 {
6536         int ret;
6537
6538         ret = si_set_temperature_range(rdev);
6539         if (ret)
6540                 return ret;
6541
6542         return ret;
6543 }
6544
6545 void si_dpm_disable(struct radeon_device *rdev)
6546 {
6547         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6548         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6549
6550         if (!si_is_smc_running(rdev))
6551                 return;
6552         si_thermal_stop_thermal_controller(rdev);
6553         si_disable_ulv(rdev);
6554         si_clear_vc(rdev);
6555         if (pi->thermal_protection)
6556                 si_enable_thermal_protection(rdev, false);
6557         si_enable_power_containment(rdev, boot_ps, false);
6558         si_enable_smc_cac(rdev, boot_ps, false);
6559         si_enable_spread_spectrum(rdev, false);
6560         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6561         si_stop_dpm(rdev);
6562         si_reset_to_default(rdev);
6563         si_dpm_stop_smc(rdev);
6564         si_force_switch_to_arb_f0(rdev);
6565
6566         ni_update_current_ps(rdev, boot_ps);
6567 }
6568
6569 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6570 {
6571         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6572         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6573         struct radeon_ps *new_ps = &requested_ps;
6574
6575         ni_update_requested_ps(rdev, new_ps);
6576
6577         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6578
6579         return 0;
6580 }
6581
6582 static int si_power_control_set_level(struct radeon_device *rdev)
6583 {
6584         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6585         int ret;
6586
6587         ret = si_restrict_performance_levels_before_switch(rdev);
6588         if (ret)
6589                 return ret;
6590         ret = si_halt_smc(rdev);
6591         if (ret)
6592                 return ret;
6593         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6594         if (ret)
6595                 return ret;
6596         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6597         if (ret)
6598                 return ret;
6599         ret = si_resume_smc(rdev);
6600         if (ret)
6601                 return ret;
6602         ret = si_set_sw_state(rdev);
6603         if (ret)
6604                 return ret;
6605         return 0;
6606 }
6607
6608 int si_dpm_set_power_state(struct radeon_device *rdev)
6609 {
6610         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6611         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6612         struct radeon_ps *old_ps = &eg_pi->current_rps;
6613         int ret;
6614
6615         ret = si_disable_ulv(rdev);
6616         if (ret) {
6617                 DRM_ERROR("si_disable_ulv failed\n");
6618                 return ret;
6619         }
6620         ret = si_restrict_performance_levels_before_switch(rdev);
6621         if (ret) {
6622                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6623                 return ret;
6624         }
6625         if (eg_pi->pcie_performance_request)
6626                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6627         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6628         ret = si_enable_power_containment(rdev, new_ps, false);
6629         if (ret) {
6630                 DRM_ERROR("si_enable_power_containment failed\n");
6631                 return ret;
6632         }
6633         ret = si_enable_smc_cac(rdev, new_ps, false);
6634         if (ret) {
6635                 DRM_ERROR("si_enable_smc_cac failed\n");
6636                 return ret;
6637         }
6638         ret = si_halt_smc(rdev);
6639         if (ret) {
6640                 DRM_ERROR("si_halt_smc failed\n");
6641                 return ret;
6642         }
6643         ret = si_upload_sw_state(rdev, new_ps);
6644         if (ret) {
6645                 DRM_ERROR("si_upload_sw_state failed\n");
6646                 return ret;
6647         }
6648         ret = si_upload_smc_data(rdev);
6649         if (ret) {
6650                 DRM_ERROR("si_upload_smc_data failed\n");
6651                 return ret;
6652         }
6653         ret = si_upload_ulv_state(rdev);
6654         if (ret) {
6655                 DRM_ERROR("si_upload_ulv_state failed\n");
6656                 return ret;
6657         }
6658         if (eg_pi->dynamic_ac_timing) {
6659                 ret = si_upload_mc_reg_table(rdev, new_ps);
6660                 if (ret) {
6661                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6662                         return ret;
6663                 }
6664         }
6665         ret = si_program_memory_timing_parameters(rdev, new_ps);
6666         if (ret) {
6667                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6668                 return ret;
6669         }
6670         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6671
6672         ret = si_resume_smc(rdev);
6673         if (ret) {
6674                 DRM_ERROR("si_resume_smc failed\n");
6675                 return ret;
6676         }
6677         ret = si_set_sw_state(rdev);
6678         if (ret) {
6679                 DRM_ERROR("si_set_sw_state failed\n");
6680                 return ret;
6681         }
6682         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6683         si_set_vce_clock(rdev, new_ps, old_ps);
6684         if (eg_pi->pcie_performance_request)
6685                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6686         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6687         if (ret) {
6688                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6689                 return ret;
6690         }
6691         ret = si_enable_smc_cac(rdev, new_ps, true);
6692         if (ret) {
6693                 DRM_ERROR("si_enable_smc_cac failed\n");
6694                 return ret;
6695         }
6696         ret = si_enable_power_containment(rdev, new_ps, true);
6697         if (ret) {
6698                 DRM_ERROR("si_enable_power_containment failed\n");
6699                 return ret;
6700         }
6701
6702         ret = si_power_control_set_level(rdev);
6703         if (ret) {
6704                 DRM_ERROR("si_power_control_set_level failed\n");
6705                 return ret;
6706         }
6707
6708         return 0;
6709 }
6710
6711 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6712 {
6713         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6714         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6715
6716         ni_update_current_ps(rdev, new_ps);
6717 }
6718
6719 #if 0
6720 void si_dpm_reset_asic(struct radeon_device *rdev)
6721 {
6722         si_restrict_performance_levels_before_switch(rdev);
6723         si_disable_ulv(rdev);
6724         si_set_boot_state(rdev);
6725 }
6726 #endif
6727
6728 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6729 {
6730         si_program_display_gap(rdev);
6731 }
6732
6733 union power_info {
6734         struct _ATOM_POWERPLAY_INFO info;
6735         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6736         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6737         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6738         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6739         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6740 };
6741
6742 union pplib_clock_info {
6743         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6744         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6745         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6746         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6747         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6748 };
6749
6750 union pplib_power_state {
6751         struct _ATOM_PPLIB_STATE v1;
6752         struct _ATOM_PPLIB_STATE_V2 v2;
6753 };
6754
6755 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6756                                           struct radeon_ps *rps,
6757                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6758                                           u8 table_rev)
6759 {
6760         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6761         rps->class = le16_to_cpu(non_clock_info->usClassification);
6762         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6763
6764         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6765                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6766                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6767         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6768                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6769                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6770         } else {
6771                 rps->vclk = 0;
6772                 rps->dclk = 0;
6773         }
6774
6775         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6776                 rdev->pm.dpm.boot_ps = rps;
6777         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6778                 rdev->pm.dpm.uvd_ps = rps;
6779 }
6780
6781 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6782                                       struct radeon_ps *rps, int index,
6783                                       union pplib_clock_info *clock_info)
6784 {
6785         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6786         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6787         struct si_power_info *si_pi = si_get_pi(rdev);
6788         struct ni_ps *ps = ni_get_ps(rps);
6789         u16 leakage_voltage;
6790         struct rv7xx_pl *pl = &ps->performance_levels[index];
6791         int ret;
6792
6793         ps->performance_level_count = index + 1;
6794
6795         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6796         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6797         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6798         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6799
6800         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6801         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6802         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6803         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6804                                                  si_pi->sys_pcie_mask,
6805                                                  si_pi->boot_pcie_gen,
6806                                                  clock_info->si.ucPCIEGen);
6807
6808         /* patch up vddc if necessary */
6809         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6810                                                         &leakage_voltage);
6811         if (ret == 0)
6812                 pl->vddc = leakage_voltage;
6813
6814         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6815                 pi->acpi_vddc = pl->vddc;
6816                 eg_pi->acpi_vddci = pl->vddci;
6817                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6818         }
6819
6820         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6821             index == 0) {
6822                 /* XXX disable for A0 tahiti */
6823                 si_pi->ulv.supported = false;
6824                 si_pi->ulv.pl = *pl;
6825                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6826                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6827                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6828                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6829         }
6830
6831         if (pi->min_vddc_in_table > pl->vddc)
6832                 pi->min_vddc_in_table = pl->vddc;
6833
6834         if (pi->max_vddc_in_table < pl->vddc)
6835                 pi->max_vddc_in_table = pl->vddc;
6836
6837         /* patch up boot state */
6838         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6839                 u16 vddc, vddci, mvdd;
6840                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6841                 pl->mclk = rdev->clock.default_mclk;
6842                 pl->sclk = rdev->clock.default_sclk;
6843                 pl->vddc = vddc;
6844                 pl->vddci = vddci;
6845                 si_pi->mvdd_bootup_value = mvdd;
6846         }
6847
6848         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6849             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6850                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6851                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6852                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6853                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6854         }
6855 }
6856
6857 static int si_parse_power_table(struct radeon_device *rdev)
6858 {
6859         struct radeon_mode_info *mode_info = &rdev->mode_info;
6860         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6861         union pplib_power_state *power_state;
6862         int i, j, k, non_clock_array_index, clock_array_index;
6863         union pplib_clock_info *clock_info;
6864         struct _StateArray *state_array;
6865         struct _ClockInfoArray *clock_info_array;
6866         struct _NonClockInfoArray *non_clock_info_array;
6867         union power_info *power_info;
6868         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6869         u16 data_offset;
6870         u8 frev, crev;
6871         u8 *power_state_offset;
6872         struct ni_ps *ps;
6873
6874         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6875                                    &frev, &crev, &data_offset))
6876                 return -EINVAL;
6877         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6878
6879         state_array = (struct _StateArray *)
6880                 (mode_info->atom_context->bios + data_offset +
6881                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6882         clock_info_array = (struct _ClockInfoArray *)
6883                 (mode_info->atom_context->bios + data_offset +
6884                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6885         non_clock_info_array = (struct _NonClockInfoArray *)
6886                 (mode_info->atom_context->bios + data_offset +
6887                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6888
6889         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6890                                   state_array->ucNumEntries, GFP_KERNEL);
6891         if (!rdev->pm.dpm.ps)
6892                 return -ENOMEM;
6893         power_state_offset = (u8 *)state_array->states;
6894         for (i = 0; i < state_array->ucNumEntries; i++) {
6895                 u8 *idx;
6896                 power_state = (union pplib_power_state *)power_state_offset;
6897                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6898                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6899                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6900                 if (!rdev->pm.power_state[i].clock_info)
6901                         return -EINVAL;
6902                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6903                 if (ps == NULL) {
6904                         kfree(rdev->pm.dpm.ps);
6905                         return -ENOMEM;
6906                 }
6907                 rdev->pm.dpm.ps[i].ps_priv = ps;
6908                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6909                                               non_clock_info,
6910                                               non_clock_info_array->ucEntrySize);
6911                 k = 0;
6912                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6913                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6914                         clock_array_index = idx[j];
6915                         if (clock_array_index >= clock_info_array->ucNumEntries)
6916                                 continue;
6917                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6918                                 break;
6919                         clock_info = (union pplib_clock_info *)
6920                                 ((u8 *)&clock_info_array->clockInfo[0] +
6921                                  (clock_array_index * clock_info_array->ucEntrySize));
6922                         si_parse_pplib_clock_info(rdev,
6923                                                   &rdev->pm.dpm.ps[i], k,
6924                                                   clock_info);
6925                         k++;
6926                 }
6927                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6928         }
6929         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6930
6931         /* fill in the vce power states */
6932         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6933                 u32 sclk, mclk;
6934                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6935                 clock_info = (union pplib_clock_info *)
6936                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6937                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6938                 sclk |= clock_info->si.ucEngineClockHigh << 16;
6939                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6940                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6941                 rdev->pm.dpm.vce_states[i].sclk = sclk;
6942                 rdev->pm.dpm.vce_states[i].mclk = mclk;
6943         }
6944
6945         return 0;
6946 }
6947
6948 int si_dpm_init(struct radeon_device *rdev)
6949 {
6950         struct rv7xx_power_info *pi;
6951         struct evergreen_power_info *eg_pi;
6952         struct ni_power_info *ni_pi;
6953         struct si_power_info *si_pi;
6954         struct atom_clock_dividers dividers;
6955         int ret;
6956         u32 mask;
6957
6958         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6959         if (si_pi == NULL)
6960                 return -ENOMEM;
6961         rdev->pm.dpm.priv = si_pi;
6962         ni_pi = &si_pi->ni;
6963         eg_pi = &ni_pi->eg;
6964         pi = &eg_pi->rv7xx;
6965
6966         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6967         if (ret)
6968                 si_pi->sys_pcie_mask = 0;
6969         else
6970                 si_pi->sys_pcie_mask = mask;
6971         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6972         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6973
6974         si_set_max_cu_value(rdev);
6975
6976         rv770_get_max_vddc(rdev);
6977         si_get_leakage_vddc(rdev);
6978         si_patch_dependency_tables_based_on_leakage(rdev);
6979
6980         pi->acpi_vddc = 0;
6981         eg_pi->acpi_vddci = 0;
6982         pi->min_vddc_in_table = 0;
6983         pi->max_vddc_in_table = 0;
6984
6985         ret = r600_get_platform_caps(rdev);
6986         if (ret)
6987                 return ret;
6988
6989         ret = r600_parse_extended_power_table(rdev);
6990         if (ret)
6991                 return ret;
6992
6993         ret = si_parse_power_table(rdev);
6994         if (ret)
6995                 return ret;
6996
6997         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6998                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6999         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7000                 r600_free_extended_power_table(rdev);
7001                 return -ENOMEM;
7002         }
7003         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7004         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7005         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7006         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7007         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7008         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7009         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7010         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7011         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7012
7013         if (rdev->pm.dpm.voltage_response_time == 0)
7014                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7015         if (rdev->pm.dpm.backbias_response_time == 0)
7016                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7017
7018         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
7019                                              0, false, &dividers);
7020         if (ret)
7021                 pi->ref_div = dividers.ref_div + 1;
7022         else
7023                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7024
7025         eg_pi->smu_uvd_hs = false;
7026
7027         pi->mclk_strobe_mode_threshold = 40000;
7028         if (si_is_special_1gb_platform(rdev))
7029                 pi->mclk_stutter_mode_threshold = 0;
7030         else
7031                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7032         pi->mclk_edc_enable_threshold = 40000;
7033         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7034
7035         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7036
7037         pi->voltage_control =
7038                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7039                                             VOLTAGE_OBJ_GPIO_LUT);
7040         if (!pi->voltage_control) {
7041                 si_pi->voltage_control_svi2 =
7042                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7043                                                     VOLTAGE_OBJ_SVID2);
7044                 if (si_pi->voltage_control_svi2)
7045                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7046                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7047         }
7048
7049         pi->mvdd_control =
7050                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7051                                             VOLTAGE_OBJ_GPIO_LUT);
7052
7053         eg_pi->vddci_control =
7054                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7055                                             VOLTAGE_OBJ_GPIO_LUT);
7056         if (!eg_pi->vddci_control)
7057                 si_pi->vddci_control_svi2 =
7058                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7059                                                     VOLTAGE_OBJ_SVID2);
7060
7061         si_pi->vddc_phase_shed_control =
7062                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7063                                             VOLTAGE_OBJ_PHASE_LUT);
7064
7065         rv770_get_engine_memory_ss(rdev);
7066
7067         pi->asi = RV770_ASI_DFLT;
7068         pi->pasi = CYPRESS_HASI_DFLT;
7069         pi->vrc = SISLANDS_VRC_DFLT;
7070
7071         pi->gfx_clock_gating = true;
7072
7073         eg_pi->sclk_deep_sleep = true;
7074         si_pi->sclk_deep_sleep_above_low = false;
7075
7076         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7077                 pi->thermal_protection = true;
7078         else
7079                 pi->thermal_protection = false;
7080
7081         eg_pi->dynamic_ac_timing = true;
7082
7083         eg_pi->light_sleep = true;
7084 #if defined(CONFIG_ACPI)
7085         eg_pi->pcie_performance_request =
7086                 radeon_acpi_is_pcie_performance_request_supported(rdev);
7087 #else
7088         eg_pi->pcie_performance_request = false;
7089 #endif
7090
7091         si_pi->sram_end = SMC_RAM_END;
7092
7093         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7094         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7095         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7096         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7097         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7098         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7099         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7100
7101         si_initialize_powertune_defaults(rdev);
7102
7103         /* make sure dc limits are valid */
7104         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7105             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7106                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7107                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7108
7109         si_pi->fan_ctrl_is_in_default_mode = true;
7110
7111         return 0;
7112 }
7113
7114 void si_dpm_fini(struct radeon_device *rdev)
7115 {
7116         int i;
7117
7118         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7119                 kfree(rdev->pm.dpm.ps[i].ps_priv);
7120         }
7121         kfree(rdev->pm.dpm.ps);
7122         kfree(rdev->pm.dpm.priv);
7123         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7124         r600_free_extended_power_table(rdev);
7125 }
7126
7127 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7128                                                     struct seq_file *m)
7129 {
7130         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7131         struct radeon_ps *rps = &eg_pi->current_rps;
7132         struct ni_ps *ps = ni_get_ps(rps);
7133         struct rv7xx_pl *pl;
7134         u32 current_index =
7135                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7136                 CURRENT_STATE_INDEX_SHIFT;
7137
7138         if (current_index >= ps->performance_level_count) {
7139                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7140         } else {
7141                 pl = &ps->performance_levels[current_index];
7142                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7143                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7144                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7145         }
7146 }
7147
7148 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7149 {
7150         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7151         struct radeon_ps *rps = &eg_pi->current_rps;
7152         struct ni_ps *ps = ni_get_ps(rps);
7153         struct rv7xx_pl *pl;
7154         u32 current_index =
7155                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7156                 CURRENT_STATE_INDEX_SHIFT;
7157
7158         if (current_index >= ps->performance_level_count) {
7159                 return 0;
7160         } else {
7161                 pl = &ps->performance_levels[current_index];
7162                 return pl->sclk;
7163         }
7164 }
7165
7166 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7167 {
7168         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7169         struct radeon_ps *rps = &eg_pi->current_rps;
7170         struct ni_ps *ps = ni_get_ps(rps);
7171         struct rv7xx_pl *pl;
7172         u32 current_index =
7173                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7174                 CURRENT_STATE_INDEX_SHIFT;
7175
7176         if (current_index >= ps->performance_level_count) {
7177                 return 0;
7178         } else {
7179                 pl = &ps->performance_levels[current_index];
7180                 return pl->mclk;
7181         }
7182 }