drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32 #include "rs690d.h"
  33
  34 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  35 {
  36         unsigned i;
  37         uint32_t tmp;
  38
  39         for (i = 0; i < rdev->usec_timeout; i++) {
  40                 /* read MC_STATUS */
  41                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  42                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  43                         return 0;
  44                 udelay(1);
  45         }
  46         return -1;
  47 }
  48
  49 static void rs690_gpu_init(struct radeon_device *rdev)
  50 {
  51         /* FIXME: is this correct ? */
  52         r420_pipes_init(rdev);
  53         if (rs690_mc_wait_for_idle(rdev)) {
  54                 printk(KERN_WARNING "Failed to wait MC idle while "
  55                        "programming pipes. Bad things might happen.\n");
  56         }
  57 }
  58
  59 union igp_info {
  60         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  61         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
  62 };
  63
  64 void rs690_pm_info(struct radeon_device *rdev)
  65 {
  66         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  67         union igp_info *info;
  68         uint16_t data_offset;
  69         uint8_t frev, crev;
  70         fixed20_12 tmp;
  71
  72         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  73                                    &frev, &crev, &data_offset)) {
  74                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
  75
  76                 /* Get various system informations from bios */
  77                 switch (crev) {
  78                 case 1:
  79                         tmp.full = dfixed_const(100);
  80                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
  81                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  82                         if (le16_to_cpu(info->info.usK8MemoryClock))
  83                                 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
  84                         else if (rdev->clock.default_mclk) {
  85                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
  86                                 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
  87                         } else
  88                                 rdev->pm.igp_system_mclk.full = dfixed_const(400);
  89                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
  90                         rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
  91                         break;
  92                 case 2:
  93                         tmp.full = dfixed_const(100);
  94                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
  95                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  96                         if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
  97                                 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
  98                         else if (rdev->clock.default_mclk)
  99                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
 100                         else
 101                                 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
 102                         rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
 103                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
 104                         rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
 105                         rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
 106                         break;
 107                 default:
 108                         /* We assume the slower possible clock ie worst case */
 109                         rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 110                         rdev->pm.igp_system_mclk.full = dfixed_const(200);
 111                         rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 112                         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 113                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 114                         break;
 115                 }
 116         } else {
 117                 /* We assume the slower possible clock ie worst case */
 118                 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 119                 rdev->pm.igp_system_mclk.full = dfixed_const(200);
 120                 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 121                 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 122                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 123         }
 124         /* Compute various bandwidth */
 125         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 126         tmp.full = dfixed_const(4);
 127         rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
 128         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 129          *              = ht_clk * ht_width / 5
 130          */
 131         tmp.full = dfixed_const(5);
 132         rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
 133                                                 rdev->pm.igp_ht_link_width);
 134         rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
 135         if (tmp.full < rdev->pm.max_bandwidth.full) {
 136                 /* HT link is a limiting factor */
 137                 rdev->pm.max_bandwidth.full = tmp.full;
 138         }
 139         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 140          *                    = (sideport_clk * 14) / 10
 141          */
 142         tmp.full = dfixed_const(14);
 143         rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 144         tmp.full = dfixed_const(10);
 145         rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
 146 }
 147
 148 static void rs690_mc_init(struct radeon_device *rdev)
 149 {
 150         u64 base;
 151         uint32_t h_addr, l_addr;
 152         unsigned long long k8_addr;
 153
 154         rs400_gart_adjust_size(rdev);
 155         rdev->mc.vram_is_ddr = true;
 156         rdev->mc.vram_width = 128;
 157         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 158         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 159         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 160         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 161         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 162         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 163         base = G_000100_MC_FB_START(base) << 16;
 164         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 165         /* Some boards seem to be configured for 128MB of sideport memory,
 166          * but really only have 64MB.  Just skip the sideport and use
 167          * UMA memory.
 168          */
 169         if (rdev->mc.igp_sideport_enabled &&
 170             (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
 171                 base += 128 * 1024 * 1024;
 172                 rdev->mc.real_vram_size -= 128 * 1024 * 1024;
 173                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 174         }
 175
 176         /* Use K8 direct mapping for fast fb access. */
 177         rdev->fastfb_working = false;
 178         h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
 179         l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
 180         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
 181 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
 182         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
 183 #endif
 184         {
 185                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
 186                  * memory is present.
 187                  */
 188                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
 189                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
 190                                         (unsigned long long)rdev->mc.aper_base, k8_addr);
 191                         rdev->mc.aper_base = (resource_size_t)k8_addr;
 192                         rdev->fastfb_working = true;
 193                 }
 194         }
 195
 196         rs690_pm_info(rdev);
 197         radeon_vram_location(rdev, &rdev->mc, base);
 198         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 199         radeon_gtt_location(rdev, &rdev->mc);
 200         radeon_update_bandwidth_info(rdev);
 201 }
 202
 203 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 204                               struct drm_display_mode *mode1,
 205                               struct drm_display_mode *mode2)
 206 {
 207         u32 tmp;
 208
 209         /*
 210          * Line Buffer Setup
 211          * There is a single line buffer shared by both display controllers.
 212          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 213          * the display controllers.  The paritioning can either be done
 214          * manually or via one of four preset allocations specified in bits 1:0:
 215          *  0 - line buffer is divided in half and shared between crtc
 216          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 217          *  2 - D1 gets the whole buffer
 218          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 219          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 220          * allocation mode. In manual allocation mode, D1 always starts at 0,
 221          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 222          */
 223         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 224         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 225         /* auto */
 226         if (mode1 && mode2) {
 227                 if (mode1->hdisplay > mode2->hdisplay) {
 228                         if (mode1->hdisplay > 2560)
 229                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 230                         else
 231                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 232                 } else if (mode2->hdisplay > mode1->hdisplay) {
 233                         if (mode2->hdisplay > 2560)
 234                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 235                         else
 236                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 237                 } else
 238                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 239         } else if (mode1) {
 240                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 241         } else if (mode2) {
 242                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 243         }
 244         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 245 }
 246
 247 struct rs690_watermark {
 248         u32        lb_request_fifo_depth;
 249         fixed20_12 num_line_pair;
 250         fixed20_12 estimated_width;
 251         fixed20_12 worst_case_latency;
 252         fixed20_12 consumption_rate;
 253         fixed20_12 active_time;
 254         fixed20_12 dbpp;
 255         fixed20_12 priority_mark_max;
 256         fixed20_12 priority_mark;
 257         fixed20_12 sclk;
 258 };
 259
 260 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 261                                   struct radeon_crtc *crtc,
 262                                   struct rs690_watermark *wm)
 263 {
 264         struct drm_display_mode *mode = &crtc->base.mode;
 265         fixed20_12 a, b, c;
 266         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 267         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 268
 269         if (!crtc->base.enabled) {
 270                 /* FIXME: wouldn't it better to set priority mark to maximum */
 271                 wm->lb_request_fifo_depth = 4;
 272                 return;
 273         }
 274
 275         if (crtc->vsc.full > dfixed_const(2))
 276                 wm->num_line_pair.full = dfixed_const(2);
 277         else
 278                 wm->num_line_pair.full = dfixed_const(1);
 279
 280         b.full = dfixed_const(mode->crtc_hdisplay);
 281         c.full = dfixed_const(256);
 282         a.full = dfixed_div(b, c);
 283         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 284         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 285         if (a.full < dfixed_const(4)) {
 286                 wm->lb_request_fifo_depth = 4;
 287         } else {
 288                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 289         }
 290
 291         /* Determine consumption rate
 292          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 293          *  vtaps = number of vertical taps,
 294          *  vsc = vertical scaling ratio, defined as source/destination
 295          *  hsc = horizontal scaling ration, defined as source/destination
 296          */
 297         a.full = dfixed_const(mode->clock);
 298         b.full = dfixed_const(1000);
 299         a.full = dfixed_div(a, b);
 300         pclk.full = dfixed_div(b, a);
 301         if (crtc->rmx_type != RMX_OFF) {
 302                 b.full = dfixed_const(2);
 303                 if (crtc->vsc.full > b.full)
 304                         b.full = crtc->vsc.full;
 305                 b.full = dfixed_mul(b, crtc->hsc);
 306                 c.full = dfixed_const(2);
 307                 b.full = dfixed_div(b, c);
 308                 consumption_time.full = dfixed_div(pclk, b);
 309         } else {
 310                 consumption_time.full = pclk.full;
 311         }
 312         a.full = dfixed_const(1);
 313         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 314
 315
 316         /* Determine line time
 317          *  LineTime = total time for one line of displayhtotal
 318          *  LineTime = total number of horizontal pixels
 319          *  pclk = pixel clock period(ns)
 320          */
 321         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 322         line_time.full = dfixed_mul(a, pclk);
 323
 324         /* Determine active time
 325          *  ActiveTime = time of active region of display within one line,
 326          *  hactive = total number of horizontal active pixels
 327          *  htotal = total number of horizontal pixels
 328          */
 329         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 330         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 331         wm->active_time.full = dfixed_mul(line_time, b);
 332         wm->active_time.full = dfixed_div(wm->active_time, a);
 333
 334         /* Maximun bandwidth is the minimun bandwidth of all component */
 335         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 336         if (rdev->mc.igp_sideport_enabled) {
 337                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 338                         rdev->pm.sideport_bandwidth.full)
 339                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 340                 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
 341                 read_delay_latency.full = dfixed_div(read_delay_latency,
 342                         rdev->pm.igp_sideport_mclk);
 343         } else {
 344                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 345                         rdev->pm.k8_bandwidth.full)
 346                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 347                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 348                         rdev->pm.ht_bandwidth.full)
 349                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 350                 read_delay_latency.full = dfixed_const(5000);
 351         }
 352
 353         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 354         a.full = dfixed_const(16);
 355         rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
 356         a.full = dfixed_const(1000);
 357         rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
 358         /* Determine chunk time
 359          * ChunkTime = the time it takes the DCP to send one chunk of data
 360          * to the LB which consists of pipeline delay and inter chunk gap
 361          * sclk = system clock(ns)
 362          */
 363         a.full = dfixed_const(256 * 13);
 364         chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
 365         a.full = dfixed_const(10);
 366         chunk_time.full = dfixed_div(chunk_time, a);
 367
 368         /* Determine the worst case latency
 369          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 370          * WorstCaseLatency = worst case time from urgent to when the MC starts
 371          *                    to return data
 372          * READ_DELAY_IDLE_MAX = constant of 1us
 373          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 374          *             which consists of pipeline delay and inter chunk gap
 375          */
 376         if (dfixed_trunc(wm->num_line_pair) > 1) {
 377                 a.full = dfixed_const(3);
 378                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 379                 wm->worst_case_latency.full += read_delay_latency.full;
 380         } else {
 381                 a.full = dfixed_const(2);
 382                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 383                 wm->worst_case_latency.full += read_delay_latency.full;
 384         }
 385
 386         /* Determine the tolerable latency
 387          * TolerableLatency = Any given request has only 1 line time
 388          *                    for the data to be returned
 389          * LBRequestFifoDepth = Number of chunk requests the LB can
 390          *                      put into the request FIFO for a display
 391          *  LineTime = total time for one line of display
 392          *  ChunkTime = the time it takes the DCP to send one chunk
 393          *              of data to the LB which consists of
 394          *  pipeline delay and inter chunk gap
 395          */
 396         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
 397                 tolerable_latency.full = line_time.full;
 398         } else {
 399                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
 400                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 401                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
 402                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 403         }
 404         /* We assume worst case 32bits (4 bytes) */
 405         wm->dbpp.full = dfixed_const(4 * 8);
 406
 407         /* Determine the maximum priority mark
 408          *  width = viewport width in pixels
 409          */
 410         a.full = dfixed_const(16);
 411         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 412         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
 413         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 414
 415         /* Determine estimated width */
 416         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 417         estimated_width.full = dfixed_div(estimated_width, consumption_time);
 418         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 419                 wm->priority_mark.full = dfixed_const(10);
 420         } else {
 421                 a.full = dfixed_const(16);
 422                 wm->priority_mark.full = dfixed_div(estimated_width, a);
 423                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 424                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 425         }
 426 }
 427
 428 void rs690_bandwidth_update(struct radeon_device *rdev)
 429 {
 430         struct drm_display_mode *mode0 = NULL;
 431         struct drm_display_mode *mode1 = NULL;
 432         struct rs690_watermark wm0;
 433         struct rs690_watermark wm1;
 434         u32 tmp;
 435         u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 436         u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 437         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 438         fixed20_12 a, b;
 439
 440         radeon_update_display_priority(rdev);
 441
 442         if (rdev->mode_info.crtcs[0]->base.enabled)
 443                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 444         if (rdev->mode_info.crtcs[1]->base.enabled)
 445                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 446         /*
 447          * Set display0/1 priority up in the memory controller for
 448          * modes if the user specifies HIGH for displaypriority
 449          * option.
 450          */
 451         if ((rdev->disp_priority == 2) &&
 452             ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
 453                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 454                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 455                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 456                 if (mode0)
 457                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 458                 if (mode1)
 459                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 460                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 461         }
 462         rs690_line_buffer_adjust(rdev, mode0, mode1);
 463
 464         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 465                 WREG32(R_006C9C_DCP_CONTROL, 0);
 466         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 467                 WREG32(R_006C9C_DCP_CONTROL, 2);
 468
 469         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 470         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 471
 472         tmp = (wm0.lb_request_fifo_depth - 1);
 473         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 474         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 475
 476         if (mode0 && mode1) {
 477                 if (dfixed_trunc(wm0.dbpp) > 64)
 478                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 479                 else
 480                         a.full = wm0.num_line_pair.full;
 481                 if (dfixed_trunc(wm1.dbpp) > 64)
 482                         b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 483                 else
 484                         b.full = wm1.num_line_pair.full;
 485                 a.full += b.full;
 486                 fill_rate.full = dfixed_div(wm0.sclk, a);
 487                 if (wm0.consumption_rate.full > fill_rate.full) {
 488                         b.full = wm0.consumption_rate.full - fill_rate.full;
 489                         b.full = dfixed_mul(b, wm0.active_time);
 490                         a.full = dfixed_mul(wm0.worst_case_latency,
 491                                                 wm0.consumption_rate);
 492                         a.full = a.full + b.full;
 493                         b.full = dfixed_const(16 * 1000);
 494                         priority_mark02.full = dfixed_div(a, b);
 495                 } else {
 496                         a.full = dfixed_mul(wm0.worst_case_latency,
 497                                                 wm0.consumption_rate);
 498                         b.full = dfixed_const(16 * 1000);
 499                         priority_mark02.full = dfixed_div(a, b);
 500                 }
 501                 if (wm1.consumption_rate.full > fill_rate.full) {
 502                         b.full = wm1.consumption_rate.full - fill_rate.full;
 503                         b.full = dfixed_mul(b, wm1.active_time);
 504                         a.full = dfixed_mul(wm1.worst_case_latency,
 505                                                 wm1.consumption_rate);
 506                         a.full = a.full + b.full;
 507                         b.full = dfixed_const(16 * 1000);
 508                         priority_mark12.full = dfixed_div(a, b);
 509                 } else {
 510                         a.full = dfixed_mul(wm1.worst_case_latency,
 511                                                 wm1.consumption_rate);
 512                         b.full = dfixed_const(16 * 1000);
 513                         priority_mark12.full = dfixed_div(a, b);
 514                 }
 515                 if (wm0.priority_mark.full > priority_mark02.full)
 516                         priority_mark02.full = wm0.priority_mark.full;
 517                 if (dfixed_trunc(priority_mark02) < 0)
 518                         priority_mark02.full = 0;
 519                 if (wm0.priority_mark_max.full > priority_mark02.full)
 520                         priority_mark02.full = wm0.priority_mark_max.full;
 521                 if (wm1.priority_mark.full > priority_mark12.full)
 522                         priority_mark12.full = wm1.priority_mark.full;
 523                 if (dfixed_trunc(priority_mark12) < 0)
 524                         priority_mark12.full = 0;
 525                 if (wm1.priority_mark_max.full > priority_mark12.full)
 526                         priority_mark12.full = wm1.priority_mark_max.full;
 527                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 528                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 529                 if (rdev->disp_priority == 2) {
 530                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 531                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 532                 }
 533         } else if (mode0) {
 534                 if (dfixed_trunc(wm0.dbpp) > 64)
 535                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 536                 else
 537                         a.full = wm0.num_line_pair.full;
 538                 fill_rate.full = dfixed_div(wm0.sclk, a);
 539                 if (wm0.consumption_rate.full > fill_rate.full) {
 540                         b.full = wm0.consumption_rate.full - fill_rate.full;
 541                         b.full = dfixed_mul(b, wm0.active_time);
 542                         a.full = dfixed_mul(wm0.worst_case_latency,
 543                                                 wm0.consumption_rate);
 544                         a.full = a.full + b.full;
 545                         b.full = dfixed_const(16 * 1000);
 546                         priority_mark02.full = dfixed_div(a, b);
 547                 } else {
 548                         a.full = dfixed_mul(wm0.worst_case_latency,
 549                                                 wm0.consumption_rate);
 550                         b.full = dfixed_const(16 * 1000);
 551                         priority_mark02.full = dfixed_div(a, b);
 552                 }
 553                 if (wm0.priority_mark.full > priority_mark02.full)
 554                         priority_mark02.full = wm0.priority_mark.full;
 555                 if (dfixed_trunc(priority_mark02) < 0)
 556                         priority_mark02.full = 0;
 557                 if (wm0.priority_mark_max.full > priority_mark02.full)
 558                         priority_mark02.full = wm0.priority_mark_max.full;
 559                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 560                 if (rdev->disp_priority == 2)
 561                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 562         } else if (mode1) {
 563                 if (dfixed_trunc(wm1.dbpp) > 64)
 564                         a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 565                 else
 566                         a.full = wm1.num_line_pair.full;
 567                 fill_rate.full = dfixed_div(wm1.sclk, a);
 568                 if (wm1.consumption_rate.full > fill_rate.full) {
 569                         b.full = wm1.consumption_rate.full - fill_rate.full;
 570                         b.full = dfixed_mul(b, wm1.active_time);
 571                         a.full = dfixed_mul(wm1.worst_case_latency,
 572                                                 wm1.consumption_rate);
 573                         a.full = a.full + b.full;
 574                         b.full = dfixed_const(16 * 1000);
 575                         priority_mark12.full = dfixed_div(a, b);
 576                 } else {
 577                         a.full = dfixed_mul(wm1.worst_case_latency,
 578                                                 wm1.consumption_rate);
 579                         b.full = dfixed_const(16 * 1000);
 580                         priority_mark12.full = dfixed_div(a, b);
 581                 }
 582                 if (wm1.priority_mark.full > priority_mark12.full)
 583                         priority_mark12.full = wm1.priority_mark.full;
 584                 if (dfixed_trunc(priority_mark12) < 0)
 585                         priority_mark12.full = 0;
 586                 if (wm1.priority_mark_max.full > priority_mark12.full)
 587                         priority_mark12.full = wm1.priority_mark_max.full;
 588                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 589                 if (rdev->disp_priority == 2)
 590                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 591         }
 592
 593         WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 594         WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 595         WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 596         WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 597 }
 598
 599 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 600 {
 601         uint32_t r;
 602
 603         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 604         r = RREG32(R_00007C_MC_DATA);
 605         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 606         return r;
 607 }
 608
 609 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 610 {
 611         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 612                 S_000078_MC_IND_WR_EN(1));
 613         WREG32(R_00007C_MC_DATA, v);
 614         WREG32(R_000078_MC_INDEX, 0x7F);
 615 }
 616
 617 static void rs690_mc_program(struct radeon_device *rdev)
 618 {
 619         struct rv515_mc_save save;
 620
 621         /* Stops all mc clients */
 622         rv515_mc_stop(rdev, &save);
 623
 624         /* Wait for mc idle */
 625         if (rs690_mc_wait_for_idle(rdev))
 626                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 627         /* Program MC, should be a 32bits limited address space */
 628         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 629                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 630                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 631         WREG32(R_000134_HDP_FB_LOCATION,
 632                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 633
 634         rv515_mc_resume(rdev, &save);
 635 }
 636
 637 static int rs690_startup(struct radeon_device *rdev)
 638 {
 639         int r;
 640
 641         rs690_mc_program(rdev);
 642         /* Resume clock */
 643         rv515_clock_startup(rdev);
 644         /* Initialize GPU configuration (# pipes, ...) */
 645         rs690_gpu_init(rdev);
 646         /* Initialize GART (initialize after TTM so we can allocate
 647          * memory through TTM but finalize after TTM) */
 648         r = rs400_gart_enable(rdev);
 649         if (r)
 650                 return r;
 651
 652         /* allocate wb buffer */
 653         r = radeon_wb_init(rdev);
 654         if (r)
 655                 return r;
 656
 657         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 658         if (r) {
 659                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 660                 return r;
 661         }
 662
 663         /* Enable IRQ */
 664         if (!rdev->irq.installed) {
 665                 r = radeon_irq_kms_init(rdev);
 666                 if (r)
 667                         return r;
 668         }
 669
 670         rs600_irq_set(rdev);
 671         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 672         /* 1M ring buffer */
 673         r = r100_cp_init(rdev, 1024 * 1024);
 674         if (r) {
 675                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 676                 return r;
 677         }
 678
 679         r = radeon_ib_pool_init(rdev);
 680         if (r) {
 681                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 682                 return r;
 683         }
 684
 685         r = r600_audio_init(rdev);
 686         if (r) {
 687                 dev_err(rdev->dev, "failed initializing audio\n");
 688                 return r;
 689         }
 690
 691         return 0;
 692 }
 693
 694 int rs690_resume(struct radeon_device *rdev)
 695 {
 696         int r;
 697
 698         /* Make sur GART are not working */
 699         rs400_gart_disable(rdev);
 700         /* Resume clock before doing reset */
 701         rv515_clock_startup(rdev);
 702         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 703         if (radeon_asic_reset(rdev)) {
 704                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 705                         RREG32(R_000E40_RBBM_STATUS),
 706                         RREG32(R_0007C0_CP_STAT));
 707         }
 708         /* post */
 709         atom_asic_init(rdev->mode_info.atom_context);
 710         /* Resume clock after posting */
 711         rv515_clock_startup(rdev);
 712         /* Initialize surface registers */
 713         radeon_surface_init(rdev);
 714
 715         rdev->accel_working = true;
 716         r = rs690_startup(rdev);
 717         if (r) {
 718                 rdev->accel_working = false;
 719         }
 720         return r;
 721 }
 722
 723 int rs690_suspend(struct radeon_device *rdev)
 724 {
 725         r600_audio_fini(rdev);
 726         r100_cp_disable(rdev);
 727         radeon_wb_disable(rdev);
 728         rs600_irq_disable(rdev);
 729         rs400_gart_disable(rdev);
 730         return 0;
 731 }
 732
 733 void rs690_fini(struct radeon_device *rdev)
 734 {
 735         r600_audio_fini(rdev);
 736         r100_cp_fini(rdev);
 737         radeon_wb_fini(rdev);
 738         radeon_ib_pool_fini(rdev);
 739         radeon_gem_fini(rdev);
 740         rs400_gart_fini(rdev);
 741         radeon_irq_kms_fini(rdev);
 742         radeon_fence_driver_fini(rdev);
 743         radeon_bo_fini(rdev);
 744         radeon_atombios_fini(rdev);
 745         kfree(rdev->bios);
 746         rdev->bios = NULL;
 747 }
 748
 749 int rs690_init(struct radeon_device *rdev)
 750 {
 751         int r;
 752
 753         /* Disable VGA */
 754         rv515_vga_render_disable(rdev);
 755         /* Initialize scratch registers */
 756         radeon_scratch_init(rdev);
 757         /* Initialize surface registers */
 758         radeon_surface_init(rdev);
 759         /* restore some register to sane defaults */
 760         r100_restore_sanity(rdev);
 761         /* TODO: disable VGA need to use VGA request */
 762         /* BIOS*/
 763         if (!radeon_get_bios(rdev)) {
 764                 if (ASIC_IS_AVIVO(rdev))
 765                         return -EINVAL;
 766         }
 767         if (rdev->is_atom_bios) {
 768                 r = radeon_atombios_init(rdev);
 769                 if (r)
 770                         return r;
 771         } else {
 772                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 773                 return -EINVAL;
 774         }
 775         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 776         if (radeon_asic_reset(rdev)) {
 777                 dev_warn(rdev->dev,
 778                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 779                         RREG32(R_000E40_RBBM_STATUS),
 780                         RREG32(R_0007C0_CP_STAT));
 781         }
 782         /* check if cards are posted or not */
 783         if (radeon_boot_test_post_card(rdev) == false)
 784                 return -EINVAL;
 785
 786         /* Initialize clocks */
 787         radeon_get_clock_info(rdev->ddev);
 788         /* initialize memory controller */
 789         rs690_mc_init(rdev);
 790         rv515_debugfs(rdev);
 791         /* Fence driver */
 792         r = radeon_fence_driver_init(rdev);
 793         if (r)
 794                 return r;
 795         /* Memory manager */
 796         r = radeon_bo_init(rdev);
 797         if (r)
 798                 return r;
 799         r = rs400_gart_init(rdev);
 800         if (r)
 801                 return r;
 802         rs600_set_safe_registers(rdev);
 803
 804         rdev->accel_working = true;
 805         r = rs690_startup(rdev);
 806         if (r) {
 807                 /* Somethings want wront with the accel init stop accel */
 808                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 809                 r100_cp_fini(rdev);
 810                 radeon_wb_fini(rdev);
 811                 radeon_ib_pool_fini(rdev);
 812                 rs400_gart_fini(rdev);
 813                 radeon_irq_kms_fini(rdev);
 814                 rdev->accel_working = false;
 815         }
 816         return 0;
 817 }