drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129         if (rdev->family >= CHIP_R600) {
 130                 rdev->pciep_rreg = &r600_pciep_rreg;
 131                 rdev->pciep_wreg = &r600_pciep_wreg;
 132         }
 133 }
 134
 135
 136 /* helper to disable agp */
 137 /**
 138  * radeon_agp_disable - AGP disable helper function
 139  *
 140  * @rdev: radeon device pointer
 141  *
 142  * Removes AGP flags and changes the gart callbacks on AGP
 143  * cards when using the internal gart rather than AGP (all asics).
 144  */
 145 void radeon_agp_disable(struct radeon_device *rdev)
 146 {
 147         rdev->flags &= ~RADEON_IS_AGP;
 148         if (rdev->family >= CHIP_R600) {
 149                 DRM_INFO("Forcing AGP to PCIE mode\n");
 150                 rdev->flags |= RADEON_IS_PCIE;
 151         } else if (rdev->family >= CHIP_RV515 ||
 152                         rdev->family == CHIP_RV380 ||
 153                         rdev->family == CHIP_RV410 ||
 154                         rdev->family == CHIP_R423) {
 155                 DRM_INFO("Forcing AGP to PCIE mode\n");
 156                 rdev->flags |= RADEON_IS_PCIE;
 157                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 158                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 159         } else {
 160                 DRM_INFO("Forcing AGP to PCI mode\n");
 161                 rdev->flags |= RADEON_IS_PCI;
 162                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 163                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 164         }
 165         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 166 }
 167
 168 /*
 169  * ASIC
 170  */
 171 static struct radeon_asic r100_asic = {
 172         .init = &r100_init,
 173         .fini = &r100_fini,
 174         .suspend = &r100_suspend,
 175         .resume = &r100_resume,
 176         .vga_set_state = &r100_vga_set_state,
 177         .asic_reset = &r100_asic_reset,
 178         .ioctl_wait_idle = NULL,
 179         .gui_idle = &r100_gui_idle,
 180         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 181         .gart = {
 182                 .tlb_flush = &r100_pci_gart_tlb_flush,
 183                 .set_page = &r100_pci_gart_set_page,
 184         },
 185         .ring = {
 186                 [RADEON_RING_TYPE_GFX_INDEX] = {
 187                         .ib_execute = &r100_ring_ib_execute,
 188                         .emit_fence = &r100_fence_ring_emit,
 189                         .emit_semaphore = &r100_semaphore_ring_emit,
 190                         .cs_parse = &r100_cs_parse,
 191                         .ring_start = &r100_ring_start,
 192                         .ring_test = &r100_ring_test,
 193                         .ib_test = &r100_ib_test,
 194                         .is_lockup = &r100_gpu_is_lockup,
 195                 }
 196         },
 197         .irq = {
 198                 .set = &r100_irq_set,
 199                 .process = &r100_irq_process,
 200         },
 201         .display = {
 202                 .bandwidth_update = &r100_bandwidth_update,
 203                 .get_vblank_counter = &r100_get_vblank_counter,
 204                 .wait_for_vblank = &r100_wait_for_vblank,
 205                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 206                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 207         },
 208         .copy = {
 209                 .blit = &r100_copy_blit,
 210                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 211                 .dma = NULL,
 212                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 213                 .copy = &r100_copy_blit,
 214                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 215         },
 216         .surface = {
 217                 .set_reg = r100_set_surface_reg,
 218                 .clear_reg = r100_clear_surface_reg,
 219         },
 220         .hpd = {
 221                 .init = &r100_hpd_init,
 222                 .fini = &r100_hpd_fini,
 223                 .sense = &r100_hpd_sense,
 224                 .set_polarity = &r100_hpd_set_polarity,
 225         },
 226         .pm = {
 227                 .misc = &r100_pm_misc,
 228                 .prepare = &r100_pm_prepare,
 229                 .finish = &r100_pm_finish,
 230                 .init_profile = &r100_pm_init_profile,
 231                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 232                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 233                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 234                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 235                 .set_memory_clock = NULL,
 236                 .get_pcie_lanes = NULL,
 237                 .set_pcie_lanes = NULL,
 238                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 239         },
 240         .pflip = {
 241                 .pre_page_flip = &r100_pre_page_flip,
 242                 .page_flip = &r100_page_flip,
 243                 .post_page_flip = &r100_post_page_flip,
 244         },
 245 };
 246
 247 static struct radeon_asic r200_asic = {
 248         .init = &r100_init,
 249         .fini = &r100_fini,
 250         .suspend = &r100_suspend,
 251         .resume = &r100_resume,
 252         .vga_set_state = &r100_vga_set_state,
 253         .asic_reset = &r100_asic_reset,
 254         .ioctl_wait_idle = NULL,
 255         .gui_idle = &r100_gui_idle,
 256         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 257         .gart = {
 258                 .tlb_flush = &r100_pci_gart_tlb_flush,
 259                 .set_page = &r100_pci_gart_set_page,
 260         },
 261         .ring = {
 262                 [RADEON_RING_TYPE_GFX_INDEX] = {
 263                         .ib_execute = &r100_ring_ib_execute,
 264                         .emit_fence = &r100_fence_ring_emit,
 265                         .emit_semaphore = &r100_semaphore_ring_emit,
 266                         .cs_parse = &r100_cs_parse,
 267                         .ring_start = &r100_ring_start,
 268                         .ring_test = &r100_ring_test,
 269                         .ib_test = &r100_ib_test,
 270                         .is_lockup = &r100_gpu_is_lockup,
 271                 }
 272         },
 273         .irq = {
 274                 .set = &r100_irq_set,
 275                 .process = &r100_irq_process,
 276         },
 277         .display = {
 278                 .bandwidth_update = &r100_bandwidth_update,
 279                 .get_vblank_counter = &r100_get_vblank_counter,
 280                 .wait_for_vblank = &r100_wait_for_vblank,
 281                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 282                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 283         },
 284         .copy = {
 285                 .blit = &r100_copy_blit,
 286                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 287                 .dma = &r200_copy_dma,
 288                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 289                 .copy = &r100_copy_blit,
 290                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 291         },
 292         .surface = {
 293                 .set_reg = r100_set_surface_reg,
 294                 .clear_reg = r100_clear_surface_reg,
 295         },
 296         .hpd = {
 297                 .init = &r100_hpd_init,
 298                 .fini = &r100_hpd_fini,
 299                 .sense = &r100_hpd_sense,
 300                 .set_polarity = &r100_hpd_set_polarity,
 301         },
 302         .pm = {
 303                 .misc = &r100_pm_misc,
 304                 .prepare = &r100_pm_prepare,
 305                 .finish = &r100_pm_finish,
 306                 .init_profile = &r100_pm_init_profile,
 307                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 308                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 309                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 310                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 311                 .set_memory_clock = NULL,
 312                 .get_pcie_lanes = NULL,
 313                 .set_pcie_lanes = NULL,
 314                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 315         },
 316         .pflip = {
 317                 .pre_page_flip = &r100_pre_page_flip,
 318                 .page_flip = &r100_page_flip,
 319                 .post_page_flip = &r100_post_page_flip,
 320         },
 321 };
 322
 323 static struct radeon_asic r300_asic = {
 324         .init = &r300_init,
 325         .fini = &r300_fini,
 326         .suspend = &r300_suspend,
 327         .resume = &r300_resume,
 328         .vga_set_state = &r100_vga_set_state,
 329         .asic_reset = &r300_asic_reset,
 330         .ioctl_wait_idle = NULL,
 331         .gui_idle = &r100_gui_idle,
 332         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 333         .gart = {
 334                 .tlb_flush = &r100_pci_gart_tlb_flush,
 335                 .set_page = &r100_pci_gart_set_page,
 336         },
 337         .ring = {
 338                 [RADEON_RING_TYPE_GFX_INDEX] = {
 339                         .ib_execute = &r100_ring_ib_execute,
 340                         .emit_fence = &r300_fence_ring_emit,
 341                         .emit_semaphore = &r100_semaphore_ring_emit,
 342                         .cs_parse = &r300_cs_parse,
 343                         .ring_start = &r300_ring_start,
 344                         .ring_test = &r100_ring_test,
 345                         .ib_test = &r100_ib_test,
 346                         .is_lockup = &r100_gpu_is_lockup,
 347                 }
 348         },
 349         .irq = {
 350                 .set = &r100_irq_set,
 351                 .process = &r100_irq_process,
 352         },
 353         .display = {
 354                 .bandwidth_update = &r100_bandwidth_update,
 355                 .get_vblank_counter = &r100_get_vblank_counter,
 356                 .wait_for_vblank = &r100_wait_for_vblank,
 357                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 358                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 359         },
 360         .copy = {
 361                 .blit = &r100_copy_blit,
 362                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 363                 .dma = &r200_copy_dma,
 364                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 365                 .copy = &r100_copy_blit,
 366                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 367         },
 368         .surface = {
 369                 .set_reg = r100_set_surface_reg,
 370                 .clear_reg = r100_clear_surface_reg,
 371         },
 372         .hpd = {
 373                 .init = &r100_hpd_init,
 374                 .fini = &r100_hpd_fini,
 375                 .sense = &r100_hpd_sense,
 376                 .set_polarity = &r100_hpd_set_polarity,
 377         },
 378         .pm = {
 379                 .misc = &r100_pm_misc,
 380                 .prepare = &r100_pm_prepare,
 381                 .finish = &r100_pm_finish,
 382                 .init_profile = &r100_pm_init_profile,
 383                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 384                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 385                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 386                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 387                 .set_memory_clock = NULL,
 388                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 389                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 390                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 391         },
 392         .pflip = {
 393                 .pre_page_flip = &r100_pre_page_flip,
 394                 .page_flip = &r100_page_flip,
 395                 .post_page_flip = &r100_post_page_flip,
 396         },
 397 };
 398
 399 static struct radeon_asic r300_asic_pcie = {
 400         .init = &r300_init,
 401         .fini = &r300_fini,
 402         .suspend = &r300_suspend,
 403         .resume = &r300_resume,
 404         .vga_set_state = &r100_vga_set_state,
 405         .asic_reset = &r300_asic_reset,
 406         .ioctl_wait_idle = NULL,
 407         .gui_idle = &r100_gui_idle,
 408         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 409         .gart = {
 410                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 411                 .set_page = &rv370_pcie_gart_set_page,
 412         },
 413         .ring = {
 414                 [RADEON_RING_TYPE_GFX_INDEX] = {
 415                         .ib_execute = &r100_ring_ib_execute,
 416                         .emit_fence = &r300_fence_ring_emit,
 417                         .emit_semaphore = &r100_semaphore_ring_emit,
 418                         .cs_parse = &r300_cs_parse,
 419                         .ring_start = &r300_ring_start,
 420                         .ring_test = &r100_ring_test,
 421                         .ib_test = &r100_ib_test,
 422                         .is_lockup = &r100_gpu_is_lockup,
 423                 }
 424         },
 425         .irq = {
 426                 .set = &r100_irq_set,
 427                 .process = &r100_irq_process,
 428         },
 429         .display = {
 430                 .bandwidth_update = &r100_bandwidth_update,
 431                 .get_vblank_counter = &r100_get_vblank_counter,
 432                 .wait_for_vblank = &r100_wait_for_vblank,
 433                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 434                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 435         },
 436         .copy = {
 437                 .blit = &r100_copy_blit,
 438                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 439                 .dma = &r200_copy_dma,
 440                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 441                 .copy = &r100_copy_blit,
 442                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 443         },
 444         .surface = {
 445                 .set_reg = r100_set_surface_reg,
 446                 .clear_reg = r100_clear_surface_reg,
 447         },
 448         .hpd = {
 449                 .init = &r100_hpd_init,
 450                 .fini = &r100_hpd_fini,
 451                 .sense = &r100_hpd_sense,
 452                 .set_polarity = &r100_hpd_set_polarity,
 453         },
 454         .pm = {
 455                 .misc = &r100_pm_misc,
 456                 .prepare = &r100_pm_prepare,
 457                 .finish = &r100_pm_finish,
 458                 .init_profile = &r100_pm_init_profile,
 459                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 460                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 461                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 462                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 463                 .set_memory_clock = NULL,
 464                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 465                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 466                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 467         },
 468         .pflip = {
 469                 .pre_page_flip = &r100_pre_page_flip,
 470                 .page_flip = &r100_page_flip,
 471                 .post_page_flip = &r100_post_page_flip,
 472         },
 473 };
 474
 475 static struct radeon_asic r420_asic = {
 476         .init = &r420_init,
 477         .fini = &r420_fini,
 478         .suspend = &r420_suspend,
 479         .resume = &r420_resume,
 480         .vga_set_state = &r100_vga_set_state,
 481         .asic_reset = &r300_asic_reset,
 482         .ioctl_wait_idle = NULL,
 483         .gui_idle = &r100_gui_idle,
 484         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 485         .gart = {
 486                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 487                 .set_page = &rv370_pcie_gart_set_page,
 488         },
 489         .ring = {
 490                 [RADEON_RING_TYPE_GFX_INDEX] = {
 491                         .ib_execute = &r100_ring_ib_execute,
 492                         .emit_fence = &r300_fence_ring_emit,
 493                         .emit_semaphore = &r100_semaphore_ring_emit,
 494                         .cs_parse = &r300_cs_parse,
 495                         .ring_start = &r300_ring_start,
 496                         .ring_test = &r100_ring_test,
 497                         .ib_test = &r100_ib_test,
 498                         .is_lockup = &r100_gpu_is_lockup,
 499                 }
 500         },
 501         .irq = {
 502                 .set = &r100_irq_set,
 503                 .process = &r100_irq_process,
 504         },
 505         .display = {
 506                 .bandwidth_update = &r100_bandwidth_update,
 507                 .get_vblank_counter = &r100_get_vblank_counter,
 508                 .wait_for_vblank = &r100_wait_for_vblank,
 509                 .set_backlight_level = &atombios_set_backlight_level,
 510                 .get_backlight_level = &atombios_get_backlight_level,
 511         },
 512         .copy = {
 513                 .blit = &r100_copy_blit,
 514                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 515                 .dma = &r200_copy_dma,
 516                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 517                 .copy = &r100_copy_blit,
 518                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 519         },
 520         .surface = {
 521                 .set_reg = r100_set_surface_reg,
 522                 .clear_reg = r100_clear_surface_reg,
 523         },
 524         .hpd = {
 525                 .init = &r100_hpd_init,
 526                 .fini = &r100_hpd_fini,
 527                 .sense = &r100_hpd_sense,
 528                 .set_polarity = &r100_hpd_set_polarity,
 529         },
 530         .pm = {
 531                 .misc = &r100_pm_misc,
 532                 .prepare = &r100_pm_prepare,
 533                 .finish = &r100_pm_finish,
 534                 .init_profile = &r420_pm_init_profile,
 535                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 536                 .get_engine_clock = &radeon_atom_get_engine_clock,
 537                 .set_engine_clock = &radeon_atom_set_engine_clock,
 538                 .get_memory_clock = &radeon_atom_get_memory_clock,
 539                 .set_memory_clock = &radeon_atom_set_memory_clock,
 540                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 541                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 542                 .set_clock_gating = &radeon_atom_set_clock_gating,
 543         },
 544         .pflip = {
 545                 .pre_page_flip = &r100_pre_page_flip,
 546                 .page_flip = &r100_page_flip,
 547                 .post_page_flip = &r100_post_page_flip,
 548         },
 549 };
 550
 551 static struct radeon_asic rs400_asic = {
 552         .init = &rs400_init,
 553         .fini = &rs400_fini,
 554         .suspend = &rs400_suspend,
 555         .resume = &rs400_resume,
 556         .vga_set_state = &r100_vga_set_state,
 557         .asic_reset = &r300_asic_reset,
 558         .ioctl_wait_idle = NULL,
 559         .gui_idle = &r100_gui_idle,
 560         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 561         .gart = {
 562                 .tlb_flush = &rs400_gart_tlb_flush,
 563                 .set_page = &rs400_gart_set_page,
 564         },
 565         .ring = {
 566                 [RADEON_RING_TYPE_GFX_INDEX] = {
 567                         .ib_execute = &r100_ring_ib_execute,
 568                         .emit_fence = &r300_fence_ring_emit,
 569                         .emit_semaphore = &r100_semaphore_ring_emit,
 570                         .cs_parse = &r300_cs_parse,
 571                         .ring_start = &r300_ring_start,
 572                         .ring_test = &r100_ring_test,
 573                         .ib_test = &r100_ib_test,
 574                         .is_lockup = &r100_gpu_is_lockup,
 575                 }
 576         },
 577         .irq = {
 578                 .set = &r100_irq_set,
 579                 .process = &r100_irq_process,
 580         },
 581         .display = {
 582                 .bandwidth_update = &r100_bandwidth_update,
 583                 .get_vblank_counter = &r100_get_vblank_counter,
 584                 .wait_for_vblank = &r100_wait_for_vblank,
 585                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 586                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 587         },
 588         .copy = {
 589                 .blit = &r100_copy_blit,
 590                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 591                 .dma = &r200_copy_dma,
 592                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 593                 .copy = &r100_copy_blit,
 594                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 595         },
 596         .surface = {
 597                 .set_reg = r100_set_surface_reg,
 598                 .clear_reg = r100_clear_surface_reg,
 599         },
 600         .hpd = {
 601                 .init = &r100_hpd_init,
 602                 .fini = &r100_hpd_fini,
 603                 .sense = &r100_hpd_sense,
 604                 .set_polarity = &r100_hpd_set_polarity,
 605         },
 606         .pm = {
 607                 .misc = &r100_pm_misc,
 608                 .prepare = &r100_pm_prepare,
 609                 .finish = &r100_pm_finish,
 610                 .init_profile = &r100_pm_init_profile,
 611                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 612                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 613                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 614                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 615                 .set_memory_clock = NULL,
 616                 .get_pcie_lanes = NULL,
 617                 .set_pcie_lanes = NULL,
 618                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 619         },
 620         .pflip = {
 621                 .pre_page_flip = &r100_pre_page_flip,
 622                 .page_flip = &r100_page_flip,
 623                 .post_page_flip = &r100_post_page_flip,
 624         },
 625 };
 626
 627 static struct radeon_asic rs600_asic = {
 628         .init = &rs600_init,
 629         .fini = &rs600_fini,
 630         .suspend = &rs600_suspend,
 631         .resume = &rs600_resume,
 632         .vga_set_state = &r100_vga_set_state,
 633         .asic_reset = &rs600_asic_reset,
 634         .ioctl_wait_idle = NULL,
 635         .gui_idle = &r100_gui_idle,
 636         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 637         .gart = {
 638                 .tlb_flush = &rs600_gart_tlb_flush,
 639                 .set_page = &rs600_gart_set_page,
 640         },
 641         .ring = {
 642                 [RADEON_RING_TYPE_GFX_INDEX] = {
 643                         .ib_execute = &r100_ring_ib_execute,
 644                         .emit_fence = &r300_fence_ring_emit,
 645                         .emit_semaphore = &r100_semaphore_ring_emit,
 646                         .cs_parse = &r300_cs_parse,
 647                         .ring_start = &r300_ring_start,
 648                         .ring_test = &r100_ring_test,
 649                         .ib_test = &r100_ib_test,
 650                         .is_lockup = &r100_gpu_is_lockup,
 651                 }
 652         },
 653         .irq = {
 654                 .set = &rs600_irq_set,
 655                 .process = &rs600_irq_process,
 656         },
 657         .display = {
 658                 .bandwidth_update = &rs600_bandwidth_update,
 659                 .get_vblank_counter = &rs600_get_vblank_counter,
 660                 .wait_for_vblank = &avivo_wait_for_vblank,
 661                 .set_backlight_level = &atombios_set_backlight_level,
 662                 .get_backlight_level = &atombios_get_backlight_level,
 663                 .hdmi_enable = &r600_hdmi_enable,
 664                 .hdmi_setmode = &r600_hdmi_setmode,
 665         },
 666         .copy = {
 667                 .blit = &r100_copy_blit,
 668                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 669                 .dma = &r200_copy_dma,
 670                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 671                 .copy = &r100_copy_blit,
 672                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 673         },
 674         .surface = {
 675                 .set_reg = r100_set_surface_reg,
 676                 .clear_reg = r100_clear_surface_reg,
 677         },
 678         .hpd = {
 679                 .init = &rs600_hpd_init,
 680                 .fini = &rs600_hpd_fini,
 681                 .sense = &rs600_hpd_sense,
 682                 .set_polarity = &rs600_hpd_set_polarity,
 683         },
 684         .pm = {
 685                 .misc = &rs600_pm_misc,
 686                 .prepare = &rs600_pm_prepare,
 687                 .finish = &rs600_pm_finish,
 688                 .init_profile = &r420_pm_init_profile,
 689                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 690                 .get_engine_clock = &radeon_atom_get_engine_clock,
 691                 .set_engine_clock = &radeon_atom_set_engine_clock,
 692                 .get_memory_clock = &radeon_atom_get_memory_clock,
 693                 .set_memory_clock = &radeon_atom_set_memory_clock,
 694                 .get_pcie_lanes = NULL,
 695                 .set_pcie_lanes = NULL,
 696                 .set_clock_gating = &radeon_atom_set_clock_gating,
 697         },
 698         .pflip = {
 699                 .pre_page_flip = &rs600_pre_page_flip,
 700                 .page_flip = &rs600_page_flip,
 701                 .post_page_flip = &rs600_post_page_flip,
 702         },
 703 };
 704
 705 static struct radeon_asic rs690_asic = {
 706         .init = &rs690_init,
 707         .fini = &rs690_fini,
 708         .suspend = &rs690_suspend,
 709         .resume = &rs690_resume,
 710         .vga_set_state = &r100_vga_set_state,
 711         .asic_reset = &rs600_asic_reset,
 712         .ioctl_wait_idle = NULL,
 713         .gui_idle = &r100_gui_idle,
 714         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 715         .gart = {
 716                 .tlb_flush = &rs400_gart_tlb_flush,
 717                 .set_page = &rs400_gart_set_page,
 718         },
 719         .ring = {
 720                 [RADEON_RING_TYPE_GFX_INDEX] = {
 721                         .ib_execute = &r100_ring_ib_execute,
 722                         .emit_fence = &r300_fence_ring_emit,
 723                         .emit_semaphore = &r100_semaphore_ring_emit,
 724                         .cs_parse = &r300_cs_parse,
 725                         .ring_start = &r300_ring_start,
 726                         .ring_test = &r100_ring_test,
 727                         .ib_test = &r100_ib_test,
 728                         .is_lockup = &r100_gpu_is_lockup,
 729                 }
 730         },
 731         .irq = {
 732                 .set = &rs600_irq_set,
 733                 .process = &rs600_irq_process,
 734         },
 735         .display = {
 736                 .get_vblank_counter = &rs600_get_vblank_counter,
 737                 .bandwidth_update = &rs690_bandwidth_update,
 738                 .wait_for_vblank = &avivo_wait_for_vblank,
 739                 .set_backlight_level = &atombios_set_backlight_level,
 740                 .get_backlight_level = &atombios_get_backlight_level,
 741                 .hdmi_enable = &r600_hdmi_enable,
 742                 .hdmi_setmode = &r600_hdmi_setmode,
 743         },
 744         .copy = {
 745                 .blit = &r100_copy_blit,
 746                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 747                 .dma = &r200_copy_dma,
 748                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 749                 .copy = &r200_copy_dma,
 750                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 751         },
 752         .surface = {
 753                 .set_reg = r100_set_surface_reg,
 754                 .clear_reg = r100_clear_surface_reg,
 755         },
 756         .hpd = {
 757                 .init = &rs600_hpd_init,
 758                 .fini = &rs600_hpd_fini,
 759                 .sense = &rs600_hpd_sense,
 760                 .set_polarity = &rs600_hpd_set_polarity,
 761         },
 762         .pm = {
 763                 .misc = &rs600_pm_misc,
 764                 .prepare = &rs600_pm_prepare,
 765                 .finish = &rs600_pm_finish,
 766                 .init_profile = &r420_pm_init_profile,
 767                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 768                 .get_engine_clock = &radeon_atom_get_engine_clock,
 769                 .set_engine_clock = &radeon_atom_set_engine_clock,
 770                 .get_memory_clock = &radeon_atom_get_memory_clock,
 771                 .set_memory_clock = &radeon_atom_set_memory_clock,
 772                 .get_pcie_lanes = NULL,
 773                 .set_pcie_lanes = NULL,
 774                 .set_clock_gating = &radeon_atom_set_clock_gating,
 775         },
 776         .pflip = {
 777                 .pre_page_flip = &rs600_pre_page_flip,
 778                 .page_flip = &rs600_page_flip,
 779                 .post_page_flip = &rs600_post_page_flip,
 780         },
 781 };
 782
 783 static struct radeon_asic rv515_asic = {
 784         .init = &rv515_init,
 785         .fini = &rv515_fini,
 786         .suspend = &rv515_suspend,
 787         .resume = &rv515_resume,
 788         .vga_set_state = &r100_vga_set_state,
 789         .asic_reset = &rs600_asic_reset,
 790         .ioctl_wait_idle = NULL,
 791         .gui_idle = &r100_gui_idle,
 792         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 793         .gart = {
 794                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 795                 .set_page = &rv370_pcie_gart_set_page,
 796         },
 797         .ring = {
 798                 [RADEON_RING_TYPE_GFX_INDEX] = {
 799                         .ib_execute = &r100_ring_ib_execute,
 800                         .emit_fence = &r300_fence_ring_emit,
 801                         .emit_semaphore = &r100_semaphore_ring_emit,
 802                         .cs_parse = &r300_cs_parse,
 803                         .ring_start = &rv515_ring_start,
 804                         .ring_test = &r100_ring_test,
 805                         .ib_test = &r100_ib_test,
 806                         .is_lockup = &r100_gpu_is_lockup,
 807                 }
 808         },
 809         .irq = {
 810                 .set = &rs600_irq_set,
 811                 .process = &rs600_irq_process,
 812         },
 813         .display = {
 814                 .get_vblank_counter = &rs600_get_vblank_counter,
 815                 .bandwidth_update = &rv515_bandwidth_update,
 816                 .wait_for_vblank = &avivo_wait_for_vblank,
 817                 .set_backlight_level = &atombios_set_backlight_level,
 818                 .get_backlight_level = &atombios_get_backlight_level,
 819         },
 820         .copy = {
 821                 .blit = &r100_copy_blit,
 822                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 823                 .dma = &r200_copy_dma,
 824                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 825                 .copy = &r100_copy_blit,
 826                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 827         },
 828         .surface = {
 829                 .set_reg = r100_set_surface_reg,
 830                 .clear_reg = r100_clear_surface_reg,
 831         },
 832         .hpd = {
 833                 .init = &rs600_hpd_init,
 834                 .fini = &rs600_hpd_fini,
 835                 .sense = &rs600_hpd_sense,
 836                 .set_polarity = &rs600_hpd_set_polarity,
 837         },
 838         .pm = {
 839                 .misc = &rs600_pm_misc,
 840                 .prepare = &rs600_pm_prepare,
 841                 .finish = &rs600_pm_finish,
 842                 .init_profile = &r420_pm_init_profile,
 843                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 844                 .get_engine_clock = &radeon_atom_get_engine_clock,
 845                 .set_engine_clock = &radeon_atom_set_engine_clock,
 846                 .get_memory_clock = &radeon_atom_get_memory_clock,
 847                 .set_memory_clock = &radeon_atom_set_memory_clock,
 848                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 849                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 850                 .set_clock_gating = &radeon_atom_set_clock_gating,
 851         },
 852         .pflip = {
 853                 .pre_page_flip = &rs600_pre_page_flip,
 854                 .page_flip = &rs600_page_flip,
 855                 .post_page_flip = &rs600_post_page_flip,
 856         },
 857 };
 858
 859 static struct radeon_asic r520_asic = {
 860         .init = &r520_init,
 861         .fini = &rv515_fini,
 862         .suspend = &rv515_suspend,
 863         .resume = &r520_resume,
 864         .vga_set_state = &r100_vga_set_state,
 865         .asic_reset = &rs600_asic_reset,
 866         .ioctl_wait_idle = NULL,
 867         .gui_idle = &r100_gui_idle,
 868         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 869         .gart = {
 870                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 871                 .set_page = &rv370_pcie_gart_set_page,
 872         },
 873         .ring = {
 874                 [RADEON_RING_TYPE_GFX_INDEX] = {
 875                         .ib_execute = &r100_ring_ib_execute,
 876                         .emit_fence = &r300_fence_ring_emit,
 877                         .emit_semaphore = &r100_semaphore_ring_emit,
 878                         .cs_parse = &r300_cs_parse,
 879                         .ring_start = &rv515_ring_start,
 880                         .ring_test = &r100_ring_test,
 881                         .ib_test = &r100_ib_test,
 882                         .is_lockup = &r100_gpu_is_lockup,
 883                 }
 884         },
 885         .irq = {
 886                 .set = &rs600_irq_set,
 887                 .process = &rs600_irq_process,
 888         },
 889         .display = {
 890                 .bandwidth_update = &rv515_bandwidth_update,
 891                 .get_vblank_counter = &rs600_get_vblank_counter,
 892                 .wait_for_vblank = &avivo_wait_for_vblank,
 893                 .set_backlight_level = &atombios_set_backlight_level,
 894                 .get_backlight_level = &atombios_get_backlight_level,
 895         },
 896         .copy = {
 897                 .blit = &r100_copy_blit,
 898                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 899                 .dma = &r200_copy_dma,
 900                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 901                 .copy = &r100_copy_blit,
 902                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 903         },
 904         .surface = {
 905                 .set_reg = r100_set_surface_reg,
 906                 .clear_reg = r100_clear_surface_reg,
 907         },
 908         .hpd = {
 909                 .init = &rs600_hpd_init,
 910                 .fini = &rs600_hpd_fini,
 911                 .sense = &rs600_hpd_sense,
 912                 .set_polarity = &rs600_hpd_set_polarity,
 913         },
 914         .pm = {
 915                 .misc = &rs600_pm_misc,
 916                 .prepare = &rs600_pm_prepare,
 917                 .finish = &rs600_pm_finish,
 918                 .init_profile = &r420_pm_init_profile,
 919                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 920                 .get_engine_clock = &radeon_atom_get_engine_clock,
 921                 .set_engine_clock = &radeon_atom_set_engine_clock,
 922                 .get_memory_clock = &radeon_atom_get_memory_clock,
 923                 .set_memory_clock = &radeon_atom_set_memory_clock,
 924                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 925                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 926                 .set_clock_gating = &radeon_atom_set_clock_gating,
 927         },
 928         .pflip = {
 929                 .pre_page_flip = &rs600_pre_page_flip,
 930                 .page_flip = &rs600_page_flip,
 931                 .post_page_flip = &rs600_post_page_flip,
 932         },
 933 };
 934
 935 static struct radeon_asic r600_asic = {
 936         .init = &r600_init,
 937         .fini = &r600_fini,
 938         .suspend = &r600_suspend,
 939         .resume = &r600_resume,
 940         .vga_set_state = &r600_vga_set_state,
 941         .asic_reset = &r600_asic_reset,
 942         .ioctl_wait_idle = r600_ioctl_wait_idle,
 943         .gui_idle = &r600_gui_idle,
 944         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 945         .get_xclk = &r600_get_xclk,
 946         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 947         .gart = {
 948                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 949                 .set_page = &rs600_gart_set_page,
 950         },
 951         .ring = {
 952                 [RADEON_RING_TYPE_GFX_INDEX] = {
 953                         .ib_execute = &r600_ring_ib_execute,
 954                         .emit_fence = &r600_fence_ring_emit,
 955                         .emit_semaphore = &r600_semaphore_ring_emit,
 956                         .cs_parse = &r600_cs_parse,
 957                         .ring_test = &r600_ring_test,
 958                         .ib_test = &r600_ib_test,
 959                         .is_lockup = &r600_gfx_is_lockup,
 960                 },
 961                 [R600_RING_TYPE_DMA_INDEX] = {
 962                         .ib_execute = &r600_dma_ring_ib_execute,
 963                         .emit_fence = &r600_dma_fence_ring_emit,
 964                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 965                         .cs_parse = &r600_dma_cs_parse,
 966                         .ring_test = &r600_dma_ring_test,
 967                         .ib_test = &r600_dma_ib_test,
 968                         .is_lockup = &r600_dma_is_lockup,
 969                 }
 970         },
 971         .irq = {
 972                 .set = &r600_irq_set,
 973                 .process = &r600_irq_process,
 974         },
 975         .display = {
 976                 .bandwidth_update = &rv515_bandwidth_update,
 977                 .get_vblank_counter = &rs600_get_vblank_counter,
 978                 .wait_for_vblank = &avivo_wait_for_vblank,
 979                 .set_backlight_level = &atombios_set_backlight_level,
 980                 .get_backlight_level = &atombios_get_backlight_level,
 981                 .hdmi_enable = &r600_hdmi_enable,
 982                 .hdmi_setmode = &r600_hdmi_setmode,
 983         },
 984         .copy = {
 985                 .blit = &r600_copy_blit,
 986                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 987                 .dma = &r600_copy_dma,
 988                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 989                 .copy = &r600_copy_blit,
 990                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 991         },
 992         .surface = {
 993                 .set_reg = r600_set_surface_reg,
 994                 .clear_reg = r600_clear_surface_reg,
 995         },
 996         .hpd = {
 997                 .init = &r600_hpd_init,
 998                 .fini = &r600_hpd_fini,
 999                 .sense = &r600_hpd_sense,
1000                 .set_polarity = &r600_hpd_set_polarity,
1001         },
1002         .pm = {
1003                 .misc = &r600_pm_misc,
1004                 .prepare = &rs600_pm_prepare,
1005                 .finish = &rs600_pm_finish,
1006                 .init_profile = &r600_pm_init_profile,
1007                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1008                 .get_engine_clock = &radeon_atom_get_engine_clock,
1009                 .set_engine_clock = &radeon_atom_set_engine_clock,
1010                 .get_memory_clock = &radeon_atom_get_memory_clock,
1011                 .set_memory_clock = &radeon_atom_set_memory_clock,
1012                 .get_pcie_lanes = &r600_get_pcie_lanes,
1013                 .set_pcie_lanes = &r600_set_pcie_lanes,
1014                 .set_clock_gating = NULL,
1015         },
1016         .pflip = {
1017                 .pre_page_flip = &rs600_pre_page_flip,
1018                 .page_flip = &rs600_page_flip,
1019                 .post_page_flip = &rs600_post_page_flip,
1020         },
1021 };
1022
1023 static struct radeon_asic rs780_asic = {
1024         .init = &r600_init,
1025         .fini = &r600_fini,
1026         .suspend = &r600_suspend,
1027         .resume = &r600_resume,
1028         .vga_set_state = &r600_vga_set_state,
1029         .asic_reset = &r600_asic_reset,
1030         .ioctl_wait_idle = r600_ioctl_wait_idle,
1031         .gui_idle = &r600_gui_idle,
1032         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1033         .get_xclk = &r600_get_xclk,
1034         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1035         .gart = {
1036                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1037                 .set_page = &rs600_gart_set_page,
1038         },
1039         .ring = {
1040                 [RADEON_RING_TYPE_GFX_INDEX] = {
1041                         .ib_execute = &r600_ring_ib_execute,
1042                         .emit_fence = &r600_fence_ring_emit,
1043                         .emit_semaphore = &r600_semaphore_ring_emit,
1044                         .cs_parse = &r600_cs_parse,
1045                         .ring_test = &r600_ring_test,
1046                         .ib_test = &r600_ib_test,
1047                         .is_lockup = &r600_gfx_is_lockup,
1048                 },
1049                 [R600_RING_TYPE_DMA_INDEX] = {
1050                         .ib_execute = &r600_dma_ring_ib_execute,
1051                         .emit_fence = &r600_dma_fence_ring_emit,
1052                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1053                         .cs_parse = &r600_dma_cs_parse,
1054                         .ring_test = &r600_dma_ring_test,
1055                         .ib_test = &r600_dma_ib_test,
1056                         .is_lockup = &r600_dma_is_lockup,
1057                 }
1058         },
1059         .irq = {
1060                 .set = &r600_irq_set,
1061                 .process = &r600_irq_process,
1062         },
1063         .display = {
1064                 .bandwidth_update = &rs690_bandwidth_update,
1065                 .get_vblank_counter = &rs600_get_vblank_counter,
1066                 .wait_for_vblank = &avivo_wait_for_vblank,
1067                 .set_backlight_level = &atombios_set_backlight_level,
1068                 .get_backlight_level = &atombios_get_backlight_level,
1069                 .hdmi_enable = &r600_hdmi_enable,
1070                 .hdmi_setmode = &r600_hdmi_setmode,
1071         },
1072         .copy = {
1073                 .blit = &r600_copy_blit,
1074                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1075                 .dma = &r600_copy_dma,
1076                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1077                 .copy = &r600_copy_blit,
1078                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1079         },
1080         .surface = {
1081                 .set_reg = r600_set_surface_reg,
1082                 .clear_reg = r600_clear_surface_reg,
1083         },
1084         .hpd = {
1085                 .init = &r600_hpd_init,
1086                 .fini = &r600_hpd_fini,
1087                 .sense = &r600_hpd_sense,
1088                 .set_polarity = &r600_hpd_set_polarity,
1089         },
1090         .pm = {
1091                 .misc = &r600_pm_misc,
1092                 .prepare = &rs600_pm_prepare,
1093                 .finish = &rs600_pm_finish,
1094                 .init_profile = &rs780_pm_init_profile,
1095                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1096                 .get_engine_clock = &radeon_atom_get_engine_clock,
1097                 .set_engine_clock = &radeon_atom_set_engine_clock,
1098                 .get_memory_clock = NULL,
1099                 .set_memory_clock = NULL,
1100                 .get_pcie_lanes = NULL,
1101                 .set_pcie_lanes = NULL,
1102                 .set_clock_gating = NULL,
1103         },
1104         .pflip = {
1105                 .pre_page_flip = &rs600_pre_page_flip,
1106                 .page_flip = &rs600_page_flip,
1107                 .post_page_flip = &rs600_post_page_flip,
1108         },
1109 };
1110
1111 static struct radeon_asic rv770_asic = {
1112         .init = &rv770_init,
1113         .fini = &rv770_fini,
1114         .suspend = &rv770_suspend,
1115         .resume = &rv770_resume,
1116         .asic_reset = &r600_asic_reset,
1117         .vga_set_state = &r600_vga_set_state,
1118         .ioctl_wait_idle = r600_ioctl_wait_idle,
1119         .gui_idle = &r600_gui_idle,
1120         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1121         .get_xclk = &rv770_get_xclk,
1122         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1123         .gart = {
1124                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1125                 .set_page = &rs600_gart_set_page,
1126         },
1127         .ring = {
1128                 [RADEON_RING_TYPE_GFX_INDEX] = {
1129                         .ib_execute = &r600_ring_ib_execute,
1130                         .emit_fence = &r600_fence_ring_emit,
1131                         .emit_semaphore = &r600_semaphore_ring_emit,
1132                         .cs_parse = &r600_cs_parse,
1133                         .ring_test = &r600_ring_test,
1134                         .ib_test = &r600_ib_test,
1135                         .is_lockup = &r600_gfx_is_lockup,
1136                 },
1137                 [R600_RING_TYPE_DMA_INDEX] = {
1138                         .ib_execute = &r600_dma_ring_ib_execute,
1139                         .emit_fence = &r600_dma_fence_ring_emit,
1140                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1141                         .cs_parse = &r600_dma_cs_parse,
1142                         .ring_test = &r600_dma_ring_test,
1143                         .ib_test = &r600_dma_ib_test,
1144                         .is_lockup = &r600_dma_is_lockup,
1145                 },
1146                 [R600_RING_TYPE_UVD_INDEX] = {
1147                         .ib_execute = &r600_uvd_ib_execute,
1148                         .emit_fence = &r600_uvd_fence_emit,
1149                         .emit_semaphore = &r600_uvd_semaphore_emit,
1150                         .cs_parse = &radeon_uvd_cs_parse,
1151                         .ring_test = &r600_uvd_ring_test,
1152                         .ib_test = &r600_uvd_ib_test,
1153                         .is_lockup = &radeon_ring_test_lockup,
1154                 }
1155         },
1156         .irq = {
1157                 .set = &r600_irq_set,
1158                 .process = &r600_irq_process,
1159         },
1160         .display = {
1161                 .bandwidth_update = &rv515_bandwidth_update,
1162                 .get_vblank_counter = &rs600_get_vblank_counter,
1163                 .wait_for_vblank = &avivo_wait_for_vblank,
1164                 .set_backlight_level = &atombios_set_backlight_level,
1165                 .get_backlight_level = &atombios_get_backlight_level,
1166                 .hdmi_enable = &r600_hdmi_enable,
1167                 .hdmi_setmode = &r600_hdmi_setmode,
1168         },
1169         .copy = {
1170                 .blit = &r600_copy_blit,
1171                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1172                 .dma = &rv770_copy_dma,
1173                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1174                 .copy = &rv770_copy_dma,
1175                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1176         },
1177         .surface = {
1178                 .set_reg = r600_set_surface_reg,
1179                 .clear_reg = r600_clear_surface_reg,
1180         },
1181         .hpd = {
1182                 .init = &r600_hpd_init,
1183                 .fini = &r600_hpd_fini,
1184                 .sense = &r600_hpd_sense,
1185                 .set_polarity = &r600_hpd_set_polarity,
1186         },
1187         .pm = {
1188                 .misc = &rv770_pm_misc,
1189                 .prepare = &rs600_pm_prepare,
1190                 .finish = &rs600_pm_finish,
1191                 .init_profile = &r600_pm_init_profile,
1192                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1193                 .get_engine_clock = &radeon_atom_get_engine_clock,
1194                 .set_engine_clock = &radeon_atom_set_engine_clock,
1195                 .get_memory_clock = &radeon_atom_get_memory_clock,
1196                 .set_memory_clock = &radeon_atom_set_memory_clock,
1197                 .get_pcie_lanes = &r600_get_pcie_lanes,
1198                 .set_pcie_lanes = &r600_set_pcie_lanes,
1199                 .set_clock_gating = &radeon_atom_set_clock_gating,
1200                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1201         },
1202         .pflip = {
1203                 .pre_page_flip = &rs600_pre_page_flip,
1204                 .page_flip = &rv770_page_flip,
1205                 .post_page_flip = &rs600_post_page_flip,
1206         },
1207 };
1208
1209 static struct radeon_asic evergreen_asic = {
1210         .init = &evergreen_init,
1211         .fini = &evergreen_fini,
1212         .suspend = &evergreen_suspend,
1213         .resume = &evergreen_resume,
1214         .asic_reset = &evergreen_asic_reset,
1215         .vga_set_state = &r600_vga_set_state,
1216         .ioctl_wait_idle = r600_ioctl_wait_idle,
1217         .gui_idle = &r600_gui_idle,
1218         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1219         .get_xclk = &rv770_get_xclk,
1220         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1221         .gart = {
1222                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1223                 .set_page = &rs600_gart_set_page,
1224         },
1225         .ring = {
1226                 [RADEON_RING_TYPE_GFX_INDEX] = {
1227                         .ib_execute = &evergreen_ring_ib_execute,
1228                         .emit_fence = &r600_fence_ring_emit,
1229                         .emit_semaphore = &r600_semaphore_ring_emit,
1230                         .cs_parse = &evergreen_cs_parse,
1231                         .ring_test = &r600_ring_test,
1232                         .ib_test = &r600_ib_test,
1233                         .is_lockup = &evergreen_gfx_is_lockup,
1234                 },
1235                 [R600_RING_TYPE_DMA_INDEX] = {
1236                         .ib_execute = &evergreen_dma_ring_ib_execute,
1237                         .emit_fence = &evergreen_dma_fence_ring_emit,
1238                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1239                         .cs_parse = &evergreen_dma_cs_parse,
1240                         .ring_test = &r600_dma_ring_test,
1241                         .ib_test = &r600_dma_ib_test,
1242                         .is_lockup = &evergreen_dma_is_lockup,
1243                 },
1244                 [R600_RING_TYPE_UVD_INDEX] = {
1245                         .ib_execute = &r600_uvd_ib_execute,
1246                         .emit_fence = &r600_uvd_fence_emit,
1247                         .emit_semaphore = &r600_uvd_semaphore_emit,
1248                         .cs_parse = &radeon_uvd_cs_parse,
1249                         .ring_test = &r600_uvd_ring_test,
1250                         .ib_test = &r600_uvd_ib_test,
1251                         .is_lockup = &radeon_ring_test_lockup,
1252                 }
1253         },
1254         .irq = {
1255                 .set = &evergreen_irq_set,
1256                 .process = &evergreen_irq_process,
1257         },
1258         .display = {
1259                 .bandwidth_update = &evergreen_bandwidth_update,
1260                 .get_vblank_counter = &evergreen_get_vblank_counter,
1261                 .wait_for_vblank = &dce4_wait_for_vblank,
1262                 .set_backlight_level = &atombios_set_backlight_level,
1263                 .get_backlight_level = &atombios_get_backlight_level,
1264                 .hdmi_enable = &evergreen_hdmi_enable,
1265                 .hdmi_setmode = &evergreen_hdmi_setmode,
1266         },
1267         .copy = {
1268                 .blit = &r600_copy_blit,
1269                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1270                 .dma = &evergreen_copy_dma,
1271                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1272                 .copy = &evergreen_copy_dma,
1273                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1274         },
1275         .surface = {
1276                 .set_reg = r600_set_surface_reg,
1277                 .clear_reg = r600_clear_surface_reg,
1278         },
1279         .hpd = {
1280                 .init = &evergreen_hpd_init,
1281                 .fini = &evergreen_hpd_fini,
1282                 .sense = &evergreen_hpd_sense,
1283                 .set_polarity = &evergreen_hpd_set_polarity,
1284         },
1285         .pm = {
1286                 .misc = &evergreen_pm_misc,
1287                 .prepare = &evergreen_pm_prepare,
1288                 .finish = &evergreen_pm_finish,
1289                 .init_profile = &r600_pm_init_profile,
1290                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1291                 .get_engine_clock = &radeon_atom_get_engine_clock,
1292                 .set_engine_clock = &radeon_atom_set_engine_clock,
1293                 .get_memory_clock = &radeon_atom_get_memory_clock,
1294                 .set_memory_clock = &radeon_atom_set_memory_clock,
1295                 .get_pcie_lanes = &r600_get_pcie_lanes,
1296                 .set_pcie_lanes = &r600_set_pcie_lanes,
1297                 .set_clock_gating = NULL,
1298                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1299         },
1300         .pflip = {
1301                 .pre_page_flip = &evergreen_pre_page_flip,
1302                 .page_flip = &evergreen_page_flip,
1303                 .post_page_flip = &evergreen_post_page_flip,
1304         },
1305 };
1306
1307 static struct radeon_asic sumo_asic = {
1308         .init = &evergreen_init,
1309         .fini = &evergreen_fini,
1310         .suspend = &evergreen_suspend,
1311         .resume = &evergreen_resume,
1312         .asic_reset = &evergreen_asic_reset,
1313         .vga_set_state = &r600_vga_set_state,
1314         .ioctl_wait_idle = r600_ioctl_wait_idle,
1315         .gui_idle = &r600_gui_idle,
1316         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1317         .get_xclk = &r600_get_xclk,
1318         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1319         .gart = {
1320                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1321                 .set_page = &rs600_gart_set_page,
1322         },
1323         .ring = {
1324                 [RADEON_RING_TYPE_GFX_INDEX] = {
1325                         .ib_execute = &evergreen_ring_ib_execute,
1326                         .emit_fence = &r600_fence_ring_emit,
1327                         .emit_semaphore = &r600_semaphore_ring_emit,
1328                         .cs_parse = &evergreen_cs_parse,
1329                         .ring_test = &r600_ring_test,
1330                         .ib_test = &r600_ib_test,
1331                         .is_lockup = &evergreen_gfx_is_lockup,
1332                 },
1333                 [R600_RING_TYPE_DMA_INDEX] = {
1334                         .ib_execute = &evergreen_dma_ring_ib_execute,
1335                         .emit_fence = &evergreen_dma_fence_ring_emit,
1336                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1337                         .cs_parse = &evergreen_dma_cs_parse,
1338                         .ring_test = &r600_dma_ring_test,
1339                         .ib_test = &r600_dma_ib_test,
1340                         .is_lockup = &evergreen_dma_is_lockup,
1341                 },
1342                 [R600_RING_TYPE_UVD_INDEX] = {
1343                         .ib_execute = &r600_uvd_ib_execute,
1344                         .emit_fence = &r600_uvd_fence_emit,
1345                         .emit_semaphore = &r600_uvd_semaphore_emit,
1346                         .cs_parse = &radeon_uvd_cs_parse,
1347                         .ring_test = &r600_uvd_ring_test,
1348                         .ib_test = &r600_uvd_ib_test,
1349                         .is_lockup = &radeon_ring_test_lockup,
1350                 }
1351         },
1352         .irq = {
1353                 .set = &evergreen_irq_set,
1354                 .process = &evergreen_irq_process,
1355         },
1356         .display = {
1357                 .bandwidth_update = &evergreen_bandwidth_update,
1358                 .get_vblank_counter = &evergreen_get_vblank_counter,
1359                 .wait_for_vblank = &dce4_wait_for_vblank,
1360                 .set_backlight_level = &atombios_set_backlight_level,
1361                 .get_backlight_level = &atombios_get_backlight_level,
1362                 .hdmi_enable = &evergreen_hdmi_enable,
1363                 .hdmi_setmode = &evergreen_hdmi_setmode,
1364         },
1365         .copy = {
1366                 .blit = &r600_copy_blit,
1367                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1368                 .dma = &evergreen_copy_dma,
1369                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1370                 .copy = &evergreen_copy_dma,
1371                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1372         },
1373         .surface = {
1374                 .set_reg = r600_set_surface_reg,
1375                 .clear_reg = r600_clear_surface_reg,
1376         },
1377         .hpd = {
1378                 .init = &evergreen_hpd_init,
1379                 .fini = &evergreen_hpd_fini,
1380                 .sense = &evergreen_hpd_sense,
1381                 .set_polarity = &evergreen_hpd_set_polarity,
1382         },
1383         .pm = {
1384                 .misc = &evergreen_pm_misc,
1385                 .prepare = &evergreen_pm_prepare,
1386                 .finish = &evergreen_pm_finish,
1387                 .init_profile = &sumo_pm_init_profile,
1388                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1389                 .get_engine_clock = &radeon_atom_get_engine_clock,
1390                 .set_engine_clock = &radeon_atom_set_engine_clock,
1391                 .get_memory_clock = NULL,
1392                 .set_memory_clock = NULL,
1393                 .get_pcie_lanes = NULL,
1394                 .set_pcie_lanes = NULL,
1395                 .set_clock_gating = NULL,
1396                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1397         },
1398         .pflip = {
1399                 .pre_page_flip = &evergreen_pre_page_flip,
1400                 .page_flip = &evergreen_page_flip,
1401                 .post_page_flip = &evergreen_post_page_flip,
1402         },
1403 };
1404
1405 static struct radeon_asic btc_asic = {
1406         .init = &evergreen_init,
1407         .fini = &evergreen_fini,
1408         .suspend = &evergreen_suspend,
1409         .resume = &evergreen_resume,
1410         .asic_reset = &evergreen_asic_reset,
1411         .vga_set_state = &r600_vga_set_state,
1412         .ioctl_wait_idle = r600_ioctl_wait_idle,
1413         .gui_idle = &r600_gui_idle,
1414         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1415         .get_xclk = &rv770_get_xclk,
1416         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1417         .gart = {
1418                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1419                 .set_page = &rs600_gart_set_page,
1420         },
1421         .ring = {
1422                 [RADEON_RING_TYPE_GFX_INDEX] = {
1423                         .ib_execute = &evergreen_ring_ib_execute,
1424                         .emit_fence = &r600_fence_ring_emit,
1425                         .emit_semaphore = &r600_semaphore_ring_emit,
1426                         .cs_parse = &evergreen_cs_parse,
1427                         .ring_test = &r600_ring_test,
1428                         .ib_test = &r600_ib_test,
1429                         .is_lockup = &evergreen_gfx_is_lockup,
1430                 },
1431                 [R600_RING_TYPE_DMA_INDEX] = {
1432                         .ib_execute = &evergreen_dma_ring_ib_execute,
1433                         .emit_fence = &evergreen_dma_fence_ring_emit,
1434                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1435                         .cs_parse = &evergreen_dma_cs_parse,
1436                         .ring_test = &r600_dma_ring_test,
1437                         .ib_test = &r600_dma_ib_test,
1438                         .is_lockup = &evergreen_dma_is_lockup,
1439                 },
1440                 [R600_RING_TYPE_UVD_INDEX] = {
1441                         .ib_execute = &r600_uvd_ib_execute,
1442                         .emit_fence = &r600_uvd_fence_emit,
1443                         .emit_semaphore = &r600_uvd_semaphore_emit,
1444                         .cs_parse = &radeon_uvd_cs_parse,
1445                         .ring_test = &r600_uvd_ring_test,
1446                         .ib_test = &r600_uvd_ib_test,
1447                         .is_lockup = &radeon_ring_test_lockup,
1448                 }
1449         },
1450         .irq = {
1451                 .set = &evergreen_irq_set,
1452                 .process = &evergreen_irq_process,
1453         },
1454         .display = {
1455                 .bandwidth_update = &evergreen_bandwidth_update,
1456                 .get_vblank_counter = &evergreen_get_vblank_counter,
1457                 .wait_for_vblank = &dce4_wait_for_vblank,
1458                 .set_backlight_level = &atombios_set_backlight_level,
1459                 .get_backlight_level = &atombios_get_backlight_level,
1460                 .hdmi_enable = &evergreen_hdmi_enable,
1461                 .hdmi_setmode = &evergreen_hdmi_setmode,
1462         },
1463         .copy = {
1464                 .blit = &r600_copy_blit,
1465                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1466                 .dma = &evergreen_copy_dma,
1467                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1468                 .copy = &evergreen_copy_dma,
1469                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1470         },
1471         .surface = {
1472                 .set_reg = r600_set_surface_reg,
1473                 .clear_reg = r600_clear_surface_reg,
1474         },
1475         .hpd = {
1476                 .init = &evergreen_hpd_init,
1477                 .fini = &evergreen_hpd_fini,
1478                 .sense = &evergreen_hpd_sense,
1479                 .set_polarity = &evergreen_hpd_set_polarity,
1480         },
1481         .pm = {
1482                 .misc = &evergreen_pm_misc,
1483                 .prepare = &evergreen_pm_prepare,
1484                 .finish = &evergreen_pm_finish,
1485                 .init_profile = &btc_pm_init_profile,
1486                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1487                 .get_engine_clock = &radeon_atom_get_engine_clock,
1488                 .set_engine_clock = &radeon_atom_set_engine_clock,
1489                 .get_memory_clock = &radeon_atom_get_memory_clock,
1490                 .set_memory_clock = &radeon_atom_set_memory_clock,
1491                 .get_pcie_lanes = &r600_get_pcie_lanes,
1492                 .set_pcie_lanes = &r600_set_pcie_lanes,
1493                 .set_clock_gating = NULL,
1494                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1495         },
1496         .pflip = {
1497                 .pre_page_flip = &evergreen_pre_page_flip,
1498                 .page_flip = &evergreen_page_flip,
1499                 .post_page_flip = &evergreen_post_page_flip,
1500         },
1501 };
1502
1503 static struct radeon_asic cayman_asic = {
1504         .init = &cayman_init,
1505         .fini = &cayman_fini,
1506         .suspend = &cayman_suspend,
1507         .resume = &cayman_resume,
1508         .asic_reset = &cayman_asic_reset,
1509         .vga_set_state = &r600_vga_set_state,
1510         .ioctl_wait_idle = r600_ioctl_wait_idle,
1511         .gui_idle = &r600_gui_idle,
1512         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1513         .get_xclk = &rv770_get_xclk,
1514         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1515         .gart = {
1516                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1517                 .set_page = &rs600_gart_set_page,
1518         },
1519         .vm = {
1520                 .init = &cayman_vm_init,
1521                 .fini = &cayman_vm_fini,
1522                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1523                 .set_page = &cayman_vm_set_page,
1524         },
1525         .ring = {
1526                 [RADEON_RING_TYPE_GFX_INDEX] = {
1527                         .ib_execute = &cayman_ring_ib_execute,
1528                         .ib_parse = &evergreen_ib_parse,
1529                         .emit_fence = &cayman_fence_ring_emit,
1530                         .emit_semaphore = &r600_semaphore_ring_emit,
1531                         .cs_parse = &evergreen_cs_parse,
1532                         .ring_test = &r600_ring_test,
1533                         .ib_test = &r600_ib_test,
1534                         .is_lockup = &cayman_gfx_is_lockup,
1535                         .vm_flush = &cayman_vm_flush,
1536                 },
1537                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1538                         .ib_execute = &cayman_ring_ib_execute,
1539                         .ib_parse = &evergreen_ib_parse,
1540                         .emit_fence = &cayman_fence_ring_emit,
1541                         .emit_semaphore = &r600_semaphore_ring_emit,
1542                         .cs_parse = &evergreen_cs_parse,
1543                         .ring_test = &r600_ring_test,
1544                         .ib_test = &r600_ib_test,
1545                         .is_lockup = &cayman_gfx_is_lockup,
1546                         .vm_flush = &cayman_vm_flush,
1547                 },
1548                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1549                         .ib_execute = &cayman_ring_ib_execute,
1550                         .ib_parse = &evergreen_ib_parse,
1551                         .emit_fence = &cayman_fence_ring_emit,
1552                         .emit_semaphore = &r600_semaphore_ring_emit,
1553                         .cs_parse = &evergreen_cs_parse,
1554                         .ring_test = &r600_ring_test,
1555                         .ib_test = &r600_ib_test,
1556                         .is_lockup = &cayman_gfx_is_lockup,
1557                         .vm_flush = &cayman_vm_flush,
1558                 },
1559                 [R600_RING_TYPE_DMA_INDEX] = {
1560                         .ib_execute = &cayman_dma_ring_ib_execute,
1561                         .ib_parse = &evergreen_dma_ib_parse,
1562                         .emit_fence = &evergreen_dma_fence_ring_emit,
1563                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1564                         .cs_parse = &evergreen_dma_cs_parse,
1565                         .ring_test = &r600_dma_ring_test,
1566                         .ib_test = &r600_dma_ib_test,
1567                         .is_lockup = &cayman_dma_is_lockup,
1568                         .vm_flush = &cayman_dma_vm_flush,
1569                 },
1570                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1571                         .ib_execute = &cayman_dma_ring_ib_execute,
1572                         .ib_parse = &evergreen_dma_ib_parse,
1573                         .emit_fence = &evergreen_dma_fence_ring_emit,
1574                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1575                         .cs_parse = &evergreen_dma_cs_parse,
1576                         .ring_test = &r600_dma_ring_test,
1577                         .ib_test = &r600_dma_ib_test,
1578                         .is_lockup = &cayman_dma_is_lockup,
1579                         .vm_flush = &cayman_dma_vm_flush,
1580                 },
1581                 [R600_RING_TYPE_UVD_INDEX] = {
1582                         .ib_execute = &r600_uvd_ib_execute,
1583                         .emit_fence = &r600_uvd_fence_emit,
1584                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1585                         .cs_parse = &radeon_uvd_cs_parse,
1586                         .ring_test = &r600_uvd_ring_test,
1587                         .ib_test = &r600_uvd_ib_test,
1588                         .is_lockup = &radeon_ring_test_lockup,
1589                 }
1590         },
1591         .irq = {
1592                 .set = &evergreen_irq_set,
1593                 .process = &evergreen_irq_process,
1594         },
1595         .display = {
1596                 .bandwidth_update = &evergreen_bandwidth_update,
1597                 .get_vblank_counter = &evergreen_get_vblank_counter,
1598                 .wait_for_vblank = &dce4_wait_for_vblank,
1599                 .set_backlight_level = &atombios_set_backlight_level,
1600                 .get_backlight_level = &atombios_get_backlight_level,
1601                 .hdmi_enable = &evergreen_hdmi_enable,
1602                 .hdmi_setmode = &evergreen_hdmi_setmode,
1603         },
1604         .copy = {
1605                 .blit = &r600_copy_blit,
1606                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1607                 .dma = &evergreen_copy_dma,
1608                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1609                 .copy = &evergreen_copy_dma,
1610                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1611         },
1612         .surface = {
1613                 .set_reg = r600_set_surface_reg,
1614                 .clear_reg = r600_clear_surface_reg,
1615         },
1616         .hpd = {
1617                 .init = &evergreen_hpd_init,
1618                 .fini = &evergreen_hpd_fini,
1619                 .sense = &evergreen_hpd_sense,
1620                 .set_polarity = &evergreen_hpd_set_polarity,
1621         },
1622         .pm = {
1623                 .misc = &evergreen_pm_misc,
1624                 .prepare = &evergreen_pm_prepare,
1625                 .finish = &evergreen_pm_finish,
1626                 .init_profile = &btc_pm_init_profile,
1627                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1628                 .get_engine_clock = &radeon_atom_get_engine_clock,
1629                 .set_engine_clock = &radeon_atom_set_engine_clock,
1630                 .get_memory_clock = &radeon_atom_get_memory_clock,
1631                 .set_memory_clock = &radeon_atom_set_memory_clock,
1632                 .get_pcie_lanes = &r600_get_pcie_lanes,
1633                 .set_pcie_lanes = &r600_set_pcie_lanes,
1634                 .set_clock_gating = NULL,
1635                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1636         },
1637         .pflip = {
1638                 .pre_page_flip = &evergreen_pre_page_flip,
1639                 .page_flip = &evergreen_page_flip,
1640                 .post_page_flip = &evergreen_post_page_flip,
1641         },
1642 };
1643
1644 static struct radeon_asic trinity_asic = {
1645         .init = &cayman_init,
1646         .fini = &cayman_fini,
1647         .suspend = &cayman_suspend,
1648         .resume = &cayman_resume,
1649         .asic_reset = &cayman_asic_reset,
1650         .vga_set_state = &r600_vga_set_state,
1651         .ioctl_wait_idle = r600_ioctl_wait_idle,
1652         .gui_idle = &r600_gui_idle,
1653         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1654         .get_xclk = &r600_get_xclk,
1655         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1656         .gart = {
1657                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1658                 .set_page = &rs600_gart_set_page,
1659         },
1660         .vm = {
1661                 .init = &cayman_vm_init,
1662                 .fini = &cayman_vm_fini,
1663                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1664                 .set_page = &cayman_vm_set_page,
1665         },
1666         .ring = {
1667                 [RADEON_RING_TYPE_GFX_INDEX] = {
1668                         .ib_execute = &cayman_ring_ib_execute,
1669                         .ib_parse = &evergreen_ib_parse,
1670                         .emit_fence = &cayman_fence_ring_emit,
1671                         .emit_semaphore = &r600_semaphore_ring_emit,
1672                         .cs_parse = &evergreen_cs_parse,
1673                         .ring_test = &r600_ring_test,
1674                         .ib_test = &r600_ib_test,
1675                         .is_lockup = &cayman_gfx_is_lockup,
1676                         .vm_flush = &cayman_vm_flush,
1677                 },
1678                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1679                         .ib_execute = &cayman_ring_ib_execute,
1680                         .ib_parse = &evergreen_ib_parse,
1681                         .emit_fence = &cayman_fence_ring_emit,
1682                         .emit_semaphore = &r600_semaphore_ring_emit,
1683                         .cs_parse = &evergreen_cs_parse,
1684                         .ring_test = &r600_ring_test,
1685                         .ib_test = &r600_ib_test,
1686                         .is_lockup = &cayman_gfx_is_lockup,
1687                         .vm_flush = &cayman_vm_flush,
1688                 },
1689                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1690                         .ib_execute = &cayman_ring_ib_execute,
1691                         .ib_parse = &evergreen_ib_parse,
1692                         .emit_fence = &cayman_fence_ring_emit,
1693                         .emit_semaphore = &r600_semaphore_ring_emit,
1694                         .cs_parse = &evergreen_cs_parse,
1695                         .ring_test = &r600_ring_test,
1696                         .ib_test = &r600_ib_test,
1697                         .is_lockup = &cayman_gfx_is_lockup,
1698                         .vm_flush = &cayman_vm_flush,
1699                 },
1700                 [R600_RING_TYPE_DMA_INDEX] = {
1701                         .ib_execute = &cayman_dma_ring_ib_execute,
1702                         .ib_parse = &evergreen_dma_ib_parse,
1703                         .emit_fence = &evergreen_dma_fence_ring_emit,
1704                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1705                         .cs_parse = &evergreen_dma_cs_parse,
1706                         .ring_test = &r600_dma_ring_test,
1707                         .ib_test = &r600_dma_ib_test,
1708                         .is_lockup = &cayman_dma_is_lockup,
1709                         .vm_flush = &cayman_dma_vm_flush,
1710                 },
1711                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1712                         .ib_execute = &cayman_dma_ring_ib_execute,
1713                         .ib_parse = &evergreen_dma_ib_parse,
1714                         .emit_fence = &evergreen_dma_fence_ring_emit,
1715                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1716                         .cs_parse = &evergreen_dma_cs_parse,
1717                         .ring_test = &r600_dma_ring_test,
1718                         .ib_test = &r600_dma_ib_test,
1719                         .is_lockup = &cayman_dma_is_lockup,
1720                         .vm_flush = &cayman_dma_vm_flush,
1721                 },
1722                 [R600_RING_TYPE_UVD_INDEX] = {
1723                         .ib_execute = &r600_uvd_ib_execute,
1724                         .emit_fence = &r600_uvd_fence_emit,
1725                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1726                         .cs_parse = &radeon_uvd_cs_parse,
1727                         .ring_test = &r600_uvd_ring_test,
1728                         .ib_test = &r600_uvd_ib_test,
1729                         .is_lockup = &radeon_ring_test_lockup,
1730                 }
1731         },
1732         .irq = {
1733                 .set = &evergreen_irq_set,
1734                 .process = &evergreen_irq_process,
1735         },
1736         .display = {
1737                 .bandwidth_update = &dce6_bandwidth_update,
1738                 .get_vblank_counter = &evergreen_get_vblank_counter,
1739                 .wait_for_vblank = &dce4_wait_for_vblank,
1740                 .set_backlight_level = &atombios_set_backlight_level,
1741                 .get_backlight_level = &atombios_get_backlight_level,
1742         },
1743         .copy = {
1744                 .blit = &r600_copy_blit,
1745                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1746                 .dma = &evergreen_copy_dma,
1747                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1748                 .copy = &evergreen_copy_dma,
1749                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1750         },
1751         .surface = {
1752                 .set_reg = r600_set_surface_reg,
1753                 .clear_reg = r600_clear_surface_reg,
1754         },
1755         .hpd = {
1756                 .init = &evergreen_hpd_init,
1757                 .fini = &evergreen_hpd_fini,
1758                 .sense = &evergreen_hpd_sense,
1759                 .set_polarity = &evergreen_hpd_set_polarity,
1760         },
1761         .pm = {
1762                 .misc = &evergreen_pm_misc,
1763                 .prepare = &evergreen_pm_prepare,
1764                 .finish = &evergreen_pm_finish,
1765                 .init_profile = &sumo_pm_init_profile,
1766                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1767                 .get_engine_clock = &radeon_atom_get_engine_clock,
1768                 .set_engine_clock = &radeon_atom_set_engine_clock,
1769                 .get_memory_clock = NULL,
1770                 .set_memory_clock = NULL,
1771                 .get_pcie_lanes = NULL,
1772                 .set_pcie_lanes = NULL,
1773                 .set_clock_gating = NULL,
1774                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1775         },
1776         .pflip = {
1777                 .pre_page_flip = &evergreen_pre_page_flip,
1778                 .page_flip = &evergreen_page_flip,
1779                 .post_page_flip = &evergreen_post_page_flip,
1780         },
1781 };
1782
1783 static struct radeon_asic si_asic = {
1784         .init = &si_init,
1785         .fini = &si_fini,
1786         .suspend = &si_suspend,
1787         .resume = &si_resume,
1788         .asic_reset = &si_asic_reset,
1789         .vga_set_state = &r600_vga_set_state,
1790         .ioctl_wait_idle = r600_ioctl_wait_idle,
1791         .gui_idle = &r600_gui_idle,
1792         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1793         .get_xclk = &si_get_xclk,
1794         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1795         .gart = {
1796                 .tlb_flush = &si_pcie_gart_tlb_flush,
1797                 .set_page = &rs600_gart_set_page,
1798         },
1799         .vm = {
1800                 .init = &si_vm_init,
1801                 .fini = &si_vm_fini,
1802                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1803                 .set_page = &si_vm_set_page,
1804         },
1805         .ring = {
1806                 [RADEON_RING_TYPE_GFX_INDEX] = {
1807                         .ib_execute = &si_ring_ib_execute,
1808                         .ib_parse = &si_ib_parse,
1809                         .emit_fence = &si_fence_ring_emit,
1810                         .emit_semaphore = &r600_semaphore_ring_emit,
1811                         .cs_parse = NULL,
1812                         .ring_test = &r600_ring_test,
1813                         .ib_test = &r600_ib_test,
1814                         .is_lockup = &si_gfx_is_lockup,
1815                         .vm_flush = &si_vm_flush,
1816                 },
1817                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1818                         .ib_execute = &si_ring_ib_execute,
1819                         .ib_parse = &si_ib_parse,
1820                         .emit_fence = &si_fence_ring_emit,
1821                         .emit_semaphore = &r600_semaphore_ring_emit,
1822                         .cs_parse = NULL,
1823                         .ring_test = &r600_ring_test,
1824                         .ib_test = &r600_ib_test,
1825                         .is_lockup = &si_gfx_is_lockup,
1826                         .vm_flush = &si_vm_flush,
1827                 },
1828                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1829                         .ib_execute = &si_ring_ib_execute,
1830                         .ib_parse = &si_ib_parse,
1831                         .emit_fence = &si_fence_ring_emit,
1832                         .emit_semaphore = &r600_semaphore_ring_emit,
1833                         .cs_parse = NULL,
1834                         .ring_test = &r600_ring_test,
1835                         .ib_test = &r600_ib_test,
1836                         .is_lockup = &si_gfx_is_lockup,
1837                         .vm_flush = &si_vm_flush,
1838                 },
1839                 [R600_RING_TYPE_DMA_INDEX] = {
1840                         .ib_execute = &cayman_dma_ring_ib_execute,
1841                         .ib_parse = &evergreen_dma_ib_parse,
1842                         .emit_fence = &evergreen_dma_fence_ring_emit,
1843                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1844                         .cs_parse = NULL,
1845                         .ring_test = &r600_dma_ring_test,
1846                         .ib_test = &r600_dma_ib_test,
1847                         .is_lockup = &si_dma_is_lockup,
1848                         .vm_flush = &si_dma_vm_flush,
1849                 },
1850                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1851                         .ib_execute = &cayman_dma_ring_ib_execute,
1852                         .ib_parse = &evergreen_dma_ib_parse,
1853                         .emit_fence = &evergreen_dma_fence_ring_emit,
1854                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1855                         .cs_parse = NULL,
1856                         .ring_test = &r600_dma_ring_test,
1857                         .ib_test = &r600_dma_ib_test,
1858                         .is_lockup = &si_dma_is_lockup,
1859                         .vm_flush = &si_dma_vm_flush,
1860                 },
1861                 [R600_RING_TYPE_UVD_INDEX] = {
1862                         .ib_execute = &r600_uvd_ib_execute,
1863                         .emit_fence = &r600_uvd_fence_emit,
1864                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1865                         .cs_parse = &radeon_uvd_cs_parse,
1866                         .ring_test = &r600_uvd_ring_test,
1867                         .ib_test = &r600_uvd_ib_test,
1868                         .is_lockup = &radeon_ring_test_lockup,
1869                 }
1870         },
1871         .irq = {
1872                 .set = &si_irq_set,
1873                 .process = &si_irq_process,
1874         },
1875         .display = {
1876                 .bandwidth_update = &dce6_bandwidth_update,
1877                 .get_vblank_counter = &evergreen_get_vblank_counter,
1878                 .wait_for_vblank = &dce4_wait_for_vblank,
1879                 .set_backlight_level = &atombios_set_backlight_level,
1880                 .get_backlight_level = &atombios_get_backlight_level,
1881         },
1882         .copy = {
1883                 .blit = NULL,
1884                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1885                 .dma = &si_copy_dma,
1886                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1887                 .copy = &si_copy_dma,
1888                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1889         },
1890         .surface = {
1891                 .set_reg = r600_set_surface_reg,
1892                 .clear_reg = r600_clear_surface_reg,
1893         },
1894         .hpd = {
1895                 .init = &evergreen_hpd_init,
1896                 .fini = &evergreen_hpd_fini,
1897                 .sense = &evergreen_hpd_sense,
1898                 .set_polarity = &evergreen_hpd_set_polarity,
1899         },
1900         .pm = {
1901                 .misc = &evergreen_pm_misc,
1902                 .prepare = &evergreen_pm_prepare,
1903                 .finish = &evergreen_pm_finish,
1904                 .init_profile = &sumo_pm_init_profile,
1905                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1906                 .get_engine_clock = &radeon_atom_get_engine_clock,
1907                 .set_engine_clock = &radeon_atom_set_engine_clock,
1908                 .get_memory_clock = &radeon_atom_get_memory_clock,
1909                 .set_memory_clock = &radeon_atom_set_memory_clock,
1910                 .get_pcie_lanes = &r600_get_pcie_lanes,
1911                 .set_pcie_lanes = &r600_set_pcie_lanes,
1912                 .set_clock_gating = NULL,
1913                 .set_uvd_clocks = &si_set_uvd_clocks,
1914         },
1915         .pflip = {
1916                 .pre_page_flip = &evergreen_pre_page_flip,
1917                 .page_flip = &evergreen_page_flip,
1918                 .post_page_flip = &evergreen_post_page_flip,
1919         },
1920 };
1921
1922 /**
1923  * radeon_asic_init - register asic specific callbacks
1924  *
1925  * @rdev: radeon device pointer
1926  *
1927  * Registers the appropriate asic specific callbacks for each
1928  * chip family.  Also sets other asics specific info like the number
1929  * of crtcs and the register aperture accessors (all asics).
1930  * Returns 0 for success.
1931  */
1932 int radeon_asic_init(struct radeon_device *rdev)
1933 {
1934         radeon_register_accessor_init(rdev);
1935
1936         /* set the number of crtcs */
1937         if (rdev->flags & RADEON_SINGLE_CRTC)
1938                 rdev->num_crtc = 1;
1939         else
1940                 rdev->num_crtc = 2;
1941
1942         rdev->has_uvd = false;
1943
1944         switch (rdev->family) {
1945         case CHIP_R100:
1946         case CHIP_RV100:
1947         case CHIP_RS100:
1948         case CHIP_RV200:
1949         case CHIP_RS200:
1950                 rdev->asic = &r100_asic;
1951                 break;
1952         case CHIP_R200:
1953         case CHIP_RV250:
1954         case CHIP_RS300:
1955         case CHIP_RV280:
1956                 rdev->asic = &r200_asic;
1957                 break;
1958         case CHIP_R300:
1959         case CHIP_R350:
1960         case CHIP_RV350:
1961         case CHIP_RV380:
1962                 if (rdev->flags & RADEON_IS_PCIE)
1963                         rdev->asic = &r300_asic_pcie;
1964                 else
1965                         rdev->asic = &r300_asic;
1966                 break;
1967         case CHIP_R420:
1968         case CHIP_R423:
1969         case CHIP_RV410:
1970                 rdev->asic = &r420_asic;
1971                 /* handle macs */
1972                 if (rdev->bios == NULL) {
1973                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1974                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1975                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1976                         rdev->asic->pm.set_memory_clock = NULL;
1977                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1978                 }
1979                 break;
1980         case CHIP_RS400:
1981         case CHIP_RS480:
1982                 rdev->asic = &rs400_asic;
1983                 break;
1984         case CHIP_RS600:
1985                 rdev->asic = &rs600_asic;
1986                 break;
1987         case CHIP_RS690:
1988         case CHIP_RS740:
1989                 rdev->asic = &rs690_asic;
1990                 break;
1991         case CHIP_RV515:
1992                 rdev->asic = &rv515_asic;
1993                 break;
1994         case CHIP_R520:
1995         case CHIP_RV530:
1996         case CHIP_RV560:
1997         case CHIP_RV570:
1998         case CHIP_R580:
1999                 rdev->asic = &r520_asic;
2000                 break;
2001         case CHIP_R600:
2002         case CHIP_RV610:
2003         case CHIP_RV630:
2004         case CHIP_RV620:
2005         case CHIP_RV635:
2006         case CHIP_RV670:
2007                 rdev->asic = &r600_asic;
2008                 if (rdev->family == CHIP_R600)
2009                         rdev->has_uvd = false;
2010                 else
2011                         rdev->has_uvd = true;
2012                 break;
2013         case CHIP_RS780:
2014         case CHIP_RS880:
2015                 rdev->asic = &rs780_asic;
2016                 rdev->has_uvd = true;
2017                 break;
2018         case CHIP_RV770:
2019         case CHIP_RV730:
2020         case CHIP_RV710:
2021         case CHIP_RV740:
2022                 rdev->asic = &rv770_asic;
2023                 rdev->has_uvd = true;
2024                 break;
2025         case CHIP_CEDAR:
2026         case CHIP_REDWOOD:
2027         case CHIP_JUNIPER:
2028         case CHIP_CYPRESS:
2029         case CHIP_HEMLOCK:
2030                 /* set num crtcs */
2031                 if (rdev->family == CHIP_CEDAR)
2032                         rdev->num_crtc = 4;
2033                 else
2034                         rdev->num_crtc = 6;
2035                 rdev->asic = &evergreen_asic;
2036                 rdev->has_uvd = true;
2037                 break;
2038         case CHIP_PALM:
2039         case CHIP_SUMO:
2040         case CHIP_SUMO2:
2041                 rdev->asic = &sumo_asic;
2042                 rdev->has_uvd = true;
2043                 break;
2044         case CHIP_BARTS:
2045         case CHIP_TURKS:
2046         case CHIP_CAICOS:
2047                 /* set num crtcs */
2048                 if (rdev->family == CHIP_CAICOS)
2049                         rdev->num_crtc = 4;
2050                 else
2051                         rdev->num_crtc = 6;
2052                 rdev->asic = &btc_asic;
2053                 rdev->has_uvd = true;
2054                 break;
2055         case CHIP_CAYMAN:
2056                 rdev->asic = &cayman_asic;
2057                 /* set num crtcs */
2058                 rdev->num_crtc = 6;
2059                 rdev->has_uvd = true;
2060                 break;
2061         case CHIP_ARUBA:
2062                 rdev->asic = &trinity_asic;
2063                 /* set num crtcs */
2064                 rdev->num_crtc = 4;
2065                 rdev->has_uvd = true;
2066                 break;
2067         case CHIP_TAHITI:
2068         case CHIP_PITCAIRN:
2069         case CHIP_VERDE:
2070         case CHIP_OLAND:
2071         case CHIP_HAINAN:
2072                 rdev->asic = &si_asic;
2073                 /* set num crtcs */
2074                 if (rdev->family == CHIP_HAINAN)
2075                         rdev->num_crtc = 0;
2076                 else if (rdev->family == CHIP_OLAND)
2077                         rdev->num_crtc = 2;
2078                 else
2079                         rdev->num_crtc = 6;
2080                 if (rdev->family == CHIP_HAINAN)
2081                         rdev->has_uvd = false;
2082                 else
2083                         rdev->has_uvd = true;
2084                 break;
2085         default:
2086                 /* FIXME: not supported yet */
2087                 return -EINVAL;
2088         }
2089
2090         if (rdev->flags & RADEON_IS_IGP) {
2091                 rdev->asic->pm.get_memory_clock = NULL;
2092                 rdev->asic->pm.set_memory_clock = NULL;
2093         }
2094
2095         return 0;
2096 }
2097