drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_audio.h"
  31 #include "atom.h"
  32 #include <linux/backlight.h>
  33
  34 extern int atom_debug;
  35
  36 static u8
  37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  38 {
  39         u8 backlight_level;
  40         u32 bios_2_scratch;
  41
  42         if (rdev->family >= CHIP_R600)
  43                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  44         else
  45                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  46
  47         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  48                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  49
  50         return backlight_level;
  51 }
  52
  53 static void
  54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  55                                        u8 backlight_level)
  56 {
  57         u32 bios_2_scratch;
  58
  59         if (rdev->family >= CHIP_R600)
  60                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  61         else
  62                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  63
  64         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  65         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  66                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  67
  68         if (rdev->family >= CHIP_R600)
  69                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  70         else
  71                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  72 }
  73
  74 u8
  75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  76 {
  77         struct drm_device *dev = radeon_encoder->base.dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79
  80         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  81                 return 0;
  82
  83         return radeon_atom_get_backlight_level_from_reg(rdev);
  84 }
  85
  86 void
  87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  88 {
  89         struct drm_encoder *encoder = &radeon_encoder->base;
  90         struct drm_device *dev = radeon_encoder->base.dev;
  91         struct radeon_device *rdev = dev->dev_private;
  92         struct radeon_encoder_atom_dig *dig;
  93         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  94         int index;
  95
  96         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  97                 return;
  98
  99         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 100             radeon_encoder->enc_priv) {
 101                 dig = radeon_encoder->enc_priv;
 102                 dig->backlight_level = level;
 103                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 104
 105                 switch (radeon_encoder->encoder_id) {
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 107                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 108                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 109                         if (dig->backlight_level == 0) {
 110                                 args.ucAction = ATOM_LCD_BLOFF;
 111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 112                         } else {
 113                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 114                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 115                                 args.ucAction = ATOM_LCD_BLON;
 116                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 117                         }
 118                         break;
 119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 120                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 123                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 124                         if (dig->backlight_level == 0)
 125                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 126                         else {
 127                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 128                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 129                         }
 130                         break;
 131                 default:
 132                         break;
 133                 }
 134         }
 135 }
 136
 137 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 138
 139 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 140 {
 141         u8 level;
 142
 143         /* Convert brightness to hardware level */
 144         if (bd->props.brightness < 0)
 145                 level = 0;
 146         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 147                 level = RADEON_MAX_BL_LEVEL;
 148         else
 149                 level = bd->props.brightness;
 150
 151         return level;
 152 }
 153
 154 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 155 {
 156         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 157         struct radeon_encoder *radeon_encoder = pdata->encoder;
 158
 159         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 160
 161         return 0;
 162 }
 163
 164 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 165 {
 166         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 167         struct radeon_encoder *radeon_encoder = pdata->encoder;
 168         struct drm_device *dev = radeon_encoder->base.dev;
 169         struct radeon_device *rdev = dev->dev_private;
 170
 171         return radeon_atom_get_backlight_level_from_reg(rdev);
 172 }
 173
 174 static const struct backlight_ops radeon_atom_backlight_ops = {
 175         .get_brightness = radeon_atom_backlight_get_brightness,
 176         .update_status  = radeon_atom_backlight_update_status,
 177 };
 178
 179 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 180                                 struct drm_connector *drm_connector)
 181 {
 182         struct drm_device *dev = radeon_encoder->base.dev;
 183         struct radeon_device *rdev = dev->dev_private;
 184         struct backlight_device *bd;
 185         struct backlight_properties props;
 186         struct radeon_backlight_privdata *pdata;
 187         struct radeon_encoder_atom_dig *dig;
 188         char bl_name[16];
 189
 190         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 191          * so don't register a backlight device
 192          */
 193         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 194             (rdev->pdev->device == 0x6741))
 195                 return;
 196
 197         if (!radeon_encoder->enc_priv)
 198                 return;
 199
 200         if (!rdev->is_atom_bios)
 201                 return;
 202
 203         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 204                 return;
 205
 206         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 207         if (!pdata) {
 208                 DRM_ERROR("Memory allocation failed\n");
 209                 goto error;
 210         }
 211
 212         memset(&props, 0, sizeof(props));
 213         props.max_brightness = RADEON_MAX_BL_LEVEL;
 214         props.type = BACKLIGHT_RAW;
 215         snprintf(bl_name, sizeof(bl_name),
 216                  "radeon_bl%d", dev->primary->index);
 217         bd = backlight_device_register(bl_name, drm_connector->kdev,
 218                                        pdata, &radeon_atom_backlight_ops, &props);
 219         if (IS_ERR(bd)) {
 220                 DRM_ERROR("Backlight registration failed\n");
 221                 goto error;
 222         }
 223
 224         pdata->encoder = radeon_encoder;
 225
 226         dig = radeon_encoder->enc_priv;
 227         dig->bl_dev = bd;
 228
 229         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 230         /* Set a reasonable default here if the level is 0 otherwise
 231          * fbdev will attempt to turn the backlight on after console
 232          * unblanking and it will try and restore 0 which turns the backlight
 233          * off again.
 234          */
 235         if (bd->props.brightness == 0)
 236                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 237         bd->props.power = FB_BLANK_UNBLANK;
 238         backlight_update_status(bd);
 239
 240         DRM_INFO("radeon atom DIG backlight initialized\n");
 241         rdev->mode_info.bl_encoder = radeon_encoder;
 242
 243         return;
 244
 245 error:
 246         kfree(pdata);
 247         return;
 248 }
 249
 250 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 251 {
 252         struct drm_device *dev = radeon_encoder->base.dev;
 253         struct radeon_device *rdev = dev->dev_private;
 254         struct backlight_device *bd = NULL;
 255         struct radeon_encoder_atom_dig *dig;
 256
 257         if (!radeon_encoder->enc_priv)
 258                 return;
 259
 260         if (!rdev->is_atom_bios)
 261                 return;
 262
 263         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 264                 return;
 265
 266         dig = radeon_encoder->enc_priv;
 267         bd = dig->bl_dev;
 268         dig->bl_dev = NULL;
 269
 270         if (bd) {
 271                 struct radeon_legacy_backlight_privdata *pdata;
 272
 273                 pdata = bl_get_data(bd);
 274                 backlight_device_unregister(bd);
 275                 kfree(pdata);
 276
 277                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 278         }
 279 }
 280
 281 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 282
 283 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 284 {
 285 }
 286
 287 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 288 {
 289 }
 290
 291 #endif
 292
 293 /* evil but including atombios.h is much worse */
 294 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 295                                 struct drm_display_mode *mode);
 296
 297 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 298                                    const struct drm_display_mode *mode,
 299                                    struct drm_display_mode *adjusted_mode)
 300 {
 301         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 302         struct drm_device *dev = encoder->dev;
 303         struct radeon_device *rdev = dev->dev_private;
 304
 305         /* set the active encoder to connector routing */
 306         radeon_encoder_set_active_device(encoder);
 307         drm_mode_set_crtcinfo(adjusted_mode, 0);
 308
 309         /* hw bug */
 310         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 311             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 312                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 313
 314         /* vertical FP must be at least 1 */
 315         if (mode->crtc_vsync_start == mode->crtc_vdisplay)
 316                 adjusted_mode->crtc_vsync_start++;
 317
 318         /* get the native mode for scaling */
 319         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 320                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 321         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 322                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 323                 if (tv_dac) {
 324                         if (tv_dac->tv_std == TV_STD_NTSC ||
 325                             tv_dac->tv_std == TV_STD_NTSC_J ||
 326                             tv_dac->tv_std == TV_STD_PAL_M)
 327                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 328                         else
 329                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 330                 }
 331         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 332                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 333         }
 334
 335         if (ASIC_IS_DCE3(rdev) &&
 336             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 337              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 338                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 339                 radeon_dp_set_link_config(connector, adjusted_mode);
 340         }
 341
 342         return true;
 343 }
 344
 345 static void
 346 atombios_dac_setup(struct drm_encoder *encoder, int action)
 347 {
 348         struct drm_device *dev = encoder->dev;
 349         struct radeon_device *rdev = dev->dev_private;
 350         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 351         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 352         int index = 0;
 353         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 354
 355         memset(&args, 0, sizeof(args));
 356
 357         switch (radeon_encoder->encoder_id) {
 358         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 359         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 360                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 361                 break;
 362         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 363         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 364                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 365                 break;
 366         }
 367
 368         args.ucAction = action;
 369
 370         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 371                 args.ucDacStandard = ATOM_DAC1_PS2;
 372         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 373                 args.ucDacStandard = ATOM_DAC1_CV;
 374         else {
 375                 switch (dac_info->tv_std) {
 376                 case TV_STD_PAL:
 377                 case TV_STD_PAL_M:
 378                 case TV_STD_SCART_PAL:
 379                 case TV_STD_SECAM:
 380                 case TV_STD_PAL_CN:
 381                         args.ucDacStandard = ATOM_DAC1_PAL;
 382                         break;
 383                 case TV_STD_NTSC:
 384                 case TV_STD_NTSC_J:
 385                 case TV_STD_PAL_60:
 386                 default:
 387                         args.ucDacStandard = ATOM_DAC1_NTSC;
 388                         break;
 389                 }
 390         }
 391         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 392
 393         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 394
 395 }
 396
 397 static void
 398 atombios_tv_setup(struct drm_encoder *encoder, int action)
 399 {
 400         struct drm_device *dev = encoder->dev;
 401         struct radeon_device *rdev = dev->dev_private;
 402         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 403         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 404         int index = 0;
 405         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 406
 407         memset(&args, 0, sizeof(args));
 408
 409         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 410
 411         args.sTVEncoder.ucAction = action;
 412
 413         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 414                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 415         else {
 416                 switch (dac_info->tv_std) {
 417                 case TV_STD_NTSC:
 418                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 419                         break;
 420                 case TV_STD_PAL:
 421                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 422                         break;
 423                 case TV_STD_PAL_M:
 424                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 425                         break;
 426                 case TV_STD_PAL_60:
 427                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 428                         break;
 429                 case TV_STD_NTSC_J:
 430                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 431                         break;
 432                 case TV_STD_SCART_PAL:
 433                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 434                         break;
 435                 case TV_STD_SECAM:
 436                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 437                         break;
 438                 case TV_STD_PAL_CN:
 439                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 440                         break;
 441                 default:
 442                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 443                         break;
 444                 }
 445         }
 446
 447         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 448
 449         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 450
 451 }
 452
 453 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 454 {
 455         int bpc = 8;
 456
 457         if (encoder->crtc) {
 458                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 459                 bpc = radeon_crtc->bpc;
 460         }
 461
 462         switch (bpc) {
 463         case 0:
 464                 return PANEL_BPC_UNDEFINE;
 465         case 6:
 466                 return PANEL_6BIT_PER_COLOR;
 467         case 8:
 468         default:
 469                 return PANEL_8BIT_PER_COLOR;
 470         case 10:
 471                 return PANEL_10BIT_PER_COLOR;
 472         case 12:
 473                 return PANEL_12BIT_PER_COLOR;
 474         case 16:
 475                 return PANEL_16BIT_PER_COLOR;
 476         }
 477 }
 478
 479 union dvo_encoder_control {
 480         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 481         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 482         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 483         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 484 };
 485
 486 void
 487 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 488 {
 489         struct drm_device *dev = encoder->dev;
 490         struct radeon_device *rdev = dev->dev_private;
 491         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 492         union dvo_encoder_control args;
 493         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 494         uint8_t frev, crev;
 495
 496         memset(&args, 0, sizeof(args));
 497
 498         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 499                 return;
 500
 501         /* some R4xx chips have the wrong frev */
 502         if (rdev->family <= CHIP_RV410)
 503                 frev = 1;
 504
 505         switch (frev) {
 506         case 1:
 507                 switch (crev) {
 508                 case 1:
 509                         /* R4xx, R5xx */
 510                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 511
 512                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 513                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 514
 515                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 516                         break;
 517                 case 2:
 518                         /* RS600/690/740 */
 519                         args.dvo.sDVOEncoder.ucAction = action;
 520                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 521                         /* DFP1, CRT1, TV1 depending on the type of port */
 522                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 523
 524                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 525                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 526                         break;
 527                 case 3:
 528                         /* R6xx */
 529                         args.dvo_v3.ucAction = action;
 530                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 531                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 532                         break;
 533                 case 4:
 534                         /* DCE8 */
 535                         args.dvo_v4.ucAction = action;
 536                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 537                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 538                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 539                         break;
 540                 default:
 541                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 542                         break;
 543                 }
 544                 break;
 545         default:
 546                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 547                 break;
 548         }
 549
 550         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 551 }
 552
 553 union lvds_encoder_control {
 554         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 555         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 556 };
 557
 558 void
 559 atombios_digital_setup(struct drm_encoder *encoder, int action)
 560 {
 561         struct drm_device *dev = encoder->dev;
 562         struct radeon_device *rdev = dev->dev_private;
 563         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 564         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 565         union lvds_encoder_control args;
 566         int index = 0;
 567         int hdmi_detected = 0;
 568         uint8_t frev, crev;
 569
 570         if (!dig)
 571                 return;
 572
 573         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 574                 hdmi_detected = 1;
 575
 576         memset(&args, 0, sizeof(args));
 577
 578         switch (radeon_encoder->encoder_id) {
 579         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 580                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 581                 break;
 582         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 583         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 584                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 585                 break;
 586         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 587                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 588                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 589                 else
 590                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 591                 break;
 592         }
 593
 594         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 595                 return;
 596
 597         switch (frev) {
 598         case 1:
 599         case 2:
 600                 switch (crev) {
 601                 case 1:
 602                         args.v1.ucMisc = 0;
 603                         args.v1.ucAction = action;
 604                         if (hdmi_detected)
 605                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 606                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 607                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 608                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 609                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 610                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 611                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 612                         } else {
 613                                 if (dig->linkb)
 614                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 615                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 616                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 617                                 /*if (pScrn->rgbBits == 8) */
 618                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 619                         }
 620                         break;
 621                 case 2:
 622                 case 3:
 623                         args.v2.ucMisc = 0;
 624                         args.v2.ucAction = action;
 625                         if (crev == 3) {
 626                                 if (dig->coherent_mode)
 627                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 628                         }
 629                         if (hdmi_detected)
 630                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 631                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 632                         args.v2.ucTruncate = 0;
 633                         args.v2.ucSpatial = 0;
 634                         args.v2.ucTemporal = 0;
 635                         args.v2.ucFRC = 0;
 636                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 637                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 638                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 639                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 640                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 641                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 642                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 643                                 }
 644                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 645                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 646                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 647                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 648                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 649                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 650                                 }
 651                         } else {
 652                                 if (dig->linkb)
 653                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 654                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 655                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 656                         }
 657                         break;
 658                 default:
 659                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 660                         break;
 661                 }
 662                 break;
 663         default:
 664                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 665                 break;
 666         }
 667
 668         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 669 }
 670
 671 int
 672 atombios_get_encoder_mode(struct drm_encoder *encoder)
 673 {
 674         struct drm_device *dev = encoder->dev;
 675         struct radeon_device *rdev = dev->dev_private;
 676         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 677         struct drm_connector *connector;
 678         struct radeon_connector *radeon_connector;
 679         struct radeon_connector_atom_dig *dig_connector;
 680         struct radeon_encoder_atom_dig *dig_enc;
 681
 682         if (radeon_encoder_is_digital(encoder)) {
 683                 dig_enc = radeon_encoder->enc_priv;
 684                 if (dig_enc->active_mst_links)
 685                         return ATOM_ENCODER_MODE_DP_MST;
 686         }
 687         if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 688                 return ATOM_ENCODER_MODE_DP_MST;
 689         /* dp bridges are always DP */
 690         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 691                 return ATOM_ENCODER_MODE_DP;
 692
 693         /* DVO is always DVO */
 694         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 695             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 696                 return ATOM_ENCODER_MODE_DVO;
 697
 698         connector = radeon_get_connector_for_encoder(encoder);
 699         /* if we don't have an active device yet, just use one of
 700          * the connectors tied to the encoder.
 701          */
 702         if (!connector)
 703                 connector = radeon_get_connector_for_encoder_init(encoder);
 704         radeon_connector = to_radeon_connector(connector);
 705
 706         switch (connector->connector_type) {
 707         case DRM_MODE_CONNECTOR_DVII:
 708         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 709                 if (radeon_audio != 0) {
 710                         if (radeon_connector->use_digital &&
 711                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 712                                 return ATOM_ENCODER_MODE_HDMI;
 713                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 714                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 715                                 return ATOM_ENCODER_MODE_HDMI;
 716                         else if (radeon_connector->use_digital)
 717                                 return ATOM_ENCODER_MODE_DVI;
 718                         else
 719                                 return ATOM_ENCODER_MODE_CRT;
 720                 } else if (radeon_connector->use_digital) {
 721                         return ATOM_ENCODER_MODE_DVI;
 722                 } else {
 723                         return ATOM_ENCODER_MODE_CRT;
 724                 }
 725                 break;
 726         case DRM_MODE_CONNECTOR_DVID:
 727         case DRM_MODE_CONNECTOR_HDMIA:
 728         default:
 729                 if (radeon_audio != 0) {
 730                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 731                                 return ATOM_ENCODER_MODE_HDMI;
 732                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 733                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 734                                 return ATOM_ENCODER_MODE_HDMI;
 735                         else
 736                                 return ATOM_ENCODER_MODE_DVI;
 737                 } else {
 738                         return ATOM_ENCODER_MODE_DVI;
 739                 }
 740                 break;
 741         case DRM_MODE_CONNECTOR_LVDS:
 742                 return ATOM_ENCODER_MODE_LVDS;
 743                 break;
 744         case DRM_MODE_CONNECTOR_DisplayPort:
 745                 dig_connector = radeon_connector->con_priv;
 746                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 747                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 748                         if (radeon_audio != 0 &&
 749                             drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 750                             ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 751                                 return ATOM_ENCODER_MODE_DP_AUDIO;
 752                         return ATOM_ENCODER_MODE_DP;
 753                 } else if (radeon_audio != 0) {
 754                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 755                                 return ATOM_ENCODER_MODE_HDMI;
 756                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 757                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 758                                 return ATOM_ENCODER_MODE_HDMI;
 759                         else
 760                                 return ATOM_ENCODER_MODE_DVI;
 761                 } else {
 762                         return ATOM_ENCODER_MODE_DVI;
 763                 }
 764                 break;
 765         case DRM_MODE_CONNECTOR_eDP:
 766                 if (radeon_audio != 0 &&
 767                     drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 768                     ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 769                         return ATOM_ENCODER_MODE_DP_AUDIO;
 770                 return ATOM_ENCODER_MODE_DP;
 771         case DRM_MODE_CONNECTOR_DVIA:
 772         case DRM_MODE_CONNECTOR_VGA:
 773                 return ATOM_ENCODER_MODE_CRT;
 774                 break;
 775         case DRM_MODE_CONNECTOR_Composite:
 776         case DRM_MODE_CONNECTOR_SVIDEO:
 777         case DRM_MODE_CONNECTOR_9PinDIN:
 778                 /* fix me */
 779                 return ATOM_ENCODER_MODE_TV;
 780                 /*return ATOM_ENCODER_MODE_CV;*/
 781                 break;
 782         }
 783 }
 784
 785 /*
 786  * DIG Encoder/Transmitter Setup
 787  *
 788  * DCE 3.0/3.1
 789  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 790  * Supports up to 3 digital outputs
 791  * - 2 DIG encoder blocks.
 792  * DIG1 can drive UNIPHY link A or link B
 793  * DIG2 can drive UNIPHY link B or LVTMA
 794  *
 795  * DCE 3.2
 796  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 797  * Supports up to 5 digital outputs
 798  * - 2 DIG encoder blocks.
 799  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 800  *
 801  * DCE 4.0/5.0/6.0
 802  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 803  * Supports up to 6 digital outputs
 804  * - 6 DIG encoder blocks.
 805  * - DIG to PHY mapping is hardcoded
 806  * DIG1 drives UNIPHY0 link A, A+B
 807  * DIG2 drives UNIPHY0 link B
 808  * DIG3 drives UNIPHY1 link A, A+B
 809  * DIG4 drives UNIPHY1 link B
 810  * DIG5 drives UNIPHY2 link A, A+B
 811  * DIG6 drives UNIPHY2 link B
 812  *
 813  * DCE 4.1
 814  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 815  * Supports up to 6 digital outputs
 816  * - 2 DIG encoder blocks.
 817  * llano
 818  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 819  * ontario
 820  * DIG1 drives UNIPHY0/1/2 link A
 821  * DIG2 drives UNIPHY0/1/2 link B
 822  *
 823  * Routing
 824  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 825  * Examples:
 826  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 827  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 828  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 829  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 830  */
 831
 832 union dig_encoder_control {
 833         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 834         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 835         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 836         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 837 };
 838
 839 void
 840 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 841 {
 842         struct drm_device *dev = encoder->dev;
 843         struct radeon_device *rdev = dev->dev_private;
 844         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 845         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 846         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 847         union dig_encoder_control args;
 848         int index = 0;
 849         uint8_t frev, crev;
 850         int dp_clock = 0;
 851         int dp_lane_count = 0;
 852         int hpd_id = RADEON_HPD_NONE;
 853
 854         if (connector) {
 855                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 856                 struct radeon_connector_atom_dig *dig_connector =
 857                         radeon_connector->con_priv;
 858
 859                 dp_clock = dig_connector->dp_clock;
 860                 dp_lane_count = dig_connector->dp_lane_count;
 861                 hpd_id = radeon_connector->hpd.hpd;
 862         }
 863
 864         /* no dig encoder assigned */
 865         if (dig->dig_encoder == -1)
 866                 return;
 867
 868         memset(&args, 0, sizeof(args));
 869
 870         if (ASIC_IS_DCE4(rdev))
 871                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 872         else {
 873                 if (dig->dig_encoder)
 874                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 875                 else
 876                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 877         }
 878
 879         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 880                 return;
 881
 882         switch (frev) {
 883         case 1:
 884                 switch (crev) {
 885                 case 1:
 886                         args.v1.ucAction = action;
 887                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 888                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 889                                 args.v3.ucPanelMode = panel_mode;
 890                         else
 891                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 892
 893                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 894                                 args.v1.ucLaneNum = dp_lane_count;
 895                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 896                                 args.v1.ucLaneNum = 8;
 897                         else
 898                                 args.v1.ucLaneNum = 4;
 899
 900                         switch (radeon_encoder->encoder_id) {
 901                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 902                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 903                                 break;
 904                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 905                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 906                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 907                                 break;
 908                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 909                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 910                                 break;
 911                         }
 912                         if (dig->linkb)
 913                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 914                         else
 915                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 916
 917                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 918                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 919
 920                         break;
 921                 case 2:
 922                 case 3:
 923                         args.v3.ucAction = action;
 924                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 925                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 926                                 args.v3.ucPanelMode = panel_mode;
 927                         else
 928                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 929
 930                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 931                                 args.v3.ucLaneNum = dp_lane_count;
 932                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 933                                 args.v3.ucLaneNum = 8;
 934                         else
 935                                 args.v3.ucLaneNum = 4;
 936
 937                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 938                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 939                         if (enc_override != -1)
 940                                 args.v3.acConfig.ucDigSel = enc_override;
 941                         else
 942                                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 943                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 944                         break;
 945                 case 4:
 946                         args.v4.ucAction = action;
 947                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 948                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 949                                 args.v4.ucPanelMode = panel_mode;
 950                         else
 951                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 952
 953                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 954                                 args.v4.ucLaneNum = dp_lane_count;
 955                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 956                                 args.v4.ucLaneNum = 8;
 957                         else
 958                                 args.v4.ucLaneNum = 4;
 959
 960                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 961                                 if (dp_clock == 540000)
 962                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 963                                 else if (dp_clock == 324000)
 964                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 965                                 else if (dp_clock == 270000)
 966                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 967                                 else
 968                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 969                         }
 970
 971                         if (enc_override != -1)
 972                                 args.v4.acConfig.ucDigSel = enc_override;
 973                         else
 974                                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 975                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 976                         if (hpd_id == RADEON_HPD_NONE)
 977                                 args.v4.ucHPD_ID = 0;
 978                         else
 979                                 args.v4.ucHPD_ID = hpd_id + 1;
 980                         break;
 981                 default:
 982                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 983                         break;
 984                 }
 985                 break;
 986         default:
 987                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 988                 break;
 989         }
 990
 991         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 992
 993 }
 994
 995 void
 996 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 997 {
 998         atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
 999 }
1000
1001 union dig_transmitter_control {
1002         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1003         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1004         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1005         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1006         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1007 };
1008
1009 void
1010 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1011 {
1012         struct drm_device *dev = encoder->dev;
1013         struct radeon_device *rdev = dev->dev_private;
1014         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1015         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1016         struct drm_connector *connector;
1017         union dig_transmitter_control args;
1018         int index = 0;
1019         uint8_t frev, crev;
1020         bool is_dp = false;
1021         int pll_id = 0;
1022         int dp_clock = 0;
1023         int dp_lane_count = 0;
1024         int connector_object_id = 0;
1025         int igp_lane_info = 0;
1026         int dig_encoder = dig->dig_encoder;
1027         int hpd_id = RADEON_HPD_NONE;
1028
1029         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1030                 connector = radeon_get_connector_for_encoder_init(encoder);
1031                 /* just needed to avoid bailing in the encoder check.  the encoder
1032                  * isn't used for init
1033                  */
1034                 dig_encoder = 0;
1035         } else
1036                 connector = radeon_get_connector_for_encoder(encoder);
1037
1038         if (connector) {
1039                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1040                 struct radeon_connector_atom_dig *dig_connector =
1041                         radeon_connector->con_priv;
1042
1043                 hpd_id = radeon_connector->hpd.hpd;
1044                 dp_clock = dig_connector->dp_clock;
1045                 dp_lane_count = dig_connector->dp_lane_count;
1046                 connector_object_id =
1047                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1048                 igp_lane_info = dig_connector->igp_lane_info;
1049         }
1050
1051         if (encoder->crtc) {
1052                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1053                 pll_id = radeon_crtc->pll_id;
1054         }
1055
1056         /* no dig encoder assigned */
1057         if (dig_encoder == -1)
1058                 return;
1059
1060         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1061                 is_dp = true;
1062
1063         memset(&args, 0, sizeof(args));
1064
1065         switch (radeon_encoder->encoder_id) {
1066         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1067                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1068                 break;
1069         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1070         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1071         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1072         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1073                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1074                 break;
1075         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1076                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1077                 break;
1078         }
1079
1080         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1081                 return;
1082
1083         switch (frev) {
1084         case 1:
1085                 switch (crev) {
1086                 case 1:
1087                         args.v1.ucAction = action;
1088                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1089                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1090                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1091                                 args.v1.asMode.ucLaneSel = lane_num;
1092                                 args.v1.asMode.ucLaneSet = lane_set;
1093                         } else {
1094                                 if (is_dp)
1095                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1096                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1097                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1098                                 else
1099                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1100                         }
1101
1102                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1103
1104                         if (dig_encoder)
1105                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1106                         else
1107                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1108
1109                         if ((rdev->flags & RADEON_IS_IGP) &&
1110                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1111                                 if (is_dp ||
1112                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1113                                         if (igp_lane_info & 0x1)
1114                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1115                                         else if (igp_lane_info & 0x2)
1116                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1117                                         else if (igp_lane_info & 0x4)
1118                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1119                                         else if (igp_lane_info & 0x8)
1120                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1121                                 } else {
1122                                         if (igp_lane_info & 0x3)
1123                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1124                                         else if (igp_lane_info & 0xc)
1125                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1126                                 }
1127                         }
1128
1129                         if (dig->linkb)
1130                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1131                         else
1132                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1133
1134                         if (is_dp)
1135                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1136                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1137                                 if (dig->coherent_mode)
1138                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1140                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1141                         }
1142                         break;
1143                 case 2:
1144                         args.v2.ucAction = action;
1145                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1146                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1147                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1148                                 args.v2.asMode.ucLaneSel = lane_num;
1149                                 args.v2.asMode.ucLaneSet = lane_set;
1150                         } else {
1151                                 if (is_dp)
1152                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1153                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1154                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1155                                 else
1156                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1157                         }
1158
1159                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1160                         if (dig->linkb)
1161                                 args.v2.acConfig.ucLinkSel = 1;
1162
1163                         switch (radeon_encoder->encoder_id) {
1164                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1165                                 args.v2.acConfig.ucTransmitterSel = 0;
1166                                 break;
1167                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1168                                 args.v2.acConfig.ucTransmitterSel = 1;
1169                                 break;
1170                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1171                                 args.v2.acConfig.ucTransmitterSel = 2;
1172                                 break;
1173                         }
1174
1175                         if (is_dp) {
1176                                 args.v2.acConfig.fCoherentMode = 1;
1177                                 args.v2.acConfig.fDPConnector = 1;
1178                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1179                                 if (dig->coherent_mode)
1180                                         args.v2.acConfig.fCoherentMode = 1;
1181                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1182                                         args.v2.acConfig.fDualLinkConnector = 1;
1183                         }
1184                         break;
1185                 case 3:
1186                         args.v3.ucAction = action;
1187                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1188                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1189                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1190                                 args.v3.asMode.ucLaneSel = lane_num;
1191                                 args.v3.asMode.ucLaneSet = lane_set;
1192                         } else {
1193                                 if (is_dp)
1194                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1195                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1196                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1197                                 else
1198                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1199                         }
1200
1201                         if (is_dp)
1202                                 args.v3.ucLaneNum = dp_lane_count;
1203                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1204                                 args.v3.ucLaneNum = 8;
1205                         else
1206                                 args.v3.ucLaneNum = 4;
1207
1208                         if (dig->linkb)
1209                                 args.v3.acConfig.ucLinkSel = 1;
1210                         if (dig_encoder & 1)
1211                                 args.v3.acConfig.ucEncoderSel = 1;
1212
1213                         /* Select the PLL for the PHY
1214                          * DP PHY should be clocked from external src if there is
1215                          * one.
1216                          */
1217                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1218                         if (is_dp && rdev->clock.dp_extclk)
1219                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1220                         else
1221                                 args.v3.acConfig.ucRefClkSource = pll_id;
1222
1223                         switch (radeon_encoder->encoder_id) {
1224                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1225                                 args.v3.acConfig.ucTransmitterSel = 0;
1226                                 break;
1227                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1228                                 args.v3.acConfig.ucTransmitterSel = 1;
1229                                 break;
1230                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1231                                 args.v3.acConfig.ucTransmitterSel = 2;
1232                                 break;
1233                         }
1234
1235                         if (is_dp)
1236                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1237                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1238                                 if (dig->coherent_mode)
1239                                         args.v3.acConfig.fCoherentMode = 1;
1240                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1241                                         args.v3.acConfig.fDualLinkConnector = 1;
1242                         }
1243                         break;
1244                 case 4:
1245                         args.v4.ucAction = action;
1246                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1247                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1248                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1249                                 args.v4.asMode.ucLaneSel = lane_num;
1250                                 args.v4.asMode.ucLaneSet = lane_set;
1251                         } else {
1252                                 if (is_dp)
1253                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1254                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1255                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1256                                 else
1257                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1258                         }
1259
1260                         if (is_dp)
1261                                 args.v4.ucLaneNum = dp_lane_count;
1262                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1263                                 args.v4.ucLaneNum = 8;
1264                         else
1265                                 args.v4.ucLaneNum = 4;
1266
1267                         if (dig->linkb)
1268                                 args.v4.acConfig.ucLinkSel = 1;
1269                         if (dig_encoder & 1)
1270                                 args.v4.acConfig.ucEncoderSel = 1;
1271
1272                         /* Select the PLL for the PHY
1273                          * DP PHY should be clocked from external src if there is
1274                          * one.
1275                          */
1276                         /* On DCE5 DCPLL usually generates the DP ref clock */
1277                         if (is_dp) {
1278                                 if (rdev->clock.dp_extclk)
1279                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1280                                 else
1281                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1282                         } else
1283                                 args.v4.acConfig.ucRefClkSource = pll_id;
1284
1285                         switch (radeon_encoder->encoder_id) {
1286                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1287                                 args.v4.acConfig.ucTransmitterSel = 0;
1288                                 break;
1289                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1290                                 args.v4.acConfig.ucTransmitterSel = 1;
1291                                 break;
1292                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1293                                 args.v4.acConfig.ucTransmitterSel = 2;
1294                                 break;
1295                         }
1296
1297                         if (is_dp)
1298                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1299                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1300                                 if (dig->coherent_mode)
1301                                         args.v4.acConfig.fCoherentMode = 1;
1302                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1303                                         args.v4.acConfig.fDualLinkConnector = 1;
1304                         }
1305                         break;
1306                 case 5:
1307                         args.v5.ucAction = action;
1308                         if (is_dp)
1309                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1310                         else
1311                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1312
1313                         switch (radeon_encoder->encoder_id) {
1314                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1315                                 if (dig->linkb)
1316                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1317                                 else
1318                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1319                                 break;
1320                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1321                                 if (dig->linkb)
1322                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1323                                 else
1324                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1325                                 break;
1326                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1327                                 if (dig->linkb)
1328                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1329                                 else
1330                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1331                                 break;
1332                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1333                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1334                                 break;
1335                         }
1336                         if (is_dp)
1337                                 args.v5.ucLaneNum = dp_lane_count;
1338                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1339                                 args.v5.ucLaneNum = 8;
1340                         else
1341                                 args.v5.ucLaneNum = 4;
1342                         args.v5.ucConnObjId = connector_object_id;
1343                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1344
1345                         if (is_dp && rdev->clock.dp_extclk)
1346                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1347                         else
1348                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1349
1350                         if (is_dp)
1351                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1352                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1353                                 if (dig->coherent_mode)
1354                                         args.v5.asConfig.ucCoherentMode = 1;
1355                         }
1356                         if (hpd_id == RADEON_HPD_NONE)
1357                                 args.v5.asConfig.ucHPDSel = 0;
1358                         else
1359                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1360                         args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1361                         args.v5.ucDPLaneSet = lane_set;
1362                         break;
1363                 default:
1364                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1365                         break;
1366                 }
1367                 break;
1368         default:
1369                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1370                 break;
1371         }
1372
1373         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1374 }
1375
1376 void
1377 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1378 {
1379         atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1380 }
1381
1382 bool
1383 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1384 {
1385         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1386         struct drm_device *dev = radeon_connector->base.dev;
1387         struct radeon_device *rdev = dev->dev_private;
1388         union dig_transmitter_control args;
1389         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1390         uint8_t frev, crev;
1391
1392         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1393                 goto done;
1394
1395         if (!ASIC_IS_DCE4(rdev))
1396                 goto done;
1397
1398         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1399             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1400                 goto done;
1401
1402         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1403                 goto done;
1404
1405         memset(&args, 0, sizeof(args));
1406
1407         args.v1.ucAction = action;
1408
1409         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1410
1411         /* wait for the panel to power up */
1412         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1413                 int i;
1414
1415                 for (i = 0; i < 300; i++) {
1416                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1417                                 return true;
1418                         mdelay(1);
1419                 }
1420                 return false;
1421         }
1422 done:
1423         return true;
1424 }
1425
1426 union external_encoder_control {
1427         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1428         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1429 };
1430
1431 static void
1432 atombios_external_encoder_setup(struct drm_encoder *encoder,
1433                                 struct drm_encoder *ext_encoder,
1434                                 int action)
1435 {
1436         struct drm_device *dev = encoder->dev;
1437         struct radeon_device *rdev = dev->dev_private;
1438         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1439         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1440         union external_encoder_control args;
1441         struct drm_connector *connector;
1442         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1443         u8 frev, crev;
1444         int dp_clock = 0;
1445         int dp_lane_count = 0;
1446         int connector_object_id = 0;
1447         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1448
1449         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1450                 connector = radeon_get_connector_for_encoder_init(encoder);
1451         else
1452                 connector = radeon_get_connector_for_encoder(encoder);
1453
1454         if (connector) {
1455                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1456                 struct radeon_connector_atom_dig *dig_connector =
1457                         radeon_connector->con_priv;
1458
1459                 dp_clock = dig_connector->dp_clock;
1460                 dp_lane_count = dig_connector->dp_lane_count;
1461                 connector_object_id =
1462                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1463         }
1464
1465         memset(&args, 0, sizeof(args));
1466
1467         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1468                 return;
1469
1470         switch (frev) {
1471         case 1:
1472                 /* no params on frev 1 */
1473                 break;
1474         case 2:
1475                 switch (crev) {
1476                 case 1:
1477                 case 2:
1478                         args.v1.sDigEncoder.ucAction = action;
1479                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1480                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1481
1482                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1483                                 if (dp_clock == 270000)
1484                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1485                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1486                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1487                                 args.v1.sDigEncoder.ucLaneNum = 8;
1488                         else
1489                                 args.v1.sDigEncoder.ucLaneNum = 4;
1490                         break;
1491                 case 3:
1492                         args.v3.sExtEncoder.ucAction = action;
1493                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1494                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1495                         else
1496                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1497                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1498
1499                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1500                                 if (dp_clock == 270000)
1501                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1502                                 else if (dp_clock == 540000)
1503                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1504                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1505                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1506                                 args.v3.sExtEncoder.ucLaneNum = 8;
1507                         else
1508                                 args.v3.sExtEncoder.ucLaneNum = 4;
1509                         switch (ext_enum) {
1510                         case GRAPH_OBJECT_ENUM_ID1:
1511                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1512                                 break;
1513                         case GRAPH_OBJECT_ENUM_ID2:
1514                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1515                                 break;
1516                         case GRAPH_OBJECT_ENUM_ID3:
1517                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1518                                 break;
1519                         }
1520                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1521                         break;
1522                 default:
1523                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1524                         return;
1525                 }
1526                 break;
1527         default:
1528                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1529                 return;
1530         }
1531         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1532 }
1533
1534 static void
1535 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1536 {
1537         struct drm_device *dev = encoder->dev;
1538         struct radeon_device *rdev = dev->dev_private;
1539         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1540         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1541         ENABLE_YUV_PS_ALLOCATION args;
1542         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1543         uint32_t temp, reg;
1544
1545         memset(&args, 0, sizeof(args));
1546
1547         if (rdev->family >= CHIP_R600)
1548                 reg = R600_BIOS_3_SCRATCH;
1549         else
1550                 reg = RADEON_BIOS_3_SCRATCH;
1551
1552         /* XXX: fix up scratch reg handling */
1553         temp = RREG32(reg);
1554         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1555                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1556                              (radeon_crtc->crtc_id << 18)));
1557         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1558                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1559         else
1560                 WREG32(reg, 0);
1561
1562         if (enable)
1563                 args.ucEnable = ATOM_ENABLE;
1564         args.ucCRTC = radeon_crtc->crtc_id;
1565
1566         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1567
1568         WREG32(reg, temp);
1569 }
1570
1571 static void
1572 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1573 {
1574         struct drm_device *dev = encoder->dev;
1575         struct radeon_device *rdev = dev->dev_private;
1576         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1577         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1578         int index = 0;
1579
1580         memset(&args, 0, sizeof(args));
1581
1582         switch (radeon_encoder->encoder_id) {
1583         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1584         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1585                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1586                 break;
1587         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1588         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1589         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1590                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1591                 break;
1592         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1593                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1594                 break;
1595         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1596                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1597                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1598                 else
1599                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1600                 break;
1601         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1602         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1603                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1604                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1605                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1606                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1607                 else
1608                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1609                 break;
1610         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1611         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1612                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1613                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1614                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1615                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1616                 else
1617                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1618                 break;
1619         default:
1620                 return;
1621         }
1622
1623         switch (mode) {
1624         case DRM_MODE_DPMS_ON:
1625                 args.ucAction = ATOM_ENABLE;
1626                 /* workaround for DVOOutputControl on some RS690 systems */
1627                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1628                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1629                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1630                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1631                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1632                 } else
1633                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1634                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1635                         if (rdev->mode_info.bl_encoder) {
1636                                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1637
1638                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1639                         } else {
1640                                 args.ucAction = ATOM_LCD_BLON;
1641                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1642                         }
1643                 }
1644                 break;
1645         case DRM_MODE_DPMS_STANDBY:
1646         case DRM_MODE_DPMS_SUSPEND:
1647         case DRM_MODE_DPMS_OFF:
1648                 args.ucAction = ATOM_DISABLE;
1649                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1650                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1651                         args.ucAction = ATOM_LCD_BLOFF;
1652                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1653                 }
1654                 break;
1655         }
1656 }
1657
1658 static void
1659 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1660 {
1661         struct drm_device *dev = encoder->dev;
1662         struct radeon_device *rdev = dev->dev_private;
1663         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1664         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1665         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1666         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1667         struct radeon_connector *radeon_connector = NULL;
1668         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1669         bool travis_quirk = false;
1670
1671         if (connector) {
1672                 radeon_connector = to_radeon_connector(connector);
1673                 radeon_dig_connector = radeon_connector->con_priv;
1674                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1675                      ENCODER_OBJECT_ID_TRAVIS) &&
1676                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1677                     !ASIC_IS_DCE5(rdev))
1678                         travis_quirk = true;
1679         }
1680
1681         switch (mode) {
1682         case DRM_MODE_DPMS_ON:
1683                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1684                         if (!connector)
1685                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1686                         else
1687                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1688
1689                         /* setup and enable the encoder */
1690                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1691                         atombios_dig_encoder_setup(encoder,
1692                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1693                                                    dig->panel_mode);
1694                         if (ext_encoder) {
1695                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1696                                         atombios_external_encoder_setup(encoder, ext_encoder,
1697                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1698                         }
1699                 } else if (ASIC_IS_DCE4(rdev)) {
1700                         /* setup and enable the encoder */
1701                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1702                 } else {
1703                         /* setup and enable the encoder and transmitter */
1704                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1705                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1706                 }
1707                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1708                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1709                                 atombios_set_edp_panel_power(connector,
1710                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1711                                 radeon_dig_connector->edp_on = true;
1712                         }
1713                 }
1714                 /* enable the transmitter */
1715                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1716                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1717                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1718                         radeon_dp_link_train(encoder, connector);
1719                         if (ASIC_IS_DCE4(rdev))
1720                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1721                 }
1722                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1723                         if (rdev->mode_info.bl_encoder)
1724                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1725                         else
1726                                 atombios_dig_transmitter_setup(encoder,
1727                                                                ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1728                 }
1729                 if (ext_encoder)
1730                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1731                 break;
1732         case DRM_MODE_DPMS_STANDBY:
1733         case DRM_MODE_DPMS_SUSPEND:
1734         case DRM_MODE_DPMS_OFF:
1735
1736                 /* don't power off encoders with active MST links */
1737                 if (dig->active_mst_links)
1738                         return;
1739
1740                 if (ASIC_IS_DCE4(rdev)) {
1741                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1742                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1743                 }
1744                 if (ext_encoder)
1745                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1746                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1747                         atombios_dig_transmitter_setup(encoder,
1748                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1749
1750                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1751                     connector && !travis_quirk)
1752                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1753                 if (ASIC_IS_DCE4(rdev)) {
1754                         /* disable the transmitter */
1755                         atombios_dig_transmitter_setup(encoder,
1756                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1757                 } else {
1758                         /* disable the encoder and transmitter */
1759                         atombios_dig_transmitter_setup(encoder,
1760                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1761                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1762                 }
1763                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1764                         if (travis_quirk)
1765                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1766                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1767                                 atombios_set_edp_panel_power(connector,
1768                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1769                                 radeon_dig_connector->edp_on = false;
1770                         }
1771                 }
1772                 break;
1773         }
1774 }
1775
1776 static void
1777 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1778 {
1779         struct drm_device *dev = encoder->dev;
1780         struct radeon_device *rdev = dev->dev_private;
1781         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1782         int encoder_mode = atombios_get_encoder_mode(encoder);
1783
1784         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1785                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1786                   radeon_encoder->active_device);
1787
1788         if ((radeon_audio != 0) &&
1789             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1790              ENCODER_MODE_IS_DP(encoder_mode)))
1791                 radeon_audio_dpms(encoder, mode);
1792
1793         switch (radeon_encoder->encoder_id) {
1794         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1795         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1796         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1797         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1798         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1799         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1800         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1801         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1802                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1803                 break;
1804         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1805         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1806         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1807         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1808         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1809                 radeon_atom_encoder_dpms_dig(encoder, mode);
1810                 break;
1811         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1812                 if (ASIC_IS_DCE5(rdev)) {
1813                         switch (mode) {
1814                         case DRM_MODE_DPMS_ON:
1815                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1816                                 break;
1817                         case DRM_MODE_DPMS_STANDBY:
1818                         case DRM_MODE_DPMS_SUSPEND:
1819                         case DRM_MODE_DPMS_OFF:
1820                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1821                                 break;
1822                         }
1823                 } else if (ASIC_IS_DCE3(rdev))
1824                         radeon_atom_encoder_dpms_dig(encoder, mode);
1825                 else
1826                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1827                 break;
1828         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1829         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1830                 if (ASIC_IS_DCE5(rdev)) {
1831                         switch (mode) {
1832                         case DRM_MODE_DPMS_ON:
1833                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1834                                 break;
1835                         case DRM_MODE_DPMS_STANDBY:
1836                         case DRM_MODE_DPMS_SUSPEND:
1837                         case DRM_MODE_DPMS_OFF:
1838                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1839                                 break;
1840                         }
1841                 } else
1842                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1843                 break;
1844         default:
1845                 return;
1846         }
1847
1848         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1849
1850 }
1851
1852 union crtc_source_param {
1853         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1854         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1855 };
1856
1857 static void
1858 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1859 {
1860         struct drm_device *dev = encoder->dev;
1861         struct radeon_device *rdev = dev->dev_private;
1862         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1863         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1864         union crtc_source_param args;
1865         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1866         uint8_t frev, crev;
1867         struct radeon_encoder_atom_dig *dig;
1868
1869         memset(&args, 0, sizeof(args));
1870
1871         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1872                 return;
1873
1874         switch (frev) {
1875         case 1:
1876                 switch (crev) {
1877                 case 1:
1878                 default:
1879                         if (ASIC_IS_AVIVO(rdev))
1880                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1881                         else {
1882                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1883                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1884                                 } else {
1885                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1886                                 }
1887                         }
1888                         switch (radeon_encoder->encoder_id) {
1889                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1890                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1891                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1892                                 break;
1893                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1894                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1895                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1896                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1897                                 else
1898                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1899                                 break;
1900                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1901                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1902                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1903                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1904                                 break;
1905                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1906                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1907                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1908                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1909                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1910                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1911                                 else
1912                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1913                                 break;
1914                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1915                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1916                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1917                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1918                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1919                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1920                                 else
1921                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1922                                 break;
1923                         }
1924                         break;
1925                 case 2:
1926                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1927                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1928                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1929
1930                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1931                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1932                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1933                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1934                                 else
1935                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1936                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1937                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1938                         } else {
1939                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1940                         }
1941                         switch (radeon_encoder->encoder_id) {
1942                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1943                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1944                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1945                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1946                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1947                                 dig = radeon_encoder->enc_priv;
1948                                 switch (dig->dig_encoder) {
1949                                 case 0:
1950                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1951                                         break;
1952                                 case 1:
1953                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1954                                         break;
1955                                 case 2:
1956                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1957                                         break;
1958                                 case 3:
1959                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1960                                         break;
1961                                 case 4:
1962                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1963                                         break;
1964                                 case 5:
1965                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1966                                         break;
1967                                 case 6:
1968                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1969                                         break;
1970                                 }
1971                                 break;
1972                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1973                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1974                                 break;
1975                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1976                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1977                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1978                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1979                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1980                                 else
1981                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1982                                 break;
1983                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1984                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1985                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1986                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1987                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1988                                 else
1989                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1990                                 break;
1991                         }
1992                         break;
1993                 }
1994                 break;
1995         default:
1996                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1997                 return;
1998         }
1999
2000         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2001
2002         /* update scratch regs with new routing */
2003         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2004 }
2005
2006 void
2007 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2008 {
2009         struct drm_device *dev = encoder->dev;
2010         struct radeon_device *rdev = dev->dev_private;
2011         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2012         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2013         uint8_t frev, crev;
2014         union crtc_source_param args;
2015
2016         memset(&args, 0, sizeof(args));
2017
2018         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2019                 return;
2020
2021         if (frev != 1 && crev != 2)
2022                 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2023
2024         args.v2.ucCRTC = radeon_crtc->crtc_id;
2025         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2026
2027         switch (fe) {
2028         case 0:
2029                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2030                 break;
2031         case 1:
2032                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2033                 break;
2034         case 2:
2035                 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2036                 break;
2037         case 3:
2038                 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2039                 break;
2040         case 4:
2041                 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2042                 break;
2043         case 5:
2044                 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2045                 break;
2046         case 6:
2047                 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2048                 break;
2049         }
2050         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2051 }
2052
2053 static void
2054 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2055                               struct drm_display_mode *mode)
2056 {
2057         struct drm_device *dev = encoder->dev;
2058         struct radeon_device *rdev = dev->dev_private;
2059         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2060         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2061
2062         /* Funky macbooks */
2063         if ((dev->pdev->device == 0x71C5) &&
2064             (dev->pdev->subsystem_vendor == 0x106b) &&
2065             (dev->pdev->subsystem_device == 0x0080)) {
2066                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2067                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2068
2069                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2070                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2071
2072                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2073                 }
2074         }
2075
2076         /* set scaler clears this on some chips */
2077         if (ASIC_IS_AVIVO(rdev) &&
2078             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2079                 if (ASIC_IS_DCE8(rdev)) {
2080                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2081                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2082                                        CIK_INTERLEAVE_EN);
2083                         else
2084                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2085                 } else if (ASIC_IS_DCE4(rdev)) {
2086                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2087                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2088                                        EVERGREEN_INTERLEAVE_EN);
2089                         else
2090                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2091                 } else {
2092                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2093                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2094                                        AVIVO_D1MODE_INTERLEAVE_EN);
2095                         else
2096                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2097                 }
2098         }
2099 }
2100
2101 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2102 {
2103         if (enc_idx < 0)
2104                 return;
2105         rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2106 }
2107
2108 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2109 {
2110         struct drm_device *dev = encoder->dev;
2111         struct radeon_device *rdev = dev->dev_private;
2112         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2113         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2114         struct drm_encoder *test_encoder;
2115         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2116         uint32_t dig_enc_in_use = 0;
2117         int enc_idx = -1;
2118
2119         if (fe_idx >= 0) {
2120                 enc_idx = fe_idx;
2121                 goto assigned;
2122         }
2123         if (ASIC_IS_DCE6(rdev)) {
2124                 /* DCE6 */
2125                 switch (radeon_encoder->encoder_id) {
2126                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2127                         if (dig->linkb)
2128                                 enc_idx = 1;
2129                         else
2130                                 enc_idx = 0;
2131                         break;
2132                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2133                         if (dig->linkb)
2134                                 enc_idx = 3;
2135                         else
2136                                 enc_idx = 2;
2137                         break;
2138                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2139                         if (dig->linkb)
2140                                 enc_idx = 5;
2141                         else
2142                                 enc_idx = 4;
2143                         break;
2144                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2145                         enc_idx = 6;
2146                         break;
2147                 }
2148                 goto assigned;
2149         } else if (ASIC_IS_DCE4(rdev)) {
2150                 /* DCE4/5 */
2151                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2152                         /* ontario follows DCE4 */
2153                         if (rdev->family == CHIP_PALM) {
2154                                 if (dig->linkb)
2155                                         enc_idx = 1;
2156                                 else
2157                                         enc_idx = 0;
2158                         } else
2159                                 /* llano follows DCE3.2 */
2160                                 enc_idx = radeon_crtc->crtc_id;
2161                 } else {
2162                         switch (radeon_encoder->encoder_id) {
2163                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2164                                 if (dig->linkb)
2165                                         enc_idx = 1;
2166                                 else
2167                                         enc_idx = 0;
2168                                 break;
2169                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2170                                 if (dig->linkb)
2171                                         enc_idx = 3;
2172                                 else
2173                                         enc_idx = 2;
2174                                 break;
2175                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2176                                 if (dig->linkb)
2177                                         enc_idx = 5;
2178                                 else
2179                                         enc_idx = 4;
2180                                 break;
2181                         }
2182                 }
2183                 goto assigned;
2184         }
2185
2186         /* on DCE32 and encoder can driver any block so just crtc id */
2187         if (ASIC_IS_DCE32(rdev)) {
2188                 enc_idx = radeon_crtc->crtc_id;
2189                 goto assigned;
2190         }
2191
2192         /* on DCE3 - LVTMA can only be driven by DIGB */
2193         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2194                 struct radeon_encoder *radeon_test_encoder;
2195
2196                 if (encoder == test_encoder)
2197                         continue;
2198
2199                 if (!radeon_encoder_is_digital(test_encoder))
2200                         continue;
2201
2202                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2203                 dig = radeon_test_encoder->enc_priv;
2204
2205                 if (dig->dig_encoder >= 0)
2206                         dig_enc_in_use |= (1 << dig->dig_encoder);
2207         }
2208
2209         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2210                 if (dig_enc_in_use & 0x2)
2211                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2212                 return 1;
2213         }
2214         if (!(dig_enc_in_use & 1))
2215                 return 0;
2216         return 1;
2217
2218 assigned:
2219         if (enc_idx == -1) {
2220                 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2221                 return 0;
2222         }
2223         if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2224                 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2225         }
2226         rdev->mode_info.active_encoders |= (1 << enc_idx);
2227         return enc_idx;
2228 }
2229
2230 /* This only needs to be called once at startup */
2231 void
2232 radeon_atom_encoder_init(struct radeon_device *rdev)
2233 {
2234         struct drm_device *dev = rdev->ddev;
2235         struct drm_encoder *encoder;
2236
2237         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2238                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2239                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2240
2241                 switch (radeon_encoder->encoder_id) {
2242                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2243                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2244                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2245                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2246                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2247                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2248                         break;
2249                 default:
2250                         break;
2251                 }
2252
2253                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2254                         atombios_external_encoder_setup(encoder, ext_encoder,
2255                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2256         }
2257 }
2258
2259 static void
2260 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2261                              struct drm_display_mode *mode,
2262                              struct drm_display_mode *adjusted_mode)
2263 {
2264         struct drm_device *dev = encoder->dev;
2265         struct radeon_device *rdev = dev->dev_private;
2266         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2267         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2268         int encoder_mode;
2269
2270         radeon_encoder->pixel_clock = adjusted_mode->clock;
2271
2272         /* need to call this here rather than in prepare() since we need some crtc info */
2273         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2274
2275         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2276                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2277                         atombios_yuv_setup(encoder, true);
2278                 else
2279                         atombios_yuv_setup(encoder, false);
2280         }
2281
2282         switch (radeon_encoder->encoder_id) {
2283         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2284         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2285         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2286         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2287                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2288                 break;
2289         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2290         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2291         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2292         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2293         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2294                 /* handled in dpms */
2295                 break;
2296         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2297         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2298         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2299                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2300                 break;
2301         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2302         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2303         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2304         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2305                 atombios_dac_setup(encoder, ATOM_ENABLE);
2306                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2307                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2308                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2309                         else
2310                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2311                 }
2312                 break;
2313         }
2314
2315         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2316
2317         encoder_mode = atombios_get_encoder_mode(encoder);
2318         if (connector && (radeon_audio != 0) &&
2319             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2320              ENCODER_MODE_IS_DP(encoder_mode)))
2321                 radeon_audio_mode_set(encoder, adjusted_mode);
2322 }
2323
2324 static bool
2325 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2326 {
2327         struct drm_device *dev = encoder->dev;
2328         struct radeon_device *rdev = dev->dev_private;
2329         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2330         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2331
2332         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2333                                        ATOM_DEVICE_CV_SUPPORT |
2334                                        ATOM_DEVICE_CRT_SUPPORT)) {
2335                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2336                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2337                 uint8_t frev, crev;
2338
2339                 memset(&args, 0, sizeof(args));
2340
2341                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2342                         return false;
2343
2344                 args.sDacload.ucMisc = 0;
2345
2346                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2347                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2348                         args.sDacload.ucDacType = ATOM_DAC_A;
2349                 else
2350                         args.sDacload.ucDacType = ATOM_DAC_B;
2351
2352                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2353                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2354                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2355                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2356                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2357                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2358                         if (crev >= 3)
2359                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2360                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2361                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2362                         if (crev >= 3)
2363                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2364                 }
2365
2366                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2367
2368                 return true;
2369         } else
2370                 return false;
2371 }
2372
2373 static enum drm_connector_status
2374 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2375 {
2376         struct drm_device *dev = encoder->dev;
2377         struct radeon_device *rdev = dev->dev_private;
2378         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2379         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2380         uint32_t bios_0_scratch;
2381
2382         if (!atombios_dac_load_detect(encoder, connector)) {
2383                 DRM_DEBUG_KMS("detect returned false \n");
2384                 return connector_status_unknown;
2385         }
2386
2387         if (rdev->family >= CHIP_R600)
2388                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2389         else
2390                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2391
2392         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2393         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2394                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2395                         return connector_status_connected;
2396         }
2397         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2398                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2399                         return connector_status_connected;
2400         }
2401         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2402                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2403                         return connector_status_connected;
2404         }
2405         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2406                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2407                         return connector_status_connected; /* CTV */
2408                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2409                         return connector_status_connected; /* STV */
2410         }
2411         return connector_status_disconnected;
2412 }
2413
2414 static enum drm_connector_status
2415 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2416 {
2417         struct drm_device *dev = encoder->dev;
2418         struct radeon_device *rdev = dev->dev_private;
2419         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2420         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2421         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2422         u32 bios_0_scratch;
2423
2424         if (!ASIC_IS_DCE4(rdev))
2425                 return connector_status_unknown;
2426
2427         if (!ext_encoder)
2428                 return connector_status_unknown;
2429
2430         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2431                 return connector_status_unknown;
2432
2433         /* load detect on the dp bridge */
2434         atombios_external_encoder_setup(encoder, ext_encoder,
2435                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2436
2437         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2438
2439         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2440         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2441                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2442                         return connector_status_connected;
2443         }
2444         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2445                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2446                         return connector_status_connected;
2447         }
2448         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2449                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2450                         return connector_status_connected;
2451         }
2452         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2453                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2454                         return connector_status_connected; /* CTV */
2455                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2456                         return connector_status_connected; /* STV */
2457         }
2458         return connector_status_disconnected;
2459 }
2460
2461 void
2462 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2463 {
2464         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2465
2466         if (ext_encoder)
2467                 /* ddc_setup on the dp bridge */
2468                 atombios_external_encoder_setup(encoder, ext_encoder,
2469                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2470
2471 }
2472
2473 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2474 {
2475         struct radeon_device *rdev = encoder->dev->dev_private;
2476         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2477         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2478
2479         if ((radeon_encoder->active_device &
2480              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2481             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2482              ENCODER_OBJECT_ID_NONE)) {
2483                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2484                 if (dig) {
2485                         if (dig->dig_encoder >= 0)
2486                                 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2487                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2488                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2489                                 if (rdev->family >= CHIP_R600)
2490                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2491                                 else
2492                                         /* RS600/690/740 have only 1 afmt block */
2493                                         dig->afmt = rdev->mode_info.afmt[0];
2494                         }
2495                 }
2496         }
2497
2498         radeon_atom_output_lock(encoder, true);
2499
2500         if (connector) {
2501                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2502
2503                 /* select the clock/data port if it uses a router */
2504                 if (radeon_connector->router.cd_valid)
2505                         radeon_router_select_cd_port(radeon_connector);
2506
2507                 /* turn eDP panel on for mode set */
2508                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2509                         atombios_set_edp_panel_power(connector,
2510                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2511         }
2512
2513         /* this is needed for the pll/ss setup to work correctly in some cases */
2514         atombios_set_encoder_crtc_source(encoder);
2515         /* set up the FMT blocks */
2516         if (ASIC_IS_DCE8(rdev))
2517                 dce8_program_fmt(encoder);
2518         else if (ASIC_IS_DCE4(rdev))
2519                 dce4_program_fmt(encoder);
2520         else if (ASIC_IS_DCE3(rdev))
2521                 dce3_program_fmt(encoder);
2522         else if (ASIC_IS_AVIVO(rdev))
2523                 avivo_program_fmt(encoder);
2524 }
2525
2526 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2527 {
2528         /* need to call this here as we need the crtc set up */
2529         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2530         radeon_atom_output_lock(encoder, false);
2531 }
2532
2533 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2534 {
2535         struct drm_device *dev = encoder->dev;
2536         struct radeon_device *rdev = dev->dev_private;
2537         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2538         struct radeon_encoder_atom_dig *dig;
2539
2540         /* check for pre-DCE3 cards with shared encoders;
2541          * can't really use the links individually, so don't disable
2542          * the encoder if it's in use by another connector
2543          */
2544         if (!ASIC_IS_DCE3(rdev)) {
2545                 struct drm_encoder *other_encoder;
2546                 struct radeon_encoder *other_radeon_encoder;
2547
2548                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2549                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2550                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2551                             drm_helper_encoder_in_use(other_encoder))
2552                                 goto disable_done;
2553                 }
2554         }
2555
2556         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2557
2558         switch (radeon_encoder->encoder_id) {
2559         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2560         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2561         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2562         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2563                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2564                 break;
2565         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2566         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2567         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2568         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2569         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2570                 /* handled in dpms */
2571                 break;
2572         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2573         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2574         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2575                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2576                 break;
2577         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2578         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2579         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2580         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2581                 atombios_dac_setup(encoder, ATOM_DISABLE);
2582                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2583                         atombios_tv_setup(encoder, ATOM_DISABLE);
2584                 break;
2585         }
2586
2587 disable_done:
2588         if (radeon_encoder_is_digital(encoder)) {
2589                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2590                         if (rdev->asic->display.hdmi_enable)
2591                                 radeon_hdmi_enable(rdev, encoder, false);
2592                 }
2593                 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2594                         dig = radeon_encoder->enc_priv;
2595                         radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2596                         dig->dig_encoder = -1;
2597                         radeon_encoder->active_device = 0;
2598                 }
2599         } else
2600                 radeon_encoder->active_device = 0;
2601 }
2602
2603 /* these are handled by the primary encoders */
2604 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2605 {
2606
2607 }
2608
2609 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2610 {
2611
2612 }
2613
2614 static void
2615 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2616                          struct drm_display_mode *mode,
2617                          struct drm_display_mode *adjusted_mode)
2618 {
2619
2620 }
2621
2622 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2623 {
2624
2625 }
2626
2627 static void
2628 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2629 {
2630
2631 }
2632
2633 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2634                                        const struct drm_display_mode *mode,
2635                                        struct drm_display_mode *adjusted_mode)
2636 {
2637         return true;
2638 }
2639
2640 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2641         .dpms = radeon_atom_ext_dpms,
2642         .mode_fixup = radeon_atom_ext_mode_fixup,
2643         .prepare = radeon_atom_ext_prepare,
2644         .mode_set = radeon_atom_ext_mode_set,
2645         .commit = radeon_atom_ext_commit,
2646         .disable = radeon_atom_ext_disable,
2647         /* no detect for TMDS/LVDS yet */
2648 };
2649
2650 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2651         .dpms = radeon_atom_encoder_dpms,
2652         .mode_fixup = radeon_atom_mode_fixup,
2653         .prepare = radeon_atom_encoder_prepare,
2654         .mode_set = radeon_atom_encoder_mode_set,
2655         .commit = radeon_atom_encoder_commit,
2656         .disable = radeon_atom_encoder_disable,
2657         .detect = radeon_atom_dig_detect,
2658 };
2659
2660 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2661         .dpms = radeon_atom_encoder_dpms,
2662         .mode_fixup = radeon_atom_mode_fixup,
2663         .prepare = radeon_atom_encoder_prepare,
2664         .mode_set = radeon_atom_encoder_mode_set,
2665         .commit = radeon_atom_encoder_commit,
2666         .detect = radeon_atom_dac_detect,
2667 };
2668
2669 void radeon_enc_destroy(struct drm_encoder *encoder)
2670 {
2671         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2672         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2673                 radeon_atom_backlight_exit(radeon_encoder);
2674         kfree(radeon_encoder->enc_priv);
2675         drm_encoder_cleanup(encoder);
2676         kfree(radeon_encoder);
2677 }
2678
2679 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2680         .destroy = radeon_enc_destroy,
2681 };
2682
2683 static struct radeon_encoder_atom_dac *
2684 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2685 {
2686         struct drm_device *dev = radeon_encoder->base.dev;
2687         struct radeon_device *rdev = dev->dev_private;
2688         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2689
2690         if (!dac)
2691                 return NULL;
2692
2693         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2694         return dac;
2695 }
2696
2697 static struct radeon_encoder_atom_dig *
2698 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2699 {
2700         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2701         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2702
2703         if (!dig)
2704                 return NULL;
2705
2706         /* coherent mode by default */
2707         dig->coherent_mode = true;
2708         dig->dig_encoder = -1;
2709
2710         if (encoder_enum == 2)
2711                 dig->linkb = true;
2712         else
2713                 dig->linkb = false;
2714
2715         return dig;
2716 }
2717
2718 void
2719 radeon_add_atom_encoder(struct drm_device *dev,
2720                         uint32_t encoder_enum,
2721                         uint32_t supported_device,
2722                         u16 caps)
2723 {
2724         struct radeon_device *rdev = dev->dev_private;
2725         struct drm_encoder *encoder;
2726         struct radeon_encoder *radeon_encoder;
2727
2728         /* see if we already added it */
2729         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2730                 radeon_encoder = to_radeon_encoder(encoder);
2731                 if (radeon_encoder->encoder_enum == encoder_enum) {
2732                         radeon_encoder->devices |= supported_device;
2733                         return;
2734                 }
2735
2736         }
2737
2738         /* add a new one */
2739         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2740         if (!radeon_encoder)
2741                 return;
2742
2743         encoder = &radeon_encoder->base;
2744         switch (rdev->num_crtc) {
2745         case 1:
2746                 encoder->possible_crtcs = 0x1;
2747                 break;
2748         case 2:
2749         default:
2750                 encoder->possible_crtcs = 0x3;
2751                 break;
2752         case 4:
2753                 encoder->possible_crtcs = 0xf;
2754                 break;
2755         case 6:
2756                 encoder->possible_crtcs = 0x3f;
2757                 break;
2758         }
2759
2760         radeon_encoder->enc_priv = NULL;
2761
2762         radeon_encoder->encoder_enum = encoder_enum;
2763         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2764         radeon_encoder->devices = supported_device;
2765         radeon_encoder->rmx_type = RMX_OFF;
2766         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2767         radeon_encoder->is_ext_encoder = false;
2768         radeon_encoder->caps = caps;
2769
2770         switch (radeon_encoder->encoder_id) {
2771         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2772         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2773         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2774         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2775                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2776                         radeon_encoder->rmx_type = RMX_FULL;
2777                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2778                                          DRM_MODE_ENCODER_LVDS, NULL);
2779                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2780                 } else {
2781                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2782                                          DRM_MODE_ENCODER_TMDS, NULL);
2783                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2784                 }
2785                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2786                 break;
2787         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2788                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2789                                  DRM_MODE_ENCODER_DAC, NULL);
2790                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2791                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2792                 break;
2793         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2795         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2796                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2797                                  DRM_MODE_ENCODER_TVDAC, NULL);
2798                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2799                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2800                 break;
2801         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2802         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2803         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2804         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2805         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2806         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2807         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2808         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2809                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2810                         radeon_encoder->rmx_type = RMX_FULL;
2811                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2812                                          DRM_MODE_ENCODER_LVDS, NULL);
2813                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2814                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2815                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2816                                          DRM_MODE_ENCODER_DAC, NULL);
2817                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2818                 } else {
2819                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2820                                          DRM_MODE_ENCODER_TMDS, NULL);
2821                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2822                 }
2823                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2824                 break;
2825         case ENCODER_OBJECT_ID_SI170B:
2826         case ENCODER_OBJECT_ID_CH7303:
2827         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2828         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2829         case ENCODER_OBJECT_ID_TITFP513:
2830         case ENCODER_OBJECT_ID_VT1623:
2831         case ENCODER_OBJECT_ID_HDMI_SI1930:
2832         case ENCODER_OBJECT_ID_TRAVIS:
2833         case ENCODER_OBJECT_ID_NUTMEG:
2834                 /* these are handled by the primary encoders */
2835                 radeon_encoder->is_ext_encoder = true;
2836                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2837                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2838                                          DRM_MODE_ENCODER_LVDS, NULL);
2839                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2840                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2841                                          DRM_MODE_ENCODER_DAC, NULL);
2842                 else
2843                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2844                                          DRM_MODE_ENCODER_TMDS, NULL);
2845                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2846                 break;
2847         }
2848 }