drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include <linux/backlight.h>
  32
  33 extern int atom_debug;
  34
  35 static u8
  36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  37 {
  38         u8 backlight_level;
  39         u32 bios_2_scratch;
  40
  41         if (rdev->family >= CHIP_R600)
  42                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  43         else
  44                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  45
  46         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  47                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  48
  49         return backlight_level;
  50 }
  51
  52 static void
  53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  54                                        u8 backlight_level)
  55 {
  56         u32 bios_2_scratch;
  57
  58         if (rdev->family >= CHIP_R600)
  59                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  60         else
  61                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  62
  63         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  64         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  65                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  66
  67         if (rdev->family >= CHIP_R600)
  68                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  69         else
  70                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  71 }
  72
  73 u8
  74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  75 {
  76         struct drm_device *dev = radeon_encoder->base.dev;
  77         struct radeon_device *rdev = dev->dev_private;
  78
  79         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  80                 return 0;
  81
  82         return radeon_atom_get_backlight_level_from_reg(rdev);
  83 }
  84
  85 void
  86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  87 {
  88         struct drm_encoder *encoder = &radeon_encoder->base;
  89         struct drm_device *dev = radeon_encoder->base.dev;
  90         struct radeon_device *rdev = dev->dev_private;
  91         struct radeon_encoder_atom_dig *dig;
  92         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  93         int index;
  94
  95         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  96                 return;
  97
  98         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  99             radeon_encoder->enc_priv) {
 100                 dig = radeon_encoder->enc_priv;
 101                 dig->backlight_level = level;
 102                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 103
 104                 switch (radeon_encoder->encoder_id) {
 105                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 107                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 108                         if (dig->backlight_level == 0) {
 109                                 args.ucAction = ATOM_LCD_BLOFF;
 110                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 111                         } else {
 112                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                                 args.ucAction = ATOM_LCD_BLON;
 115                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                         }
 117                         break;
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 119                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 122                         if (dig->backlight_level == 0)
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 124                         else {
 125                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 127                         }
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 136
 137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 138 {
 139         u8 level;
 140
 141         /* Convert brightness to hardware level */
 142         if (bd->props.brightness < 0)
 143                 level = 0;
 144         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 145                 level = RADEON_MAX_BL_LEVEL;
 146         else
 147                 level = bd->props.brightness;
 148
 149         return level;
 150 }
 151
 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 153 {
 154         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 155         struct radeon_encoder *radeon_encoder = pdata->encoder;
 156
 157         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 158
 159         return 0;
 160 }
 161
 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 163 {
 164         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 165         struct radeon_encoder *radeon_encoder = pdata->encoder;
 166         struct drm_device *dev = radeon_encoder->base.dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168
 169         return radeon_atom_get_backlight_level_from_reg(rdev);
 170 }
 171
 172 static const struct backlight_ops radeon_atom_backlight_ops = {
 173         .get_brightness = radeon_atom_backlight_get_brightness,
 174         .update_status  = radeon_atom_backlight_update_status,
 175 };
 176
 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 178                                 struct drm_connector *drm_connector)
 179 {
 180         struct drm_device *dev = radeon_encoder->base.dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         struct backlight_device *bd;
 183         struct backlight_properties props;
 184         struct radeon_backlight_privdata *pdata;
 185         struct radeon_encoder_atom_dig *dig;
 186         char bl_name[16];
 187
 188         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 189          * so don't register a backlight device
 190          */
 191         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 192             (rdev->pdev->device == 0x6741))
 193                 return;
 194
 195         if (!radeon_encoder->enc_priv)
 196                 return;
 197
 198         if (!rdev->is_atom_bios)
 199                 return;
 200
 201         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 202                 return;
 203
 204         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 205         if (!pdata) {
 206                 DRM_ERROR("Memory allocation failed\n");
 207                 goto error;
 208         }
 209
 210         memset(&props, 0, sizeof(props));
 211         props.max_brightness = RADEON_MAX_BL_LEVEL;
 212         props.type = BACKLIGHT_RAW;
 213         snprintf(bl_name, sizeof(bl_name),
 214                  "radeon_bl%d", dev->primary->index);
 215         bd = backlight_device_register(bl_name, &drm_connector->kdev,
 216                                        pdata, &radeon_atom_backlight_ops, &props);
 217         if (IS_ERR(bd)) {
 218                 DRM_ERROR("Backlight registration failed\n");
 219                 goto error;
 220         }
 221
 222         pdata->encoder = radeon_encoder;
 223
 224         dig = radeon_encoder->enc_priv;
 225         dig->bl_dev = bd;
 226
 227         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 228         /* Set a reasonable default here if the level is 0 otherwise
 229          * fbdev will attempt to turn the backlight on after console
 230          * unblanking and it will try and restore 0 which turns the backlight
 231          * off again.
 232          */
 233         if (bd->props.brightness == 0)
 234                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 235         bd->props.power = FB_BLANK_UNBLANK;
 236         backlight_update_status(bd);
 237
 238         DRM_INFO("radeon atom DIG backlight initialized\n");
 239
 240         return;
 241
 242 error:
 243         kfree(pdata);
 244         return;
 245 }
 246
 247 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 248 {
 249         struct drm_device *dev = radeon_encoder->base.dev;
 250         struct radeon_device *rdev = dev->dev_private;
 251         struct backlight_device *bd = NULL;
 252         struct radeon_encoder_atom_dig *dig;
 253
 254         if (!radeon_encoder->enc_priv)
 255                 return;
 256
 257         if (!rdev->is_atom_bios)
 258                 return;
 259
 260         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 261                 return;
 262
 263         dig = radeon_encoder->enc_priv;
 264         bd = dig->bl_dev;
 265         dig->bl_dev = NULL;
 266
 267         if (bd) {
 268                 struct radeon_legacy_backlight_privdata *pdata;
 269
 270                 pdata = bl_get_data(bd);
 271                 backlight_device_unregister(bd);
 272                 kfree(pdata);
 273
 274                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 275         }
 276 }
 277
 278 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 279
 280 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 281 {
 282 }
 283
 284 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 285 {
 286 }
 287
 288 #endif
 289
 290 /* evil but including atombios.h is much worse */
 291 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 292                                 struct drm_display_mode *mode);
 293
 294
 295 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 296 {
 297         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 298         switch (radeon_encoder->encoder_id) {
 299         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 300         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 301         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 302         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 303         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 304         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 305         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 306         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 307         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 308         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 309         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 310                 return true;
 311         default:
 312                 return false;
 313         }
 314 }
 315
 316 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 317                                    const struct drm_display_mode *mode,
 318                                    struct drm_display_mode *adjusted_mode)
 319 {
 320         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 321         struct drm_device *dev = encoder->dev;
 322         struct radeon_device *rdev = dev->dev_private;
 323
 324         /* set the active encoder to connector routing */
 325         radeon_encoder_set_active_device(encoder);
 326         drm_mode_set_crtcinfo(adjusted_mode, 0);
 327
 328         /* hw bug */
 329         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 330             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 331                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 332
 333         /* get the native mode for LVDS */
 334         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 335                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 336
 337         /* get the native mode for TV */
 338         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 339                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 340                 if (tv_dac) {
 341                         if (tv_dac->tv_std == TV_STD_NTSC ||
 342                             tv_dac->tv_std == TV_STD_NTSC_J ||
 343                             tv_dac->tv_std == TV_STD_PAL_M)
 344                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 345                         else
 346                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 347                 }
 348         }
 349
 350         if (ASIC_IS_DCE3(rdev) &&
 351             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 352              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 353                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 354                 radeon_dp_set_link_config(connector, adjusted_mode);
 355         }
 356
 357         return true;
 358 }
 359
 360 static void
 361 atombios_dac_setup(struct drm_encoder *encoder, int action)
 362 {
 363         struct drm_device *dev = encoder->dev;
 364         struct radeon_device *rdev = dev->dev_private;
 365         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 366         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 367         int index = 0;
 368         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 369
 370         memset(&args, 0, sizeof(args));
 371
 372         switch (radeon_encoder->encoder_id) {
 373         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 374         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 375                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 376                 break;
 377         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 378         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 379                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 380                 break;
 381         }
 382
 383         args.ucAction = action;
 384
 385         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 386                 args.ucDacStandard = ATOM_DAC1_PS2;
 387         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 388                 args.ucDacStandard = ATOM_DAC1_CV;
 389         else {
 390                 switch (dac_info->tv_std) {
 391                 case TV_STD_PAL:
 392                 case TV_STD_PAL_M:
 393                 case TV_STD_SCART_PAL:
 394                 case TV_STD_SECAM:
 395                 case TV_STD_PAL_CN:
 396                         args.ucDacStandard = ATOM_DAC1_PAL;
 397                         break;
 398                 case TV_STD_NTSC:
 399                 case TV_STD_NTSC_J:
 400                 case TV_STD_PAL_60:
 401                 default:
 402                         args.ucDacStandard = ATOM_DAC1_NTSC;
 403                         break;
 404                 }
 405         }
 406         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 407
 408         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 409
 410 }
 411
 412 static void
 413 atombios_tv_setup(struct drm_encoder *encoder, int action)
 414 {
 415         struct drm_device *dev = encoder->dev;
 416         struct radeon_device *rdev = dev->dev_private;
 417         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 418         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 419         int index = 0;
 420         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 421
 422         memset(&args, 0, sizeof(args));
 423
 424         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 425
 426         args.sTVEncoder.ucAction = action;
 427
 428         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 429                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 430         else {
 431                 switch (dac_info->tv_std) {
 432                 case TV_STD_NTSC:
 433                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 434                         break;
 435                 case TV_STD_PAL:
 436                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 437                         break;
 438                 case TV_STD_PAL_M:
 439                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 440                         break;
 441                 case TV_STD_PAL_60:
 442                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 443                         break;
 444                 case TV_STD_NTSC_J:
 445                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 446                         break;
 447                 case TV_STD_SCART_PAL:
 448                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 449                         break;
 450                 case TV_STD_SECAM:
 451                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 452                         break;
 453                 case TV_STD_PAL_CN:
 454                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 455                         break;
 456                 default:
 457                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 458                         break;
 459                 }
 460         }
 461
 462         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 463
 464         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 465
 466 }
 467
 468 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 469 {
 470         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 471         int bpc = 8;
 472
 473         if (connector)
 474                 bpc = radeon_get_monitor_bpc(connector);
 475
 476         switch (bpc) {
 477         case 0:
 478                 return PANEL_BPC_UNDEFINE;
 479         case 6:
 480                 return PANEL_6BIT_PER_COLOR;
 481         case 8:
 482         default:
 483                 return PANEL_8BIT_PER_COLOR;
 484         case 10:
 485                 return PANEL_10BIT_PER_COLOR;
 486         case 12:
 487                 return PANEL_12BIT_PER_COLOR;
 488         case 16:
 489                 return PANEL_16BIT_PER_COLOR;
 490         }
 491 }
 492
 493
 494 union dvo_encoder_control {
 495         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 496         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 497         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 498 };
 499
 500 void
 501 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 502 {
 503         struct drm_device *dev = encoder->dev;
 504         struct radeon_device *rdev = dev->dev_private;
 505         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 506         union dvo_encoder_control args;
 507         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 508         uint8_t frev, crev;
 509
 510         memset(&args, 0, sizeof(args));
 511
 512         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 513                 return;
 514
 515         /* some R4xx chips have the wrong frev */
 516         if (rdev->family <= CHIP_RV410)
 517                 frev = 1;
 518
 519         switch (frev) {
 520         case 1:
 521                 switch (crev) {
 522                 case 1:
 523                         /* R4xx, R5xx */
 524                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 525
 526                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 527                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 528
 529                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 530                         break;
 531                 case 2:
 532                         /* RS600/690/740 */
 533                         args.dvo.sDVOEncoder.ucAction = action;
 534                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 535                         /* DFP1, CRT1, TV1 depending on the type of port */
 536                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 537
 538                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 539                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 540                         break;
 541                 case 3:
 542                         /* R6xx */
 543                         args.dvo_v3.ucAction = action;
 544                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 545                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 546                         break;
 547                 default:
 548                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 549                         break;
 550                 }
 551                 break;
 552         default:
 553                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 554                 break;
 555         }
 556
 557         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 558 }
 559
 560 union lvds_encoder_control {
 561         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 562         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 563 };
 564
 565 void
 566 atombios_digital_setup(struct drm_encoder *encoder, int action)
 567 {
 568         struct drm_device *dev = encoder->dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 571         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 572         union lvds_encoder_control args;
 573         int index = 0;
 574         int hdmi_detected = 0;
 575         uint8_t frev, crev;
 576
 577         if (!dig)
 578                 return;
 579
 580         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 581                 hdmi_detected = 1;
 582
 583         memset(&args, 0, sizeof(args));
 584
 585         switch (radeon_encoder->encoder_id) {
 586         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 587                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 588                 break;
 589         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 590         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 591                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 592                 break;
 593         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 594                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 595                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 596                 else
 597                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 598                 break;
 599         }
 600
 601         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 602                 return;
 603
 604         switch (frev) {
 605         case 1:
 606         case 2:
 607                 switch (crev) {
 608                 case 1:
 609                         args.v1.ucMisc = 0;
 610                         args.v1.ucAction = action;
 611                         if (hdmi_detected)
 612                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 613                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 614                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 615                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 616                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 617                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 618                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 619                         } else {
 620                                 if (dig->linkb)
 621                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 622                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 623                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 624                                 /*if (pScrn->rgbBits == 8) */
 625                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 626                         }
 627                         break;
 628                 case 2:
 629                 case 3:
 630                         args.v2.ucMisc = 0;
 631                         args.v2.ucAction = action;
 632                         if (crev == 3) {
 633                                 if (dig->coherent_mode)
 634                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 635                         }
 636                         if (hdmi_detected)
 637                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 638                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 639                         args.v2.ucTruncate = 0;
 640                         args.v2.ucSpatial = 0;
 641                         args.v2.ucTemporal = 0;
 642                         args.v2.ucFRC = 0;
 643                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 644                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 645                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 646                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 647                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 648                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 649                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 650                                 }
 651                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 652                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 653                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 654                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 655                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 656                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 657                                 }
 658                         } else {
 659                                 if (dig->linkb)
 660                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 661                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 662                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 663                         }
 664                         break;
 665                 default:
 666                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 667                         break;
 668                 }
 669                 break;
 670         default:
 671                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 672                 break;
 673         }
 674
 675         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 676 }
 677
 678 int
 679 atombios_get_encoder_mode(struct drm_encoder *encoder)
 680 {
 681         struct drm_device *dev = encoder->dev;
 682         struct radeon_device *rdev = dev->dev_private;
 683         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 684         struct drm_connector *connector;
 685         struct radeon_connector *radeon_connector;
 686         struct radeon_connector_atom_dig *dig_connector;
 687
 688         /* dp bridges are always DP */
 689         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 690                 return ATOM_ENCODER_MODE_DP;
 691
 692         /* DVO is always DVO */
 693         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 694             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 695                 return ATOM_ENCODER_MODE_DVO;
 696
 697         connector = radeon_get_connector_for_encoder(encoder);
 698         /* if we don't have an active device yet, just use one of
 699          * the connectors tied to the encoder.
 700          */
 701         if (!connector)
 702                 connector = radeon_get_connector_for_encoder_init(encoder);
 703         radeon_connector = to_radeon_connector(connector);
 704
 705         switch (connector->connector_type) {
 706         case DRM_MODE_CONNECTOR_DVII:
 707         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 708                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 709                     radeon_audio &&
 710                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 711                         return ATOM_ENCODER_MODE_HDMI;
 712                 else if (radeon_connector->use_digital)
 713                         return ATOM_ENCODER_MODE_DVI;
 714                 else
 715                         return ATOM_ENCODER_MODE_CRT;
 716                 break;
 717         case DRM_MODE_CONNECTOR_DVID:
 718         case DRM_MODE_CONNECTOR_HDMIA:
 719         default:
 720                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 721                     radeon_audio &&
 722                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 723                         return ATOM_ENCODER_MODE_HDMI;
 724                 else
 725                         return ATOM_ENCODER_MODE_DVI;
 726                 break;
 727         case DRM_MODE_CONNECTOR_LVDS:
 728                 return ATOM_ENCODER_MODE_LVDS;
 729                 break;
 730         case DRM_MODE_CONNECTOR_DisplayPort:
 731                 dig_connector = radeon_connector->con_priv;
 732                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 733                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 734                         return ATOM_ENCODER_MODE_DP;
 735                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 736                          radeon_audio &&
 737                          !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
 738                         return ATOM_ENCODER_MODE_HDMI;
 739                 else
 740                         return ATOM_ENCODER_MODE_DVI;
 741                 break;
 742         case DRM_MODE_CONNECTOR_eDP:
 743                 return ATOM_ENCODER_MODE_DP;
 744         case DRM_MODE_CONNECTOR_DVIA:
 745         case DRM_MODE_CONNECTOR_VGA:
 746                 return ATOM_ENCODER_MODE_CRT;
 747                 break;
 748         case DRM_MODE_CONNECTOR_Composite:
 749         case DRM_MODE_CONNECTOR_SVIDEO:
 750         case DRM_MODE_CONNECTOR_9PinDIN:
 751                 /* fix me */
 752                 return ATOM_ENCODER_MODE_TV;
 753                 /*return ATOM_ENCODER_MODE_CV;*/
 754                 break;
 755         }
 756 }
 757
 758 /*
 759  * DIG Encoder/Transmitter Setup
 760  *
 761  * DCE 3.0/3.1
 762  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 763  * Supports up to 3 digital outputs
 764  * - 2 DIG encoder blocks.
 765  * DIG1 can drive UNIPHY link A or link B
 766  * DIG2 can drive UNIPHY link B or LVTMA
 767  *
 768  * DCE 3.2
 769  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 770  * Supports up to 5 digital outputs
 771  * - 2 DIG encoder blocks.
 772  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 773  *
 774  * DCE 4.0/5.0/6.0
 775  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 776  * Supports up to 6 digital outputs
 777  * - 6 DIG encoder blocks.
 778  * - DIG to PHY mapping is hardcoded
 779  * DIG1 drives UNIPHY0 link A, A+B
 780  * DIG2 drives UNIPHY0 link B
 781  * DIG3 drives UNIPHY1 link A, A+B
 782  * DIG4 drives UNIPHY1 link B
 783  * DIG5 drives UNIPHY2 link A, A+B
 784  * DIG6 drives UNIPHY2 link B
 785  *
 786  * DCE 4.1
 787  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 788  * Supports up to 6 digital outputs
 789  * - 2 DIG encoder blocks.
 790  * llano
 791  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 792  * ontario
 793  * DIG1 drives UNIPHY0/1/2 link A
 794  * DIG2 drives UNIPHY0/1/2 link B
 795  *
 796  * Routing
 797  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 798  * Examples:
 799  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 800  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 801  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 802  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 803  */
 804
 805 union dig_encoder_control {
 806         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 807         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 808         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 809         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 810 };
 811
 812 void
 813 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 814 {
 815         struct drm_device *dev = encoder->dev;
 816         struct radeon_device *rdev = dev->dev_private;
 817         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 818         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 819         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 820         union dig_encoder_control args;
 821         int index = 0;
 822         uint8_t frev, crev;
 823         int dp_clock = 0;
 824         int dp_lane_count = 0;
 825         int hpd_id = RADEON_HPD_NONE;
 826
 827         if (connector) {
 828                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 829                 struct radeon_connector_atom_dig *dig_connector =
 830                         radeon_connector->con_priv;
 831
 832                 dp_clock = dig_connector->dp_clock;
 833                 dp_lane_count = dig_connector->dp_lane_count;
 834                 hpd_id = radeon_connector->hpd.hpd;
 835         }
 836
 837         /* no dig encoder assigned */
 838         if (dig->dig_encoder == -1)
 839                 return;
 840
 841         memset(&args, 0, sizeof(args));
 842
 843         if (ASIC_IS_DCE4(rdev))
 844                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 845         else {
 846                 if (dig->dig_encoder)
 847                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 848                 else
 849                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 850         }
 851
 852         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 853                 return;
 854
 855         switch (frev) {
 856         case 1:
 857                 switch (crev) {
 858                 case 1:
 859                         args.v1.ucAction = action;
 860                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 861                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 862                                 args.v3.ucPanelMode = panel_mode;
 863                         else
 864                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 865
 866                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 867                                 args.v1.ucLaneNum = dp_lane_count;
 868                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 869                                 args.v1.ucLaneNum = 8;
 870                         else
 871                                 args.v1.ucLaneNum = 4;
 872
 873                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 874                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 875                         switch (radeon_encoder->encoder_id) {
 876                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 877                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 878                                 break;
 879                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 880                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 881                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 882                                 break;
 883                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 884                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 885                                 break;
 886                         }
 887                         if (dig->linkb)
 888                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 889                         else
 890                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 891                         break;
 892                 case 2:
 893                 case 3:
 894                         args.v3.ucAction = action;
 895                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 896                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 897                                 args.v3.ucPanelMode = panel_mode;
 898                         else
 899                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 900
 901                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 902                                 args.v3.ucLaneNum = dp_lane_count;
 903                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 904                                 args.v3.ucLaneNum = 8;
 905                         else
 906                                 args.v3.ucLaneNum = 4;
 907
 908                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 909                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 910                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 911                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 912                         break;
 913                 case 4:
 914                         args.v4.ucAction = action;
 915                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 916                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 917                                 args.v4.ucPanelMode = panel_mode;
 918                         else
 919                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 920
 921                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 922                                 args.v4.ucLaneNum = dp_lane_count;
 923                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 924                                 args.v4.ucLaneNum = 8;
 925                         else
 926                                 args.v4.ucLaneNum = 4;
 927
 928                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 929                                 if (dp_clock == 270000)
 930                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 931                                 else if (dp_clock == 540000)
 932                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 933                         }
 934                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 935                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 936                         if (hpd_id == RADEON_HPD_NONE)
 937                                 args.v4.ucHPD_ID = 0;
 938                         else
 939                                 args.v4.ucHPD_ID = hpd_id + 1;
 940                         break;
 941                 default:
 942                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 943                         break;
 944                 }
 945                 break;
 946         default:
 947                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 948                 break;
 949         }
 950
 951         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 952
 953 }
 954
 955 union dig_transmitter_control {
 956         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 957         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 958         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 959         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 960         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 961 };
 962
 963 void
 964 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 965 {
 966         struct drm_device *dev = encoder->dev;
 967         struct radeon_device *rdev = dev->dev_private;
 968         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 969         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 970         struct drm_connector *connector;
 971         union dig_transmitter_control args;
 972         int index = 0;
 973         uint8_t frev, crev;
 974         bool is_dp = false;
 975         int pll_id = 0;
 976         int dp_clock = 0;
 977         int dp_lane_count = 0;
 978         int connector_object_id = 0;
 979         int igp_lane_info = 0;
 980         int dig_encoder = dig->dig_encoder;
 981         int hpd_id = RADEON_HPD_NONE;
 982
 983         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 984                 connector = radeon_get_connector_for_encoder_init(encoder);
 985                 /* just needed to avoid bailing in the encoder check.  the encoder
 986                  * isn't used for init
 987                  */
 988                 dig_encoder = 0;
 989         } else
 990                 connector = radeon_get_connector_for_encoder(encoder);
 991
 992         if (connector) {
 993                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 994                 struct radeon_connector_atom_dig *dig_connector =
 995                         radeon_connector->con_priv;
 996
 997                 hpd_id = radeon_connector->hpd.hpd;
 998                 dp_clock = dig_connector->dp_clock;
 999                 dp_lane_count = dig_connector->dp_lane_count;
1000                 connector_object_id =
1001                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1002                 igp_lane_info = dig_connector->igp_lane_info;
1003         }
1004
1005         if (encoder->crtc) {
1006                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1007                 pll_id = radeon_crtc->pll_id;
1008         }
1009
1010         /* no dig encoder assigned */
1011         if (dig_encoder == -1)
1012                 return;
1013
1014         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1015                 is_dp = true;
1016
1017         memset(&args, 0, sizeof(args));
1018
1019         switch (radeon_encoder->encoder_id) {
1020         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1021                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1022                 break;
1023         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1024         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1025         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1026                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1027                 break;
1028         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1029                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1030                 break;
1031         }
1032
1033         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1034                 return;
1035
1036         switch (frev) {
1037         case 1:
1038                 switch (crev) {
1039                 case 1:
1040                         args.v1.ucAction = action;
1041                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1042                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1043                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1044                                 args.v1.asMode.ucLaneSel = lane_num;
1045                                 args.v1.asMode.ucLaneSet = lane_set;
1046                         } else {
1047                                 if (is_dp)
1048                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1049                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1050                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1051                                 else
1052                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1053                         }
1054
1055                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1056
1057                         if (dig_encoder)
1058                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1059                         else
1060                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1061
1062                         if ((rdev->flags & RADEON_IS_IGP) &&
1063                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1064                                 if (is_dp ||
1065                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1066                                         if (igp_lane_info & 0x1)
1067                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1068                                         else if (igp_lane_info & 0x2)
1069                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1070                                         else if (igp_lane_info & 0x4)
1071                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1072                                         else if (igp_lane_info & 0x8)
1073                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1074                                 } else {
1075                                         if (igp_lane_info & 0x3)
1076                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1077                                         else if (igp_lane_info & 0xc)
1078                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1079                                 }
1080                         }
1081
1082                         if (dig->linkb)
1083                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1084                         else
1085                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1086
1087                         if (is_dp)
1088                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1089                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1090                                 if (dig->coherent_mode)
1091                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1092                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1093                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1094                         }
1095                         break;
1096                 case 2:
1097                         args.v2.ucAction = action;
1098                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1099                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1100                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1101                                 args.v2.asMode.ucLaneSel = lane_num;
1102                                 args.v2.asMode.ucLaneSet = lane_set;
1103                         } else {
1104                                 if (is_dp)
1105                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1106                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1107                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1108                                 else
1109                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1110                         }
1111
1112                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1113                         if (dig->linkb)
1114                                 args.v2.acConfig.ucLinkSel = 1;
1115
1116                         switch (radeon_encoder->encoder_id) {
1117                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1118                                 args.v2.acConfig.ucTransmitterSel = 0;
1119                                 break;
1120                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1121                                 args.v2.acConfig.ucTransmitterSel = 1;
1122                                 break;
1123                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1124                                 args.v2.acConfig.ucTransmitterSel = 2;
1125                                 break;
1126                         }
1127
1128                         if (is_dp) {
1129                                 args.v2.acConfig.fCoherentMode = 1;
1130                                 args.v2.acConfig.fDPConnector = 1;
1131                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1132                                 if (dig->coherent_mode)
1133                                         args.v2.acConfig.fCoherentMode = 1;
1134                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1135                                         args.v2.acConfig.fDualLinkConnector = 1;
1136                         }
1137                         break;
1138                 case 3:
1139                         args.v3.ucAction = action;
1140                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1141                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1142                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1143                                 args.v3.asMode.ucLaneSel = lane_num;
1144                                 args.v3.asMode.ucLaneSet = lane_set;
1145                         } else {
1146                                 if (is_dp)
1147                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1148                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1149                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1150                                 else
1151                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1152                         }
1153
1154                         if (is_dp)
1155                                 args.v3.ucLaneNum = dp_lane_count;
1156                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1157                                 args.v3.ucLaneNum = 8;
1158                         else
1159                                 args.v3.ucLaneNum = 4;
1160
1161                         if (dig->linkb)
1162                                 args.v3.acConfig.ucLinkSel = 1;
1163                         if (dig_encoder & 1)
1164                                 args.v3.acConfig.ucEncoderSel = 1;
1165
1166                         /* Select the PLL for the PHY
1167                          * DP PHY should be clocked from external src if there is
1168                          * one.
1169                          */
1170                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1171                         if (is_dp && rdev->clock.dp_extclk)
1172                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1173                         else
1174                                 args.v3.acConfig.ucRefClkSource = pll_id;
1175
1176                         switch (radeon_encoder->encoder_id) {
1177                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1178                                 args.v3.acConfig.ucTransmitterSel = 0;
1179                                 break;
1180                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1181                                 args.v3.acConfig.ucTransmitterSel = 1;
1182                                 break;
1183                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1184                                 args.v3.acConfig.ucTransmitterSel = 2;
1185                                 break;
1186                         }
1187
1188                         if (is_dp)
1189                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1190                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1191                                 if (dig->coherent_mode)
1192                                         args.v3.acConfig.fCoherentMode = 1;
1193                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1194                                         args.v3.acConfig.fDualLinkConnector = 1;
1195                         }
1196                         break;
1197                 case 4:
1198                         args.v4.ucAction = action;
1199                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1200                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1201                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1202                                 args.v4.asMode.ucLaneSel = lane_num;
1203                                 args.v4.asMode.ucLaneSet = lane_set;
1204                         } else {
1205                                 if (is_dp)
1206                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1207                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1208                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1209                                 else
1210                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1211                         }
1212
1213                         if (is_dp)
1214                                 args.v4.ucLaneNum = dp_lane_count;
1215                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1216                                 args.v4.ucLaneNum = 8;
1217                         else
1218                                 args.v4.ucLaneNum = 4;
1219
1220                         if (dig->linkb)
1221                                 args.v4.acConfig.ucLinkSel = 1;
1222                         if (dig_encoder & 1)
1223                                 args.v4.acConfig.ucEncoderSel = 1;
1224
1225                         /* Select the PLL for the PHY
1226                          * DP PHY should be clocked from external src if there is
1227                          * one.
1228                          */
1229                         /* On DCE5 DCPLL usually generates the DP ref clock */
1230                         if (is_dp) {
1231                                 if (rdev->clock.dp_extclk)
1232                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1233                                 else
1234                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1235                         } else
1236                                 args.v4.acConfig.ucRefClkSource = pll_id;
1237
1238                         switch (radeon_encoder->encoder_id) {
1239                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1240                                 args.v4.acConfig.ucTransmitterSel = 0;
1241                                 break;
1242                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1243                                 args.v4.acConfig.ucTransmitterSel = 1;
1244                                 break;
1245                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1246                                 args.v4.acConfig.ucTransmitterSel = 2;
1247                                 break;
1248                         }
1249
1250                         if (is_dp)
1251                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1252                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1253                                 if (dig->coherent_mode)
1254                                         args.v4.acConfig.fCoherentMode = 1;
1255                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1256                                         args.v4.acConfig.fDualLinkConnector = 1;
1257                         }
1258                         break;
1259                 case 5:
1260                         args.v5.ucAction = action;
1261                         if (is_dp)
1262                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1263                         else
1264                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1265
1266                         switch (radeon_encoder->encoder_id) {
1267                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1268                                 if (dig->linkb)
1269                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1270                                 else
1271                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1272                                 break;
1273                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1274                                 if (dig->linkb)
1275                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1276                                 else
1277                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1278                                 break;
1279                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1280                                 if (dig->linkb)
1281                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1282                                 else
1283                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1284                                 break;
1285                         }
1286                         if (is_dp)
1287                                 args.v5.ucLaneNum = dp_lane_count;
1288                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1289                                 args.v5.ucLaneNum = 8;
1290                         else
1291                                 args.v5.ucLaneNum = 4;
1292                         args.v5.ucConnObjId = connector_object_id;
1293                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1294
1295                         if (is_dp && rdev->clock.dp_extclk)
1296                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1297                         else
1298                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1299
1300                         if (is_dp)
1301                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1302                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1303                                 if (dig->coherent_mode)
1304                                         args.v5.asConfig.ucCoherentMode = 1;
1305                         }
1306                         if (hpd_id == RADEON_HPD_NONE)
1307                                 args.v5.asConfig.ucHPDSel = 0;
1308                         else
1309                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1310                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1311                         args.v5.ucDPLaneSet = lane_set;
1312                         break;
1313                 default:
1314                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1315                         break;
1316                 }
1317                 break;
1318         default:
1319                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1320                 break;
1321         }
1322
1323         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1324 }
1325
1326 bool
1327 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1328 {
1329         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1330         struct drm_device *dev = radeon_connector->base.dev;
1331         struct radeon_device *rdev = dev->dev_private;
1332         union dig_transmitter_control args;
1333         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1334         uint8_t frev, crev;
1335
1336         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1337                 goto done;
1338
1339         if (!ASIC_IS_DCE4(rdev))
1340                 goto done;
1341
1342         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1343             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1344                 goto done;
1345
1346         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1347                 goto done;
1348
1349         memset(&args, 0, sizeof(args));
1350
1351         args.v1.ucAction = action;
1352
1353         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1354
1355         /* wait for the panel to power up */
1356         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1357                 int i;
1358
1359                 for (i = 0; i < 300; i++) {
1360                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1361                                 return true;
1362                         mdelay(1);
1363                 }
1364                 return false;
1365         }
1366 done:
1367         return true;
1368 }
1369
1370 union external_encoder_control {
1371         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1372         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1373 };
1374
1375 static void
1376 atombios_external_encoder_setup(struct drm_encoder *encoder,
1377                                 struct drm_encoder *ext_encoder,
1378                                 int action)
1379 {
1380         struct drm_device *dev = encoder->dev;
1381         struct radeon_device *rdev = dev->dev_private;
1382         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1383         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1384         union external_encoder_control args;
1385         struct drm_connector *connector;
1386         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1387         u8 frev, crev;
1388         int dp_clock = 0;
1389         int dp_lane_count = 0;
1390         int connector_object_id = 0;
1391         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1392
1393         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1394                 connector = radeon_get_connector_for_encoder_init(encoder);
1395         else
1396                 connector = radeon_get_connector_for_encoder(encoder);
1397
1398         if (connector) {
1399                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1400                 struct radeon_connector_atom_dig *dig_connector =
1401                         radeon_connector->con_priv;
1402
1403                 dp_clock = dig_connector->dp_clock;
1404                 dp_lane_count = dig_connector->dp_lane_count;
1405                 connector_object_id =
1406                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1407         }
1408
1409         memset(&args, 0, sizeof(args));
1410
1411         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1412                 return;
1413
1414         switch (frev) {
1415         case 1:
1416                 /* no params on frev 1 */
1417                 break;
1418         case 2:
1419                 switch (crev) {
1420                 case 1:
1421                 case 2:
1422                         args.v1.sDigEncoder.ucAction = action;
1423                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1424                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1425
1426                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1427                                 if (dp_clock == 270000)
1428                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1429                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1430                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1431                                 args.v1.sDigEncoder.ucLaneNum = 8;
1432                         else
1433                                 args.v1.sDigEncoder.ucLaneNum = 4;
1434                         break;
1435                 case 3:
1436                         args.v3.sExtEncoder.ucAction = action;
1437                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1438                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1439                         else
1440                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1441                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1442
1443                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1444                                 if (dp_clock == 270000)
1445                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1446                                 else if (dp_clock == 540000)
1447                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1448                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1449                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1450                                 args.v3.sExtEncoder.ucLaneNum = 8;
1451                         else
1452                                 args.v3.sExtEncoder.ucLaneNum = 4;
1453                         switch (ext_enum) {
1454                         case GRAPH_OBJECT_ENUM_ID1:
1455                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1456                                 break;
1457                         case GRAPH_OBJECT_ENUM_ID2:
1458                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1459                                 break;
1460                         case GRAPH_OBJECT_ENUM_ID3:
1461                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1462                                 break;
1463                         }
1464                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1465                         break;
1466                 default:
1467                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1468                         return;
1469                 }
1470                 break;
1471         default:
1472                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1473                 return;
1474         }
1475         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1476 }
1477
1478 static void
1479 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1480 {
1481         struct drm_device *dev = encoder->dev;
1482         struct radeon_device *rdev = dev->dev_private;
1483         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1484         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1485         ENABLE_YUV_PS_ALLOCATION args;
1486         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1487         uint32_t temp, reg;
1488
1489         memset(&args, 0, sizeof(args));
1490
1491         if (rdev->family >= CHIP_R600)
1492                 reg = R600_BIOS_3_SCRATCH;
1493         else
1494                 reg = RADEON_BIOS_3_SCRATCH;
1495
1496         /* XXX: fix up scratch reg handling */
1497         temp = RREG32(reg);
1498         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1499                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1500                              (radeon_crtc->crtc_id << 18)));
1501         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1502                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1503         else
1504                 WREG32(reg, 0);
1505
1506         if (enable)
1507                 args.ucEnable = ATOM_ENABLE;
1508         args.ucCRTC = radeon_crtc->crtc_id;
1509
1510         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1511
1512         WREG32(reg, temp);
1513 }
1514
1515 static void
1516 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1517 {
1518         struct drm_device *dev = encoder->dev;
1519         struct radeon_device *rdev = dev->dev_private;
1520         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1521         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1522         int index = 0;
1523
1524         memset(&args, 0, sizeof(args));
1525
1526         switch (radeon_encoder->encoder_id) {
1527         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1528         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1529                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1530                 break;
1531         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1532         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1533         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1534                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1535                 break;
1536         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1537                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1538                 break;
1539         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1540                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1541                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1542                 else
1543                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1544                 break;
1545         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1546         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1547                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1548                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1549                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1550                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1551                 else
1552                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1553                 break;
1554         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1555         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1556                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1557                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1558                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1559                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1560                 else
1561                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1562                 break;
1563         default:
1564                 return;
1565         }
1566
1567         switch (mode) {
1568         case DRM_MODE_DPMS_ON:
1569                 args.ucAction = ATOM_ENABLE;
1570                 /* workaround for DVOOutputControl on some RS690 systems */
1571                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1572                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1573                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1574                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1575                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1576                 } else
1577                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1578                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1579                         args.ucAction = ATOM_LCD_BLON;
1580                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1581                 }
1582                 break;
1583         case DRM_MODE_DPMS_STANDBY:
1584         case DRM_MODE_DPMS_SUSPEND:
1585         case DRM_MODE_DPMS_OFF:
1586                 args.ucAction = ATOM_DISABLE;
1587                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1588                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1589                         args.ucAction = ATOM_LCD_BLOFF;
1590                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1591                 }
1592                 break;
1593         }
1594 }
1595
1596 static void
1597 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1598 {
1599         struct drm_device *dev = encoder->dev;
1600         struct radeon_device *rdev = dev->dev_private;
1601         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1602         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1603         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1604         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1605         struct radeon_connector *radeon_connector = NULL;
1606         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1607
1608         if (connector) {
1609                 radeon_connector = to_radeon_connector(connector);
1610                 radeon_dig_connector = radeon_connector->con_priv;
1611         }
1612
1613         switch (mode) {
1614         case DRM_MODE_DPMS_ON:
1615                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1616                         if (!connector)
1617                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1618                         else
1619                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1620
1621                         /* setup and enable the encoder */
1622                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1623                         atombios_dig_encoder_setup(encoder,
1624                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1625                                                    dig->panel_mode);
1626                         if (ext_encoder) {
1627                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1628                                         atombios_external_encoder_setup(encoder, ext_encoder,
1629                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1630                         }
1631                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1632                 } else if (ASIC_IS_DCE4(rdev)) {
1633                         /* setup and enable the encoder */
1634                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1635                         /* enable the transmitter */
1636                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1637                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1638                 } else {
1639                         /* setup and enable the encoder and transmitter */
1640                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1641                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1642                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1643                         /* some dce3.x boards have a bug in their transmitter control table.
1644                          * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1645                          * does the same thing and more.
1646                          */
1647                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1648                             (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1649                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1650                 }
1651                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1652                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1653                                 atombios_set_edp_panel_power(connector,
1654                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1655                                 radeon_dig_connector->edp_on = true;
1656                         }
1657                         radeon_dp_link_train(encoder, connector);
1658                         if (ASIC_IS_DCE4(rdev))
1659                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1660                 }
1661                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1662                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1663                 break;
1664         case DRM_MODE_DPMS_STANDBY:
1665         case DRM_MODE_DPMS_SUSPEND:
1666         case DRM_MODE_DPMS_OFF:
1667                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1668                         /* disable the transmitter */
1669                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1670                 } else if (ASIC_IS_DCE4(rdev)) {
1671                         /* disable the transmitter */
1672                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1673                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1674                 } else {
1675                         /* disable the encoder and transmitter */
1676                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1677                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1678                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1679                 }
1680                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1681                         if (ASIC_IS_DCE4(rdev))
1682                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1683                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1684                                 atombios_set_edp_panel_power(connector,
1685                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1686                                 radeon_dig_connector->edp_on = false;
1687                         }
1688                 }
1689                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1690                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1691                 break;
1692         }
1693 }
1694
1695 static void
1696 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1697                              struct drm_encoder *ext_encoder,
1698                              int mode)
1699 {
1700         struct drm_device *dev = encoder->dev;
1701         struct radeon_device *rdev = dev->dev_private;
1702
1703         switch (mode) {
1704         case DRM_MODE_DPMS_ON:
1705         default:
1706                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1707                         atombios_external_encoder_setup(encoder, ext_encoder,
1708                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1709                         atombios_external_encoder_setup(encoder, ext_encoder,
1710                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1711                 } else
1712                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1713                 break;
1714         case DRM_MODE_DPMS_STANDBY:
1715         case DRM_MODE_DPMS_SUSPEND:
1716         case DRM_MODE_DPMS_OFF:
1717                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1718                         atombios_external_encoder_setup(encoder, ext_encoder,
1719                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1720                         atombios_external_encoder_setup(encoder, ext_encoder,
1721                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1722                 } else
1723                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1724                 break;
1725         }
1726 }
1727
1728 static void
1729 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1730 {
1731         struct drm_device *dev = encoder->dev;
1732         struct radeon_device *rdev = dev->dev_private;
1733         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1734         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1735
1736         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1737                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1738                   radeon_encoder->active_device);
1739         switch (radeon_encoder->encoder_id) {
1740         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1741         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1742         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1743         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1744         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1745         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1746         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1747         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1748                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1749                 break;
1750         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1751         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1752         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1753         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1754                 radeon_atom_encoder_dpms_dig(encoder, mode);
1755                 break;
1756         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1757                 if (ASIC_IS_DCE5(rdev)) {
1758                         switch (mode) {
1759                         case DRM_MODE_DPMS_ON:
1760                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1761                                 break;
1762                         case DRM_MODE_DPMS_STANDBY:
1763                         case DRM_MODE_DPMS_SUSPEND:
1764                         case DRM_MODE_DPMS_OFF:
1765                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1766                                 break;
1767                         }
1768                 } else if (ASIC_IS_DCE3(rdev))
1769                         radeon_atom_encoder_dpms_dig(encoder, mode);
1770                 else
1771                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1772                 break;
1773         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1774         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1775                 if (ASIC_IS_DCE5(rdev)) {
1776                         switch (mode) {
1777                         case DRM_MODE_DPMS_ON:
1778                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1779                                 break;
1780                         case DRM_MODE_DPMS_STANDBY:
1781                         case DRM_MODE_DPMS_SUSPEND:
1782                         case DRM_MODE_DPMS_OFF:
1783                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1784                                 break;
1785                         }
1786                 } else
1787                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1788                 break;
1789         default:
1790                 return;
1791         }
1792
1793         if (ext_encoder)
1794                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1795
1796         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1797
1798 }
1799
1800 union crtc_source_param {
1801         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1802         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1803 };
1804
1805 static void
1806 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1807 {
1808         struct drm_device *dev = encoder->dev;
1809         struct radeon_device *rdev = dev->dev_private;
1810         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1811         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1812         union crtc_source_param args;
1813         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1814         uint8_t frev, crev;
1815         struct radeon_encoder_atom_dig *dig;
1816
1817         memset(&args, 0, sizeof(args));
1818
1819         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1820                 return;
1821
1822         switch (frev) {
1823         case 1:
1824                 switch (crev) {
1825                 case 1:
1826                 default:
1827                         if (ASIC_IS_AVIVO(rdev))
1828                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1829                         else {
1830                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1831                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1832                                 } else {
1833                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1834                                 }
1835                         }
1836                         switch (radeon_encoder->encoder_id) {
1837                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1838                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1839                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1840                                 break;
1841                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1842                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1843                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1844                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1845                                 else
1846                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1847                                 break;
1848                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1849                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1850                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1851                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1852                                 break;
1853                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1854                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1855                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1856                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1857                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1858                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1859                                 else
1860                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1861                                 break;
1862                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1863                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1864                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1865                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1866                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1867                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1868                                 else
1869                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1870                                 break;
1871                         }
1872                         break;
1873                 case 2:
1874                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1875                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1876                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1877
1878                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1879                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1880                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1881                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1882                                 else
1883                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1884                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1885                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1886                         } else {
1887                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1888                         }
1889                         switch (radeon_encoder->encoder_id) {
1890                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1891                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1892                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1893                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1894                                 dig = radeon_encoder->enc_priv;
1895                                 switch (dig->dig_encoder) {
1896                                 case 0:
1897                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1898                                         break;
1899                                 case 1:
1900                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1901                                         break;
1902                                 case 2:
1903                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1904                                         break;
1905                                 case 3:
1906                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1907                                         break;
1908                                 case 4:
1909                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1910                                         break;
1911                                 case 5:
1912                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1913                                         break;
1914                                 }
1915                                 break;
1916                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1917                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1918                                 break;
1919                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1920                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1921                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1922                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1923                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1924                                 else
1925                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1926                                 break;
1927                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1928                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1929                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1930                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1931                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1932                                 else
1933                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1934                                 break;
1935                         }
1936                         break;
1937                 }
1938                 break;
1939         default:
1940                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1941                 return;
1942         }
1943
1944         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1945
1946         /* update scratch regs with new routing */
1947         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1948 }
1949
1950 static void
1951 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1952                               struct drm_display_mode *mode)
1953 {
1954         struct drm_device *dev = encoder->dev;
1955         struct radeon_device *rdev = dev->dev_private;
1956         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1957         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1958
1959         /* Funky macbooks */
1960         if ((dev->pdev->device == 0x71C5) &&
1961             (dev->pdev->subsystem_vendor == 0x106b) &&
1962             (dev->pdev->subsystem_device == 0x0080)) {
1963                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1964                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1965
1966                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1967                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1968
1969                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1970                 }
1971         }
1972
1973         /* set scaler clears this on some chips */
1974         if (ASIC_IS_AVIVO(rdev) &&
1975             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1976                 if (ASIC_IS_DCE4(rdev)) {
1977                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1978                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1979                                        EVERGREEN_INTERLEAVE_EN);
1980                         else
1981                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1982                 } else {
1983                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1984                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1985                                        AVIVO_D1MODE_INTERLEAVE_EN);
1986                         else
1987                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1988                 }
1989         }
1990 }
1991
1992 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1993 {
1994         struct drm_device *dev = encoder->dev;
1995         struct radeon_device *rdev = dev->dev_private;
1996         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1997         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1998         struct drm_encoder *test_encoder;
1999         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2000         uint32_t dig_enc_in_use = 0;
2001
2002         if (ASIC_IS_DCE6(rdev)) {
2003                 /* DCE6 */
2004                 switch (radeon_encoder->encoder_id) {
2005                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2006                         if (dig->linkb)
2007                                 return 1;
2008                         else
2009                                 return 0;
2010                         break;
2011                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2012                         if (dig->linkb)
2013                                 return 3;
2014                         else
2015                                 return 2;
2016                         break;
2017                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2018                         if (dig->linkb)
2019                                 return 5;
2020                         else
2021                                 return 4;
2022                         break;
2023                 }
2024         } else if (ASIC_IS_DCE4(rdev)) {
2025                 /* DCE4/5 */
2026                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2027                         /* ontario follows DCE4 */
2028                         if (rdev->family == CHIP_PALM) {
2029                                 if (dig->linkb)
2030                                         return 1;
2031                                 else
2032                                         return 0;
2033                         } else
2034                                 /* llano follows DCE3.2 */
2035                                 return radeon_crtc->crtc_id;
2036                 } else {
2037                         switch (radeon_encoder->encoder_id) {
2038                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2039                                 if (dig->linkb)
2040                                         return 1;
2041                                 else
2042                                         return 0;
2043                                 break;
2044                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2045                                 if (dig->linkb)
2046                                         return 3;
2047                                 else
2048                                         return 2;
2049                                 break;
2050                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2051                                 if (dig->linkb)
2052                                         return 5;
2053                                 else
2054                                         return 4;
2055                                 break;
2056                         }
2057                 }
2058         }
2059
2060         /* on DCE32 and encoder can driver any block so just crtc id */
2061         if (ASIC_IS_DCE32(rdev)) {
2062                 return radeon_crtc->crtc_id;
2063         }
2064
2065         /* on DCE3 - LVTMA can only be driven by DIGB */
2066         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2067                 struct radeon_encoder *radeon_test_encoder;
2068
2069                 if (encoder == test_encoder)
2070                         continue;
2071
2072                 if (!radeon_encoder_is_digital(test_encoder))
2073                         continue;
2074
2075                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2076                 dig = radeon_test_encoder->enc_priv;
2077
2078                 if (dig->dig_encoder >= 0)
2079                         dig_enc_in_use |= (1 << dig->dig_encoder);
2080         }
2081
2082         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2083                 if (dig_enc_in_use & 0x2)
2084                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2085                 return 1;
2086         }
2087         if (!(dig_enc_in_use & 1))
2088                 return 0;
2089         return 1;
2090 }
2091
2092 /* This only needs to be called once at startup */
2093 void
2094 radeon_atom_encoder_init(struct radeon_device *rdev)
2095 {
2096         struct drm_device *dev = rdev->ddev;
2097         struct drm_encoder *encoder;
2098
2099         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2100                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2101                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2102
2103                 switch (radeon_encoder->encoder_id) {
2104                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2105                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2106                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2107                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2108                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2109                         break;
2110                 default:
2111                         break;
2112                 }
2113
2114                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2115                         atombios_external_encoder_setup(encoder, ext_encoder,
2116                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2117         }
2118 }
2119
2120 static void
2121 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2122                              struct drm_display_mode *mode,
2123                              struct drm_display_mode *adjusted_mode)
2124 {
2125         struct drm_device *dev = encoder->dev;
2126         struct radeon_device *rdev = dev->dev_private;
2127         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2128
2129         radeon_encoder->pixel_clock = adjusted_mode->clock;
2130
2131         /* need to call this here rather than in prepare() since we need some crtc info */
2132         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2133
2134         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2135                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2136                         atombios_yuv_setup(encoder, true);
2137                 else
2138                         atombios_yuv_setup(encoder, false);
2139         }
2140
2141         switch (radeon_encoder->encoder_id) {
2142         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2143         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2144         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2145         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2146                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2147                 break;
2148         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2149         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2150         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2151         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2152                 /* handled in dpms */
2153                 break;
2154         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2155         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2156         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2157                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2158                 break;
2159         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2160         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2161         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2162         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2163                 atombios_dac_setup(encoder, ATOM_ENABLE);
2164                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2165                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2166                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2167                         else
2168                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2169                 }
2170                 break;
2171         }
2172
2173         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2174
2175         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2176                 if (rdev->asic->display.hdmi_enable)
2177                         radeon_hdmi_enable(rdev, encoder, true);
2178                 if (rdev->asic->display.hdmi_setmode)
2179                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2180         }
2181 }
2182
2183 static bool
2184 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2185 {
2186         struct drm_device *dev = encoder->dev;
2187         struct radeon_device *rdev = dev->dev_private;
2188         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2189         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2190
2191         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2192                                        ATOM_DEVICE_CV_SUPPORT |
2193                                        ATOM_DEVICE_CRT_SUPPORT)) {
2194                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2195                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2196                 uint8_t frev, crev;
2197
2198                 memset(&args, 0, sizeof(args));
2199
2200                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2201                         return false;
2202
2203                 args.sDacload.ucMisc = 0;
2204
2205                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2206                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2207                         args.sDacload.ucDacType = ATOM_DAC_A;
2208                 else
2209                         args.sDacload.ucDacType = ATOM_DAC_B;
2210
2211                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2212                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2213                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2214                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2215                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2216                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2217                         if (crev >= 3)
2218                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2219                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2220                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2221                         if (crev >= 3)
2222                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2223                 }
2224
2225                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2226
2227                 return true;
2228         } else
2229                 return false;
2230 }
2231
2232 static enum drm_connector_status
2233 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2234 {
2235         struct drm_device *dev = encoder->dev;
2236         struct radeon_device *rdev = dev->dev_private;
2237         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2238         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2239         uint32_t bios_0_scratch;
2240
2241         if (!atombios_dac_load_detect(encoder, connector)) {
2242                 DRM_DEBUG_KMS("detect returned false \n");
2243                 return connector_status_unknown;
2244         }
2245
2246         if (rdev->family >= CHIP_R600)
2247                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2248         else
2249                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2250
2251         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2252         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2253                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2254                         return connector_status_connected;
2255         }
2256         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2257                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2258                         return connector_status_connected;
2259         }
2260         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2261                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2262                         return connector_status_connected;
2263         }
2264         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2265                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2266                         return connector_status_connected; /* CTV */
2267                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2268                         return connector_status_connected; /* STV */
2269         }
2270         return connector_status_disconnected;
2271 }
2272
2273 static enum drm_connector_status
2274 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2275 {
2276         struct drm_device *dev = encoder->dev;
2277         struct radeon_device *rdev = dev->dev_private;
2278         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2279         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2280         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2281         u32 bios_0_scratch;
2282
2283         if (!ASIC_IS_DCE4(rdev))
2284                 return connector_status_unknown;
2285
2286         if (!ext_encoder)
2287                 return connector_status_unknown;
2288
2289         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2290                 return connector_status_unknown;
2291
2292         /* load detect on the dp bridge */
2293         atombios_external_encoder_setup(encoder, ext_encoder,
2294                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2295
2296         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2297
2298         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2299         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2300                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2301                         return connector_status_connected;
2302         }
2303         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2304                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2305                         return connector_status_connected;
2306         }
2307         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2308                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2309                         return connector_status_connected;
2310         }
2311         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2312                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2313                         return connector_status_connected; /* CTV */
2314                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2315                         return connector_status_connected; /* STV */
2316         }
2317         return connector_status_disconnected;
2318 }
2319
2320 void
2321 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2322 {
2323         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2324
2325         if (ext_encoder)
2326                 /* ddc_setup on the dp bridge */
2327                 atombios_external_encoder_setup(encoder, ext_encoder,
2328                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2329
2330 }
2331
2332 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2333 {
2334         struct radeon_device *rdev = encoder->dev->dev_private;
2335         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2336         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2337
2338         if ((radeon_encoder->active_device &
2339              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2340             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2341              ENCODER_OBJECT_ID_NONE)) {
2342                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2343                 if (dig) {
2344                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2345                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2346                                 if (rdev->family >= CHIP_R600)
2347                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2348                                 else
2349                                         /* RS600/690/740 have only 1 afmt block */
2350                                         dig->afmt = rdev->mode_info.afmt[0];
2351                         }
2352                 }
2353         }
2354
2355         radeon_atom_output_lock(encoder, true);
2356
2357         if (connector) {
2358                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2359
2360                 /* select the clock/data port if it uses a router */
2361                 if (radeon_connector->router.cd_valid)
2362                         radeon_router_select_cd_port(radeon_connector);
2363
2364                 /* turn eDP panel on for mode set */
2365                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2366                         atombios_set_edp_panel_power(connector,
2367                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2368         }
2369
2370         /* this is needed for the pll/ss setup to work correctly in some cases */
2371         atombios_set_encoder_crtc_source(encoder);
2372 }
2373
2374 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2375 {
2376         /* need to call this here as we need the crtc set up */
2377         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2378         radeon_atom_output_lock(encoder, false);
2379 }
2380
2381 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2382 {
2383         struct drm_device *dev = encoder->dev;
2384         struct radeon_device *rdev = dev->dev_private;
2385         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2386         struct radeon_encoder_atom_dig *dig;
2387
2388         /* check for pre-DCE3 cards with shared encoders;
2389          * can't really use the links individually, so don't disable
2390          * the encoder if it's in use by another connector
2391          */
2392         if (!ASIC_IS_DCE3(rdev)) {
2393                 struct drm_encoder *other_encoder;
2394                 struct radeon_encoder *other_radeon_encoder;
2395
2396                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2397                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2398                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2399                             drm_helper_encoder_in_use(other_encoder))
2400                                 goto disable_done;
2401                 }
2402         }
2403
2404         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2405
2406         switch (radeon_encoder->encoder_id) {
2407         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2408         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2409         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2410         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2411                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2412                 break;
2413         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2414         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2415         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2416         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2417                 /* handled in dpms */
2418                 break;
2419         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2420         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2421         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2422                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2423                 break;
2424         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2425         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2426         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2427         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2428                 atombios_dac_setup(encoder, ATOM_DISABLE);
2429                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2430                         atombios_tv_setup(encoder, ATOM_DISABLE);
2431                 break;
2432         }
2433
2434 disable_done:
2435         if (radeon_encoder_is_digital(encoder)) {
2436                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2437                         if (rdev->asic->display.hdmi_enable)
2438                                 radeon_hdmi_enable(rdev, encoder, false);
2439                 }
2440                 dig = radeon_encoder->enc_priv;
2441                 dig->dig_encoder = -1;
2442         }
2443         radeon_encoder->active_device = 0;
2444 }
2445
2446 /* these are handled by the primary encoders */
2447 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2448 {
2449
2450 }
2451
2452 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2453 {
2454
2455 }
2456
2457 static void
2458 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2459                          struct drm_display_mode *mode,
2460                          struct drm_display_mode *adjusted_mode)
2461 {
2462
2463 }
2464
2465 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2466 {
2467
2468 }
2469
2470 static void
2471 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2472 {
2473
2474 }
2475
2476 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2477                                        const struct drm_display_mode *mode,
2478                                        struct drm_display_mode *adjusted_mode)
2479 {
2480         return true;
2481 }
2482
2483 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2484         .dpms = radeon_atom_ext_dpms,
2485         .mode_fixup = radeon_atom_ext_mode_fixup,
2486         .prepare = radeon_atom_ext_prepare,
2487         .mode_set = radeon_atom_ext_mode_set,
2488         .commit = radeon_atom_ext_commit,
2489         .disable = radeon_atom_ext_disable,
2490         /* no detect for TMDS/LVDS yet */
2491 };
2492
2493 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2494         .dpms = radeon_atom_encoder_dpms,
2495         .mode_fixup = radeon_atom_mode_fixup,
2496         .prepare = radeon_atom_encoder_prepare,
2497         .mode_set = radeon_atom_encoder_mode_set,
2498         .commit = radeon_atom_encoder_commit,
2499         .disable = radeon_atom_encoder_disable,
2500         .detect = radeon_atom_dig_detect,
2501 };
2502
2503 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2504         .dpms = radeon_atom_encoder_dpms,
2505         .mode_fixup = radeon_atom_mode_fixup,
2506         .prepare = radeon_atom_encoder_prepare,
2507         .mode_set = radeon_atom_encoder_mode_set,
2508         .commit = radeon_atom_encoder_commit,
2509         .detect = radeon_atom_dac_detect,
2510 };
2511
2512 void radeon_enc_destroy(struct drm_encoder *encoder)
2513 {
2514         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2515         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2516                 radeon_atom_backlight_exit(radeon_encoder);
2517         kfree(radeon_encoder->enc_priv);
2518         drm_encoder_cleanup(encoder);
2519         kfree(radeon_encoder);
2520 }
2521
2522 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2523         .destroy = radeon_enc_destroy,
2524 };
2525
2526 static struct radeon_encoder_atom_dac *
2527 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2528 {
2529         struct drm_device *dev = radeon_encoder->base.dev;
2530         struct radeon_device *rdev = dev->dev_private;
2531         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2532
2533         if (!dac)
2534                 return NULL;
2535
2536         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2537         return dac;
2538 }
2539
2540 static struct radeon_encoder_atom_dig *
2541 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2542 {
2543         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2544         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2545
2546         if (!dig)
2547                 return NULL;
2548
2549         /* coherent mode by default */
2550         dig->coherent_mode = true;
2551         dig->dig_encoder = -1;
2552
2553         if (encoder_enum == 2)
2554                 dig->linkb = true;
2555         else
2556                 dig->linkb = false;
2557
2558         return dig;
2559 }
2560
2561 void
2562 radeon_add_atom_encoder(struct drm_device *dev,
2563                         uint32_t encoder_enum,
2564                         uint32_t supported_device,
2565                         u16 caps)
2566 {
2567         struct radeon_device *rdev = dev->dev_private;
2568         struct drm_encoder *encoder;
2569         struct radeon_encoder *radeon_encoder;
2570
2571         /* see if we already added it */
2572         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2573                 radeon_encoder = to_radeon_encoder(encoder);
2574                 if (radeon_encoder->encoder_enum == encoder_enum) {
2575                         radeon_encoder->devices |= supported_device;
2576                         return;
2577                 }
2578
2579         }
2580
2581         /* add a new one */
2582         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2583         if (!radeon_encoder)
2584                 return;
2585
2586         encoder = &radeon_encoder->base;
2587         switch (rdev->num_crtc) {
2588         case 1:
2589                 encoder->possible_crtcs = 0x1;
2590                 break;
2591         case 2:
2592         default:
2593                 encoder->possible_crtcs = 0x3;
2594                 break;
2595         case 4:
2596                 encoder->possible_crtcs = 0xf;
2597                 break;
2598         case 6:
2599                 encoder->possible_crtcs = 0x3f;
2600                 break;
2601         }
2602
2603         radeon_encoder->enc_priv = NULL;
2604
2605         radeon_encoder->encoder_enum = encoder_enum;
2606         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2607         radeon_encoder->devices = supported_device;
2608         radeon_encoder->rmx_type = RMX_OFF;
2609         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2610         radeon_encoder->is_ext_encoder = false;
2611         radeon_encoder->caps = caps;
2612
2613         switch (radeon_encoder->encoder_id) {
2614         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2615         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2616         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2617         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2618                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2619                         radeon_encoder->rmx_type = RMX_FULL;
2620                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2621                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2622                 } else {
2623                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2624                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2625                 }
2626                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2627                 break;
2628         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2629                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2630                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2631                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2632                 break;
2633         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2634         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2635         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2636                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2637                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2638                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2639                 break;
2640         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2641         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2642         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2643         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2644         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2645         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2646         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2647                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2648                         radeon_encoder->rmx_type = RMX_FULL;
2649                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2650                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2651                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2652                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2653                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2654                 } else {
2655                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2656                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2657                 }
2658                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2659                 break;
2660         case ENCODER_OBJECT_ID_SI170B:
2661         case ENCODER_OBJECT_ID_CH7303:
2662         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2663         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2664         case ENCODER_OBJECT_ID_TITFP513:
2665         case ENCODER_OBJECT_ID_VT1623:
2666         case ENCODER_OBJECT_ID_HDMI_SI1930:
2667         case ENCODER_OBJECT_ID_TRAVIS:
2668         case ENCODER_OBJECT_ID_NUTMEG:
2669                 /* these are handled by the primary encoders */
2670                 radeon_encoder->is_ext_encoder = true;
2671                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2672                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2673                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2674                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2675                 else
2676                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2677                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2678                 break;
2679         }
2680 }