drivers/gpu/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98         int r = 0;
  99
 100         memset(&args, 0, sizeof(args));
 101
 102         mutex_lock(&chan->mutex);
 103         mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
 104
 105         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 106
 107         radeon_atom_copy_swap(base, send, send_bytes, true);
 108
 109         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 110         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 111         args.v1.ucDataOutLen = 0;
 112         args.v1.ucChannelID = chan->rec.i2c_id;
 113         args.v1.ucDelay = delay / 10;
 114         if (ASIC_IS_DCE4(rdev))
 115                 args.v2.ucHPD_ID = chan->rec.hpd;
 116
 117         atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118
 119         *ack = args.v1.ucReplyStatus;
 120
 121         /* timeout */
 122         if (args.v1.ucReplyStatus == 1) {
 123                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 124                 r = -ETIMEDOUT;
 125                 goto done;
 126         }
 127
 128         /* flags not zero */
 129         if (args.v1.ucReplyStatus == 2) {
 130                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 131                 r = -EIO;
 132                 goto done;
 133         }
 134
 135         /* error */
 136         if (args.v1.ucReplyStatus == 3) {
 137                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 138                 r = -EIO;
 139                 goto done;
 140         }
 141
 142         recv_bytes = args.v1.ucDataOutLen;
 143         if (recv_bytes > recv_size)
 144                 recv_bytes = recv_size;
 145
 146         if (recv && recv_size)
 147                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
 148
 149         r = recv_bytes;
 150 done:
 151         mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
 152         mutex_unlock(&chan->mutex);
 153
 154         return r;
 155 }
 156
 157 #define BARE_ADDRESS_SIZE 3
 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 159
 160 static ssize_t
 161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 162 {
 163         struct radeon_i2c_chan *chan =
 164                 container_of(aux, struct radeon_i2c_chan, aux);
 165         int ret;
 166         u8 tx_buf[20];
 167         size_t tx_size;
 168         u8 ack, delay = 0;
 169
 170         if (WARN_ON(msg->size > 16))
 171                 return -E2BIG;
 172
 173         tx_buf[0] = msg->address & 0xff;
 174         tx_buf[1] = (msg->address >> 8) & 0xff;
 175         tx_buf[2] = (msg->request << 4) |
 176                 ((msg->address >> 16) & 0xf);
 177         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 178
 179         switch (msg->request & ~DP_AUX_I2C_MOT) {
 180         case DP_AUX_NATIVE_WRITE:
 181         case DP_AUX_I2C_WRITE:
 182         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 183                 /* The atom implementation only supports writes with a max payload of
 184                  * 12 bytes since it uses 4 bits for the total count (header + payload)
 185                  * in the parameter space.  The atom interface supports 16 byte
 186                  * payloads for reads. The hw itself supports up to 16 bytes of payload.
 187                  */
 188                 if (WARN_ON_ONCE(msg->size > 12))
 189                         return -E2BIG;
 190                 /* tx_size needs to be 4 even for bare address packets since the atom
 191                  * table needs the info in tx_buf[3].
 192                  */
 193                 tx_size = HEADER_SIZE + msg->size;
 194                 if (msg->size == 0)
 195                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 196                 else
 197                         tx_buf[3] |= tx_size << 4;
 198                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 199                 ret = radeon_process_aux_ch(chan,
 200                                             tx_buf, tx_size, NULL, 0, delay, &ack);
 201                 if (ret >= 0)
 202                         /* Return payload size. */
 203                         ret = msg->size;
 204                 break;
 205         case DP_AUX_NATIVE_READ:
 206         case DP_AUX_I2C_READ:
 207                 /* tx_size needs to be 4 even for bare address packets since the atom
 208                  * table needs the info in tx_buf[3].
 209                  */
 210                 tx_size = HEADER_SIZE;
 211                 if (msg->size == 0)
 212                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 213                 else
 214                         tx_buf[3] |= tx_size << 4;
 215                 ret = radeon_process_aux_ch(chan,
 216                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 217                 break;
 218         default:
 219                 ret = -EINVAL;
 220                 break;
 221         }
 222
 223         if (ret >= 0)
 224                 msg->reply = ack >> 4;
 225
 226         return ret;
 227 }
 228
 229 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 230 {
 231         struct drm_device *dev = radeon_connector->base.dev;
 232         struct radeon_device *rdev = dev->dev_private;
 233         int ret;
 234
 235         radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
 236         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
 237         if (ASIC_IS_DCE5(rdev)) {
 238                 if (radeon_auxch)
 239                         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
 240                 else
 241                         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
 242         } else {
 243                 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
 244         }
 245
 246         ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
 247         if (!ret)
 248                 radeon_connector->ddc_bus->has_aux = true;
 249
 250         WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
 251 }
 252
 253 /***** general DP utility functions *****/
 254
 255 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 256 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 257
 258 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
 259                                 int lane_count,
 260                                 u8 train_set[4])
 261 {
 262         u8 v = 0;
 263         u8 p = 0;
 264         int lane;
 265
 266         for (lane = 0; lane < lane_count; lane++) {
 267                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 268                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 269
 270                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 271                           lane,
 272                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 273                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 274
 275                 if (this_v > v)
 276                         v = this_v;
 277                 if (this_p > p)
 278                         p = this_p;
 279         }
 280
 281         if (v >= DP_VOLTAGE_MAX)
 282                 v |= DP_TRAIN_MAX_SWING_REACHED;
 283
 284         if (p >= DP_PRE_EMPHASIS_MAX)
 285                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 286
 287         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 288                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 289                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 290
 291         for (lane = 0; lane < 4; lane++)
 292                 train_set[lane] = v | p;
 293 }
 294
 295 /* convert bits per color to bits per pixel */
 296 /* get bpc from the EDID */
 297 static int convert_bpc_to_bpp(int bpc)
 298 {
 299         if (bpc == 0)
 300                 return 24;
 301         else
 302                 return bpc * 3;
 303 }
 304
 305 /***** radeon specific DP functions *****/
 306
 307 int radeon_dp_get_dp_link_config(struct drm_connector *connector,
 308                                  const u8 dpcd[DP_DPCD_SIZE],
 309                                  unsigned pix_clock,
 310                                  unsigned *dp_lanes, unsigned *dp_rate)
 311 {
 312         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 313         static const unsigned link_rates[3] = { 162000, 270000, 540000 };
 314         unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
 315         unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
 316         unsigned lane_num, i, max_pix_clock;
 317
 318         for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 319                 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
 320                         max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
 321                         if (max_pix_clock >= pix_clock) {
 322                                 *dp_lanes = lane_num;
 323                                 *dp_rate = link_rates[i];
 324                                 return 0;
 325                         }
 326                 }
 327         }
 328
 329         return -EINVAL;
 330 }
 331
 332 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 333                                     int action, int dp_clock,
 334                                     u8 ucconfig, u8 lane_num)
 335 {
 336         DP_ENCODER_SERVICE_PARAMETERS args;
 337         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 338
 339         memset(&args, 0, sizeof(args));
 340         args.ucLinkClock = dp_clock / 10;
 341         args.ucConfig = ucconfig;
 342         args.ucAction = action;
 343         args.ucLaneNum = lane_num;
 344         args.ucStatus = 0;
 345
 346         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 347         return args.ucStatus;
 348 }
 349
 350 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 351 {
 352         struct drm_device *dev = radeon_connector->base.dev;
 353         struct radeon_device *rdev = dev->dev_private;
 354
 355         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 356                                          radeon_connector->ddc_bus->rec.i2c_id, 0);
 357 }
 358
 359 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 360 {
 361         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 362         u8 buf[3];
 363
 364         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 365                 return;
 366
 367         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 368                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 369                               buf[0], buf[1], buf[2]);
 370
 371         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 372                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 373                               buf[0], buf[1], buf[2]);
 374 }
 375
 376 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 377 {
 378         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 379         u8 msg[DP_DPCD_SIZE];
 380         int ret, i;
 381
 382         for (i = 0; i < 7; i++) {
 383                 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
 384                                        DP_DPCD_SIZE);
 385                 if (ret == DP_DPCD_SIZE) {
 386                         memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 387
 388                         DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 389                                       dig_connector->dpcd);
 390
 391                         radeon_dp_probe_oui(radeon_connector);
 392
 393                         return true;
 394                 }
 395         }
 396         dig_connector->dpcd[0] = 0;
 397         return false;
 398 }
 399
 400 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 401                              struct drm_connector *connector)
 402 {
 403         struct drm_device *dev = encoder->dev;
 404         struct radeon_device *rdev = dev->dev_private;
 405         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 406         struct radeon_connector_atom_dig *dig_connector;
 407         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 408         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 409         u8 tmp;
 410
 411         if (!ASIC_IS_DCE4(rdev))
 412                 return panel_mode;
 413
 414         if (!radeon_connector->con_priv)
 415                 return panel_mode;
 416
 417         dig_connector = radeon_connector->con_priv;
 418
 419         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 420                 /* DP bridge chips */
 421                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 422                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 423                         if (tmp & 1)
 424                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 425                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 426                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 427                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 428                         else
 429                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 430                 }
 431         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 432                 /* eDP */
 433                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 434                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 435                         if (tmp & 1)
 436                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 437                 }
 438         }
 439
 440         return panel_mode;
 441 }
 442
 443 void radeon_dp_set_link_config(struct drm_connector *connector,
 444                                const struct drm_display_mode *mode)
 445 {
 446         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 447         struct radeon_connector_atom_dig *dig_connector;
 448         int ret;
 449
 450         if (!radeon_connector->con_priv)
 451                 return;
 452         dig_connector = radeon_connector->con_priv;
 453
 454         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 455             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 456                 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
 457                                                    mode->clock,
 458                                                    &dig_connector->dp_lane_count,
 459                                                    &dig_connector->dp_clock);
 460                 if (ret) {
 461                         dig_connector->dp_clock = 0;
 462                         dig_connector->dp_lane_count = 0;
 463                 }
 464         }
 465 }
 466
 467 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 468                                 struct drm_display_mode *mode)
 469 {
 470         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 471         struct radeon_connector_atom_dig *dig_connector;
 472         unsigned dp_clock, dp_lanes;
 473         int ret;
 474
 475         if ((mode->clock > 340000) &&
 476             (!radeon_connector_is_dp12_capable(connector)))
 477                 return MODE_CLOCK_HIGH;
 478
 479         if (!radeon_connector->con_priv)
 480                 return MODE_CLOCK_HIGH;
 481         dig_connector = radeon_connector->con_priv;
 482
 483         ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
 484                                            mode->clock,
 485                                            &dp_lanes,
 486                                            &dp_clock);
 487         if (ret)
 488                 return MODE_CLOCK_HIGH;
 489
 490         if ((dp_clock == 540000) &&
 491             (!radeon_connector_is_dp12_capable(connector)))
 492                 return MODE_CLOCK_HIGH;
 493
 494         return MODE_OK;
 495 }
 496
 497 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 498 {
 499         u8 link_status[DP_LINK_STATUS_SIZE];
 500         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 501
 502         if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
 503             <= 0)
 504                 return false;
 505         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 506                 return false;
 507         return true;
 508 }
 509
 510 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 511                                   u8 power_state)
 512 {
 513         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 514         struct radeon_connector_atom_dig *dig_connector;
 515
 516         if (!radeon_connector->con_priv)
 517                 return;
 518
 519         dig_connector = radeon_connector->con_priv;
 520
 521         /* power up/down the sink */
 522         if (dig_connector->dpcd[0] >= 0x11) {
 523                 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
 524                                    DP_SET_POWER, power_state);
 525                 usleep_range(1000, 2000);
 526         }
 527 }
 528
 529
 530 struct radeon_dp_link_train_info {
 531         struct radeon_device *rdev;
 532         struct drm_encoder *encoder;
 533         struct drm_connector *connector;
 534         int enc_id;
 535         int dp_clock;
 536         int dp_lane_count;
 537         bool tp3_supported;
 538         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 539         u8 train_set[4];
 540         u8 link_status[DP_LINK_STATUS_SIZE];
 541         u8 tries;
 542         bool use_dpencoder;
 543         struct drm_dp_aux *aux;
 544 };
 545
 546 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 547 {
 548         /* set the initial vs/emph on the source */
 549         atombios_dig_transmitter_setup(dp_info->encoder,
 550                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 551                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 552
 553         /* set the vs/emph on the sink */
 554         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 555                           dp_info->train_set, dp_info->dp_lane_count);
 556 }
 557
 558 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 559 {
 560         int rtp = 0;
 561
 562         /* set training pattern on the source */
 563         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 564                 switch (tp) {
 565                 case DP_TRAINING_PATTERN_1:
 566                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 567                         break;
 568                 case DP_TRAINING_PATTERN_2:
 569                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 570                         break;
 571                 case DP_TRAINING_PATTERN_3:
 572                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 573                         break;
 574                 }
 575                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 576         } else {
 577                 switch (tp) {
 578                 case DP_TRAINING_PATTERN_1:
 579                         rtp = 0;
 580                         break;
 581                 case DP_TRAINING_PATTERN_2:
 582                         rtp = 1;
 583                         break;
 584                 }
 585                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 586                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 587         }
 588
 589         /* enable training pattern on the sink */
 590         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 591 }
 592
 593 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 594 {
 595         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 596         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 597         u8 tmp;
 598
 599         /* power up the sink */
 600         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 601
 602         /* possibly enable downspread on the sink */
 603         if (dp_info->dpcd[3] & 0x1)
 604                 drm_dp_dpcd_writeb(dp_info->aux,
 605                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 606         else
 607                 drm_dp_dpcd_writeb(dp_info->aux,
 608                                    DP_DOWNSPREAD_CTRL, 0);
 609
 610         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 611                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 612
 613         /* set the lane count on the sink */
 614         tmp = dp_info->dp_lane_count;
 615         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 616                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 617         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 618
 619         /* set the link rate on the sink */
 620         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 621         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 622
 623         /* start training on the source */
 624         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 625                 atombios_dig_encoder_setup(dp_info->encoder,
 626                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 627         else
 628                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 629                                           dp_info->dp_clock, dp_info->enc_id, 0);
 630
 631         /* disable the training pattern on the sink */
 632         drm_dp_dpcd_writeb(dp_info->aux,
 633                            DP_TRAINING_PATTERN_SET,
 634                            DP_TRAINING_PATTERN_DISABLE);
 635
 636         return 0;
 637 }
 638
 639 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 640 {
 641         udelay(400);
 642
 643         /* disable the training pattern on the sink */
 644         drm_dp_dpcd_writeb(dp_info->aux,
 645                            DP_TRAINING_PATTERN_SET,
 646                            DP_TRAINING_PATTERN_DISABLE);
 647
 648         /* disable the training pattern on the source */
 649         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 650                 atombios_dig_encoder_setup(dp_info->encoder,
 651                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 652         else
 653                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 654                                           dp_info->dp_clock, dp_info->enc_id, 0);
 655
 656         return 0;
 657 }
 658
 659 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 660 {
 661         bool clock_recovery;
 662         u8 voltage;
 663         int i;
 664
 665         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 666         memset(dp_info->train_set, 0, 4);
 667         radeon_dp_update_vs_emph(dp_info);
 668
 669         udelay(400);
 670
 671         /* clock recovery loop */
 672         clock_recovery = false;
 673         dp_info->tries = 0;
 674         voltage = 0xff;
 675         while (1) {
 676                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 677
 678                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 679                                                  dp_info->link_status) <= 0) {
 680                         DRM_ERROR("displayport link status failed\n");
 681                         break;
 682                 }
 683
 684                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 685                         clock_recovery = true;
 686                         break;
 687                 }
 688
 689                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 690                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 691                                 break;
 692                 }
 693                 if (i == dp_info->dp_lane_count) {
 694                         DRM_ERROR("clock recovery reached max voltage\n");
 695                         break;
 696                 }
 697
 698                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 699                         ++dp_info->tries;
 700                         if (dp_info->tries == 5) {
 701                                 DRM_ERROR("clock recovery tried 5 times\n");
 702                                 break;
 703                         }
 704                 } else
 705                         dp_info->tries = 0;
 706
 707                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 708
 709                 /* Compute new train_set as requested by sink */
 710                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 711
 712                 radeon_dp_update_vs_emph(dp_info);
 713         }
 714         if (!clock_recovery) {
 715                 DRM_ERROR("clock recovery failed\n");
 716                 return -1;
 717         } else {
 718                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 719                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 720                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 721                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 722                 return 0;
 723         }
 724 }
 725
 726 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 727 {
 728         bool channel_eq;
 729
 730         if (dp_info->tp3_supported)
 731                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 732         else
 733                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 734
 735         /* channel equalization loop */
 736         dp_info->tries = 0;
 737         channel_eq = false;
 738         while (1) {
 739                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 740
 741                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 742                                                  dp_info->link_status) <= 0) {
 743                         DRM_ERROR("displayport link status failed\n");
 744                         break;
 745                 }
 746
 747                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 748                         channel_eq = true;
 749                         break;
 750                 }
 751
 752                 /* Try 5 times */
 753                 if (dp_info->tries > 5) {
 754                         DRM_ERROR("channel eq failed: 5 tries\n");
 755                         break;
 756                 }
 757
 758                 /* Compute new train_set as requested by sink */
 759                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 760
 761                 radeon_dp_update_vs_emph(dp_info);
 762                 dp_info->tries++;
 763         }
 764
 765         if (!channel_eq) {
 766                 DRM_ERROR("channel eq failed\n");
 767                 return -1;
 768         } else {
 769                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 770                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 771                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 772                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 773                 return 0;
 774         }
 775 }
 776
 777 void radeon_dp_link_train(struct drm_encoder *encoder,
 778                           struct drm_connector *connector)
 779 {
 780         struct drm_device *dev = encoder->dev;
 781         struct radeon_device *rdev = dev->dev_private;
 782         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 783         struct radeon_encoder_atom_dig *dig;
 784         struct radeon_connector *radeon_connector;
 785         struct radeon_connector_atom_dig *dig_connector;
 786         struct radeon_dp_link_train_info dp_info;
 787         int index;
 788         u8 tmp, frev, crev;
 789
 790         if (!radeon_encoder->enc_priv)
 791                 return;
 792         dig = radeon_encoder->enc_priv;
 793
 794         radeon_connector = to_radeon_connector(connector);
 795         if (!radeon_connector->con_priv)
 796                 return;
 797         dig_connector = radeon_connector->con_priv;
 798
 799         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 800             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 801                 return;
 802
 803         /* DPEncoderService newer than 1.1 can't program properly the
 804          * training pattern. When facing such version use the
 805          * DIGXEncoderControl (X== 1 | 2)
 806          */
 807         dp_info.use_dpencoder = true;
 808         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 809         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 810                 if (crev > 1) {
 811                         dp_info.use_dpencoder = false;
 812                 }
 813         }
 814
 815         dp_info.enc_id = 0;
 816         if (dig->dig_encoder)
 817                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 818         else
 819                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 820         if (dig->linkb)
 821                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 822         else
 823                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 824
 825         if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 826             == 1) {
 827                 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 828                         dp_info.tp3_supported = true;
 829                 else
 830                         dp_info.tp3_supported = false;
 831         } else {
 832                 dp_info.tp3_supported = false;
 833         }
 834
 835         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 836         dp_info.rdev = rdev;
 837         dp_info.encoder = encoder;
 838         dp_info.connector = connector;
 839         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 840         dp_info.dp_clock = dig_connector->dp_clock;
 841         dp_info.aux = &radeon_connector->ddc_bus->aux;
 842
 843         if (radeon_dp_link_train_init(&dp_info))
 844                 goto done;
 845         if (radeon_dp_link_train_cr(&dp_info))
 846                 goto done;
 847         if (radeon_dp_link_train_ce(&dp_info))
 848                 goto done;
 849 done:
 850         if (radeon_dp_link_train_finish(&dp_info))
 851                 return;
 852 }