drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42 #include "nouveau_fifo.h"
  43 #include "nouveau_fence.h"
  44 #include "nouveau_software.h"
  45
  46 static void nouveau_stub_takedown(struct drm_device *dev) {}
  47 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  48
  49 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  50 {
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         struct nouveau_engine *engine = &dev_priv->engine;
  53
  54         switch (dev_priv->chipset & 0xf0) {
  55         case 0x00:
  56                 engine->instmem.init            = nv04_instmem_init;
  57                 engine->instmem.takedown        = nv04_instmem_takedown;
  58                 engine->instmem.suspend         = nv04_instmem_suspend;
  59                 engine->instmem.resume          = nv04_instmem_resume;
  60                 engine->instmem.get             = nv04_instmem_get;
  61                 engine->instmem.put             = nv04_instmem_put;
  62                 engine->instmem.map             = nv04_instmem_map;
  63                 engine->instmem.unmap           = nv04_instmem_unmap;
  64                 engine->instmem.flush           = nv04_instmem_flush;
  65                 engine->mc.init                 = nv04_mc_init;
  66                 engine->mc.takedown             = nv04_mc_takedown;
  67                 engine->timer.init              = nv04_timer_init;
  68                 engine->timer.read              = nv04_timer_read;
  69                 engine->timer.takedown          = nv04_timer_takedown;
  70                 engine->fb.init                 = nv04_fb_init;
  71                 engine->fb.takedown             = nv04_fb_takedown;
  72                 engine->display.early_init      = nv04_display_early_init;
  73                 engine->display.late_takedown   = nv04_display_late_takedown;
  74                 engine->display.create          = nv04_display_create;
  75                 engine->display.destroy         = nv04_display_destroy;
  76                 engine->display.init            = nv04_display_init;
  77                 engine->display.fini            = nv04_display_fini;
  78                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  79                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  80                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  81                 engine->vram.init               = nv04_fb_vram_init;
  82                 engine->vram.takedown           = nouveau_stub_takedown;
  83                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  84                 break;
  85         case 0x10:
  86                 engine->instmem.init            = nv04_instmem_init;
  87                 engine->instmem.takedown        = nv04_instmem_takedown;
  88                 engine->instmem.suspend         = nv04_instmem_suspend;
  89                 engine->instmem.resume          = nv04_instmem_resume;
  90                 engine->instmem.get             = nv04_instmem_get;
  91                 engine->instmem.put             = nv04_instmem_put;
  92                 engine->instmem.map             = nv04_instmem_map;
  93                 engine->instmem.unmap           = nv04_instmem_unmap;
  94                 engine->instmem.flush           = nv04_instmem_flush;
  95                 engine->mc.init                 = nv04_mc_init;
  96                 engine->mc.takedown             = nv04_mc_takedown;
  97                 engine->timer.init              = nv04_timer_init;
  98                 engine->timer.read              = nv04_timer_read;
  99                 engine->timer.takedown          = nv04_timer_takedown;
 100                 engine->fb.init                 = nv10_fb_init;
 101                 engine->fb.takedown             = nv10_fb_takedown;
 102                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 103                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 104                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 105                 engine->display.early_init      = nv04_display_early_init;
 106                 engine->display.late_takedown   = nv04_display_late_takedown;
 107                 engine->display.create          = nv04_display_create;
 108                 engine->display.destroy         = nv04_display_destroy;
 109                 engine->display.init            = nv04_display_init;
 110                 engine->display.fini            = nv04_display_fini;
 111                 engine->gpio.drive              = nv10_gpio_drive;
 112                 engine->gpio.sense              = nv10_gpio_sense;
 113                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 114                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 115                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 116                 if (dev_priv->chipset == 0x1a ||
 117                     dev_priv->chipset == 0x1f)
 118                         engine->vram.init       = nv1a_fb_vram_init;
 119                 else
 120                         engine->vram.init       = nv10_fb_vram_init;
 121                 engine->vram.takedown           = nouveau_stub_takedown;
 122                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 123                 break;
 124         case 0x20:
 125                 engine->instmem.init            = nv04_instmem_init;
 126                 engine->instmem.takedown        = nv04_instmem_takedown;
 127                 engine->instmem.suspend         = nv04_instmem_suspend;
 128                 engine->instmem.resume          = nv04_instmem_resume;
 129                 engine->instmem.get             = nv04_instmem_get;
 130                 engine->instmem.put             = nv04_instmem_put;
 131                 engine->instmem.map             = nv04_instmem_map;
 132                 engine->instmem.unmap           = nv04_instmem_unmap;
 133                 engine->instmem.flush           = nv04_instmem_flush;
 134                 engine->mc.init                 = nv04_mc_init;
 135                 engine->mc.takedown             = nv04_mc_takedown;
 136                 engine->timer.init              = nv04_timer_init;
 137                 engine->timer.read              = nv04_timer_read;
 138                 engine->timer.takedown          = nv04_timer_takedown;
 139                 engine->fb.init                 = nv20_fb_init;
 140                 engine->fb.takedown             = nv20_fb_takedown;
 141                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 142                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 143                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 144                 engine->display.early_init      = nv04_display_early_init;
 145                 engine->display.late_takedown   = nv04_display_late_takedown;
 146                 engine->display.create          = nv04_display_create;
 147                 engine->display.destroy         = nv04_display_destroy;
 148                 engine->display.init            = nv04_display_init;
 149                 engine->display.fini            = nv04_display_fini;
 150                 engine->gpio.drive              = nv10_gpio_drive;
 151                 engine->gpio.sense              = nv10_gpio_sense;
 152                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 153                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 154                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 155                 engine->vram.init               = nv20_fb_vram_init;
 156                 engine->vram.takedown           = nouveau_stub_takedown;
 157                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 158                 break;
 159         case 0x30:
 160                 engine->instmem.init            = nv04_instmem_init;
 161                 engine->instmem.takedown        = nv04_instmem_takedown;
 162                 engine->instmem.suspend         = nv04_instmem_suspend;
 163                 engine->instmem.resume          = nv04_instmem_resume;
 164                 engine->instmem.get             = nv04_instmem_get;
 165                 engine->instmem.put             = nv04_instmem_put;
 166                 engine->instmem.map             = nv04_instmem_map;
 167                 engine->instmem.unmap           = nv04_instmem_unmap;
 168                 engine->instmem.flush           = nv04_instmem_flush;
 169                 engine->mc.init                 = nv04_mc_init;
 170                 engine->mc.takedown             = nv04_mc_takedown;
 171                 engine->timer.init              = nv04_timer_init;
 172                 engine->timer.read              = nv04_timer_read;
 173                 engine->timer.takedown          = nv04_timer_takedown;
 174                 engine->fb.init                 = nv30_fb_init;
 175                 engine->fb.takedown             = nv30_fb_takedown;
 176                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 177                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 178                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 179                 engine->display.early_init      = nv04_display_early_init;
 180                 engine->display.late_takedown   = nv04_display_late_takedown;
 181                 engine->display.create          = nv04_display_create;
 182                 engine->display.destroy         = nv04_display_destroy;
 183                 engine->display.init            = nv04_display_init;
 184                 engine->display.fini            = nv04_display_fini;
 185                 engine->gpio.drive              = nv10_gpio_drive;
 186                 engine->gpio.sense              = nv10_gpio_sense;
 187                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 188                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 189                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 190                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 191                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 192                 engine->vram.init               = nv20_fb_vram_init;
 193                 engine->vram.takedown           = nouveau_stub_takedown;
 194                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 195                 break;
 196         case 0x40:
 197         case 0x60:
 198                 engine->instmem.init            = nv04_instmem_init;
 199                 engine->instmem.takedown        = nv04_instmem_takedown;
 200                 engine->instmem.suspend         = nv04_instmem_suspend;
 201                 engine->instmem.resume          = nv04_instmem_resume;
 202                 engine->instmem.get             = nv04_instmem_get;
 203                 engine->instmem.put             = nv04_instmem_put;
 204                 engine->instmem.map             = nv04_instmem_map;
 205                 engine->instmem.unmap           = nv04_instmem_unmap;
 206                 engine->instmem.flush           = nv04_instmem_flush;
 207                 engine->mc.init                 = nv40_mc_init;
 208                 engine->mc.takedown             = nv40_mc_takedown;
 209                 engine->timer.init              = nv04_timer_init;
 210                 engine->timer.read              = nv04_timer_read;
 211                 engine->timer.takedown          = nv04_timer_takedown;
 212                 engine->fb.init                 = nv40_fb_init;
 213                 engine->fb.takedown             = nv40_fb_takedown;
 214                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 215                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 216                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 217                 engine->display.early_init      = nv04_display_early_init;
 218                 engine->display.late_takedown   = nv04_display_late_takedown;
 219                 engine->display.create          = nv04_display_create;
 220                 engine->display.destroy         = nv04_display_destroy;
 221                 engine->display.init            = nv04_display_init;
 222                 engine->display.fini            = nv04_display_fini;
 223                 engine->gpio.init               = nv10_gpio_init;
 224                 engine->gpio.fini               = nv10_gpio_fini;
 225                 engine->gpio.drive              = nv10_gpio_drive;
 226                 engine->gpio.sense              = nv10_gpio_sense;
 227                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 228                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 229                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 230                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 231                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 232                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 233                 engine->pm.temp_get             = nv40_temp_get;
 234                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 235                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 236                 engine->vram.init               = nv40_fb_vram_init;
 237                 engine->vram.takedown           = nouveau_stub_takedown;
 238                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 239                 break;
 240         case 0x50:
 241         case 0x80: /* gotta love NVIDIA's consistency.. */
 242         case 0x90:
 243         case 0xa0:
 244                 engine->instmem.init            = nv50_instmem_init;
 245                 engine->instmem.takedown        = nv50_instmem_takedown;
 246                 engine->instmem.suspend         = nv50_instmem_suspend;
 247                 engine->instmem.resume          = nv50_instmem_resume;
 248                 engine->instmem.get             = nv50_instmem_get;
 249                 engine->instmem.put             = nv50_instmem_put;
 250                 engine->instmem.map             = nv50_instmem_map;
 251                 engine->instmem.unmap           = nv50_instmem_unmap;
 252                 if (dev_priv->chipset == 0x50)
 253                         engine->instmem.flush   = nv50_instmem_flush;
 254                 else
 255                         engine->instmem.flush   = nv84_instmem_flush;
 256                 engine->mc.init                 = nv50_mc_init;
 257                 engine->mc.takedown             = nv50_mc_takedown;
 258                 engine->timer.init              = nv04_timer_init;
 259                 engine->timer.read              = nv04_timer_read;
 260                 engine->timer.takedown          = nv04_timer_takedown;
 261                 engine->fb.init                 = nv50_fb_init;
 262                 engine->fb.takedown             = nv50_fb_takedown;
 263                 engine->display.early_init      = nv50_display_early_init;
 264                 engine->display.late_takedown   = nv50_display_late_takedown;
 265                 engine->display.create          = nv50_display_create;
 266                 engine->display.destroy         = nv50_display_destroy;
 267                 engine->display.init            = nv50_display_init;
 268                 engine->display.fini            = nv50_display_fini;
 269                 engine->gpio.init               = nv50_gpio_init;
 270                 engine->gpio.fini               = nv50_gpio_fini;
 271                 engine->gpio.drive              = nv50_gpio_drive;
 272                 engine->gpio.sense              = nv50_gpio_sense;
 273                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 274                 switch (dev_priv->chipset) {
 275                 case 0x84:
 276                 case 0x86:
 277                 case 0x92:
 278                 case 0x94:
 279                 case 0x96:
 280                 case 0x98:
 281                 case 0xa0:
 282                 case 0xaa:
 283                 case 0xac:
 284                 case 0x50:
 285                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 286                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 287                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 288                         break;
 289                 default:
 290                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 291                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 292                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 293                         break;
 294                 }
 295                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 296                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 297                 if (dev_priv->chipset >= 0x84)
 298                         engine->pm.temp_get     = nv84_temp_get;
 299                 else
 300                         engine->pm.temp_get     = nv40_temp_get;
 301                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 302                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 303                 engine->vram.init               = nv50_vram_init;
 304                 engine->vram.takedown           = nv50_vram_fini;
 305                 engine->vram.get                = nv50_vram_new;
 306                 engine->vram.put                = nv50_vram_del;
 307                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 308                 break;
 309         case 0xc0:
 310                 engine->instmem.init            = nvc0_instmem_init;
 311                 engine->instmem.takedown        = nvc0_instmem_takedown;
 312                 engine->instmem.suspend         = nvc0_instmem_suspend;
 313                 engine->instmem.resume          = nvc0_instmem_resume;
 314                 engine->instmem.get             = nv50_instmem_get;
 315                 engine->instmem.put             = nv50_instmem_put;
 316                 engine->instmem.map             = nv50_instmem_map;
 317                 engine->instmem.unmap           = nv50_instmem_unmap;
 318                 engine->instmem.flush           = nv84_instmem_flush;
 319                 engine->mc.init                 = nv50_mc_init;
 320                 engine->mc.takedown             = nv50_mc_takedown;
 321                 engine->timer.init              = nv04_timer_init;
 322                 engine->timer.read              = nv04_timer_read;
 323                 engine->timer.takedown          = nv04_timer_takedown;
 324                 engine->fb.init                 = nvc0_fb_init;
 325                 engine->fb.takedown             = nvc0_fb_takedown;
 326                 engine->display.early_init      = nv50_display_early_init;
 327                 engine->display.late_takedown   = nv50_display_late_takedown;
 328                 engine->display.create          = nv50_display_create;
 329                 engine->display.destroy         = nv50_display_destroy;
 330                 engine->display.init            = nv50_display_init;
 331                 engine->display.fini            = nv50_display_fini;
 332                 engine->gpio.init               = nv50_gpio_init;
 333                 engine->gpio.fini               = nv50_gpio_fini;
 334                 engine->gpio.drive              = nv50_gpio_drive;
 335                 engine->gpio.sense              = nv50_gpio_sense;
 336                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 337                 engine->vram.init               = nvc0_vram_init;
 338                 engine->vram.takedown           = nv50_vram_fini;
 339                 engine->vram.get                = nvc0_vram_new;
 340                 engine->vram.put                = nv50_vram_del;
 341                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 342                 engine->pm.temp_get             = nv84_temp_get;
 343                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 344                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 345                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 346                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 347                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 348                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 349                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 350                 break;
 351         case 0xd0:
 352                 engine->instmem.init            = nvc0_instmem_init;
 353                 engine->instmem.takedown        = nvc0_instmem_takedown;
 354                 engine->instmem.suspend         = nvc0_instmem_suspend;
 355                 engine->instmem.resume          = nvc0_instmem_resume;
 356                 engine->instmem.get             = nv50_instmem_get;
 357                 engine->instmem.put             = nv50_instmem_put;
 358                 engine->instmem.map             = nv50_instmem_map;
 359                 engine->instmem.unmap           = nv50_instmem_unmap;
 360                 engine->instmem.flush           = nv84_instmem_flush;
 361                 engine->mc.init                 = nv50_mc_init;
 362                 engine->mc.takedown             = nv50_mc_takedown;
 363                 engine->timer.init              = nv04_timer_init;
 364                 engine->timer.read              = nv04_timer_read;
 365                 engine->timer.takedown          = nv04_timer_takedown;
 366                 engine->fb.init                 = nvc0_fb_init;
 367                 engine->fb.takedown             = nvc0_fb_takedown;
 368                 engine->display.early_init      = nouveau_stub_init;
 369                 engine->display.late_takedown   = nouveau_stub_takedown;
 370                 engine->display.create          = nvd0_display_create;
 371                 engine->display.destroy         = nvd0_display_destroy;
 372                 engine->display.init            = nvd0_display_init;
 373                 engine->display.fini            = nvd0_display_fini;
 374                 engine->gpio.init               = nv50_gpio_init;
 375                 engine->gpio.fini               = nv50_gpio_fini;
 376                 engine->gpio.drive              = nvd0_gpio_drive;
 377                 engine->gpio.sense              = nvd0_gpio_sense;
 378                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 379                 engine->vram.init               = nvc0_vram_init;
 380                 engine->vram.takedown           = nv50_vram_fini;
 381                 engine->vram.get                = nvc0_vram_new;
 382                 engine->vram.put                = nv50_vram_del;
 383                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 384                 engine->pm.temp_get             = nv84_temp_get;
 385                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 386                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 387                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 388                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 389                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 390                 break;
 391         case 0xe0:
 392                 engine->instmem.init            = nvc0_instmem_init;
 393                 engine->instmem.takedown        = nvc0_instmem_takedown;
 394                 engine->instmem.suspend         = nvc0_instmem_suspend;
 395                 engine->instmem.resume          = nvc0_instmem_resume;
 396                 engine->instmem.get             = nv50_instmem_get;
 397                 engine->instmem.put             = nv50_instmem_put;
 398                 engine->instmem.map             = nv50_instmem_map;
 399                 engine->instmem.unmap           = nv50_instmem_unmap;
 400                 engine->instmem.flush           = nv84_instmem_flush;
 401                 engine->mc.init                 = nv50_mc_init;
 402                 engine->mc.takedown             = nv50_mc_takedown;
 403                 engine->timer.init              = nv04_timer_init;
 404                 engine->timer.read              = nv04_timer_read;
 405                 engine->timer.takedown          = nv04_timer_takedown;
 406                 engine->fb.init                 = nvc0_fb_init;
 407                 engine->fb.takedown             = nvc0_fb_takedown;
 408                 engine->display.early_init      = nouveau_stub_init;
 409                 engine->display.late_takedown   = nouveau_stub_takedown;
 410                 engine->display.create          = nvd0_display_create;
 411                 engine->display.destroy         = nvd0_display_destroy;
 412                 engine->display.init            = nvd0_display_init;
 413                 engine->display.fini            = nvd0_display_fini;
 414                 engine->gpio.init               = nv50_gpio_init;
 415                 engine->gpio.fini               = nv50_gpio_fini;
 416                 engine->gpio.drive              = nvd0_gpio_drive;
 417                 engine->gpio.sense              = nvd0_gpio_sense;
 418                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 419                 engine->vram.init               = nvc0_vram_init;
 420                 engine->vram.takedown           = nv50_vram_fini;
 421                 engine->vram.get                = nvc0_vram_new;
 422                 engine->vram.put                = nv50_vram_del;
 423                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 424                 break;
 425         default:
 426                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 427                 return 1;
 428         }
 429
 430         /* headless mode */
 431         if (nouveau_modeset == 2) {
 432                 engine->display.early_init = nouveau_stub_init;
 433                 engine->display.late_takedown = nouveau_stub_takedown;
 434                 engine->display.create = nouveau_stub_init;
 435                 engine->display.init = nouveau_stub_init;
 436                 engine->display.destroy = nouveau_stub_takedown;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static unsigned int
 443 nouveau_vga_set_decode(void *priv, bool state)
 444 {
 445         struct drm_device *dev = priv;
 446         struct drm_nouveau_private *dev_priv = dev->dev_private;
 447
 448         if (dev_priv->chipset >= 0x40)
 449                 nv_wr32(dev, 0x88054, state);
 450         else
 451                 nv_wr32(dev, 0x1854, state);
 452
 453         if (state)
 454                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 455                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 456         else
 457                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 458 }
 459
 460 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 461                                          enum vga_switcheroo_state state)
 462 {
 463         struct drm_device *dev = pci_get_drvdata(pdev);
 464         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 465         if (state == VGA_SWITCHEROO_ON) {
 466                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 467                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 468                 nouveau_pci_resume(pdev);
 469                 drm_kms_helper_poll_enable(dev);
 470                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 471         } else {
 472                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 473                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 474                 drm_kms_helper_poll_disable(dev);
 475                 nouveau_switcheroo_optimus_dsm();
 476                 nouveau_pci_suspend(pdev, pmm);
 477                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 478         }
 479 }
 480
 481 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 482 {
 483         struct drm_device *dev = pci_get_drvdata(pdev);
 484         nouveau_fbcon_output_poll_changed(dev);
 485 }
 486
 487 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 488 {
 489         struct drm_device *dev = pci_get_drvdata(pdev);
 490         bool can_switch;
 491
 492         spin_lock(&dev->count_lock);
 493         can_switch = (dev->open_count == 0);
 494         spin_unlock(&dev->count_lock);
 495         return can_switch;
 496 }
 497
 498 static void
 499 nouveau_card_channel_fini(struct drm_device *dev)
 500 {
 501         struct drm_nouveau_private *dev_priv = dev->dev_private;
 502
 503         if (dev_priv->channel)
 504                 nouveau_channel_put_unlocked(&dev_priv->channel);
 505 }
 506
 507 static int
 508 nouveau_card_channel_init(struct drm_device *dev)
 509 {
 510         struct drm_nouveau_private *dev_priv = dev->dev_private;
 511         struct nouveau_channel *chan;
 512         int ret;
 513
 514         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 515         dev_priv->channel = chan;
 516         if (ret)
 517                 return ret;
 518         mutex_unlock(&dev_priv->channel->mutex);
 519
 520         nouveau_bo_move_init(chan);
 521         return 0;
 522 }
 523
 524 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 525         .set_gpu_state = nouveau_switcheroo_set_state,
 526         .reprobe = nouveau_switcheroo_reprobe,
 527         .can_switch = nouveau_switcheroo_can_switch,
 528 };
 529
 530 int
 531 nouveau_card_init(struct drm_device *dev)
 532 {
 533         struct drm_nouveau_private *dev_priv = dev->dev_private;
 534         struct nouveau_engine *engine;
 535         int ret, e = 0;
 536
 537         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 538         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 539
 540         /* Initialise internal driver API hooks */
 541         ret = nouveau_init_engine_ptrs(dev);
 542         if (ret)
 543                 goto out;
 544         engine = &dev_priv->engine;
 545         spin_lock_init(&dev_priv->channels.lock);
 546         spin_lock_init(&dev_priv->tile.lock);
 547         spin_lock_init(&dev_priv->context_switch_lock);
 548         spin_lock_init(&dev_priv->vm_lock);
 549
 550         /* Make the CRTCs and I2C buses accessible */
 551         ret = engine->display.early_init(dev);
 552         if (ret)
 553                 goto out;
 554
 555         /* Parse BIOS tables / Run init tables if card not POSTed */
 556         ret = nouveau_bios_init(dev);
 557         if (ret)
 558                 goto out_display_early;
 559
 560         /* workaround an odd issue on nvc1 by disabling the device's
 561          * nosnoop capability.  hopefully won't cause issues until a
 562          * better fix is found - assuming there is one...
 563          */
 564         if (dev_priv->chipset == 0xc1) {
 565                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 566         }
 567
 568         /* PMC */
 569         ret = engine->mc.init(dev);
 570         if (ret)
 571                 goto out_bios;
 572
 573         /* PTIMER */
 574         ret = engine->timer.init(dev);
 575         if (ret)
 576                 goto out_mc;
 577
 578         /* PFB */
 579         ret = engine->fb.init(dev);
 580         if (ret)
 581                 goto out_timer;
 582
 583         ret = engine->vram.init(dev);
 584         if (ret)
 585                 goto out_fb;
 586
 587         /* PGPIO */
 588         ret = nouveau_gpio_create(dev);
 589         if (ret)
 590                 goto out_vram;
 591
 592         ret = nouveau_gpuobj_init(dev);
 593         if (ret)
 594                 goto out_gpio;
 595
 596         ret = engine->instmem.init(dev);
 597         if (ret)
 598                 goto out_gpuobj;
 599
 600         ret = nouveau_mem_vram_init(dev);
 601         if (ret)
 602                 goto out_instmem;
 603
 604         ret = nouveau_mem_gart_init(dev);
 605         if (ret)
 606                 goto out_ttmvram;
 607
 608         if (!dev_priv->noaccel) {
 609                 switch (dev_priv->card_type) {
 610                 case NV_04:
 611                         nv04_fifo_create(dev);
 612                         break;
 613                 case NV_10:
 614                 case NV_20:
 615                 case NV_30:
 616                         if (dev_priv->chipset < 0x17)
 617                                 nv10_fifo_create(dev);
 618                         else
 619                                 nv17_fifo_create(dev);
 620                         break;
 621                 case NV_40:
 622                         nv40_fifo_create(dev);
 623                         break;
 624                 case NV_50:
 625                         if (dev_priv->chipset == 0x50)
 626                                 nv50_fifo_create(dev);
 627                         else
 628                                 nv84_fifo_create(dev);
 629                         break;
 630                 case NV_C0:
 631                 case NV_D0:
 632                         nvc0_fifo_create(dev);
 633                         break;
 634                 case NV_E0:
 635                         nve0_fifo_create(dev);
 636                         break;
 637                 default:
 638                         break;
 639                 }
 640
 641                 switch (dev_priv->card_type) {
 642                 case NV_04:
 643                         nv04_fence_create(dev);
 644                         break;
 645                 case NV_10:
 646                 case NV_20:
 647                 case NV_30:
 648                 case NV_40:
 649                 case NV_50:
 650                         if (dev_priv->chipset < 0x84)
 651                                 nv10_fence_create(dev);
 652                         else
 653                                 nv84_fence_create(dev);
 654                         break;
 655                 case NV_C0:
 656                 case NV_D0:
 657                 case NV_E0:
 658                         nvc0_fence_create(dev);
 659                         break;
 660                 default:
 661                         break;
 662                 }
 663
 664                 switch (dev_priv->card_type) {
 665                 case NV_04:
 666                 case NV_10:
 667                 case NV_20:
 668                 case NV_30:
 669                 case NV_40:
 670                         nv04_software_create(dev);
 671                         break;
 672                 case NV_50:
 673                         nv50_software_create(dev);
 674                         break;
 675                 case NV_C0:
 676                 case NV_D0:
 677                 case NV_E0:
 678                         nvc0_software_create(dev);
 679                         break;
 680                 default:
 681                         break;
 682                 }
 683
 684                 switch (dev_priv->card_type) {
 685                 case NV_04:
 686                         nv04_graph_create(dev);
 687                         break;
 688                 case NV_10:
 689                         nv10_graph_create(dev);
 690                         break;
 691                 case NV_20:
 692                 case NV_30:
 693                         nv20_graph_create(dev);
 694                         break;
 695                 case NV_40:
 696                         nv40_graph_create(dev);
 697                         break;
 698                 case NV_50:
 699                         nv50_graph_create(dev);
 700                         break;
 701                 case NV_C0:
 702                 case NV_D0:
 703                         nvc0_graph_create(dev);
 704                         break;
 705                 case NV_E0:
 706                         nve0_graph_create(dev);
 707                         break;
 708                 default:
 709                         break;
 710                 }
 711
 712                 switch (dev_priv->chipset) {
 713                 case 0x84:
 714                 case 0x86:
 715                 case 0x92:
 716                 case 0x94:
 717                 case 0x96:
 718                 case 0xa0:
 719                         nv84_crypt_create(dev);
 720                         break;
 721                 case 0x98:
 722                 case 0xaa:
 723                 case 0xac:
 724                         nv98_crypt_create(dev);
 725                         break;
 726                 }
 727
 728                 switch (dev_priv->card_type) {
 729                 case NV_50:
 730                         switch (dev_priv->chipset) {
 731                         case 0xa3:
 732                         case 0xa5:
 733                         case 0xa8:
 734                                 nva3_copy_create(dev);
 735                                 break;
 736                         }
 737                         break;
 738                 case NV_C0:
 739                         if (!(nv_rd32(dev, 0x022500) & 0x00000200))
 740                                 nvc0_copy_create(dev, 1);
 741                 case NV_D0:
 742                         if (!(nv_rd32(dev, 0x022500) & 0x00000100))
 743                                 nvc0_copy_create(dev, 0);
 744                         break;
 745                 default:
 746                         break;
 747                 }
 748
 749                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 750                         nv84_bsp_create(dev);
 751                         nv84_vp_create(dev);
 752                         nv98_ppp_create(dev);
 753                 } else
 754                 if (dev_priv->chipset >= 0x84) {
 755                         nv50_mpeg_create(dev);
 756                         nv84_bsp_create(dev);
 757                         nv84_vp_create(dev);
 758                 } else
 759                 if (dev_priv->chipset >= 0x50) {
 760                         nv50_mpeg_create(dev);
 761                 } else
 762                 if (dev_priv->card_type == NV_40 ||
 763                     dev_priv->chipset == 0x31 ||
 764                     dev_priv->chipset == 0x34 ||
 765                     dev_priv->chipset == 0x36) {
 766                         nv31_mpeg_create(dev);
 767                 }
 768
 769                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 770                         if (dev_priv->eng[e]) {
 771                                 ret = dev_priv->eng[e]->init(dev, e);
 772                                 if (ret)
 773                                         goto out_engine;
 774                         }
 775                 }
 776         }
 777
 778         ret = nouveau_irq_init(dev);
 779         if (ret)
 780                 goto out_engine;
 781
 782         ret = nouveau_display_create(dev);
 783         if (ret)
 784                 goto out_irq;
 785
 786         nouveau_backlight_init(dev);
 787         nouveau_pm_init(dev);
 788
 789         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 790                 ret = nouveau_card_channel_init(dev);
 791                 if (ret)
 792                         goto out_pm;
 793         }
 794
 795         if (dev->mode_config.num_crtc) {
 796                 ret = nouveau_display_init(dev);
 797                 if (ret)
 798                         goto out_chan;
 799
 800                 nouveau_fbcon_init(dev);
 801         }
 802
 803         return 0;
 804
 805 out_chan:
 806         nouveau_card_channel_fini(dev);
 807 out_pm:
 808         nouveau_pm_fini(dev);
 809         nouveau_backlight_exit(dev);
 810         nouveau_display_destroy(dev);
 811 out_irq:
 812         nouveau_irq_fini(dev);
 813 out_engine:
 814         if (!dev_priv->noaccel) {
 815                 for (e = e - 1; e >= 0; e--) {
 816                         if (!dev_priv->eng[e])
 817                                 continue;
 818                         dev_priv->eng[e]->fini(dev, e, false);
 819                         dev_priv->eng[e]->destroy(dev,e );
 820                 }
 821         }
 822         nouveau_mem_gart_fini(dev);
 823 out_ttmvram:
 824         nouveau_mem_vram_fini(dev);
 825 out_instmem:
 826         engine->instmem.takedown(dev);
 827 out_gpuobj:
 828         nouveau_gpuobj_takedown(dev);
 829 out_gpio:
 830         nouveau_gpio_destroy(dev);
 831 out_vram:
 832         engine->vram.takedown(dev);
 833 out_fb:
 834         engine->fb.takedown(dev);
 835 out_timer:
 836         engine->timer.takedown(dev);
 837 out_mc:
 838         engine->mc.takedown(dev);
 839 out_bios:
 840         nouveau_bios_takedown(dev);
 841 out_display_early:
 842         engine->display.late_takedown(dev);
 843 out:
 844         vga_switcheroo_unregister_client(dev->pdev);
 845         vga_client_register(dev->pdev, NULL, NULL, NULL);
 846         return ret;
 847 }
 848
 849 static void nouveau_card_takedown(struct drm_device *dev)
 850 {
 851         struct drm_nouveau_private *dev_priv = dev->dev_private;
 852         struct nouveau_engine *engine = &dev_priv->engine;
 853         int e;
 854
 855         if (dev->mode_config.num_crtc) {
 856                 nouveau_fbcon_fini(dev);
 857                 nouveau_display_fini(dev);
 858         }
 859
 860         nouveau_card_channel_fini(dev);
 861         nouveau_pm_fini(dev);
 862         nouveau_backlight_exit(dev);
 863         nouveau_display_destroy(dev);
 864
 865         if (!dev_priv->noaccel) {
 866                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 867                         if (dev_priv->eng[e]) {
 868                                 dev_priv->eng[e]->fini(dev, e, false);
 869                                 dev_priv->eng[e]->destroy(dev,e );
 870                         }
 871                 }
 872         }
 873
 874         if (dev_priv->vga_ram) {
 875                 nouveau_bo_unpin(dev_priv->vga_ram);
 876                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 877         }
 878
 879         mutex_lock(&dev->struct_mutex);
 880         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 881         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 882         mutex_unlock(&dev->struct_mutex);
 883         nouveau_mem_gart_fini(dev);
 884         nouveau_mem_vram_fini(dev);
 885
 886         engine->instmem.takedown(dev);
 887         nouveau_gpuobj_takedown(dev);
 888
 889         nouveau_gpio_destroy(dev);
 890         engine->vram.takedown(dev);
 891         engine->fb.takedown(dev);
 892         engine->timer.takedown(dev);
 893         engine->mc.takedown(dev);
 894
 895         nouveau_bios_takedown(dev);
 896         engine->display.late_takedown(dev);
 897
 898         nouveau_irq_fini(dev);
 899
 900         vga_switcheroo_unregister_client(dev->pdev);
 901         vga_client_register(dev->pdev, NULL, NULL, NULL);
 902 }
 903
 904 int
 905 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 906 {
 907         struct drm_nouveau_private *dev_priv = dev->dev_private;
 908         struct nouveau_fpriv *fpriv;
 909         int ret;
 910
 911         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 912         if (unlikely(!fpriv))
 913                 return -ENOMEM;
 914
 915         spin_lock_init(&fpriv->lock);
 916         INIT_LIST_HEAD(&fpriv->channels);
 917
 918         if (dev_priv->card_type == NV_50) {
 919                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 920                                      &fpriv->vm);
 921                 if (ret) {
 922                         kfree(fpriv);
 923                         return ret;
 924                 }
 925         } else
 926         if (dev_priv->card_type >= NV_C0) {
 927                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 928                                      &fpriv->vm);
 929                 if (ret) {
 930                         kfree(fpriv);
 931                         return ret;
 932                 }
 933         }
 934
 935         file_priv->driver_priv = fpriv;
 936         return 0;
 937 }
 938
 939 /* here a client dies, release the stuff that was allocated for its
 940  * file_priv */
 941 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 942 {
 943         nouveau_channel_cleanup(dev, file_priv);
 944 }
 945
 946 void
 947 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 948 {
 949         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 950         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 951         kfree(fpriv);
 952 }
 953
 954 /* first module load, setup the mmio/fb mapping */
 955 /* KMS: we need mmio at load time, not when the first drm client opens. */
 956 int nouveau_firstopen(struct drm_device *dev)
 957 {
 958         return 0;
 959 }
 960
 961 /* if we have an OF card, copy vbios to RAMIN */
 962 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 963 {
 964 #if defined(__powerpc__)
 965         int size, i;
 966         const uint32_t *bios;
 967         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 968         if (!dn) {
 969                 NV_INFO(dev, "Unable to get the OF node\n");
 970                 return;
 971         }
 972
 973         bios = of_get_property(dn, "NVDA,BMP", &size);
 974         if (bios) {
 975                 for (i = 0; i < size; i += 4)
 976                         nv_wi32(dev, i, bios[i/4]);
 977                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 978         } else {
 979                 NV_INFO(dev, "Unable to get the OF bios\n");
 980         }
 981 #endif
 982 }
 983
 984 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 985 {
 986         struct pci_dev *pdev = dev->pdev;
 987         struct apertures_struct *aper = alloc_apertures(3);
 988         if (!aper)
 989                 return NULL;
 990
 991         aper->ranges[0].base = pci_resource_start(pdev, 1);
 992         aper->ranges[0].size = pci_resource_len(pdev, 1);
 993         aper->count = 1;
 994
 995         if (pci_resource_len(pdev, 2)) {
 996                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 997                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 998                 aper->count++;
 999         }
1000
1001         if (pci_resource_len(pdev, 3)) {
1002                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1003                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1004                 aper->count++;
1005         }
1006
1007         return aper;
1008 }
1009
1010 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1011 {
1012         struct drm_nouveau_private *dev_priv = dev->dev_private;
1013         bool primary = false;
1014         dev_priv->apertures = nouveau_get_apertures(dev);
1015         if (!dev_priv->apertures)
1016                 return -ENOMEM;
1017
1018 #ifdef CONFIG_X86
1019         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1020 #endif
1021
1022         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1023         return 0;
1024 }
1025
1026 int nouveau_load(struct drm_device *dev, unsigned long flags)
1027 {
1028         struct drm_nouveau_private *dev_priv;
1029         unsigned long long offset, length;
1030         uint32_t reg0 = ~0, strap;
1031         int ret;
1032
1033         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1034         if (!dev_priv) {
1035                 ret = -ENOMEM;
1036                 goto err_out;
1037         }
1038         dev->dev_private = dev_priv;
1039         dev_priv->dev = dev;
1040
1041         pci_set_master(dev->pdev);
1042
1043         dev_priv->flags = flags & NOUVEAU_FLAGS;
1044
1045         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1046                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1047
1048         /* first up, map the start of mmio and determine the chipset */
1049         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1050         if (dev_priv->mmio) {
1051 #ifdef __BIG_ENDIAN
1052                 /* put the card into big-endian mode if it's not */
1053                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1054                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1055                 DRM_MEMORYBARRIER();
1056 #endif
1057
1058                 /* determine chipset and derive architecture from it */
1059                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1060                 if ((reg0 & 0x0f000000) > 0) {
1061                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1062                         switch (dev_priv->chipset & 0xf0) {
1063                         case 0x10:
1064                         case 0x20:
1065                         case 0x30:
1066                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1067                                 break;
1068                         case 0x40:
1069                         case 0x60:
1070                                 dev_priv->card_type = NV_40;
1071                                 break;
1072                         case 0x50:
1073                         case 0x80:
1074                         case 0x90:
1075                         case 0xa0:
1076                                 dev_priv->card_type = NV_50;
1077                                 break;
1078                         case 0xc0:
1079                                 dev_priv->card_type = NV_C0;
1080                                 break;
1081                         case 0xd0:
1082                                 dev_priv->card_type = NV_D0;
1083                                 break;
1084                         case 0xe0:
1085                                 dev_priv->card_type = NV_E0;
1086                                 break;
1087                         default:
1088                                 break;
1089                         }
1090                 } else
1091                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1092                         if (reg0 & 0x00f00000)
1093                                 dev_priv->chipset = 0x05;
1094                         else
1095                                 dev_priv->chipset = 0x04;
1096                         dev_priv->card_type = NV_04;
1097                 }
1098
1099                 iounmap(dev_priv->mmio);
1100         }
1101
1102         if (!dev_priv->card_type) {
1103                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1104                 ret = -EINVAL;
1105                 goto err_priv;
1106         }
1107
1108         NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
1109                      dev_priv->card_type, reg0);
1110
1111         /* map the mmio regs, limiting the amount to preserve vmap space */
1112         offset = pci_resource_start(dev->pdev, 0);
1113         length = pci_resource_len(dev->pdev, 0);
1114         if (dev_priv->card_type < NV_E0)
1115                 length = min(length, (unsigned long long)0x00800000);
1116
1117         dev_priv->mmio = ioremap(offset, length);
1118         if (!dev_priv->mmio) {
1119                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1120                          "Please report your setup to " DRIVER_EMAIL "\n");
1121                 ret = -EINVAL;
1122                 goto err_priv;
1123         }
1124         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1125
1126         /* determine frequency of timing crystal */
1127         strap = nv_rd32(dev, 0x101000);
1128         if ( dev_priv->chipset < 0x17 ||
1129             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1130                 strap &= 0x00000040;
1131         else
1132                 strap &= 0x00400040;
1133
1134         switch (strap) {
1135         case 0x00000000: dev_priv->crystal = 13500; break;
1136         case 0x00000040: dev_priv->crystal = 14318; break;
1137         case 0x00400000: dev_priv->crystal = 27000; break;
1138         case 0x00400040: dev_priv->crystal = 25000; break;
1139         }
1140
1141         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1142
1143         /* Determine whether we'll attempt acceleration or not, some
1144          * cards are disabled by default here due to them being known
1145          * non-functional, or never been tested due to lack of hw.
1146          */
1147         dev_priv->noaccel = !!nouveau_noaccel;
1148         if (nouveau_noaccel == -1) {
1149                 switch (dev_priv->chipset) {
1150                 case 0xd9: /* known broken */
1151                 case 0xe4: /* needs binary driver firmware */
1152                 case 0xe7: /* needs binary driver firmware */
1153                         NV_INFO(dev, "acceleration disabled by default, pass "
1154                                      "noaccel=0 to force enable\n");
1155                         dev_priv->noaccel = true;
1156                         break;
1157                 default:
1158                         dev_priv->noaccel = false;
1159                         break;
1160                 }
1161         }
1162
1163         ret = nouveau_remove_conflicting_drivers(dev);
1164         if (ret)
1165                 goto err_mmio;
1166
1167         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1168         if (dev_priv->card_type >= NV_40) {
1169                 int ramin_bar = 2;
1170                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1171                         ramin_bar = 3;
1172
1173                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1174                 dev_priv->ramin =
1175                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1176                                 dev_priv->ramin_size);
1177                 if (!dev_priv->ramin) {
1178                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1179                         ret = -ENOMEM;
1180                         goto err_mmio;
1181                 }
1182         } else {
1183                 dev_priv->ramin_size = 1 * 1024 * 1024;
1184                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1185                                           dev_priv->ramin_size);
1186                 if (!dev_priv->ramin) {
1187                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1188                         ret = -ENOMEM;
1189                         goto err_mmio;
1190                 }
1191         }
1192
1193         nouveau_OF_copy_vbios_to_ramin(dev);
1194
1195         /* Special flags */
1196         if (dev->pci_device == 0x01a0)
1197                 dev_priv->flags |= NV_NFORCE;
1198         else if (dev->pci_device == 0x01f0)
1199                 dev_priv->flags |= NV_NFORCE2;
1200
1201         /* For kernel modesetting, init card now and bring up fbcon */
1202         ret = nouveau_card_init(dev);
1203         if (ret)
1204                 goto err_ramin;
1205
1206         return 0;
1207
1208 err_ramin:
1209         iounmap(dev_priv->ramin);
1210 err_mmio:
1211         iounmap(dev_priv->mmio);
1212 err_priv:
1213         kfree(dev_priv);
1214         dev->dev_private = NULL;
1215 err_out:
1216         return ret;
1217 }
1218
1219 void nouveau_lastclose(struct drm_device *dev)
1220 {
1221         vga_switcheroo_process_delayed_switch();
1222 }
1223
1224 int nouveau_unload(struct drm_device *dev)
1225 {
1226         struct drm_nouveau_private *dev_priv = dev->dev_private;
1227
1228         nouveau_card_takedown(dev);
1229
1230         iounmap(dev_priv->mmio);
1231         iounmap(dev_priv->ramin);
1232
1233         kfree(dev_priv);
1234         dev->dev_private = NULL;
1235         return 0;
1236 }
1237
1238 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1239 bool
1240 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1241                 uint32_t reg, uint32_t mask, uint32_t val)
1242 {
1243         struct drm_nouveau_private *dev_priv = dev->dev_private;
1244         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1245         uint64_t start = ptimer->read(dev);
1246
1247         do {
1248                 if ((nv_rd32(dev, reg) & mask) == val)
1249                         return true;
1250         } while (ptimer->read(dev) - start < timeout);
1251
1252         return false;
1253 }
1254
1255 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1256 bool
1257 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1258                 uint32_t reg, uint32_t mask, uint32_t val)
1259 {
1260         struct drm_nouveau_private *dev_priv = dev->dev_private;
1261         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1262         uint64_t start = ptimer->read(dev);
1263
1264         do {
1265                 if ((nv_rd32(dev, reg) & mask) != val)
1266                         return true;
1267         } while (ptimer->read(dev) - start < timeout);
1268
1269         return false;
1270 }
1271
1272 /* Wait until cond(data) == true, up until timeout has hit */
1273 bool
1274 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1275                 bool (*cond)(void *), void *data)
1276 {
1277         struct drm_nouveau_private *dev_priv = dev->dev_private;
1278         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1279         u64 start = ptimer->read(dev);
1280
1281         do {
1282                 if (cond(data) == true)
1283                         return true;
1284         } while (ptimer->read(dev) - start < timeout);
1285
1286         return false;
1287 }
1288
1289 /* Waits for PGRAPH to go completely idle */
1290 bool nouveau_wait_for_idle(struct drm_device *dev)
1291 {
1292         struct drm_nouveau_private *dev_priv = dev->dev_private;
1293         uint32_t mask = ~0;
1294
1295         if (dev_priv->card_type == NV_40)
1296                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1297
1298         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1299                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1300                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1301                 return false;
1302         }
1303
1304         return true;
1305 }
1306