drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <core/engine.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include <subdev/fb.h>
  34 #include <subdev/vm.h>
  35 #include <subdev/bar.h>
  36
  37 #include "nouveau_drm.h"
  38 #include "nouveau_dma.h"
  39 #include "nouveau_fence.h"
  40
  41 #include "nouveau_bo.h"
  42 #include "nouveau_ttm.h"
  43 #include "nouveau_gem.h"
  44
  45 /*
  46  * NV10-NV40 tiling helpers
  47  */
  48
  49 static void
  50 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  51                            u32 addr, u32 size, u32 pitch, u32 flags)
  52 {
  53         struct nouveau_drm *drm = nouveau_drm(dev);
  54         int i = reg - drm->tile.reg;
  55         struct nouveau_fb *pfb = nouveau_fb(drm->device);
  56         struct nouveau_fb_tile *tile = &pfb->tile.region[i];
  57         struct nouveau_engine *engine;
  58
  59         nouveau_fence_unref(&reg->fence);
  60
  61         if (tile->pitch)
  62                 pfb->tile.fini(pfb, i, tile);
  63
  64         if (pitch)
  65                 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
  66
  67         pfb->tile.prog(pfb, i, tile);
  68
  69         if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
  70                 engine->tile_prog(engine, i);
  71         if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
  72                 engine->tile_prog(engine, i);
  73 }
  74
  75 static struct nouveau_drm_tile *
  76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  77 {
  78         struct nouveau_drm *drm = nouveau_drm(dev);
  79         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  80
  81         spin_lock(&drm->tile.lock);
  82
  83         if (!tile->used &&
  84             (!tile->fence || nouveau_fence_done(tile->fence)))
  85                 tile->used = true;
  86         else
  87                 tile = NULL;
  88
  89         spin_unlock(&drm->tile.lock);
  90         return tile;
  91 }
  92
  93 static void
  94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  95                         struct nouveau_fence *fence)
  96 {
  97         struct nouveau_drm *drm = nouveau_drm(dev);
  98
  99         if (tile) {
 100                 spin_lock(&drm->tile.lock);
 101                 if (fence) {
 102                         /* Mark it as pending. */
 103                         tile->fence = fence;
 104                         nouveau_fence_ref(fence);
 105                 }
 106
 107                 tile->used = false;
 108                 spin_unlock(&drm->tile.lock);
 109         }
 110 }
 111
 112 static struct nouveau_drm_tile *
 113 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 114                    u32 size, u32 pitch, u32 flags)
 115 {
 116         struct nouveau_drm *drm = nouveau_drm(dev);
 117         struct nouveau_fb *pfb = nouveau_fb(drm->device);
 118         struct nouveau_drm_tile *tile, *found = NULL;
 119         int i;
 120
 121         for (i = 0; i < pfb->tile.regions; i++) {
 122                 tile = nv10_bo_get_tile_region(dev, i);
 123
 124                 if (pitch && !found) {
 125                         found = tile;
 126                         continue;
 127
 128                 } else if (tile && pfb->tile.region[i].pitch) {
 129                         /* Kill an unused tile region. */
 130                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 131                 }
 132
 133                 nv10_bo_put_tile_region(dev, tile, NULL);
 134         }
 135
 136         if (found)
 137                 nv10_bo_update_tile_region(dev, found, addr, size,
 138                                             pitch, flags);
 139         return found;
 140 }
 141
 142 static void
 143 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 144 {
 145         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 146         struct drm_device *dev = drm->dev;
 147         struct nouveau_bo *nvbo = nouveau_bo(bo);
 148
 149         if (unlikely(nvbo->gem))
 150                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
 151         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 152         kfree(nvbo);
 153 }
 154
 155 static void
 156 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
 157                        int *align, int *size)
 158 {
 159         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 160         struct nouveau_device *device = nv_device(drm->device);
 161
 162         if (device->card_type < NV_50) {
 163                 if (nvbo->tile_mode) {
 164                         if (device->chipset >= 0x40) {
 165                                 *align = 65536;
 166                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 167
 168                         } else if (device->chipset >= 0x30) {
 169                                 *align = 32768;
 170                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 171
 172                         } else if (device->chipset >= 0x20) {
 173                                 *align = 16384;
 174                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 175
 176                         } else if (device->chipset >= 0x10) {
 177                                 *align = 16384;
 178                                 *size = roundup(*size, 32 * nvbo->tile_mode);
 179                         }
 180                 }
 181         } else {
 182                 *size = roundup(*size, (1 << nvbo->page_shift));
 183                 *align = max((1 <<  nvbo->page_shift), *align);
 184         }
 185
 186         *size = roundup(*size, PAGE_SIZE);
 187 }
 188
 189 int
 190 nouveau_bo_new(struct drm_device *dev, int size, int align,
 191                uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
 192                struct sg_table *sg,
 193                struct nouveau_bo **pnvbo)
 194 {
 195         struct nouveau_drm *drm = nouveau_drm(dev);
 196         struct nouveau_bo *nvbo;
 197         size_t acc_size;
 198         int ret;
 199         int type = ttm_bo_type_device;
 200
 201         if (sg)
 202                 type = ttm_bo_type_sg;
 203
 204         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 205         if (!nvbo)
 206                 return -ENOMEM;
 207         INIT_LIST_HEAD(&nvbo->head);
 208         INIT_LIST_HEAD(&nvbo->entry);
 209         INIT_LIST_HEAD(&nvbo->vma_list);
 210         nvbo->tile_mode = tile_mode;
 211         nvbo->tile_flags = tile_flags;
 212         nvbo->bo.bdev = &drm->ttm.bdev;
 213
 214         nvbo->page_shift = 12;
 215         if (drm->client.base.vm) {
 216                 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
 217                         nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
 218         }
 219
 220         nouveau_bo_fixup_align(nvbo, flags, &align, &size);
 221         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 222         nouveau_bo_placement_set(nvbo, flags, 0);
 223
 224         acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
 225                                        sizeof(struct nouveau_bo));
 226
 227         ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
 228                           type, &nvbo->placement,
 229                           align >> PAGE_SHIFT, false, NULL, acc_size, sg,
 230                           nouveau_bo_del_ttm);
 231         if (ret) {
 232                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 233                 return ret;
 234         }
 235
 236         *pnvbo = nvbo;
 237         return 0;
 238 }
 239
 240 static void
 241 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
 242 {
 243         *n = 0;
 244
 245         if (type & TTM_PL_FLAG_VRAM)
 246                 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
 247         if (type & TTM_PL_FLAG_TT)
 248                 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
 249         if (type & TTM_PL_FLAG_SYSTEM)
 250                 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
 251 }
 252
 253 static void
 254 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 255 {
 256         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 257         struct nouveau_fb *pfb = nouveau_fb(drm->device);
 258         u32 vram_pages = pfb->ram.size >> PAGE_SHIFT;
 259
 260         if (nv_device(drm->device)->card_type == NV_10 &&
 261             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
 262             nvbo->bo.mem.num_pages < vram_pages / 4) {
 263                 /*
 264                  * Make sure that the color and depth buffers are handled
 265                  * by independent memory controller units. Up to a 9x
 266                  * speed up when alpha-blending and depth-test are enabled
 267                  * at the same time.
 268                  */
 269                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 270                         nvbo->placement.fpfn = vram_pages / 2;
 271                         nvbo->placement.lpfn = ~0;
 272                 } else {
 273                         nvbo->placement.fpfn = 0;
 274                         nvbo->placement.lpfn = vram_pages / 2;
 275                 }
 276         }
 277 }
 278
 279 void
 280 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 281 {
 282         struct ttm_placement *pl = &nvbo->placement;
 283         uint32_t flags = TTM_PL_MASK_CACHING |
 284                 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 285
 286         pl->placement = nvbo->placements;
 287         set_placement_list(nvbo->placements, &pl->num_placement,
 288                            type, flags);
 289
 290         pl->busy_placement = nvbo->busy_placements;
 291         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 292                            type | busy, flags);
 293
 294         set_placement_range(nvbo, type);
 295 }
 296
 297 int
 298 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 299 {
 300         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 301         struct ttm_buffer_object *bo = &nvbo->bo;
 302         int ret;
 303
 304         ret = ttm_bo_reserve(bo, false, false, false, 0);
 305         if (ret)
 306                 goto out;
 307
 308         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 309                 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 310                          1 << bo->mem.mem_type, memtype);
 311                 ret = -EINVAL;
 312                 goto out;
 313         }
 314
 315         if (nvbo->pin_refcnt++)
 316                 goto out;
 317
 318         nouveau_bo_placement_set(nvbo, memtype, 0);
 319
 320         ret = nouveau_bo_validate(nvbo, false, false);
 321         if (ret == 0) {
 322                 switch (bo->mem.mem_type) {
 323                 case TTM_PL_VRAM:
 324                         drm->gem.vram_available -= bo->mem.size;
 325                         break;
 326                 case TTM_PL_TT:
 327                         drm->gem.gart_available -= bo->mem.size;
 328                         break;
 329                 default:
 330                         break;
 331                 }
 332         }
 333 out:
 334         ttm_bo_unreserve(bo);
 335         return ret;
 336 }
 337
 338 int
 339 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 340 {
 341         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 342         struct ttm_buffer_object *bo = &nvbo->bo;
 343         int ret;
 344
 345         ret = ttm_bo_reserve(bo, false, false, false, 0);
 346         if (ret)
 347                 return ret;
 348
 349         if (--nvbo->pin_refcnt)
 350                 goto out;
 351
 352         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 353
 354         ret = nouveau_bo_validate(nvbo, false, false);
 355         if (ret == 0) {
 356                 switch (bo->mem.mem_type) {
 357                 case TTM_PL_VRAM:
 358                         drm->gem.vram_available += bo->mem.size;
 359                         break;
 360                 case TTM_PL_TT:
 361                         drm->gem.gart_available += bo->mem.size;
 362                         break;
 363                 default:
 364                         break;
 365                 }
 366         }
 367
 368 out:
 369         ttm_bo_unreserve(bo);
 370         return ret;
 371 }
 372
 373 int
 374 nouveau_bo_map(struct nouveau_bo *nvbo)
 375 {
 376         int ret;
 377
 378         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
 379         if (ret)
 380                 return ret;
 381
 382         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 383         ttm_bo_unreserve(&nvbo->bo);
 384         return ret;
 385 }
 386
 387 void
 388 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 389 {
 390         if (nvbo)
 391                 ttm_bo_kunmap(&nvbo->kmap);
 392 }
 393
 394 int
 395 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 396                     bool no_wait_gpu)
 397 {
 398         int ret;
 399
 400         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
 401                               interruptible, no_wait_gpu);
 402         if (ret)
 403                 return ret;
 404
 405         return 0;
 406 }
 407
 408 u16
 409 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 410 {
 411         bool is_iomem;
 412         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 413         mem = &mem[index];
 414         if (is_iomem)
 415                 return ioread16_native((void __force __iomem *)mem);
 416         else
 417                 return *mem;
 418 }
 419
 420 void
 421 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 422 {
 423         bool is_iomem;
 424         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 425         mem = &mem[index];
 426         if (is_iomem)
 427                 iowrite16_native(val, (void __force __iomem *)mem);
 428         else
 429                 *mem = val;
 430 }
 431
 432 u32
 433 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 434 {
 435         bool is_iomem;
 436         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 437         mem = &mem[index];
 438         if (is_iomem)
 439                 return ioread32_native((void __force __iomem *)mem);
 440         else
 441                 return *mem;
 442 }
 443
 444 void
 445 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 446 {
 447         bool is_iomem;
 448         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 449         mem = &mem[index];
 450         if (is_iomem)
 451                 iowrite32_native(val, (void __force __iomem *)mem);
 452         else
 453                 *mem = val;
 454 }
 455
 456 static struct ttm_tt *
 457 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
 458                       uint32_t page_flags, struct page *dummy_read)
 459 {
 460 #if __OS_HAS_AGP
 461         struct nouveau_drm *drm = nouveau_bdev(bdev);
 462         struct drm_device *dev = drm->dev;
 463
 464         if (drm->agp.stat == ENABLED) {
 465                 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
 466                                          page_flags, dummy_read);
 467         }
 468 #endif
 469
 470         return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
 471 }
 472
 473 static int
 474 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 475 {
 476         /* We'll do this from user space. */
 477         return 0;
 478 }
 479
 480 static int
 481 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 482                          struct ttm_mem_type_manager *man)
 483 {
 484         struct nouveau_drm *drm = nouveau_bdev(bdev);
 485
 486         switch (type) {
 487         case TTM_PL_SYSTEM:
 488                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 489                 man->available_caching = TTM_PL_MASK_CACHING;
 490                 man->default_caching = TTM_PL_FLAG_CACHED;
 491                 break;
 492         case TTM_PL_VRAM:
 493                 if (nv_device(drm->device)->card_type >= NV_50) {
 494                         man->func = &nouveau_vram_manager;
 495                         man->io_reserve_fastpath = false;
 496                         man->use_io_reserve_lru = true;
 497                 } else {
 498                         man->func = &ttm_bo_manager_func;
 499                 }
 500                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 501                              TTM_MEMTYPE_FLAG_MAPPABLE;
 502                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 503                                          TTM_PL_FLAG_WC;
 504                 man->default_caching = TTM_PL_FLAG_WC;
 505                 break;
 506         case TTM_PL_TT:
 507                 if (nv_device(drm->device)->card_type >= NV_50)
 508                         man->func = &nouveau_gart_manager;
 509                 else
 510                 if (drm->agp.stat != ENABLED)
 511                         man->func = &nv04_gart_manager;
 512                 else
 513                         man->func = &ttm_bo_manager_func;
 514
 515                 if (drm->agp.stat == ENABLED) {
 516                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 517                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 518                                 TTM_PL_FLAG_WC;
 519                         man->default_caching = TTM_PL_FLAG_WC;
 520                 } else {
 521                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 522                                      TTM_MEMTYPE_FLAG_CMA;
 523                         man->available_caching = TTM_PL_MASK_CACHING;
 524                         man->default_caching = TTM_PL_FLAG_CACHED;
 525                 }
 526
 527                 break;
 528         default:
 529                 return -EINVAL;
 530         }
 531         return 0;
 532 }
 533
 534 static void
 535 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 536 {
 537         struct nouveau_bo *nvbo = nouveau_bo(bo);
 538
 539         switch (bo->mem.mem_type) {
 540         case TTM_PL_VRAM:
 541                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 542                                          TTM_PL_FLAG_SYSTEM);
 543                 break;
 544         default:
 545                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 546                 break;
 547         }
 548
 549         *pl = nvbo->placement;
 550 }
 551
 552
 553 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 554  * TTM_PL_{VRAM,TT} directly.
 555  */
 556
 557 static int
 558 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 559                               struct nouveau_bo *nvbo, bool evict,
 560                               bool no_wait_gpu, struct ttm_mem_reg *new_mem)
 561 {
 562         struct nouveau_fence *fence = NULL;
 563         int ret;
 564
 565         ret = nouveau_fence_new(chan, false, &fence);
 566         if (ret)
 567                 return ret;
 568
 569         ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, evict,
 570                                         no_wait_gpu, new_mem);
 571         nouveau_fence_unref(&fence);
 572         return ret;
 573 }
 574
 575 static int
 576 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 577 {
 578         int ret = RING_SPACE(chan, 2);
 579         if (ret == 0) {
 580                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 581                 OUT_RING  (chan, handle);
 582                 FIRE_RING (chan);
 583         }
 584         return ret;
 585 }
 586
 587 static int
 588 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 589                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 590 {
 591         struct nouveau_mem *node = old_mem->mm_node;
 592         int ret = RING_SPACE(chan, 10);
 593         if (ret == 0) {
 594                 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
 595                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 596                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 597                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 598                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 599                 OUT_RING  (chan, PAGE_SIZE);
 600                 OUT_RING  (chan, PAGE_SIZE);
 601                 OUT_RING  (chan, PAGE_SIZE);
 602                 OUT_RING  (chan, new_mem->num_pages);
 603                 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
 604         }
 605         return ret;
 606 }
 607
 608 static int
 609 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 610 {
 611         int ret = RING_SPACE(chan, 2);
 612         if (ret == 0) {
 613                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 614                 OUT_RING  (chan, handle);
 615         }
 616         return ret;
 617 }
 618
 619 static int
 620 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 621                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 622 {
 623         struct nouveau_mem *node = old_mem->mm_node;
 624         u64 src_offset = node->vma[0].offset;
 625         u64 dst_offset = node->vma[1].offset;
 626         u32 page_count = new_mem->num_pages;
 627         int ret;
 628
 629         page_count = new_mem->num_pages;
 630         while (page_count) {
 631                 int line_count = (page_count > 8191) ? 8191 : page_count;
 632
 633                 ret = RING_SPACE(chan, 11);
 634                 if (ret)
 635                         return ret;
 636
 637                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
 638                 OUT_RING  (chan, upper_32_bits(src_offset));
 639                 OUT_RING  (chan, lower_32_bits(src_offset));
 640                 OUT_RING  (chan, upper_32_bits(dst_offset));
 641                 OUT_RING  (chan, lower_32_bits(dst_offset));
 642                 OUT_RING  (chan, PAGE_SIZE);
 643                 OUT_RING  (chan, PAGE_SIZE);
 644                 OUT_RING  (chan, PAGE_SIZE);
 645                 OUT_RING  (chan, line_count);
 646                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 647                 OUT_RING  (chan, 0x00000110);
 648
 649                 page_count -= line_count;
 650                 src_offset += (PAGE_SIZE * line_count);
 651                 dst_offset += (PAGE_SIZE * line_count);
 652         }
 653
 654         return 0;
 655 }
 656
 657 static int
 658 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 659                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 660 {
 661         struct nouveau_mem *node = old_mem->mm_node;
 662         u64 src_offset = node->vma[0].offset;
 663         u64 dst_offset = node->vma[1].offset;
 664         u32 page_count = new_mem->num_pages;
 665         int ret;
 666
 667         page_count = new_mem->num_pages;
 668         while (page_count) {
 669                 int line_count = (page_count > 2047) ? 2047 : page_count;
 670
 671                 ret = RING_SPACE(chan, 12);
 672                 if (ret)
 673                         return ret;
 674
 675                 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
 676                 OUT_RING  (chan, upper_32_bits(dst_offset));
 677                 OUT_RING  (chan, lower_32_bits(dst_offset));
 678                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
 679                 OUT_RING  (chan, upper_32_bits(src_offset));
 680                 OUT_RING  (chan, lower_32_bits(src_offset));
 681                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 682                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 683                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 684                 OUT_RING  (chan, line_count);
 685                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 686                 OUT_RING  (chan, 0x00100110);
 687
 688                 page_count -= line_count;
 689                 src_offset += (PAGE_SIZE * line_count);
 690                 dst_offset += (PAGE_SIZE * line_count);
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int
 697 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 698                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 699 {
 700         struct nouveau_mem *node = old_mem->mm_node;
 701         u64 src_offset = node->vma[0].offset;
 702         u64 dst_offset = node->vma[1].offset;
 703         u32 page_count = new_mem->num_pages;
 704         int ret;
 705
 706         page_count = new_mem->num_pages;
 707         while (page_count) {
 708                 int line_count = (page_count > 8191) ? 8191 : page_count;
 709
 710                 ret = RING_SPACE(chan, 11);
 711                 if (ret)
 712                         return ret;
 713
 714                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 715                 OUT_RING  (chan, upper_32_bits(src_offset));
 716                 OUT_RING  (chan, lower_32_bits(src_offset));
 717                 OUT_RING  (chan, upper_32_bits(dst_offset));
 718                 OUT_RING  (chan, lower_32_bits(dst_offset));
 719                 OUT_RING  (chan, PAGE_SIZE);
 720                 OUT_RING  (chan, PAGE_SIZE);
 721                 OUT_RING  (chan, PAGE_SIZE);
 722                 OUT_RING  (chan, line_count);
 723                 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
 724                 OUT_RING  (chan, 0x00000110);
 725
 726                 page_count -= line_count;
 727                 src_offset += (PAGE_SIZE * line_count);
 728                 dst_offset += (PAGE_SIZE * line_count);
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int
 735 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 736                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 737 {
 738         struct nouveau_mem *node = old_mem->mm_node;
 739         int ret = RING_SPACE(chan, 7);
 740         if (ret == 0) {
 741                 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
 742                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 743                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 744                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 745                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 746                 OUT_RING  (chan, 0x00000000 /* COPY */);
 747                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 748         }
 749         return ret;
 750 }
 751
 752 static int
 753 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 754                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 755 {
 756         struct nouveau_mem *node = old_mem->mm_node;
 757         int ret = RING_SPACE(chan, 7);
 758         if (ret == 0) {
 759                 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
 760                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 761                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 762                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 763                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 764                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 765                 OUT_RING  (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
 766         }
 767         return ret;
 768 }
 769
 770 static int
 771 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
 772 {
 773         int ret = RING_SPACE(chan, 6);
 774         if (ret == 0) {
 775                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 776                 OUT_RING  (chan, handle);
 777                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
 778                 OUT_RING  (chan, NvNotify0);
 779                 OUT_RING  (chan, NvDmaFB);
 780                 OUT_RING  (chan, NvDmaFB);
 781         }
 782
 783         return ret;
 784 }
 785
 786 static int
 787 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 788                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 789 {
 790         struct nouveau_mem *node = old_mem->mm_node;
 791         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 792         u64 src_offset = node->vma[0].offset;
 793         u64 dst_offset = node->vma[1].offset;
 794         int src_tiled = !!node->memtype;
 795         int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
 796         int ret;
 797
 798         while (length) {
 799                 u32 amount, stride, height;
 800
 801                 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
 802                 if (ret)
 803                         return ret;
 804
 805                 amount  = min(length, (u64)(4 * 1024 * 1024));
 806                 stride  = 16 * 4;
 807                 height  = amount / stride;
 808
 809                 if (src_tiled) {
 810                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
 811                         OUT_RING  (chan, 0);
 812                         OUT_RING  (chan, 0);
 813                         OUT_RING  (chan, stride);
 814                         OUT_RING  (chan, height);
 815                         OUT_RING  (chan, 1);
 816                         OUT_RING  (chan, 0);
 817                         OUT_RING  (chan, 0);
 818                 } else {
 819                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
 820                         OUT_RING  (chan, 1);
 821                 }
 822                 if (dst_tiled) {
 823                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
 824                         OUT_RING  (chan, 0);
 825                         OUT_RING  (chan, 0);
 826                         OUT_RING  (chan, stride);
 827                         OUT_RING  (chan, height);
 828                         OUT_RING  (chan, 1);
 829                         OUT_RING  (chan, 0);
 830                         OUT_RING  (chan, 0);
 831                 } else {
 832                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
 833                         OUT_RING  (chan, 1);
 834                 }
 835
 836                 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
 837                 OUT_RING  (chan, upper_32_bits(src_offset));
 838                 OUT_RING  (chan, upper_32_bits(dst_offset));
 839                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 840                 OUT_RING  (chan, lower_32_bits(src_offset));
 841                 OUT_RING  (chan, lower_32_bits(dst_offset));
 842                 OUT_RING  (chan, stride);
 843                 OUT_RING  (chan, stride);
 844                 OUT_RING  (chan, stride);
 845                 OUT_RING  (chan, height);
 846                 OUT_RING  (chan, 0x00000101);
 847                 OUT_RING  (chan, 0x00000000);
 848                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 849                 OUT_RING  (chan, 0);
 850
 851                 length -= amount;
 852                 src_offset += amount;
 853                 dst_offset += amount;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int
 860 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
 861 {
 862         int ret = RING_SPACE(chan, 4);
 863         if (ret == 0) {
 864                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 865                 OUT_RING  (chan, handle);
 866                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
 867                 OUT_RING  (chan, NvNotify0);
 868         }
 869
 870         return ret;
 871 }
 872
 873 static inline uint32_t
 874 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 875                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 876 {
 877         if (mem->mem_type == TTM_PL_TT)
 878                 return NvDmaTT;
 879         return NvDmaFB;
 880 }
 881
 882 static int
 883 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 884                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 885 {
 886         u32 src_offset = old_mem->start << PAGE_SHIFT;
 887         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 888         u32 page_count = new_mem->num_pages;
 889         int ret;
 890
 891         ret = RING_SPACE(chan, 3);
 892         if (ret)
 893                 return ret;
 894
 895         BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 896         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 897         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 898
 899         page_count = new_mem->num_pages;
 900         while (page_count) {
 901                 int line_count = (page_count > 2047) ? 2047 : page_count;
 902
 903                 ret = RING_SPACE(chan, 11);
 904                 if (ret)
 905                         return ret;
 906
 907                 BEGIN_NV04(chan, NvSubCopy,
 908                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 909                 OUT_RING  (chan, src_offset);
 910                 OUT_RING  (chan, dst_offset);
 911                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 912                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 913                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 914                 OUT_RING  (chan, line_count);
 915                 OUT_RING  (chan, 0x00000101);
 916                 OUT_RING  (chan, 0x00000000);
 917                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 918                 OUT_RING  (chan, 0);
 919
 920                 page_count -= line_count;
 921                 src_offset += (PAGE_SIZE * line_count);
 922                 dst_offset += (PAGE_SIZE * line_count);
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int
 929 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
 930                    struct ttm_mem_reg *mem, struct nouveau_vma *vma)
 931 {
 932         struct nouveau_mem *node = mem->mm_node;
 933         int ret;
 934
 935         ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages <<
 936                              PAGE_SHIFT, node->page_shift,
 937                              NV_MEM_ACCESS_RW, vma);
 938         if (ret)
 939                 return ret;
 940
 941         if (mem->mem_type == TTM_PL_VRAM)
 942                 nouveau_vm_map(vma, node);
 943         else
 944                 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
 945
 946         return 0;
 947 }
 948
 949 static int
 950 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 951                      bool no_wait_gpu, struct ttm_mem_reg *new_mem)
 952 {
 953         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 954         struct nouveau_channel *chan = chan = drm->channel;
 955         struct nouveau_bo *nvbo = nouveau_bo(bo);
 956         struct ttm_mem_reg *old_mem = &bo->mem;
 957         int ret;
 958
 959         mutex_lock(&chan->cli->mutex);
 960
 961         /* create temporary vmas for the transfer and attach them to the
 962          * old nouveau_mem node, these will get cleaned up after ttm has
 963          * destroyed the ttm_mem_reg
 964          */
 965         if (nv_device(drm->device)->card_type >= NV_50) {
 966                 struct nouveau_mem *node = old_mem->mm_node;
 967
 968                 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
 969                 if (ret)
 970                         goto out;
 971
 972                 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
 973                 if (ret)
 974                         goto out;
 975         }
 976
 977         ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
 978         if (ret == 0) {
 979                 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
 980                                                     no_wait_gpu, new_mem);
 981         }
 982
 983 out:
 984         mutex_unlock(&chan->cli->mutex);
 985         return ret;
 986 }
 987
 988 void
 989 nouveau_bo_move_init(struct nouveau_drm *drm)
 990 {
 991         static const struct {
 992                 const char *name;
 993                 int engine;
 994                 u32 oclass;
 995                 int (*exec)(struct nouveau_channel *,
 996                             struct ttm_buffer_object *,
 997                             struct ttm_mem_reg *, struct ttm_mem_reg *);
 998                 int (*init)(struct nouveau_channel *, u32 handle);
 999         } _methods[] = {
1000                 {  "COPY", 0, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1001                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1002                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1003                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1004                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1005                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1006                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1007                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1008                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1009                 {},
1010                 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1011         }, *mthd = _methods;
1012         const char *name = "CPU";
1013         int ret;
1014
1015         do {
1016                 struct nouveau_object *object;
1017                 struct nouveau_channel *chan;
1018                 u32 handle = (mthd->engine << 16) | mthd->oclass;
1019
1020                 if (mthd->init == nve0_bo_move_init)
1021                         chan = drm->cechan;
1022                 else
1023                         chan = drm->channel;
1024                 if (chan == NULL)
1025                         continue;
1026
1027                 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1028                                          mthd->oclass, NULL, 0, &object);
1029                 if (ret == 0) {
1030                         ret = mthd->init(chan, handle);
1031                         if (ret) {
1032                                 nouveau_object_del(nv_object(drm),
1033                                                    chan->handle, handle);
1034                                 continue;
1035                         }
1036
1037                         drm->ttm.move = mthd->exec;
1038                         name = mthd->name;
1039                         break;
1040                 }
1041         } while ((++mthd)->exec);
1042
1043         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1044 }
1045
1046 static int
1047 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1048                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1049 {
1050         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1051         struct ttm_placement placement;
1052         struct ttm_mem_reg tmp_mem;
1053         int ret;
1054
1055         placement.fpfn = placement.lpfn = 0;
1056         placement.num_placement = placement.num_busy_placement = 1;
1057         placement.placement = placement.busy_placement = &placement_memtype;
1058
1059         tmp_mem = *new_mem;
1060         tmp_mem.mm_node = NULL;
1061         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1062         if (ret)
1063                 return ret;
1064
1065         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1066         if (ret)
1067                 goto out;
1068
1069         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1070         if (ret)
1071                 goto out;
1072
1073         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1074 out:
1075         ttm_bo_mem_put(bo, &tmp_mem);
1076         return ret;
1077 }
1078
1079 static int
1080 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1081                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1082 {
1083         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1084         struct ttm_placement placement;
1085         struct ttm_mem_reg tmp_mem;
1086         int ret;
1087
1088         placement.fpfn = placement.lpfn = 0;
1089         placement.num_placement = placement.num_busy_placement = 1;
1090         placement.placement = placement.busy_placement = &placement_memtype;
1091
1092         tmp_mem = *new_mem;
1093         tmp_mem.mm_node = NULL;
1094         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1095         if (ret)
1096                 return ret;
1097
1098         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1099         if (ret)
1100                 goto out;
1101
1102         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1103         if (ret)
1104                 goto out;
1105
1106 out:
1107         ttm_bo_mem_put(bo, &tmp_mem);
1108         return ret;
1109 }
1110
1111 static void
1112 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1113 {
1114         struct nouveau_bo *nvbo = nouveau_bo(bo);
1115         struct nouveau_vma *vma;
1116
1117         /* ttm can now (stupidly) pass the driver bos it didn't create... */
1118         if (bo->destroy != nouveau_bo_del_ttm)
1119                 return;
1120
1121         list_for_each_entry(vma, &nvbo->vma_list, head) {
1122                 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1123                         nouveau_vm_map(vma, new_mem->mm_node);
1124                 } else
1125                 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1126                     nvbo->page_shift == vma->vm->vmm->spg_shift) {
1127                         if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1128                                 nouveau_vm_map_sg_table(vma, 0, new_mem->
1129                                                   num_pages << PAGE_SHIFT,
1130                                                   new_mem->mm_node);
1131                         else
1132                                 nouveau_vm_map_sg(vma, 0, new_mem->
1133                                                   num_pages << PAGE_SHIFT,
1134                                                   new_mem->mm_node);
1135                 } else {
1136                         nouveau_vm_unmap(vma);
1137                 }
1138         }
1139 }
1140
1141 static int
1142 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1143                    struct nouveau_drm_tile **new_tile)
1144 {
1145         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1146         struct drm_device *dev = drm->dev;
1147         struct nouveau_bo *nvbo = nouveau_bo(bo);
1148         u64 offset = new_mem->start << PAGE_SHIFT;
1149
1150         *new_tile = NULL;
1151         if (new_mem->mem_type != TTM_PL_VRAM)
1152                 return 0;
1153
1154         if (nv_device(drm->device)->card_type >= NV_10) {
1155                 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1156                                                 nvbo->tile_mode,
1157                                                 nvbo->tile_flags);
1158         }
1159
1160         return 0;
1161 }
1162
1163 static void
1164 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1165                       struct nouveau_drm_tile *new_tile,
1166                       struct nouveau_drm_tile **old_tile)
1167 {
1168         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1169         struct drm_device *dev = drm->dev;
1170
1171         nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1172         *old_tile = new_tile;
1173 }
1174
1175 static int
1176 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1177                 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1178 {
1179         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1180         struct nouveau_bo *nvbo = nouveau_bo(bo);
1181         struct ttm_mem_reg *old_mem = &bo->mem;
1182         struct nouveau_drm_tile *new_tile = NULL;
1183         int ret = 0;
1184
1185         if (nv_device(drm->device)->card_type < NV_50) {
1186                 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1187                 if (ret)
1188                         return ret;
1189         }
1190
1191         /* Fake bo copy. */
1192         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1193                 BUG_ON(bo->mem.mm_node != NULL);
1194                 bo->mem = *new_mem;
1195                 new_mem->mm_node = NULL;
1196                 goto out;
1197         }
1198
1199         /* CPU copy if we have no accelerated method available */
1200         if (!drm->ttm.move) {
1201                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1202                 goto out;
1203         }
1204
1205         /* Hardware assisted copy. */
1206         if (new_mem->mem_type == TTM_PL_SYSTEM)
1207                 ret = nouveau_bo_move_flipd(bo, evict, intr,
1208                                             no_wait_gpu, new_mem);
1209         else if (old_mem->mem_type == TTM_PL_SYSTEM)
1210                 ret = nouveau_bo_move_flips(bo, evict, intr,
1211                                             no_wait_gpu, new_mem);
1212         else
1213                 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1214                                            no_wait_gpu, new_mem);
1215
1216         if (!ret)
1217                 goto out;
1218
1219         /* Fallback to software copy. */
1220         ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1221
1222 out:
1223         if (nv_device(drm->device)->card_type < NV_50) {
1224                 if (ret)
1225                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1226                 else
1227                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1228         }
1229
1230         return ret;
1231 }
1232
1233 static int
1234 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1235 {
1236         return 0;
1237 }
1238
1239 static int
1240 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1241 {
1242         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1243         struct nouveau_drm *drm = nouveau_bdev(bdev);
1244         struct drm_device *dev = drm->dev;
1245         int ret;
1246
1247         mem->bus.addr = NULL;
1248         mem->bus.offset = 0;
1249         mem->bus.size = mem->num_pages << PAGE_SHIFT;
1250         mem->bus.base = 0;
1251         mem->bus.is_iomem = false;
1252         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1253                 return -EINVAL;
1254         switch (mem->mem_type) {
1255         case TTM_PL_SYSTEM:
1256                 /* System memory */
1257                 return 0;
1258         case TTM_PL_TT:
1259 #if __OS_HAS_AGP
1260                 if (drm->agp.stat == ENABLED) {
1261                         mem->bus.offset = mem->start << PAGE_SHIFT;
1262                         mem->bus.base = drm->agp.base;
1263                         mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1264                 }
1265 #endif
1266                 break;
1267         case TTM_PL_VRAM:
1268                 mem->bus.offset = mem->start << PAGE_SHIFT;
1269                 mem->bus.base = pci_resource_start(dev->pdev, 1);
1270                 mem->bus.is_iomem = true;
1271                 if (nv_device(drm->device)->card_type >= NV_50) {
1272                         struct nouveau_bar *bar = nouveau_bar(drm->device);
1273                         struct nouveau_mem *node = mem->mm_node;
1274
1275                         ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1276                                         &node->bar_vma);
1277                         if (ret)
1278                                 return ret;
1279
1280                         mem->bus.offset = node->bar_vma.offset;
1281                 }
1282                 break;
1283         default:
1284                 return -EINVAL;
1285         }
1286         return 0;
1287 }
1288
1289 static void
1290 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1291 {
1292         struct nouveau_drm *drm = nouveau_bdev(bdev);
1293         struct nouveau_bar *bar = nouveau_bar(drm->device);
1294         struct nouveau_mem *node = mem->mm_node;
1295
1296         if (!node->bar_vma.node)
1297                 return;
1298
1299         bar->unmap(bar, &node->bar_vma);
1300 }
1301
1302 static int
1303 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1304 {
1305         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1306         struct nouveau_bo *nvbo = nouveau_bo(bo);
1307         struct nouveau_device *device = nv_device(drm->device);
1308         u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1309
1310         /* as long as the bo isn't in vram, and isn't tiled, we've got
1311          * nothing to do here.
1312          */
1313         if (bo->mem.mem_type != TTM_PL_VRAM) {
1314                 if (nv_device(drm->device)->card_type < NV_50 ||
1315                     !nouveau_bo_tile_layout(nvbo))
1316                         return 0;
1317         }
1318
1319         /* make sure bo is in mappable vram */
1320         if (bo->mem.start + bo->mem.num_pages < mappable)
1321                 return 0;
1322
1323
1324         nvbo->placement.fpfn = 0;
1325         nvbo->placement.lpfn = mappable;
1326         nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1327         return nouveau_bo_validate(nvbo, false, false);
1328 }
1329
1330 static int
1331 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1332 {
1333         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1334         struct nouveau_drm *drm;
1335         struct drm_device *dev;
1336         unsigned i;
1337         int r;
1338         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1339
1340         if (ttm->state != tt_unpopulated)
1341                 return 0;
1342
1343         if (slave && ttm->sg) {
1344                 /* make userspace faulting work */
1345                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1346                                                  ttm_dma->dma_address, ttm->num_pages);
1347                 ttm->state = tt_unbound;
1348                 return 0;
1349         }
1350
1351         drm = nouveau_bdev(ttm->bdev);
1352         dev = drm->dev;
1353
1354 #if __OS_HAS_AGP
1355         if (drm->agp.stat == ENABLED) {
1356                 return ttm_agp_tt_populate(ttm);
1357         }
1358 #endif
1359
1360 #ifdef CONFIG_SWIOTLB
1361         if (swiotlb_nr_tbl()) {
1362                 return ttm_dma_populate((void *)ttm, dev->dev);
1363         }
1364 #endif
1365
1366         r = ttm_pool_populate(ttm);
1367         if (r) {
1368                 return r;
1369         }
1370
1371         for (i = 0; i < ttm->num_pages; i++) {
1372                 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1373                                                    0, PAGE_SIZE,
1374                                                    PCI_DMA_BIDIRECTIONAL);
1375                 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1376                         while (--i) {
1377                                 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1378                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1379                                 ttm_dma->dma_address[i] = 0;
1380                         }
1381                         ttm_pool_unpopulate(ttm);
1382                         return -EFAULT;
1383                 }
1384         }
1385         return 0;
1386 }
1387
1388 static void
1389 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1390 {
1391         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1392         struct nouveau_drm *drm;
1393         struct drm_device *dev;
1394         unsigned i;
1395         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1396
1397         if (slave)
1398                 return;
1399
1400         drm = nouveau_bdev(ttm->bdev);
1401         dev = drm->dev;
1402
1403 #if __OS_HAS_AGP
1404         if (drm->agp.stat == ENABLED) {
1405                 ttm_agp_tt_unpopulate(ttm);
1406                 return;
1407         }
1408 #endif
1409
1410 #ifdef CONFIG_SWIOTLB
1411         if (swiotlb_nr_tbl()) {
1412                 ttm_dma_unpopulate((void *)ttm, dev->dev);
1413                 return;
1414         }
1415 #endif
1416
1417         for (i = 0; i < ttm->num_pages; i++) {
1418                 if (ttm_dma->dma_address[i]) {
1419                         pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1420                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1421                 }
1422         }
1423
1424         ttm_pool_unpopulate(ttm);
1425 }
1426
1427 void
1428 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1429 {
1430         struct nouveau_fence *old_fence = NULL;
1431
1432         if (likely(fence))
1433                 nouveau_fence_ref(fence);
1434
1435         spin_lock(&nvbo->bo.bdev->fence_lock);
1436         old_fence = nvbo->bo.sync_obj;
1437         nvbo->bo.sync_obj = fence;
1438         spin_unlock(&nvbo->bo.bdev->fence_lock);
1439
1440         nouveau_fence_unref(&old_fence);
1441 }
1442
1443 static void
1444 nouveau_bo_fence_unref(void **sync_obj)
1445 {
1446         nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1447 }
1448
1449 static void *
1450 nouveau_bo_fence_ref(void *sync_obj)
1451 {
1452         return nouveau_fence_ref(sync_obj);
1453 }
1454
1455 static bool
1456 nouveau_bo_fence_signalled(void *sync_obj)
1457 {
1458         return nouveau_fence_done(sync_obj);
1459 }
1460
1461 static int
1462 nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1463 {
1464         return nouveau_fence_wait(sync_obj, lazy, intr);
1465 }
1466
1467 static int
1468 nouveau_bo_fence_flush(void *sync_obj)
1469 {
1470         return 0;
1471 }
1472
1473 struct ttm_bo_driver nouveau_bo_driver = {
1474         .ttm_tt_create = &nouveau_ttm_tt_create,
1475         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1476         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1477         .invalidate_caches = nouveau_bo_invalidate_caches,
1478         .init_mem_type = nouveau_bo_init_mem_type,
1479         .evict_flags = nouveau_bo_evict_flags,
1480         .move_notify = nouveau_bo_move_ntfy,
1481         .move = nouveau_bo_move,
1482         .verify_access = nouveau_bo_verify_access,
1483         .sync_obj_signaled = nouveau_bo_fence_signalled,
1484         .sync_obj_wait = nouveau_bo_fence_wait,
1485         .sync_obj_flush = nouveau_bo_fence_flush,
1486         .sync_obj_unref = nouveau_bo_fence_unref,
1487         .sync_obj_ref = nouveau_bo_fence_ref,
1488         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1489         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1490         .io_mem_free = &nouveau_ttm_io_mem_free,
1491 };
1492
1493 struct nouveau_vma *
1494 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1495 {
1496         struct nouveau_vma *vma;
1497         list_for_each_entry(vma, &nvbo->vma_list, head) {
1498                 if (vma->vm == vm)
1499                         return vma;
1500         }
1501
1502         return NULL;
1503 }
1504
1505 int
1506 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1507                    struct nouveau_vma *vma)
1508 {
1509         const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1510         struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1511         int ret;
1512
1513         ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1514                              NV_MEM_ACCESS_RW, vma);
1515         if (ret)
1516                 return ret;
1517
1518         if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1519                 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1520         else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1521                 if (node->sg)
1522                         nouveau_vm_map_sg_table(vma, 0, size, node);
1523                 else
1524                         nouveau_vm_map_sg(vma, 0, size, node);
1525         }
1526
1527         list_add_tail(&vma->head, &nvbo->vma_list);
1528         vma->refcount = 1;
1529         return 0;
1530 }
1531
1532 void
1533 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1534 {
1535         if (vma->node) {
1536                 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1537                         spin_lock(&nvbo->bo.bdev->fence_lock);
1538                         ttm_bo_wait(&nvbo->bo, false, false, false);
1539                         spin_unlock(&nvbo->bo.bdev->fence_lock);
1540                         nouveau_vm_unmap(vma);
1541                 }
1542
1543                 nouveau_vm_put(vma);
1544                 list_del(&vma->head);
1545         }
1546 }