drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  40 {
  41         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  42 }
  43
  44 static void
  45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  46 {
  47         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         uint32_t enabled_bits;
  50
  51         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  52
  53         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  54              "HDMI port enabled, expecting disabled\n");
  55 }
  56
  57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  58 {
  59         struct intel_digital_port *intel_dig_port =
  60                 container_of(encoder, struct intel_digital_port, base.base);
  61         return &intel_dig_port->hdmi;
  62 }
  63
  64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  65 {
  66         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  67 }
  68
  69 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  70 {
  71         uint8_t *data = (uint8_t *)frame;
  72         uint8_t sum = 0;
  73         unsigned i;
  74
  75         frame->checksum = 0;
  76         frame->ecc = 0;
  77
  78         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  79                 sum += data[i];
  80
  81         frame->checksum = 0x100 - sum;
  82 }
  83
  84 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  85 {
  86         switch (frame->type) {
  87         case DIP_TYPE_AVI:
  88                 return VIDEO_DIP_SELECT_AVI;
  89         case DIP_TYPE_SPD:
  90                 return VIDEO_DIP_SELECT_SPD;
  91         default:
  92                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  93                 return 0;
  94         }
  95 }
  96
  97 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  98 {
  99         switch (frame->type) {
 100         case DIP_TYPE_AVI:
 101                 return VIDEO_DIP_ENABLE_AVI;
 102         case DIP_TYPE_SPD:
 103                 return VIDEO_DIP_ENABLE_SPD;
 104         default:
 105                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 106                 return 0;
 107         }
 108 }
 109
 110 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 111 {
 112         switch (frame->type) {
 113         case DIP_TYPE_AVI:
 114                 return VIDEO_DIP_ENABLE_AVI_HSW;
 115         case DIP_TYPE_SPD:
 116                 return VIDEO_DIP_ENABLE_SPD_HSW;
 117         default:
 118                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 119                 return 0;
 120         }
 121 }
 122
 123 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
 124                                   enum transcoder cpu_transcoder)
 125 {
 126         switch (frame->type) {
 127         case DIP_TYPE_AVI:
 128                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 129         case DIP_TYPE_SPD:
 130                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 131         default:
 132                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 133                 return 0;
 134         }
 135 }
 136
 137 static void g4x_write_infoframe(struct drm_encoder *encoder,
 138                                 struct dip_infoframe *frame)
 139 {
 140         uint32_t *data = (uint32_t *)frame;
 141         struct drm_device *dev = encoder->dev;
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         u32 val = I915_READ(VIDEO_DIP_CTL);
 144         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 145
 146         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 147
 148         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 149         val |= g4x_infoframe_index(frame);
 150
 151         val &= ~g4x_infoframe_enable(frame);
 152
 153         I915_WRITE(VIDEO_DIP_CTL, val);
 154
 155         mmiowb();
 156         for (i = 0; i < len; i += 4) {
 157                 I915_WRITE(VIDEO_DIP_DATA, *data);
 158                 data++;
 159         }
 160         /* Write every possible data byte to force correct ECC calculation. */
 161         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 162                 I915_WRITE(VIDEO_DIP_DATA, 0);
 163         mmiowb();
 164
 165         val |= g4x_infoframe_enable(frame);
 166         val &= ~VIDEO_DIP_FREQ_MASK;
 167         val |= VIDEO_DIP_FREQ_VSYNC;
 168
 169         I915_WRITE(VIDEO_DIP_CTL, val);
 170         POSTING_READ(VIDEO_DIP_CTL);
 171 }
 172
 173 static void ibx_write_infoframe(struct drm_encoder *encoder,
 174                                 struct dip_infoframe *frame)
 175 {
 176         uint32_t *data = (uint32_t *)frame;
 177         struct drm_device *dev = encoder->dev;
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 180         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 181         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 182         u32 val = I915_READ(reg);
 183
 184         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 185
 186         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 187         val |= g4x_infoframe_index(frame);
 188
 189         val &= ~g4x_infoframe_enable(frame);
 190
 191         I915_WRITE(reg, val);
 192
 193         mmiowb();
 194         for (i = 0; i < len; i += 4) {
 195                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 196                 data++;
 197         }
 198         /* Write every possible data byte to force correct ECC calculation. */
 199         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 200                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 201         mmiowb();
 202
 203         val |= g4x_infoframe_enable(frame);
 204         val &= ~VIDEO_DIP_FREQ_MASK;
 205         val |= VIDEO_DIP_FREQ_VSYNC;
 206
 207         I915_WRITE(reg, val);
 208         POSTING_READ(reg);
 209 }
 210
 211 static void cpt_write_infoframe(struct drm_encoder *encoder,
 212                                 struct dip_infoframe *frame)
 213 {
 214         uint32_t *data = (uint32_t *)frame;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 218         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 219         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 220         u32 val = I915_READ(reg);
 221
 222         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 223
 224         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 225         val |= g4x_infoframe_index(frame);
 226
 227         /* The DIP control register spec says that we need to update the AVI
 228          * infoframe without clearing its enable bit */
 229         if (frame->type != DIP_TYPE_AVI)
 230                 val &= ~g4x_infoframe_enable(frame);
 231
 232         I915_WRITE(reg, val);
 233
 234         mmiowb();
 235         for (i = 0; i < len; i += 4) {
 236                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 237                 data++;
 238         }
 239         /* Write every possible data byte to force correct ECC calculation. */
 240         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 241                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 242         mmiowb();
 243
 244         val |= g4x_infoframe_enable(frame);
 245         val &= ~VIDEO_DIP_FREQ_MASK;
 246         val |= VIDEO_DIP_FREQ_VSYNC;
 247
 248         I915_WRITE(reg, val);
 249         POSTING_READ(reg);
 250 }
 251
 252 static void vlv_write_infoframe(struct drm_encoder *encoder,
 253                                      struct dip_infoframe *frame)
 254 {
 255         uint32_t *data = (uint32_t *)frame;
 256         struct drm_device *dev = encoder->dev;
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 259         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 260         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 261         u32 val = I915_READ(reg);
 262
 263         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 264
 265         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 266         val |= g4x_infoframe_index(frame);
 267
 268         val &= ~g4x_infoframe_enable(frame);
 269
 270         I915_WRITE(reg, val);
 271
 272         mmiowb();
 273         for (i = 0; i < len; i += 4) {
 274                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 275                 data++;
 276         }
 277         /* Write every possible data byte to force correct ECC calculation. */
 278         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 279                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 280         mmiowb();
 281
 282         val |= g4x_infoframe_enable(frame);
 283         val &= ~VIDEO_DIP_FREQ_MASK;
 284         val |= VIDEO_DIP_FREQ_VSYNC;
 285
 286         I915_WRITE(reg, val);
 287         POSTING_READ(reg);
 288 }
 289
 290 static void hsw_write_infoframe(struct drm_encoder *encoder,
 291                                 struct dip_infoframe *frame)
 292 {
 293         uint32_t *data = (uint32_t *)frame;
 294         struct drm_device *dev = encoder->dev;
 295         struct drm_i915_private *dev_priv = dev->dev_private;
 296         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 297         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
 298         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->cpu_transcoder);
 299         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 300         u32 val = I915_READ(ctl_reg);
 301
 302         if (data_reg == 0)
 303                 return;
 304
 305         val &= ~hsw_infoframe_enable(frame);
 306         I915_WRITE(ctl_reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(data_reg + i, *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(data_reg + i, 0);
 316         mmiowb();
 317
 318         val |= hsw_infoframe_enable(frame);
 319         I915_WRITE(ctl_reg, val);
 320         POSTING_READ(ctl_reg);
 321 }
 322
 323 static void intel_set_infoframe(struct drm_encoder *encoder,
 324                                 struct dip_infoframe *frame)
 325 {
 326         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 327
 328         intel_dip_infoframe_csum(frame);
 329         intel_hdmi->write_infoframe(encoder, frame);
 330 }
 331
 332 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 333                                          struct drm_display_mode *adjusted_mode)
 334 {
 335         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 336         struct dip_infoframe avi_if = {
 337                 .type = DIP_TYPE_AVI,
 338                 .ver = DIP_VERSION_AVI,
 339                 .len = DIP_LEN_AVI,
 340         };
 341
 342         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 343                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 344
 345         if (intel_hdmi->rgb_quant_range_selectable) {
 346                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
 347                         avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
 348                 else
 349                         avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
 350         }
 351
 352         avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
 353
 354         intel_set_infoframe(encoder, &avi_if);
 355 }
 356
 357 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 358 {
 359         struct dip_infoframe spd_if;
 360
 361         memset(&spd_if, 0, sizeof(spd_if));
 362         spd_if.type = DIP_TYPE_SPD;
 363         spd_if.ver = DIP_VERSION_SPD;
 364         spd_if.len = DIP_LEN_SPD;
 365         strcpy(spd_if.body.spd.vn, "Intel");
 366         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 367         spd_if.body.spd.sdi = DIP_SPD_PC;
 368
 369         intel_set_infoframe(encoder, &spd_if);
 370 }
 371
 372 static void g4x_set_infoframes(struct drm_encoder *encoder,
 373                                struct drm_display_mode *adjusted_mode)
 374 {
 375         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 376         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 377         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 378         u32 reg = VIDEO_DIP_CTL;
 379         u32 val = I915_READ(reg);
 380         u32 port;
 381
 382         assert_hdmi_port_disabled(intel_hdmi);
 383
 384         /* If the registers were not initialized yet, they might be zeroes,
 385          * which means we're selecting the AVI DIP and we're setting its
 386          * frequency to once. This seems to really confuse the HW and make
 387          * things stop working (the register spec says the AVI always needs to
 388          * be sent every VSync). So here we avoid writing to the register more
 389          * than we need and also explicitly select the AVI DIP and explicitly
 390          * set its frequency to every VSync. Avoiding to write it twice seems to
 391          * be enough to solve the problem, but being defensive shouldn't hurt us
 392          * either. */
 393         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 394
 395         if (!intel_hdmi->has_hdmi_sink) {
 396                 if (!(val & VIDEO_DIP_ENABLE))
 397                         return;
 398                 val &= ~VIDEO_DIP_ENABLE;
 399                 I915_WRITE(reg, val);
 400                 POSTING_READ(reg);
 401                 return;
 402         }
 403
 404         switch (intel_dig_port->port) {
 405         case PORT_B:
 406                 port = VIDEO_DIP_PORT_B;
 407                 break;
 408         case PORT_C:
 409                 port = VIDEO_DIP_PORT_C;
 410                 break;
 411         default:
 412                 BUG();
 413                 return;
 414         }
 415
 416         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 417                 if (val & VIDEO_DIP_ENABLE) {
 418                         val &= ~VIDEO_DIP_ENABLE;
 419                         I915_WRITE(reg, val);
 420                         POSTING_READ(reg);
 421                 }
 422                 val &= ~VIDEO_DIP_PORT_MASK;
 423                 val |= port;
 424         }
 425
 426         val |= VIDEO_DIP_ENABLE;
 427         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 428
 429         I915_WRITE(reg, val);
 430         POSTING_READ(reg);
 431
 432         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 433         intel_hdmi_set_spd_infoframe(encoder);
 434 }
 435
 436 static void ibx_set_infoframes(struct drm_encoder *encoder,
 437                                struct drm_display_mode *adjusted_mode)
 438 {
 439         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 440         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 441         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 442         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 443         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 444         u32 val = I915_READ(reg);
 445         u32 port;
 446
 447         assert_hdmi_port_disabled(intel_hdmi);
 448
 449         /* See the big comment in g4x_set_infoframes() */
 450         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 451
 452         if (!intel_hdmi->has_hdmi_sink) {
 453                 if (!(val & VIDEO_DIP_ENABLE))
 454                         return;
 455                 val &= ~VIDEO_DIP_ENABLE;
 456                 I915_WRITE(reg, val);
 457                 POSTING_READ(reg);
 458                 return;
 459         }
 460
 461         switch (intel_dig_port->port) {
 462         case PORT_B:
 463                 port = VIDEO_DIP_PORT_B;
 464                 break;
 465         case PORT_C:
 466                 port = VIDEO_DIP_PORT_C;
 467                 break;
 468         case PORT_D:
 469                 port = VIDEO_DIP_PORT_D;
 470                 break;
 471         default:
 472                 BUG();
 473                 return;
 474         }
 475
 476         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 477                 if (val & VIDEO_DIP_ENABLE) {
 478                         val &= ~VIDEO_DIP_ENABLE;
 479                         I915_WRITE(reg, val);
 480                         POSTING_READ(reg);
 481                 }
 482                 val &= ~VIDEO_DIP_PORT_MASK;
 483                 val |= port;
 484         }
 485
 486         val |= VIDEO_DIP_ENABLE;
 487         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 488                  VIDEO_DIP_ENABLE_GCP);
 489
 490         I915_WRITE(reg, val);
 491         POSTING_READ(reg);
 492
 493         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 494         intel_hdmi_set_spd_infoframe(encoder);
 495 }
 496
 497 static void cpt_set_infoframes(struct drm_encoder *encoder,
 498                                struct drm_display_mode *adjusted_mode)
 499 {
 500         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 501         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 502         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 503         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 504         u32 val = I915_READ(reg);
 505
 506         assert_hdmi_port_disabled(intel_hdmi);
 507
 508         /* See the big comment in g4x_set_infoframes() */
 509         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 510
 511         if (!intel_hdmi->has_hdmi_sink) {
 512                 if (!(val & VIDEO_DIP_ENABLE))
 513                         return;
 514                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 515                 I915_WRITE(reg, val);
 516                 POSTING_READ(reg);
 517                 return;
 518         }
 519
 520         /* Set both together, unset both together: see the spec. */
 521         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 522         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 523                  VIDEO_DIP_ENABLE_GCP);
 524
 525         I915_WRITE(reg, val);
 526         POSTING_READ(reg);
 527
 528         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 529         intel_hdmi_set_spd_infoframe(encoder);
 530 }
 531
 532 static void vlv_set_infoframes(struct drm_encoder *encoder,
 533                                struct drm_display_mode *adjusted_mode)
 534 {
 535         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 536         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 537         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 538         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 539         u32 val = I915_READ(reg);
 540
 541         assert_hdmi_port_disabled(intel_hdmi);
 542
 543         /* See the big comment in g4x_set_infoframes() */
 544         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 545
 546         if (!intel_hdmi->has_hdmi_sink) {
 547                 if (!(val & VIDEO_DIP_ENABLE))
 548                         return;
 549                 val &= ~VIDEO_DIP_ENABLE;
 550                 I915_WRITE(reg, val);
 551                 POSTING_READ(reg);
 552                 return;
 553         }
 554
 555         val |= VIDEO_DIP_ENABLE;
 556         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 557                  VIDEO_DIP_ENABLE_GCP);
 558
 559         I915_WRITE(reg, val);
 560         POSTING_READ(reg);
 561
 562         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 563         intel_hdmi_set_spd_infoframe(encoder);
 564 }
 565
 566 static void hsw_set_infoframes(struct drm_encoder *encoder,
 567                                struct drm_display_mode *adjusted_mode)
 568 {
 569         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 570         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 571         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 572         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
 573         u32 val = I915_READ(reg);
 574
 575         assert_hdmi_port_disabled(intel_hdmi);
 576
 577         if (!intel_hdmi->has_hdmi_sink) {
 578                 I915_WRITE(reg, 0);
 579                 POSTING_READ(reg);
 580                 return;
 581         }
 582
 583         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 584                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 585
 586         I915_WRITE(reg, val);
 587         POSTING_READ(reg);
 588
 589         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 590         intel_hdmi_set_spd_infoframe(encoder);
 591 }
 592
 593 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 594                                 struct drm_display_mode *mode,
 595                                 struct drm_display_mode *adjusted_mode)
 596 {
 597         struct drm_device *dev = encoder->dev;
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 600         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 601         u32 hdmi_val;
 602
 603         hdmi_val = SDVO_ENCODING_HDMI;
 604         if (!HAS_PCH_SPLIT(dev))
 605                 hdmi_val |= intel_hdmi->color_range;
 606         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 607                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 608         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 609                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 610
 611         if (intel_crtc->bpp > 24)
 612                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 613         else
 614                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 615
 616         /* Required on CPT */
 617         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 618                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 619
 620         if (intel_hdmi->has_audio) {
 621                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 622                                  pipe_name(intel_crtc->pipe));
 623                 hdmi_val |= SDVO_AUDIO_ENABLE;
 624                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 625                 intel_write_eld(encoder, adjusted_mode);
 626         }
 627
 628         if (HAS_PCH_CPT(dev))
 629                 hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
 630         else
 631                 hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe);
 632
 633         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 634         POSTING_READ(intel_hdmi->hdmi_reg);
 635
 636         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 637 }
 638
 639 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 640                                     enum pipe *pipe)
 641 {
 642         struct drm_device *dev = encoder->base.dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 645         u32 tmp;
 646
 647         tmp = I915_READ(intel_hdmi->hdmi_reg);
 648
 649         if (!(tmp & SDVO_ENABLE))
 650                 return false;
 651
 652         if (HAS_PCH_CPT(dev))
 653                 *pipe = PORT_TO_PIPE_CPT(tmp);
 654         else
 655                 *pipe = PORT_TO_PIPE(tmp);
 656
 657         return true;
 658 }
 659
 660 static void intel_enable_hdmi(struct intel_encoder *encoder)
 661 {
 662         struct drm_device *dev = encoder->base.dev;
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 665         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 666         u32 temp;
 667         u32 enable_bits = SDVO_ENABLE;
 668
 669         if (intel_hdmi->has_audio)
 670                 enable_bits |= SDVO_AUDIO_ENABLE;
 671
 672         temp = I915_READ(intel_hdmi->hdmi_reg);
 673
 674         /* HW workaround for IBX, we need to move the port to transcoder A
 675          * before disabling it, so restore the transcoder select bit here. */
 676         if (HAS_PCH_IBX(dev))
 677                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 678
 679         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 680          * we do this anyway which shows more stable in testing.
 681          */
 682         if (HAS_PCH_SPLIT(dev)) {
 683                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 684                 POSTING_READ(intel_hdmi->hdmi_reg);
 685         }
 686
 687         temp |= enable_bits;
 688
 689         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 690         POSTING_READ(intel_hdmi->hdmi_reg);
 691
 692         /* HW workaround, need to write this twice for issue that may result
 693          * in first write getting masked.
 694          */
 695         if (HAS_PCH_SPLIT(dev)) {
 696                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 697                 POSTING_READ(intel_hdmi->hdmi_reg);
 698         }
 699 }
 700
 701 static void intel_disable_hdmi(struct intel_encoder *encoder)
 702 {
 703         struct drm_device *dev = encoder->base.dev;
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 706         u32 temp;
 707         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 708
 709         temp = I915_READ(intel_hdmi->hdmi_reg);
 710
 711         /* HW workaround for IBX, we need to move the port to transcoder A
 712          * before disabling it. */
 713         if (HAS_PCH_IBX(dev)) {
 714                 struct drm_crtc *crtc = encoder->base.crtc;
 715                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 716
 717                 if (temp & SDVO_PIPE_B_SELECT) {
 718                         temp &= ~SDVO_PIPE_B_SELECT;
 719                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 720                         POSTING_READ(intel_hdmi->hdmi_reg);
 721
 722                         /* Again we need to write this twice. */
 723                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 724                         POSTING_READ(intel_hdmi->hdmi_reg);
 725
 726                         /* Transcoder selection bits only update
 727                          * effectively on vblank. */
 728                         if (crtc)
 729                                 intel_wait_for_vblank(dev, pipe);
 730                         else
 731                                 msleep(50);
 732                 }
 733         }
 734
 735         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 736          * we do this anyway which shows more stable in testing.
 737          */
 738         if (HAS_PCH_SPLIT(dev)) {
 739                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 740                 POSTING_READ(intel_hdmi->hdmi_reg);
 741         }
 742
 743         temp &= ~enable_bits;
 744
 745         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 746         POSTING_READ(intel_hdmi->hdmi_reg);
 747
 748         /* HW workaround, need to write this twice for issue that may result
 749          * in first write getting masked.
 750          */
 751         if (HAS_PCH_SPLIT(dev)) {
 752                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 753                 POSTING_READ(intel_hdmi->hdmi_reg);
 754         }
 755 }
 756
 757 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 758                                  struct drm_display_mode *mode)
 759 {
 760         if (mode->clock > 165000)
 761                 return MODE_CLOCK_HIGH;
 762         if (mode->clock < 20000)
 763                 return MODE_CLOCK_LOW;
 764
 765         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 766                 return MODE_NO_DBLESCAN;
 767
 768         return MODE_OK;
 769 }
 770
 771 bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 772                            const struct drm_display_mode *mode,
 773                            struct drm_display_mode *adjusted_mode)
 774 {
 775         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 776
 777         if (intel_hdmi->color_range_auto) {
 778                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 779                 if (intel_hdmi->has_hdmi_sink &&
 780                     drm_mode_cea_vic(adjusted_mode) > 1)
 781                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 782                 else
 783                         intel_hdmi->color_range = 0;
 784         }
 785
 786         if (intel_hdmi->color_range)
 787                 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
 788
 789         return true;
 790 }
 791
 792 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
 793 {
 794         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
 797         uint32_t bit;
 798
 799         switch (intel_dig_port->port) {
 800         case PORT_B:
 801                 bit = PORTB_HOTPLUG_LIVE_STATUS;
 802                 break;
 803         case PORT_C:
 804                 bit = PORTC_HOTPLUG_LIVE_STATUS;
 805                 break;
 806         default:
 807                 bit = 0;
 808                 break;
 809         }
 810
 811         return I915_READ(PORT_HOTPLUG_STAT) & bit;
 812 }
 813
 814 static enum drm_connector_status
 815 intel_hdmi_detect(struct drm_connector *connector, bool force)
 816 {
 817         struct drm_device *dev = connector->dev;
 818         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 819         struct intel_digital_port *intel_dig_port =
 820                 hdmi_to_dig_port(intel_hdmi);
 821         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         struct edid *edid;
 824         enum drm_connector_status status = connector_status_disconnected;
 825
 826
 827         if (IS_G4X(dev) && !g4x_hdmi_connected(intel_hdmi))
 828                 return status;
 829         else if (HAS_PCH_SPLIT(dev) &&
 830                  !ibx_digital_port_connected(dev_priv, intel_dig_port))
 831                  return status;
 832
 833         intel_hdmi->has_hdmi_sink = false;
 834         intel_hdmi->has_audio = false;
 835         intel_hdmi->rgb_quant_range_selectable = false;
 836         edid = drm_get_edid(connector,
 837                             intel_gmbus_get_adapter(dev_priv,
 838                                                     intel_hdmi->ddc_bus));
 839
 840         if (edid) {
 841                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 842                         status = connector_status_connected;
 843                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 844                                 intel_hdmi->has_hdmi_sink =
 845                                                 drm_detect_hdmi_monitor(edid);
 846                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 847                         intel_hdmi->rgb_quant_range_selectable =
 848                                 drm_rgb_quant_range_selectable(edid);
 849                 }
 850                 kfree(edid);
 851         }
 852
 853         if (status == connector_status_connected) {
 854                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 855                         intel_hdmi->has_audio =
 856                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 857                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 858         }
 859
 860         return status;
 861 }
 862
 863 static int intel_hdmi_get_modes(struct drm_connector *connector)
 864 {
 865         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 866         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 867
 868         /* We should parse the EDID data and find out if it's an HDMI sink so
 869          * we can send audio to it.
 870          */
 871
 872         return intel_ddc_get_modes(connector,
 873                                    intel_gmbus_get_adapter(dev_priv,
 874                                                            intel_hdmi->ddc_bus));
 875 }
 876
 877 static bool
 878 intel_hdmi_detect_audio(struct drm_connector *connector)
 879 {
 880         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 881         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 882         struct edid *edid;
 883         bool has_audio = false;
 884
 885         edid = drm_get_edid(connector,
 886                             intel_gmbus_get_adapter(dev_priv,
 887                                                     intel_hdmi->ddc_bus));
 888         if (edid) {
 889                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 890                         has_audio = drm_detect_monitor_audio(edid);
 891                 kfree(edid);
 892         }
 893
 894         return has_audio;
 895 }
 896
 897 static int
 898 intel_hdmi_set_property(struct drm_connector *connector,
 899                         struct drm_property *property,
 900                         uint64_t val)
 901 {
 902         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 903         struct intel_digital_port *intel_dig_port =
 904                 hdmi_to_dig_port(intel_hdmi);
 905         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 906         int ret;
 907
 908         ret = drm_object_property_set_value(&connector->base, property, val);
 909         if (ret)
 910                 return ret;
 911
 912         if (property == dev_priv->force_audio_property) {
 913                 enum hdmi_force_audio i = val;
 914                 bool has_audio;
 915
 916                 if (i == intel_hdmi->force_audio)
 917                         return 0;
 918
 919                 intel_hdmi->force_audio = i;
 920
 921                 if (i == HDMI_AUDIO_AUTO)
 922                         has_audio = intel_hdmi_detect_audio(connector);
 923                 else
 924                         has_audio = (i == HDMI_AUDIO_ON);
 925
 926                 if (i == HDMI_AUDIO_OFF_DVI)
 927                         intel_hdmi->has_hdmi_sink = 0;
 928
 929                 intel_hdmi->has_audio = has_audio;
 930                 goto done;
 931         }
 932
 933         if (property == dev_priv->broadcast_rgb_property) {
 934                 switch (val) {
 935                 case INTEL_BROADCAST_RGB_AUTO:
 936                         intel_hdmi->color_range_auto = true;
 937                         break;
 938                 case INTEL_BROADCAST_RGB_FULL:
 939                         intel_hdmi->color_range_auto = false;
 940                         intel_hdmi->color_range = 0;
 941                         break;
 942                 case INTEL_BROADCAST_RGB_LIMITED:
 943                         intel_hdmi->color_range_auto = false;
 944                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 945                         break;
 946                 default:
 947                         return -EINVAL;
 948                 }
 949                 goto done;
 950         }
 951
 952         return -EINVAL;
 953
 954 done:
 955         if (intel_dig_port->base.base.crtc)
 956                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
 957
 958         return 0;
 959 }
 960
 961 static void intel_hdmi_destroy(struct drm_connector *connector)
 962 {
 963         drm_sysfs_connector_remove(connector);
 964         drm_connector_cleanup(connector);
 965         kfree(connector);
 966 }
 967
 968 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 969         .mode_fixup = intel_hdmi_mode_fixup,
 970         .mode_set = intel_hdmi_mode_set,
 971         .disable = intel_encoder_noop,
 972 };
 973
 974 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 975         .dpms = intel_connector_dpms,
 976         .detect = intel_hdmi_detect,
 977         .fill_modes = drm_helper_probe_single_connector_modes,
 978         .set_property = intel_hdmi_set_property,
 979         .destroy = intel_hdmi_destroy,
 980 };
 981
 982 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 983         .get_modes = intel_hdmi_get_modes,
 984         .mode_valid = intel_hdmi_mode_valid,
 985         .best_encoder = intel_best_encoder,
 986 };
 987
 988 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 989         .destroy = intel_encoder_destroy,
 990 };
 991
 992 static void
 993 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 994 {
 995         intel_attach_force_audio_property(connector);
 996         intel_attach_broadcast_rgb_property(connector);
 997         intel_hdmi->color_range_auto = true;
 998 }
 999
1000 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1001                                struct intel_connector *intel_connector)
1002 {
1003         struct drm_connector *connector = &intel_connector->base;
1004         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1005         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1006         struct drm_device *dev = intel_encoder->base.dev;
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         enum port port = intel_dig_port->port;
1009
1010         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1011                            DRM_MODE_CONNECTOR_HDMIA);
1012         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1013
1014         connector->polled = DRM_CONNECTOR_POLL_HPD;
1015         connector->interlace_allowed = 1;
1016         connector->doublescan_allowed = 0;
1017
1018         switch (port) {
1019         case PORT_B:
1020                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1021                 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
1022                 break;
1023         case PORT_C:
1024                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1025                 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
1026                 break;
1027         case PORT_D:
1028                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1029                 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
1030                 break;
1031         case PORT_A:
1032                 /* Internal port only for eDP. */
1033         default:
1034                 BUG();
1035         }
1036
1037         if (!HAS_PCH_SPLIT(dev)) {
1038                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1039                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1040         } else if (IS_VALLEYVIEW(dev)) {
1041                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1042                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1043         } else if (HAS_DDI(dev)) {
1044                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1045                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1046         } else if (HAS_PCH_IBX(dev)) {
1047                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1048                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1049         } else {
1050                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1051                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1052         }
1053
1054         if (HAS_DDI(dev))
1055                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1056         else
1057                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1058
1059         intel_hdmi_add_properties(intel_hdmi, connector);
1060
1061         intel_connector_attach_encoder(intel_connector, intel_encoder);
1062         drm_sysfs_connector_add(connector);
1063
1064         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1065          * 0xd.  Failure to do so will result in spurious interrupts being
1066          * generated on the port when a cable is not attached.
1067          */
1068         if (IS_G4X(dev) && !IS_GM45(dev)) {
1069                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1070                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1071         }
1072 }
1073
1074 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1075 {
1076         struct intel_digital_port *intel_dig_port;
1077         struct intel_encoder *intel_encoder;
1078         struct drm_encoder *encoder;
1079         struct intel_connector *intel_connector;
1080
1081         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1082         if (!intel_dig_port)
1083                 return;
1084
1085         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1086         if (!intel_connector) {
1087                 kfree(intel_dig_port);
1088                 return;
1089         }
1090
1091         intel_encoder = &intel_dig_port->base;
1092         encoder = &intel_encoder->base;
1093
1094         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1095                          DRM_MODE_ENCODER_TMDS);
1096         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1097
1098         intel_encoder->enable = intel_enable_hdmi;
1099         intel_encoder->disable = intel_disable_hdmi;
1100         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1101
1102         intel_encoder->type = INTEL_OUTPUT_HDMI;
1103         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1104         intel_encoder->cloneable = false;
1105
1106         intel_dig_port->port = port;
1107         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1108         intel_dig_port->dp.output_reg = 0;
1109
1110         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1111 }