2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
36 #define _wait_for(COND, MS, W) ({ \
37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
40 if (time_after(jiffies, timeout__)) { \
44 if (W && drm_can_sleep()) { \
53 #define wait_for_atomic_us(COND, US) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
57 if (time_after(jiffies, timeout__)) { \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
69 #define KHz(x) (1000*x)
70 #define MHz(x) KHz(1000*x)
73 * Display related stuff
76 /* store information about an Ixxx DVO */
77 /* The i830->i865 use multiple DVOs with multiple i2cs */
78 /* the i915, i945 have a single sDVO i2c bus - which is different */
80 /* maximum connectors per crtcs in the mode set */
81 #define INTELFB_CONN_LIMIT 4
83 #define INTEL_I2C_BUS_DVO 1
84 #define INTEL_I2C_BUS_SDVO 2
86 /* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88 #define INTEL_OUTPUT_UNUSED 0
89 #define INTEL_OUTPUT_ANALOG 1
90 #define INTEL_OUTPUT_DVO 2
91 #define INTEL_OUTPUT_SDVO 3
92 #define INTEL_OUTPUT_LVDS 4
93 #define INTEL_OUTPUT_TVOUT 5
94 #define INTEL_OUTPUT_HDMI 6
95 #define INTEL_OUTPUT_DISPLAYPORT 7
96 #define INTEL_OUTPUT_EDP 8
97 #define INTEL_OUTPUT_UNKNOWN 9
99 #define INTEL_DVO_CHIP_NONE 0
100 #define INTEL_DVO_CHIP_LVDS 1
101 #define INTEL_DVO_CHIP_TMDS 2
102 #define INTEL_DVO_CHIP_TVOUT 4
104 /* drm_display_mode->private_flags */
105 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
107 #define INTEL_MODE_DP_FORCE_6BPC (0x10)
108 /* This flag must be set by the encoder's mode_fixup if it changes the crtc
109 * timings in the mode to prevent the crtc fixup from overwriting them.
110 * Currently only lvds needs that. */
111 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
113 * Set when limited 16-235 (as opposed to full 0-255) RGB color range is
116 #define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
119 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
122 mode->clock *= multiplier;
123 mode->private_flags |= multiplier;
127 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
129 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
132 struct intel_framebuffer {
133 struct drm_framebuffer base;
134 struct drm_i915_gem_object *obj;
138 struct drm_fb_helper helper;
139 struct intel_framebuffer ifb;
140 struct list_head fbdev_list;
141 struct drm_display_mode *our_mode;
144 struct intel_encoder {
145 struct drm_encoder base;
147 * The new crtc this encoder will be driven from. Only differs from
148 * base->crtc while a modeset is in progress.
150 struct intel_crtc *new_crtc;
155 * Intel hw has only one MUX where encoders could be clone, hence a
156 * simple flag is enough to compute the possible_clones mask.
159 bool connectors_active;
160 void (*hot_plug)(struct intel_encoder *);
161 void (*pre_pll_enable)(struct intel_encoder *);
162 void (*pre_enable)(struct intel_encoder *);
163 void (*enable)(struct intel_encoder *);
164 void (*disable)(struct intel_encoder *);
165 void (*post_disable)(struct intel_encoder *);
166 /* Read out the current hw state of this connector, returning true if
167 * the encoder is active. If the encoder is enabled it also set the pipe
168 * it is connected to in the pipe parameter. */
169 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
174 struct drm_display_mode *fixed_mode;
178 struct intel_connector {
179 struct drm_connector base;
181 * The fixed encoder this connector is connected to.
183 struct intel_encoder *encoder;
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
189 struct intel_encoder *new_encoder;
191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state)(struct intel_connector *);
195 /* Panel info for eDP and LVDS */
196 struct intel_panel panel;
198 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
203 struct drm_crtc base;
206 enum transcoder cpu_transcoder;
207 u8 lut_r[256], lut_g[256], lut_b[256];
209 * Whether the crtc and the connected output pipeline is active. Implies
210 * that crtc->enabled is set, i.e. the current mode configuration has
211 * some outputs connected to this crtc.
215 bool primary_disabled; /* is the crtc obscured by a plane? */
217 struct intel_overlay *overlay;
218 struct intel_unpin_work *unpin_work;
221 atomic_t unpin_work_count;
223 /* Display surface base address adjustement for pageflips. Note that on
224 * gen4+ this only adjusts up to a tile, offsets within a tile are
225 * handled in the hw itself (with the TILEOFF register). */
226 unsigned long dspaddr_offset;
228 struct drm_i915_gem_object *cursor_bo;
229 uint32_t cursor_addr;
230 int16_t cursor_x, cursor_y;
231 int16_t cursor_width, cursor_height;
235 /* We can share PLLs across outputs if the timings match */
236 struct intel_pch_pll *pch_pll;
237 uint32_t ddi_pll_sel;
239 /* reset counter value when the last flip was submitted */
240 unsigned int reset_counter;
244 struct drm_plane base;
246 struct drm_i915_gem_object *obj;
249 u32 lut_r[1024], lut_g[1024], lut_b[1024];
250 void (*update_plane)(struct drm_plane *plane,
251 struct drm_framebuffer *fb,
252 struct drm_i915_gem_object *obj,
253 int crtc_x, int crtc_y,
254 unsigned int crtc_w, unsigned int crtc_h,
255 uint32_t x, uint32_t y,
256 uint32_t src_w, uint32_t src_h);
257 void (*disable_plane)(struct drm_plane *plane);
258 int (*update_colorkey)(struct drm_plane *plane,
259 struct drm_intel_sprite_colorkey *key);
260 void (*get_colorkey)(struct drm_plane *plane,
261 struct drm_intel_sprite_colorkey *key);
264 struct intel_watermark_params {
265 unsigned long fifo_size;
266 unsigned long max_wm;
267 unsigned long default_wm;
268 unsigned long guard_size;
269 unsigned long cacheline_size;
272 struct cxsr_latency {
275 unsigned long fsb_freq;
276 unsigned long mem_freq;
277 unsigned long display_sr;
278 unsigned long display_hpll_disable;
279 unsigned long cursor_sr;
280 unsigned long cursor_hpll_disable;
283 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
284 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
285 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
286 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
287 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
289 #define DIP_HEADER_SIZE 5
291 #define DIP_TYPE_AVI 0x82
292 #define DIP_VERSION_AVI 0x2
293 #define DIP_LEN_AVI 13
294 #define DIP_AVI_PR_1 0
295 #define DIP_AVI_PR_2 1
296 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
297 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
298 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
300 #define DIP_TYPE_SPD 0x83
301 #define DIP_VERSION_SPD 0x1
302 #define DIP_LEN_SPD 25
303 #define DIP_SPD_UNKNOWN 0
304 #define DIP_SPD_DSTB 0x1
305 #define DIP_SPD_DVDP 0x2
306 #define DIP_SPD_DVHS 0x3
307 #define DIP_SPD_HDDVR 0x4
308 #define DIP_SPD_DVC 0x5
309 #define DIP_SPD_DSC 0x6
310 #define DIP_SPD_VCD 0x7
311 #define DIP_SPD_GAME 0x8
312 #define DIP_SPD_PC 0x9
313 #define DIP_SPD_BD 0xa
314 #define DIP_SPD_SCD 0xb
316 struct dip_infoframe {
317 uint8_t type; /* HB0 */
318 uint8_t ver; /* HB1 */
319 uint8_t len; /* HB2 - body len, not including checksum */
320 uint8_t ecc; /* Header ECC */
321 uint8_t checksum; /* PB0 */
324 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
326 /* PB2 - C 7:6, M 5:4, R 3:0 */
328 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
332 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
335 uint16_t top_bar_end;
336 uint16_t bottom_bar_start;
337 uint16_t left_bar_end;
338 uint16_t right_bar_start;
339 } __attribute__ ((packed)) avi;
344 } __attribute__ ((packed)) spd;
346 } __attribute__ ((packed)) body;
347 } __attribute__((packed));
352 uint32_t color_range;
353 bool color_range_auto;
356 enum hdmi_force_audio force_audio;
357 bool rgb_quant_range_selectable;
358 void (*write_infoframe)(struct drm_encoder *encoder,
359 struct dip_infoframe *frame);
360 void (*set_infoframes)(struct drm_encoder *encoder,
361 struct drm_display_mode *adjusted_mode);
364 #define DP_MAX_DOWNSTREAM_PORTS 0x10
365 #define DP_LINK_CONFIGURATION_SIZE 9
369 uint32_t aux_ch_ctl_reg;
371 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
373 enum hdmi_force_audio force_audio;
374 uint32_t color_range;
375 bool color_range_auto;
378 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
379 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
380 struct i2c_adapter adapter;
381 struct i2c_algo_dp_aux_data algo;
383 uint8_t train_set[4];
384 int panel_power_up_delay;
385 int panel_power_down_delay;
386 int panel_power_cycle_delay;
387 int backlight_on_delay;
388 int backlight_off_delay;
389 struct delayed_work panel_vdd_work;
391 struct intel_connector *attached_connector;
394 struct intel_digital_port {
395 struct intel_encoder base;
399 struct intel_hdmi hdmi;
402 static inline struct drm_crtc *
403 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 return dev_priv->pipe_to_crtc_mapping[pipe];
409 static inline struct drm_crtc *
410 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
412 struct drm_i915_private *dev_priv = dev->dev_private;
413 return dev_priv->plane_to_crtc_mapping[plane];
416 struct intel_unpin_work {
417 struct work_struct work;
418 struct drm_crtc *crtc;
419 struct drm_i915_gem_object *old_fb_obj;
420 struct drm_i915_gem_object *pending_flip_obj;
421 struct drm_pending_vblank_event *event;
423 #define INTEL_FLIP_INACTIVE 0
424 #define INTEL_FLIP_PENDING 1
425 #define INTEL_FLIP_COMPLETE 2
426 bool enable_stall_check;
429 struct intel_fbc_work {
430 struct delayed_work work;
431 struct drm_crtc *crtc;
432 struct drm_framebuffer *fb;
436 int intel_pch_rawclk(struct drm_device *dev);
438 int intel_connector_update_modes(struct drm_connector *connector,
440 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
442 extern void intel_attach_force_audio_property(struct drm_connector *connector);
443 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
445 extern void intel_crt_init(struct drm_device *dev);
446 extern void intel_hdmi_init(struct drm_device *dev,
447 int hdmi_reg, enum port port);
448 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
449 struct intel_connector *intel_connector);
450 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
451 extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
452 const struct drm_display_mode *mode,
453 struct drm_display_mode *adjusted_mode);
454 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
455 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
457 extern void intel_dvo_init(struct drm_device *dev);
458 extern void intel_tv_init(struct drm_device *dev);
459 extern void intel_mark_busy(struct drm_device *dev);
460 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
461 extern void intel_mark_idle(struct drm_device *dev);
462 extern bool intel_lvds_init(struct drm_device *dev);
463 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
464 extern void intel_dp_init(struct drm_device *dev, int output_reg,
466 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
467 struct intel_connector *intel_connector);
469 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
470 struct drm_display_mode *adjusted_mode);
471 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
472 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
473 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
474 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
475 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
476 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
477 extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
478 const struct drm_display_mode *mode,
479 struct drm_display_mode *adjusted_mode);
480 extern bool intel_dpd_is_edp(struct drm_device *dev);
481 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
482 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
483 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
484 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
485 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
486 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
487 extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
488 extern int intel_edp_target_clock(struct intel_encoder *,
489 struct drm_display_mode *mode);
490 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
491 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
492 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
496 extern int intel_panel_init(struct intel_panel *panel,
497 struct drm_display_mode *fixed_mode);
498 extern void intel_panel_fini(struct intel_panel *panel);
500 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
501 struct drm_display_mode *adjusted_mode);
502 extern void intel_pch_panel_fitting(struct drm_device *dev,
504 const struct drm_display_mode *mode,
505 struct drm_display_mode *adjusted_mode);
506 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
507 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
508 extern int intel_panel_setup_backlight(struct drm_connector *connector);
509 extern void intel_panel_enable_backlight(struct drm_device *dev,
511 extern void intel_panel_disable_backlight(struct drm_device *dev);
512 extern void intel_panel_destroy_backlight(struct drm_device *dev);
513 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
515 struct intel_set_config {
516 struct drm_encoder **save_connector_encoders;
517 struct drm_crtc **save_encoder_crtcs;
523 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
524 int x, int y, struct drm_framebuffer *old_fb);
525 extern void intel_modeset_disable(struct drm_device *dev);
526 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
527 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
528 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
529 extern void intel_encoder_destroy(struct drm_encoder *encoder);
530 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
531 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
532 extern void intel_connector_dpms(struct drm_connector *, int mode);
533 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
534 extern void intel_modeset_check_state(struct drm_device *dev);
537 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
539 return to_intel_connector(connector)->encoder;
542 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
544 struct intel_digital_port *intel_dig_port =
545 container_of(encoder, struct intel_digital_port, base.base);
546 return &intel_dig_port->dp;
549 static inline struct intel_digital_port *
550 enc_to_dig_port(struct drm_encoder *encoder)
552 return container_of(encoder, struct intel_digital_port, base.base);
555 static inline struct intel_digital_port *
556 dp_to_dig_port(struct intel_dp *intel_dp)
558 return container_of(intel_dp, struct intel_digital_port, dp);
561 static inline struct intel_digital_port *
562 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
564 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
567 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
568 struct intel_digital_port *port);
570 extern void intel_connector_attach_encoder(struct intel_connector *connector,
571 struct intel_encoder *encoder);
572 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
574 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
575 struct drm_crtc *crtc);
576 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
577 struct drm_file *file_priv);
578 extern enum transcoder
579 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
581 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
582 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
583 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
585 struct intel_load_detect_pipe {
586 struct drm_framebuffer *release_fb;
587 bool load_detect_temp;
590 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
591 struct drm_display_mode *mode,
592 struct intel_load_detect_pipe *old);
593 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
594 struct intel_load_detect_pipe *old);
596 extern void intelfb_restore(void);
597 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
598 u16 blue, int regno);
599 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
600 u16 *blue, int regno);
601 extern void intel_enable_clock_gating(struct drm_device *dev);
603 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
604 struct drm_i915_gem_object *obj,
605 struct intel_ring_buffer *pipelined);
606 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
608 extern int intel_framebuffer_init(struct drm_device *dev,
609 struct intel_framebuffer *ifb,
610 struct drm_mode_fb_cmd2 *mode_cmd,
611 struct drm_i915_gem_object *obj);
612 extern int intel_fbdev_init(struct drm_device *dev);
613 extern void intel_fbdev_initial_config(struct drm_device *dev);
614 extern void intel_fbdev_fini(struct drm_device *dev);
615 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
616 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
617 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
618 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
620 extern void intel_setup_overlay(struct drm_device *dev);
621 extern void intel_cleanup_overlay(struct drm_device *dev);
622 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
623 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
625 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
626 struct drm_file *file_priv);
628 extern void intel_fb_output_poll_changed(struct drm_device *dev);
629 extern void intel_fb_restore_mode(struct drm_device *dev);
631 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
633 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
634 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
636 extern void intel_init_clock_gating(struct drm_device *dev);
637 extern void intel_write_eld(struct drm_encoder *encoder,
638 struct drm_display_mode *mode);
639 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
640 extern void intel_prepare_ddi(struct drm_device *dev);
641 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
642 extern void intel_ddi_init(struct drm_device *dev, enum port port);
644 /* For use by IVB LP watermark workaround in intel_sprite.c */
645 extern void intel_update_watermarks(struct drm_device *dev);
646 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
647 uint32_t sprite_width,
649 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
650 struct drm_display_mode *mode);
652 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
653 unsigned int tiling_mode,
657 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
658 struct drm_file *file_priv);
659 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
660 struct drm_file *file_priv);
662 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
664 /* Power-related functions, located in intel_pm.c */
665 extern void intel_init_pm(struct drm_device *dev);
667 extern bool intel_fbc_enabled(struct drm_device *dev);
668 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
669 extern void intel_update_fbc(struct drm_device *dev);
671 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
672 extern void intel_gpu_ips_teardown(void);
674 extern void intel_init_power_well(struct drm_device *dev);
675 extern void intel_set_power_well(struct drm_device *dev, bool enable);
676 extern void intel_enable_gt_powersave(struct drm_device *dev);
677 extern void intel_disable_gt_powersave(struct drm_device *dev);
678 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
679 extern void ironlake_teardown_rc6(struct drm_device *dev);
681 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
683 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
684 extern void intel_ddi_pll_init(struct drm_device *dev);
685 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
686 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
687 enum transcoder cpu_transcoder);
688 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
689 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
690 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
691 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
692 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
693 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
694 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
696 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
697 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
699 extern void intel_display_handle_reset(struct drm_device *dev);
701 #endif /* __INTEL_DRV_H__ */