drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 static int
 113 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 114 {
 115         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 116
 117         switch (max_link_bw) {
 118         case DP_LINK_BW_1_62:
 119         case DP_LINK_BW_2_7:
 120                 break;
 121         default:
 122                 max_link_bw = DP_LINK_BW_1_62;
 123                 break;
 124         }
 125         return max_link_bw;
 126 }
 127
 128 /*
 129  * The units on the numbers in the next two are... bizarre.  Examples will
 130  * make it clearer; this one parallels an example in the eDP spec.
 131  *
 132  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 133  *
 134  *     270000 * 1 * 8 / 10 == 216000
 135  *
 136  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 137  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 138  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 139  * 119000.  At 18bpp that's 2142000 kilobits per second.
 140  *
 141  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 142  * get the result in decakilobits instead of kilobits.
 143  */
 144
 145 static int
 146 intel_dp_link_required(int pixel_clock, int bpp)
 147 {
 148         return (pixel_clock * bpp + 9) / 10;
 149 }
 150
 151 static int
 152 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 153 {
 154         return (max_link_clock * max_lanes * 8) / 10;
 155 }
 156
 157 static int
 158 intel_dp_mode_valid(struct drm_connector *connector,
 159                     struct drm_display_mode *mode)
 160 {
 161         struct intel_dp *intel_dp = intel_attached_dp(connector);
 162         struct intel_connector *intel_connector = to_intel_connector(connector);
 163         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 164         int target_clock = mode->clock;
 165         int max_rate, mode_rate, max_lanes, max_link_clock;
 166
 167         if (is_edp(intel_dp) && fixed_mode) {
 168                 if (mode->hdisplay > fixed_mode->hdisplay)
 169                         return MODE_PANEL;
 170
 171                 if (mode->vdisplay > fixed_mode->vdisplay)
 172                         return MODE_PANEL;
 173
 174                 target_clock = fixed_mode->clock;
 175         }
 176
 177         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 178         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 179
 180         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 181         mode_rate = intel_dp_link_required(target_clock, 18);
 182
 183         if (mode_rate > max_rate)
 184                 return MODE_CLOCK_HIGH;
 185
 186         if (mode->clock < 10000)
 187                 return MODE_CLOCK_LOW;
 188
 189         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 190                 return MODE_H_ILLEGAL;
 191
 192         return MODE_OK;
 193 }
 194
 195 static uint32_t
 196 pack_aux(uint8_t *src, int src_bytes)
 197 {
 198         int     i;
 199         uint32_t v = 0;
 200
 201         if (src_bytes > 4)
 202                 src_bytes = 4;
 203         for (i = 0; i < src_bytes; i++)
 204                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 205         return v;
 206 }
 207
 208 static void
 209 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 210 {
 211         int i;
 212         if (dst_bytes > 4)
 213                 dst_bytes = 4;
 214         for (i = 0; i < dst_bytes; i++)
 215                 dst[i] = src >> ((3-i) * 8);
 216 }
 217
 218 /* hrawclock is 1/4 the FSB frequency */
 219 static int
 220 intel_hrawclk(struct drm_device *dev)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         uint32_t clkcfg;
 224
 225         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 226         if (IS_VALLEYVIEW(dev))
 227                 return 200;
 228
 229         clkcfg = I915_READ(CLKCFG);
 230         switch (clkcfg & CLKCFG_FSB_MASK) {
 231         case CLKCFG_FSB_400:
 232                 return 100;
 233         case CLKCFG_FSB_533:
 234                 return 133;
 235         case CLKCFG_FSB_667:
 236                 return 166;
 237         case CLKCFG_FSB_800:
 238                 return 200;
 239         case CLKCFG_FSB_1067:
 240                 return 266;
 241         case CLKCFG_FSB_1333:
 242                 return 333;
 243         /* these two are just a guess; one of them might be right */
 244         case CLKCFG_FSB_1600:
 245         case CLKCFG_FSB_1600_ALT:
 246                 return 400;
 247         default:
 248                 return 133;
 249         }
 250 }
 251
 252 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 253 {
 254         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         u32 pp_stat_reg;
 257
 258         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 259         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 260 }
 261
 262 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 263 {
 264         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         u32 pp_ctrl_reg;
 267
 268         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 269         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 270 }
 271
 272 static void
 273 intel_dp_check_edp(struct intel_dp *intel_dp)
 274 {
 275         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         u32 pp_stat_reg, pp_ctrl_reg;
 278
 279         if (!is_edp(intel_dp))
 280                 return;
 281
 282         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 283         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 284
 285         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 286                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 287                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 288                                 I915_READ(pp_stat_reg),
 289                                 I915_READ(pp_ctrl_reg));
 290         }
 291 }
 292
 293 static uint32_t
 294 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_device *dev = intel_dig_port->base.base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 300         uint32_t status;
 301         bool done;
 302
 303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 304         if (has_aux_irq)
 305                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 306                                           msecs_to_jiffies_timeout(10));
 307         else
 308                 done = wait_for_atomic(C, 10) == 0;
 309         if (!done)
 310                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 311                           has_aux_irq);
 312 #undef C
 313
 314         return status;
 315 }
 316
 317 static int
 318 intel_dp_aux_ch(struct intel_dp *intel_dp,
 319                 uint8_t *send, int send_bytes,
 320                 uint8_t *recv, int recv_size)
 321 {
 322         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 323         struct drm_device *dev = intel_dig_port->base.base.dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 326         uint32_t ch_data = ch_ctl + 4;
 327         int i, ret, recv_bytes;
 328         uint32_t status;
 329         uint32_t aux_clock_divider;
 330         int try, precharge;
 331         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 332
 333         /* dp aux is extremely sensitive to irq latency, hence request the
 334          * lowest possible wakeup latency and so prevent the cpu from going into
 335          * deep sleep states.
 336          */
 337         pm_qos_update_request(&dev_priv->pm_qos, 0);
 338
 339         intel_dp_check_edp(intel_dp);
 340         /* The clock divider is based off the hrawclk,
 341          * and would like to run at 2MHz. So, take the
 342          * hrawclk value and divide by 2 and use that
 343          *
 344          * Note that PCH attached eDP panels should use a 125MHz input
 345          * clock divider.
 346          */
 347         if (is_cpu_edp(intel_dp)) {
 348                 if (HAS_DDI(dev))
 349                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 350                 else if (IS_VALLEYVIEW(dev))
 351                         aux_clock_divider = 100;
 352                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 353                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 354                 else
 355                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 356         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 357                 /* Workaround for non-ULT HSW */
 358                 aux_clock_divider = 74;
 359         } else if (HAS_PCH_SPLIT(dev)) {
 360                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 361         } else {
 362                 aux_clock_divider = intel_hrawclk(dev) / 2;
 363         }
 364
 365         if (IS_GEN6(dev))
 366                 precharge = 3;
 367         else
 368                 precharge = 5;
 369
 370         /* Try to wait for any previous AUX channel activity */
 371         for (try = 0; try < 3; try++) {
 372                 status = I915_READ_NOTRACE(ch_ctl);
 373                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 374                         break;
 375                 msleep(1);
 376         }
 377
 378         if (try == 3) {
 379                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 380                      I915_READ(ch_ctl));
 381                 ret = -EBUSY;
 382                 goto out;
 383         }
 384
 385         /* Must try at least 3 times according to DP spec */
 386         for (try = 0; try < 5; try++) {
 387                 /* Load the send data into the aux channel data registers */
 388                 for (i = 0; i < send_bytes; i += 4)
 389                         I915_WRITE(ch_data + i,
 390                                    pack_aux(send + i, send_bytes - i));
 391
 392                 /* Send the command and wait for it to complete */
 393                 I915_WRITE(ch_ctl,
 394                            DP_AUX_CH_CTL_SEND_BUSY |
 395                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 396                            DP_AUX_CH_CTL_TIME_OUT_400us |
 397                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 398                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 399                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 400                            DP_AUX_CH_CTL_DONE |
 401                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 402                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 403
 404                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 405
 406                 /* Clear done status and any errors */
 407                 I915_WRITE(ch_ctl,
 408                            status |
 409                            DP_AUX_CH_CTL_DONE |
 410                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 411                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 412
 413                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 414                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 415                         continue;
 416                 if (status & DP_AUX_CH_CTL_DONE)
 417                         break;
 418         }
 419
 420         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 421                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 422                 ret = -EBUSY;
 423                 goto out;
 424         }
 425
 426         /* Check for timeout or receive error.
 427          * Timeouts occur when the sink is not connected
 428          */
 429         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 430                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 431                 ret = -EIO;
 432                 goto out;
 433         }
 434
 435         /* Timeouts occur when the device isn't connected, so they're
 436          * "normal" -- don't fill the kernel log with these */
 437         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 438                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 439                 ret = -ETIMEDOUT;
 440                 goto out;
 441         }
 442
 443         /* Unload any bytes sent back from the other side */
 444         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 445                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 446         if (recv_bytes > recv_size)
 447                 recv_bytes = recv_size;
 448
 449         for (i = 0; i < recv_bytes; i += 4)
 450                 unpack_aux(I915_READ(ch_data + i),
 451                            recv + i, recv_bytes - i);
 452
 453         ret = recv_bytes;
 454 out:
 455         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 456
 457         return ret;
 458 }
 459
 460 /* Write data to the aux channel in native mode */
 461 static int
 462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 463                           uint16_t address, uint8_t *send, int send_bytes)
 464 {
 465         int ret;
 466         uint8_t msg[20];
 467         int msg_bytes;
 468         uint8_t ack;
 469
 470         intel_dp_check_edp(intel_dp);
 471         if (send_bytes > 16)
 472                 return -1;
 473         msg[0] = AUX_NATIVE_WRITE << 4;
 474         msg[1] = address >> 8;
 475         msg[2] = address & 0xff;
 476         msg[3] = send_bytes - 1;
 477         memcpy(&msg[4], send, send_bytes);
 478         msg_bytes = send_bytes + 4;
 479         for (;;) {
 480                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 481                 if (ret < 0)
 482                         return ret;
 483                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 484                         break;
 485                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 486                         udelay(100);
 487                 else
 488                         return -EIO;
 489         }
 490         return send_bytes;
 491 }
 492
 493 /* Write a single byte to the aux channel in native mode */
 494 static int
 495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 496                             uint16_t address, uint8_t byte)
 497 {
 498         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 499 }
 500
 501 /* read bytes from a native aux channel */
 502 static int
 503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 504                          uint16_t address, uint8_t *recv, int recv_bytes)
 505 {
 506         uint8_t msg[4];
 507         int msg_bytes;
 508         uint8_t reply[20];
 509         int reply_bytes;
 510         uint8_t ack;
 511         int ret;
 512
 513         intel_dp_check_edp(intel_dp);
 514         msg[0] = AUX_NATIVE_READ << 4;
 515         msg[1] = address >> 8;
 516         msg[2] = address & 0xff;
 517         msg[3] = recv_bytes - 1;
 518
 519         msg_bytes = 4;
 520         reply_bytes = recv_bytes + 1;
 521
 522         for (;;) {
 523                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 524                                       reply, reply_bytes);
 525                 if (ret == 0)
 526                         return -EPROTO;
 527                 if (ret < 0)
 528                         return ret;
 529                 ack = reply[0];
 530                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 531                         memcpy(recv, reply + 1, ret - 1);
 532                         return ret - 1;
 533                 }
 534                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 535                         udelay(100);
 536                 else
 537                         return -EIO;
 538         }
 539 }
 540
 541 static int
 542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 543                     uint8_t write_byte, uint8_t *read_byte)
 544 {
 545         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 546         struct intel_dp *intel_dp = container_of(adapter,
 547                                                 struct intel_dp,
 548                                                 adapter);
 549         uint16_t address = algo_data->address;
 550         uint8_t msg[5];
 551         uint8_t reply[2];
 552         unsigned retry;
 553         int msg_bytes;
 554         int reply_bytes;
 555         int ret;
 556
 557         intel_dp_check_edp(intel_dp);
 558         /* Set up the command byte */
 559         if (mode & MODE_I2C_READ)
 560                 msg[0] = AUX_I2C_READ << 4;
 561         else
 562                 msg[0] = AUX_I2C_WRITE << 4;
 563
 564         if (!(mode & MODE_I2C_STOP))
 565                 msg[0] |= AUX_I2C_MOT << 4;
 566
 567         msg[1] = address >> 8;
 568         msg[2] = address;
 569
 570         switch (mode) {
 571         case MODE_I2C_WRITE:
 572                 msg[3] = 0;
 573                 msg[4] = write_byte;
 574                 msg_bytes = 5;
 575                 reply_bytes = 1;
 576                 break;
 577         case MODE_I2C_READ:
 578                 msg[3] = 0;
 579                 msg_bytes = 4;
 580                 reply_bytes = 2;
 581                 break;
 582         default:
 583                 msg_bytes = 3;
 584                 reply_bytes = 1;
 585                 break;
 586         }
 587
 588         for (retry = 0; retry < 5; retry++) {
 589                 ret = intel_dp_aux_ch(intel_dp,
 590                                       msg, msg_bytes,
 591                                       reply, reply_bytes);
 592                 if (ret < 0) {
 593                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 594                         return ret;
 595                 }
 596
 597                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 598                 case AUX_NATIVE_REPLY_ACK:
 599                         /* I2C-over-AUX Reply field is only valid
 600                          * when paired with AUX ACK.
 601                          */
 602                         break;
 603                 case AUX_NATIVE_REPLY_NACK:
 604                         DRM_DEBUG_KMS("aux_ch native nack\n");
 605                         return -EREMOTEIO;
 606                 case AUX_NATIVE_REPLY_DEFER:
 607                         /*
 608                          * For now, just give more slack to branch devices. We
 609                          * could check the DPCD for I2C bit rate capabilities,
 610                          * and if available, adjust the interval. We could also
 611                          * be more careful with DP-to-Legacy adapters where a
 612                          * long legacy cable may force very low I2C bit rates.
 613                          */
 614                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 615                             DP_DWN_STRM_PORT_PRESENT)
 616                                 usleep_range(500, 600);
 617                         else
 618                                 usleep_range(300, 400);
 619                         continue;
 620                 default:
 621                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 622                                   reply[0]);
 623                         return -EREMOTEIO;
 624                 }
 625
 626                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 627                 case AUX_I2C_REPLY_ACK:
 628                         if (mode == MODE_I2C_READ) {
 629                                 *read_byte = reply[1];
 630                         }
 631                         return reply_bytes - 1;
 632                 case AUX_I2C_REPLY_NACK:
 633                         DRM_DEBUG_KMS("aux_i2c nack\n");
 634                         return -EREMOTEIO;
 635                 case AUX_I2C_REPLY_DEFER:
 636                         DRM_DEBUG_KMS("aux_i2c defer\n");
 637                         udelay(100);
 638                         break;
 639                 default:
 640                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 641                         return -EREMOTEIO;
 642                 }
 643         }
 644
 645         DRM_ERROR("too many retries, giving up\n");
 646         return -EREMOTEIO;
 647 }
 648
 649 static int
 650 intel_dp_i2c_init(struct intel_dp *intel_dp,
 651                   struct intel_connector *intel_connector, const char *name)
 652 {
 653         int     ret;
 654
 655         DRM_DEBUG_KMS("i2c_init %s\n", name);
 656         intel_dp->algo.running = false;
 657         intel_dp->algo.address = 0;
 658         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 659
 660         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 661         intel_dp->adapter.owner = THIS_MODULE;
 662         intel_dp->adapter.class = I2C_CLASS_DDC;
 663         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 664         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 665         intel_dp->adapter.algo_data = &intel_dp->algo;
 666         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 667
 668         ironlake_edp_panel_vdd_on(intel_dp);
 669         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 670         ironlake_edp_panel_vdd_off(intel_dp, false);
 671         return ret;
 672 }
 673
 674 bool
 675 intel_dp_compute_config(struct intel_encoder *encoder,
 676                         struct intel_crtc_config *pipe_config)
 677 {
 678         struct drm_device *dev = encoder->base.dev;
 679         struct drm_i915_private *dev_priv = dev->dev_private;
 680         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 681         struct drm_display_mode *mode = &pipe_config->requested_mode;
 682         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 683         struct intel_connector *intel_connector = intel_dp->attached_connector;
 684         int lane_count, clock;
 685         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 686         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 687         int bpp, mode_rate;
 688         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 689         int target_clock, link_avail, link_clock;
 690
 691         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 692                 pipe_config->has_pch_encoder = true;
 693
 694         pipe_config->has_dp_encoder = true;
 695
 696         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 697                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 698                                        adjusted_mode);
 699                 intel_pch_panel_fitting(dev,
 700                                         intel_connector->panel.fitting_mode,
 701                                         mode, adjusted_mode);
 702         }
 703         /* We need to take the panel's fixed mode into account. */
 704         target_clock = adjusted_mode->clock;
 705
 706         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 707                 return false;
 708
 709         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 710                       "max bw %02x pixel clock %iKHz\n",
 711                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 712
 713         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 714          * bpc in between. */
 715         bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 716         if (is_edp(intel_dp) && dev_priv->edp.bpp)
 717                 bpp = min_t(int, bpp, dev_priv->edp.bpp);
 718
 719         for (; bpp >= 6*3; bpp -= 2*3) {
 720                 mode_rate = intel_dp_link_required(target_clock, bpp);
 721
 722                 for (clock = 0; clock <= max_clock; clock++) {
 723                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 724                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 725                                 link_avail = intel_dp_max_data_rate(link_clock,
 726                                                                     lane_count);
 727
 728                                 if (mode_rate <= link_avail) {
 729                                         goto found;
 730                                 }
 731                         }
 732                 }
 733         }
 734
 735         return false;
 736
 737 found:
 738         if (intel_dp->color_range_auto) {
 739                 /*
 740                  * See:
 741                  * CEA-861-E - 5.1 Default Encoding Parameters
 742                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 743                  */
 744                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 745                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 746                 else
 747                         intel_dp->color_range = 0;
 748         }
 749
 750         if (intel_dp->color_range)
 751                 pipe_config->limited_color_range = true;
 752
 753         intel_dp->link_bw = bws[clock];
 754         intel_dp->lane_count = lane_count;
 755         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 756         pipe_config->pipe_bpp = bpp;
 757         pipe_config->pixel_target_clock = target_clock;
 758
 759         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 760                       intel_dp->link_bw, intel_dp->lane_count,
 761                       adjusted_mode->clock, bpp);
 762         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 763                       mode_rate, link_avail);
 764
 765         intel_link_compute_m_n(bpp, lane_count,
 766                                target_clock, adjusted_mode->clock,
 767                                &pipe_config->dp_m_n);
 768
 769         return true;
 770 }
 771
 772 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 773 {
 774         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 775         intel_dp->link_configuration[0] = intel_dp->link_bw;
 776         intel_dp->link_configuration[1] = intel_dp->lane_count;
 777         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 778         /*
 779          * Check for DPCD version > 1.1 and enhanced framing support
 780          */
 781         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 782             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 783                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 784         }
 785 }
 786
 787 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 788 {
 789         struct drm_device *dev = crtc->dev;
 790         struct drm_i915_private *dev_priv = dev->dev_private;
 791         u32 dpa_ctl;
 792
 793         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 794         dpa_ctl = I915_READ(DP_A);
 795         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 796
 797         if (clock < 200000) {
 798                 /* For a long time we've carried around a ILK-DevA w/a for the
 799                  * 160MHz clock. If we're really unlucky, it's still required.
 800                  */
 801                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 802                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 803         } else {
 804                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 805         }
 806
 807         I915_WRITE(DP_A, dpa_ctl);
 808
 809         POSTING_READ(DP_A);
 810         udelay(500);
 811 }
 812
 813 static void
 814 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 815                   struct drm_display_mode *adjusted_mode)
 816 {
 817         struct drm_device *dev = encoder->dev;
 818         struct drm_i915_private *dev_priv = dev->dev_private;
 819         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 820         struct drm_crtc *crtc = encoder->crtc;
 821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 822
 823         /*
 824          * There are four kinds of DP registers:
 825          *
 826          *      IBX PCH
 827          *      SNB CPU
 828          *      IVB CPU
 829          *      CPT PCH
 830          *
 831          * IBX PCH and CPU are the same for almost everything,
 832          * except that the CPU DP PLL is configured in this
 833          * register
 834          *
 835          * CPT PCH is quite different, having many bits moved
 836          * to the TRANS_DP_CTL register instead. That
 837          * configuration happens (oddly) in ironlake_pch_enable
 838          */
 839
 840         /* Preserve the BIOS-computed detected bit. This is
 841          * supposed to be read-only.
 842          */
 843         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 844
 845         /* Handle DP bits in common between all three register formats */
 846         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 847
 848         switch (intel_dp->lane_count) {
 849         case 1:
 850                 intel_dp->DP |= DP_PORT_WIDTH_1;
 851                 break;
 852         case 2:
 853                 intel_dp->DP |= DP_PORT_WIDTH_2;
 854                 break;
 855         case 4:
 856                 intel_dp->DP |= DP_PORT_WIDTH_4;
 857                 break;
 858         }
 859         if (intel_dp->has_audio) {
 860                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 861                                  pipe_name(intel_crtc->pipe));
 862                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 863                 intel_write_eld(encoder, adjusted_mode);
 864         }
 865
 866         intel_dp_init_link_config(intel_dp);
 867
 868         /* Split out the IBX/CPU vs CPT settings */
 869
 870         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 871                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 872                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 873                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 874                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 875                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 876
 877                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 878                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 879
 880                 intel_dp->DP |= intel_crtc->pipe << 29;
 881
 882                 /* don't miss out required setting for eDP */
 883                 if (adjusted_mode->clock < 200000)
 884                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 885                 else
 886                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 887         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 888                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 889                         intel_dp->DP |= intel_dp->color_range;
 890
 891                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 892                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 893                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 894                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 895                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 896
 897                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 898                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 899
 900                 if (intel_crtc->pipe == 1)
 901                         intel_dp->DP |= DP_PIPEB_SELECT;
 902
 903                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 904                         /* don't miss out required setting for eDP */
 905                         if (adjusted_mode->clock < 200000)
 906                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 907                         else
 908                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 909                 }
 910         } else {
 911                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 912         }
 913
 914         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 915                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 916 }
 917
 918 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 919 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 920
 921 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 922 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 923
 924 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 925 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 926
 927 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 928                                        u32 mask,
 929                                        u32 value)
 930 {
 931         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 pp_stat_reg, pp_ctrl_reg;
 934
 935         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 936         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 937
 938         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 939                         mask, value,
 940                         I915_READ(pp_stat_reg),
 941                         I915_READ(pp_ctrl_reg));
 942
 943         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 944                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 945                                 I915_READ(pp_stat_reg),
 946                                 I915_READ(pp_ctrl_reg));
 947         }
 948 }
 949
 950 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 951 {
 952         DRM_DEBUG_KMS("Wait for panel power on\n");
 953         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 954 }
 955
 956 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 957 {
 958         DRM_DEBUG_KMS("Wait for panel power off time\n");
 959         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 960 }
 961
 962 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 963 {
 964         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 965         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 966 }
 967
 968
 969 /* Read the current pp_control value, unlocking the register if it
 970  * is locked
 971  */
 972
 973 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 974 {
 975         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 976         struct drm_i915_private *dev_priv = dev->dev_private;
 977         u32 control;
 978         u32 pp_ctrl_reg;
 979
 980         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 981         control = I915_READ(pp_ctrl_reg);
 982
 983         control &= ~PANEL_UNLOCK_MASK;
 984         control |= PANEL_UNLOCK_REGS;
 985         return control;
 986 }
 987
 988 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 989 {
 990         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         u32 pp;
 993         u32 pp_stat_reg, pp_ctrl_reg;
 994
 995         if (!is_edp(intel_dp))
 996                 return;
 997         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 998
 999         WARN(intel_dp->want_panel_vdd,
1000              "eDP VDD already requested on\n");
1001
1002         intel_dp->want_panel_vdd = true;
1003
1004         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1005                 DRM_DEBUG_KMS("eDP VDD already on\n");
1006                 return;
1007         }
1008
1009         if (!ironlake_edp_have_panel_power(intel_dp))
1010                 ironlake_wait_panel_power_cycle(intel_dp);
1011
1012         pp = ironlake_get_pp_control(intel_dp);
1013         pp |= EDP_FORCE_VDD;
1014
1015         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1016         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1017
1018         I915_WRITE(pp_ctrl_reg, pp);
1019         POSTING_READ(pp_ctrl_reg);
1020         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1021                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1022         /*
1023          * If the panel wasn't on, delay before accessing aux channel
1024          */
1025         if (!ironlake_edp_have_panel_power(intel_dp)) {
1026                 DRM_DEBUG_KMS("eDP was not running\n");
1027                 msleep(intel_dp->panel_power_up_delay);
1028         }
1029 }
1030
1031 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1032 {
1033         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         u32 pp;
1036         u32 pp_stat_reg, pp_ctrl_reg;
1037
1038         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1039
1040         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1041                 pp = ironlake_get_pp_control(intel_dp);
1042                 pp &= ~EDP_FORCE_VDD;
1043
1044                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1045                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1046
1047                 I915_WRITE(pp_ctrl_reg, pp);
1048                 POSTING_READ(pp_ctrl_reg);
1049
1050                 /* Make sure sequencer is idle before allowing subsequent activity */
1051                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1052                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1053                 msleep(intel_dp->panel_power_down_delay);
1054         }
1055 }
1056
1057 static void ironlake_panel_vdd_work(struct work_struct *__work)
1058 {
1059         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1060                                                  struct intel_dp, panel_vdd_work);
1061         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062
1063         mutex_lock(&dev->mode_config.mutex);
1064         ironlake_panel_vdd_off_sync(intel_dp);
1065         mutex_unlock(&dev->mode_config.mutex);
1066 }
1067
1068 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1069 {
1070         if (!is_edp(intel_dp))
1071                 return;
1072
1073         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1074         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1075
1076         intel_dp->want_panel_vdd = false;
1077
1078         if (sync) {
1079                 ironlake_panel_vdd_off_sync(intel_dp);
1080         } else {
1081                 /*
1082                  * Queue the timer to fire a long
1083                  * time from now (relative to the power down delay)
1084                  * to keep the panel power up across a sequence of operations
1085                  */
1086                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1087                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1088         }
1089 }
1090
1091 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1092 {
1093         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         u32 pp;
1096         u32 pp_ctrl_reg;
1097
1098         if (!is_edp(intel_dp))
1099                 return;
1100
1101         DRM_DEBUG_KMS("Turn eDP power on\n");
1102
1103         if (ironlake_edp_have_panel_power(intel_dp)) {
1104                 DRM_DEBUG_KMS("eDP power already on\n");
1105                 return;
1106         }
1107
1108         ironlake_wait_panel_power_cycle(intel_dp);
1109
1110         pp = ironlake_get_pp_control(intel_dp);
1111         if (IS_GEN5(dev)) {
1112                 /* ILK workaround: disable reset around power sequence */
1113                 pp &= ~PANEL_POWER_RESET;
1114                 I915_WRITE(PCH_PP_CONTROL, pp);
1115                 POSTING_READ(PCH_PP_CONTROL);
1116         }
1117
1118         pp |= POWER_TARGET_ON;
1119         if (!IS_GEN5(dev))
1120                 pp |= PANEL_POWER_RESET;
1121
1122         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1123
1124         I915_WRITE(pp_ctrl_reg, pp);
1125         POSTING_READ(pp_ctrl_reg);
1126
1127         ironlake_wait_panel_on(intel_dp);
1128
1129         if (IS_GEN5(dev)) {
1130                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1131                 I915_WRITE(PCH_PP_CONTROL, pp);
1132                 POSTING_READ(PCH_PP_CONTROL);
1133         }
1134 }
1135
1136 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1137 {
1138         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1139         struct drm_i915_private *dev_priv = dev->dev_private;
1140         u32 pp;
1141         u32 pp_ctrl_reg;
1142
1143         if (!is_edp(intel_dp))
1144                 return;
1145
1146         DRM_DEBUG_KMS("Turn eDP power off\n");
1147
1148         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1149
1150         pp = ironlake_get_pp_control(intel_dp);
1151         /* We need to switch off panel power _and_ force vdd, for otherwise some
1152          * panels get very unhappy and cease to work. */
1153         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1154
1155         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1156
1157         I915_WRITE(pp_ctrl_reg, pp);
1158         POSTING_READ(pp_ctrl_reg);
1159
1160         intel_dp->want_panel_vdd = false;
1161
1162         ironlake_wait_panel_off(intel_dp);
1163 }
1164
1165 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1166 {
1167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1168         struct drm_device *dev = intel_dig_port->base.base.dev;
1169         struct drm_i915_private *dev_priv = dev->dev_private;
1170         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1171         u32 pp;
1172         u32 pp_ctrl_reg;
1173
1174         if (!is_edp(intel_dp))
1175                 return;
1176
1177         DRM_DEBUG_KMS("\n");
1178         /*
1179          * If we enable the backlight right away following a panel power
1180          * on, we may see slight flicker as the panel syncs with the eDP
1181          * link.  So delay a bit to make sure the image is solid before
1182          * allowing it to appear.
1183          */
1184         msleep(intel_dp->backlight_on_delay);
1185         pp = ironlake_get_pp_control(intel_dp);
1186         pp |= EDP_BLC_ENABLE;
1187
1188         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1189
1190         I915_WRITE(pp_ctrl_reg, pp);
1191         POSTING_READ(pp_ctrl_reg);
1192
1193         intel_panel_enable_backlight(dev, pipe);
1194 }
1195
1196 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1197 {
1198         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         u32 pp;
1201         u32 pp_ctrl_reg;
1202
1203         if (!is_edp(intel_dp))
1204                 return;
1205
1206         intel_panel_disable_backlight(dev);
1207
1208         DRM_DEBUG_KMS("\n");
1209         pp = ironlake_get_pp_control(intel_dp);
1210         pp &= ~EDP_BLC_ENABLE;
1211
1212         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1213
1214         I915_WRITE(pp_ctrl_reg, pp);
1215         POSTING_READ(pp_ctrl_reg);
1216         msleep(intel_dp->backlight_off_delay);
1217 }
1218
1219 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1220 {
1221         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1222         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1223         struct drm_device *dev = crtc->dev;
1224         struct drm_i915_private *dev_priv = dev->dev_private;
1225         u32 dpa_ctl;
1226
1227         assert_pipe_disabled(dev_priv,
1228                              to_intel_crtc(crtc)->pipe);
1229
1230         DRM_DEBUG_KMS("\n");
1231         dpa_ctl = I915_READ(DP_A);
1232         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1233         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1234
1235         /* We don't adjust intel_dp->DP while tearing down the link, to
1236          * facilitate link retraining (e.g. after hotplug). Hence clear all
1237          * enable bits here to ensure that we don't enable too much. */
1238         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1239         intel_dp->DP |= DP_PLL_ENABLE;
1240         I915_WRITE(DP_A, intel_dp->DP);
1241         POSTING_READ(DP_A);
1242         udelay(200);
1243 }
1244
1245 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1246 {
1247         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1248         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1249         struct drm_device *dev = crtc->dev;
1250         struct drm_i915_private *dev_priv = dev->dev_private;
1251         u32 dpa_ctl;
1252
1253         assert_pipe_disabled(dev_priv,
1254                              to_intel_crtc(crtc)->pipe);
1255
1256         dpa_ctl = I915_READ(DP_A);
1257         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1258              "dp pll off, should be on\n");
1259         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1260
1261         /* We can't rely on the value tracked for the DP register in
1262          * intel_dp->DP because link_down must not change that (otherwise link
1263          * re-training will fail. */
1264         dpa_ctl &= ~DP_PLL_ENABLE;
1265         I915_WRITE(DP_A, dpa_ctl);
1266         POSTING_READ(DP_A);
1267         udelay(200);
1268 }
1269
1270 /* If the sink supports it, try to set the power state appropriately */
1271 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1272 {
1273         int ret, i;
1274
1275         /* Should have a valid DPCD by this point */
1276         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1277                 return;
1278
1279         if (mode != DRM_MODE_DPMS_ON) {
1280                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1281                                                   DP_SET_POWER_D3);
1282                 if (ret != 1)
1283                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1284         } else {
1285                 /*
1286                  * When turning on, we need to retry for 1ms to give the sink
1287                  * time to wake up.
1288                  */
1289                 for (i = 0; i < 3; i++) {
1290                         ret = intel_dp_aux_native_write_1(intel_dp,
1291                                                           DP_SET_POWER,
1292                                                           DP_SET_POWER_D0);
1293                         if (ret == 1)
1294                                 break;
1295                         msleep(1);
1296                 }
1297         }
1298 }
1299
1300 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1301                                   enum pipe *pipe)
1302 {
1303         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1304         struct drm_device *dev = encoder->base.dev;
1305         struct drm_i915_private *dev_priv = dev->dev_private;
1306         u32 tmp = I915_READ(intel_dp->output_reg);
1307
1308         if (!(tmp & DP_PORT_EN))
1309                 return false;
1310
1311         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1312                 *pipe = PORT_TO_PIPE_CPT(tmp);
1313         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1314                 *pipe = PORT_TO_PIPE(tmp);
1315         } else {
1316                 u32 trans_sel;
1317                 u32 trans_dp;
1318                 int i;
1319
1320                 switch (intel_dp->output_reg) {
1321                 case PCH_DP_B:
1322                         trans_sel = TRANS_DP_PORT_SEL_B;
1323                         break;
1324                 case PCH_DP_C:
1325                         trans_sel = TRANS_DP_PORT_SEL_C;
1326                         break;
1327                 case PCH_DP_D:
1328                         trans_sel = TRANS_DP_PORT_SEL_D;
1329                         break;
1330                 default:
1331                         return true;
1332                 }
1333
1334                 for_each_pipe(i) {
1335                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1336                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1337                                 *pipe = i;
1338                                 return true;
1339                         }
1340                 }
1341
1342                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1343                               intel_dp->output_reg);
1344         }
1345
1346         return true;
1347 }
1348
1349 static void intel_disable_dp(struct intel_encoder *encoder)
1350 {
1351         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1352
1353         /* Make sure the panel is off before trying to change the mode. But also
1354          * ensure that we have vdd while we switch off the panel. */
1355         ironlake_edp_panel_vdd_on(intel_dp);
1356         ironlake_edp_backlight_off(intel_dp);
1357         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1358         ironlake_edp_panel_off(intel_dp);
1359
1360         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1361         if (!is_cpu_edp(intel_dp))
1362                 intel_dp_link_down(intel_dp);
1363 }
1364
1365 static void intel_post_disable_dp(struct intel_encoder *encoder)
1366 {
1367         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1368         struct drm_device *dev = encoder->base.dev;
1369
1370         if (is_cpu_edp(intel_dp)) {
1371                 intel_dp_link_down(intel_dp);
1372                 if (!IS_VALLEYVIEW(dev))
1373                         ironlake_edp_pll_off(intel_dp);
1374         }
1375 }
1376
1377 static void intel_enable_dp(struct intel_encoder *encoder)
1378 {
1379         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1380         struct drm_device *dev = encoder->base.dev;
1381         struct drm_i915_private *dev_priv = dev->dev_private;
1382         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1383
1384         if (WARN_ON(dp_reg & DP_PORT_EN))
1385                 return;
1386
1387         ironlake_edp_panel_vdd_on(intel_dp);
1388         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1389         intel_dp_start_link_train(intel_dp);
1390         ironlake_edp_panel_on(intel_dp);
1391         ironlake_edp_panel_vdd_off(intel_dp, true);
1392         intel_dp_complete_link_train(intel_dp);
1393         intel_dp_stop_link_train(intel_dp);
1394         ironlake_edp_backlight_on(intel_dp);
1395 }
1396
1397 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1398 {
1399         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1400         struct drm_device *dev = encoder->base.dev;
1401
1402         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1403                 ironlake_edp_pll_on(intel_dp);
1404 }
1405
1406 /*
1407  * Native read with retry for link status and receiver capability reads for
1408  * cases where the sink may still be asleep.
1409  */
1410 static bool
1411 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1412                                uint8_t *recv, int recv_bytes)
1413 {
1414         int ret, i;
1415
1416         /*
1417          * Sinks are *supposed* to come up within 1ms from an off state,
1418          * but we're also supposed to retry 3 times per the spec.
1419          */
1420         for (i = 0; i < 3; i++) {
1421                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1422                                                recv_bytes);
1423                 if (ret == recv_bytes)
1424                         return true;
1425                 msleep(1);
1426         }
1427
1428         return false;
1429 }
1430
1431 /*
1432  * Fetch AUX CH registers 0x202 - 0x207 which contain
1433  * link status information
1434  */
1435 static bool
1436 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1437 {
1438         return intel_dp_aux_native_read_retry(intel_dp,
1439                                               DP_LANE0_1_STATUS,
1440                                               link_status,
1441                                               DP_LINK_STATUS_SIZE);
1442 }
1443
1444 #if 0
1445 static char     *voltage_names[] = {
1446         "0.4V", "0.6V", "0.8V", "1.2V"
1447 };
1448 static char     *pre_emph_names[] = {
1449         "0dB", "3.5dB", "6dB", "9.5dB"
1450 };
1451 static char     *link_train_names[] = {
1452         "pattern 1", "pattern 2", "idle", "off"
1453 };
1454 #endif
1455
1456 /*
1457  * These are source-specific values; current Intel hardware supports
1458  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1459  */
1460
1461 static uint8_t
1462 intel_dp_voltage_max(struct intel_dp *intel_dp)
1463 {
1464         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1465
1466         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1467                 return DP_TRAIN_VOLTAGE_SWING_800;
1468         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1469                 return DP_TRAIN_VOLTAGE_SWING_1200;
1470         else
1471                 return DP_TRAIN_VOLTAGE_SWING_800;
1472 }
1473
1474 static uint8_t
1475 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1476 {
1477         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1478
1479         if (HAS_DDI(dev)) {
1480                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1481                 case DP_TRAIN_VOLTAGE_SWING_400:
1482                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1483                 case DP_TRAIN_VOLTAGE_SWING_600:
1484                         return DP_TRAIN_PRE_EMPHASIS_6;
1485                 case DP_TRAIN_VOLTAGE_SWING_800:
1486                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1487                 case DP_TRAIN_VOLTAGE_SWING_1200:
1488                 default:
1489                         return DP_TRAIN_PRE_EMPHASIS_0;
1490                 }
1491         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1492                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1493                 case DP_TRAIN_VOLTAGE_SWING_400:
1494                         return DP_TRAIN_PRE_EMPHASIS_6;
1495                 case DP_TRAIN_VOLTAGE_SWING_600:
1496                 case DP_TRAIN_VOLTAGE_SWING_800:
1497                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1498                 default:
1499                         return DP_TRAIN_PRE_EMPHASIS_0;
1500                 }
1501         } else {
1502                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1503                 case DP_TRAIN_VOLTAGE_SWING_400:
1504                         return DP_TRAIN_PRE_EMPHASIS_6;
1505                 case DP_TRAIN_VOLTAGE_SWING_600:
1506                         return DP_TRAIN_PRE_EMPHASIS_6;
1507                 case DP_TRAIN_VOLTAGE_SWING_800:
1508                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1509                 case DP_TRAIN_VOLTAGE_SWING_1200:
1510                 default:
1511                         return DP_TRAIN_PRE_EMPHASIS_0;
1512                 }
1513         }
1514 }
1515
1516 static void
1517 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1518 {
1519         uint8_t v = 0;
1520         uint8_t p = 0;
1521         int lane;
1522         uint8_t voltage_max;
1523         uint8_t preemph_max;
1524
1525         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1526                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1527                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1528
1529                 if (this_v > v)
1530                         v = this_v;
1531                 if (this_p > p)
1532                         p = this_p;
1533         }
1534
1535         voltage_max = intel_dp_voltage_max(intel_dp);
1536         if (v >= voltage_max)
1537                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1538
1539         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1540         if (p >= preemph_max)
1541                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1542
1543         for (lane = 0; lane < 4; lane++)
1544                 intel_dp->train_set[lane] = v | p;
1545 }
1546
1547 static uint32_t
1548 intel_gen4_signal_levels(uint8_t train_set)
1549 {
1550         uint32_t        signal_levels = 0;
1551
1552         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1553         case DP_TRAIN_VOLTAGE_SWING_400:
1554         default:
1555                 signal_levels |= DP_VOLTAGE_0_4;
1556                 break;
1557         case DP_TRAIN_VOLTAGE_SWING_600:
1558                 signal_levels |= DP_VOLTAGE_0_6;
1559                 break;
1560         case DP_TRAIN_VOLTAGE_SWING_800:
1561                 signal_levels |= DP_VOLTAGE_0_8;
1562                 break;
1563         case DP_TRAIN_VOLTAGE_SWING_1200:
1564                 signal_levels |= DP_VOLTAGE_1_2;
1565                 break;
1566         }
1567         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1568         case DP_TRAIN_PRE_EMPHASIS_0:
1569         default:
1570                 signal_levels |= DP_PRE_EMPHASIS_0;
1571                 break;
1572         case DP_TRAIN_PRE_EMPHASIS_3_5:
1573                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1574                 break;
1575         case DP_TRAIN_PRE_EMPHASIS_6:
1576                 signal_levels |= DP_PRE_EMPHASIS_6;
1577                 break;
1578         case DP_TRAIN_PRE_EMPHASIS_9_5:
1579                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1580                 break;
1581         }
1582         return signal_levels;
1583 }
1584
1585 /* Gen6's DP voltage swing and pre-emphasis control */
1586 static uint32_t
1587 intel_gen6_edp_signal_levels(uint8_t train_set)
1588 {
1589         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1590                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1591         switch (signal_levels) {
1592         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1593         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1594                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1595         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1596                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1597         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1598         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1599                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1600         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1601         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1602                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1603         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1604         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1605                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1606         default:
1607                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1608                               "0x%x\n", signal_levels);
1609                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1610         }
1611 }
1612
1613 /* Gen7's DP voltage swing and pre-emphasis control */
1614 static uint32_t
1615 intel_gen7_edp_signal_levels(uint8_t train_set)
1616 {
1617         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1618                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1619         switch (signal_levels) {
1620         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1621                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1622         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1623                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1624         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1625                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1626
1627         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1628                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1629         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1630                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1631
1632         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1633                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1634         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1635                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1636
1637         default:
1638                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1639                               "0x%x\n", signal_levels);
1640                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1641         }
1642 }
1643
1644 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1645 static uint32_t
1646 intel_hsw_signal_levels(uint8_t train_set)
1647 {
1648         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1649                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1650         switch (signal_levels) {
1651         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1652                 return DDI_BUF_EMP_400MV_0DB_HSW;
1653         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1654                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1655         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1656                 return DDI_BUF_EMP_400MV_6DB_HSW;
1657         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1658                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1659
1660         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1661                 return DDI_BUF_EMP_600MV_0DB_HSW;
1662         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1663                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1664         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1665                 return DDI_BUF_EMP_600MV_6DB_HSW;
1666
1667         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1668                 return DDI_BUF_EMP_800MV_0DB_HSW;
1669         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1670                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1671         default:
1672                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1673                               "0x%x\n", signal_levels);
1674                 return DDI_BUF_EMP_400MV_0DB_HSW;
1675         }
1676 }
1677
1678 /* Properly updates "DP" with the correct signal levels. */
1679 static void
1680 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1681 {
1682         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1683         struct drm_device *dev = intel_dig_port->base.base.dev;
1684         uint32_t signal_levels, mask;
1685         uint8_t train_set = intel_dp->train_set[0];
1686
1687         if (HAS_DDI(dev)) {
1688                 signal_levels = intel_hsw_signal_levels(train_set);
1689                 mask = DDI_BUF_EMP_MASK;
1690         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1691                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1692                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1693         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1694                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1695                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1696         } else {
1697                 signal_levels = intel_gen4_signal_levels(train_set);
1698                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1699         }
1700
1701         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1702
1703         *DP = (*DP & ~mask) | signal_levels;
1704 }
1705
1706 static bool
1707 intel_dp_set_link_train(struct intel_dp *intel_dp,
1708                         uint32_t dp_reg_value,
1709                         uint8_t dp_train_pat)
1710 {
1711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1712         struct drm_device *dev = intel_dig_port->base.base.dev;
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         enum port port = intel_dig_port->port;
1715         int ret;
1716
1717         if (HAS_DDI(dev)) {
1718                 uint32_t temp = I915_READ(DP_TP_CTL(port));
1719
1720                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1721                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1722                 else
1723                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1724
1725                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1726                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1727                 case DP_TRAINING_PATTERN_DISABLE:
1728                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1729
1730                         break;
1731                 case DP_TRAINING_PATTERN_1:
1732                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1733                         break;
1734                 case DP_TRAINING_PATTERN_2:
1735                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1736                         break;
1737                 case DP_TRAINING_PATTERN_3:
1738                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1739                         break;
1740                 }
1741                 I915_WRITE(DP_TP_CTL(port), temp);
1742
1743         } else if (HAS_PCH_CPT(dev) &&
1744                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1745                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1746
1747                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1748                 case DP_TRAINING_PATTERN_DISABLE:
1749                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1750                         break;
1751                 case DP_TRAINING_PATTERN_1:
1752                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1753                         break;
1754                 case DP_TRAINING_PATTERN_2:
1755                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1756                         break;
1757                 case DP_TRAINING_PATTERN_3:
1758                         DRM_ERROR("DP training pattern 3 not supported\n");
1759                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1760                         break;
1761                 }
1762
1763         } else {
1764                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1765
1766                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1767                 case DP_TRAINING_PATTERN_DISABLE:
1768                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1769                         break;
1770                 case DP_TRAINING_PATTERN_1:
1771                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1772                         break;
1773                 case DP_TRAINING_PATTERN_2:
1774                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1775                         break;
1776                 case DP_TRAINING_PATTERN_3:
1777                         DRM_ERROR("DP training pattern 3 not supported\n");
1778                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1779                         break;
1780                 }
1781         }
1782
1783         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1784         POSTING_READ(intel_dp->output_reg);
1785
1786         intel_dp_aux_native_write_1(intel_dp,
1787                                     DP_TRAINING_PATTERN_SET,
1788                                     dp_train_pat);
1789
1790         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1791             DP_TRAINING_PATTERN_DISABLE) {
1792                 ret = intel_dp_aux_native_write(intel_dp,
1793                                                 DP_TRAINING_LANE0_SET,
1794                                                 intel_dp->train_set,
1795                                                 intel_dp->lane_count);
1796                 if (ret != intel_dp->lane_count)
1797                         return false;
1798         }
1799
1800         return true;
1801 }
1802
1803 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1804 {
1805         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1806         struct drm_device *dev = intel_dig_port->base.base.dev;
1807         struct drm_i915_private *dev_priv = dev->dev_private;
1808         enum port port = intel_dig_port->port;
1809         uint32_t val;
1810
1811         if (!HAS_DDI(dev))
1812                 return;
1813
1814         val = I915_READ(DP_TP_CTL(port));
1815         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1816         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1817         I915_WRITE(DP_TP_CTL(port), val);
1818
1819         /*
1820          * On PORT_A we can have only eDP in SST mode. There the only reason
1821          * we need to set idle transmission mode is to work around a HW issue
1822          * where we enable the pipe while not in idle link-training mode.
1823          * In this case there is requirement to wait for a minimum number of
1824          * idle patterns to be sent.
1825          */
1826         if (port == PORT_A)
1827                 return;
1828
1829         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
1830                      1))
1831                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1832 }
1833
1834 /* Enable corresponding port and start training pattern 1 */
1835 void
1836 intel_dp_start_link_train(struct intel_dp *intel_dp)
1837 {
1838         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1839         struct drm_device *dev = encoder->dev;
1840         int i;
1841         uint8_t voltage;
1842         bool clock_recovery = false;
1843         int voltage_tries, loop_tries;
1844         uint32_t DP = intel_dp->DP;
1845
1846         if (HAS_DDI(dev))
1847                 intel_ddi_prepare_link_retrain(encoder);
1848
1849         /* Write the link configuration data */
1850         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1851                                   intel_dp->link_configuration,
1852                                   DP_LINK_CONFIGURATION_SIZE);
1853
1854         DP |= DP_PORT_EN;
1855
1856         memset(intel_dp->train_set, 0, 4);
1857         voltage = 0xff;
1858         voltage_tries = 0;
1859         loop_tries = 0;
1860         clock_recovery = false;
1861         for (;;) {
1862                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1863                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1864
1865                 intel_dp_set_signal_levels(intel_dp, &DP);
1866
1867                 /* Set training pattern 1 */
1868                 if (!intel_dp_set_link_train(intel_dp, DP,
1869                                              DP_TRAINING_PATTERN_1 |
1870                                              DP_LINK_SCRAMBLING_DISABLE))
1871                         break;
1872
1873                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1874                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1875                         DRM_ERROR("failed to get link status\n");
1876                         break;
1877                 }
1878
1879                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1880                         DRM_DEBUG_KMS("clock recovery OK\n");
1881                         clock_recovery = true;
1882                         break;
1883                 }
1884
1885                 /* Check to see if we've tried the max voltage */
1886                 for (i = 0; i < intel_dp->lane_count; i++)
1887                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1888                                 break;
1889                 if (i == intel_dp->lane_count) {
1890                         ++loop_tries;
1891                         if (loop_tries == 5) {
1892                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1893                                 break;
1894                         }
1895                         memset(intel_dp->train_set, 0, 4);
1896                         voltage_tries = 0;
1897                         continue;
1898                 }
1899
1900                 /* Check to see if we've tried the same voltage 5 times */
1901                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1902                         ++voltage_tries;
1903                         if (voltage_tries == 5) {
1904                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1905                                 break;
1906                         }
1907                 } else
1908                         voltage_tries = 0;
1909                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1910
1911                 /* Compute new intel_dp->train_set as requested by target */
1912                 intel_get_adjust_train(intel_dp, link_status);
1913         }
1914
1915         intel_dp->DP = DP;
1916 }
1917
1918 void
1919 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1920 {
1921         bool channel_eq = false;
1922         int tries, cr_tries;
1923         uint32_t DP = intel_dp->DP;
1924
1925         /* channel equalization */
1926         tries = 0;
1927         cr_tries = 0;
1928         channel_eq = false;
1929         for (;;) {
1930                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1931
1932                 if (cr_tries > 5) {
1933                         DRM_ERROR("failed to train DP, aborting\n");
1934                         intel_dp_link_down(intel_dp);
1935                         break;
1936                 }
1937
1938                 intel_dp_set_signal_levels(intel_dp, &DP);
1939
1940                 /* channel eq pattern */
1941                 if (!intel_dp_set_link_train(intel_dp, DP,
1942                                              DP_TRAINING_PATTERN_2 |
1943                                              DP_LINK_SCRAMBLING_DISABLE))
1944                         break;
1945
1946                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1947                 if (!intel_dp_get_link_status(intel_dp, link_status))
1948                         break;
1949
1950                 /* Make sure clock is still ok */
1951                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1952                         intel_dp_start_link_train(intel_dp);
1953                         cr_tries++;
1954                         continue;
1955                 }
1956
1957                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1958                         channel_eq = true;
1959                         break;
1960                 }
1961
1962                 /* Try 5 times, then try clock recovery if that fails */
1963                 if (tries > 5) {
1964                         intel_dp_link_down(intel_dp);
1965                         intel_dp_start_link_train(intel_dp);
1966                         tries = 0;
1967                         cr_tries++;
1968                         continue;
1969                 }
1970
1971                 /* Compute new intel_dp->train_set as requested by target */
1972                 intel_get_adjust_train(intel_dp, link_status);
1973                 ++tries;
1974         }
1975
1976         intel_dp_set_idle_link_train(intel_dp);
1977
1978         intel_dp->DP = DP;
1979
1980         if (channel_eq)
1981                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
1982
1983 }
1984
1985 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
1986 {
1987         intel_dp_set_link_train(intel_dp, intel_dp->DP,
1988                                 DP_TRAINING_PATTERN_DISABLE);
1989 }
1990
1991 static void
1992 intel_dp_link_down(struct intel_dp *intel_dp)
1993 {
1994         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1995         struct drm_device *dev = intel_dig_port->base.base.dev;
1996         struct drm_i915_private *dev_priv = dev->dev_private;
1997         struct intel_crtc *intel_crtc =
1998                 to_intel_crtc(intel_dig_port->base.base.crtc);
1999         uint32_t DP = intel_dp->DP;
2000
2001         /*
2002          * DDI code has a strict mode set sequence and we should try to respect
2003          * it, otherwise we might hang the machine in many different ways. So we
2004          * really should be disabling the port only on a complete crtc_disable
2005          * sequence. This function is just called under two conditions on DDI
2006          * code:
2007          * - Link train failed while doing crtc_enable, and on this case we
2008          *   really should respect the mode set sequence and wait for a
2009          *   crtc_disable.
2010          * - Someone turned the monitor off and intel_dp_check_link_status
2011          *   called us. We don't need to disable the whole port on this case, so
2012          *   when someone turns the monitor on again,
2013          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2014          *   train.
2015          */
2016         if (HAS_DDI(dev))
2017                 return;
2018
2019         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2020                 return;
2021
2022         DRM_DEBUG_KMS("\n");
2023
2024         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2025                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2026                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2027         } else {
2028                 DP &= ~DP_LINK_TRAIN_MASK;
2029                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2030         }
2031         POSTING_READ(intel_dp->output_reg);
2032
2033         /* We don't really know why we're doing this */
2034         intel_wait_for_vblank(dev, intel_crtc->pipe);
2035
2036         if (HAS_PCH_IBX(dev) &&
2037             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2038                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2039
2040                 /* Hardware workaround: leaving our transcoder select
2041                  * set to transcoder B while it's off will prevent the
2042                  * corresponding HDMI output on transcoder A.
2043                  *
2044                  * Combine this with another hardware workaround:
2045                  * transcoder select bit can only be cleared while the
2046                  * port is enabled.
2047                  */
2048                 DP &= ~DP_PIPEB_SELECT;
2049                 I915_WRITE(intel_dp->output_reg, DP);
2050
2051                 /* Changes to enable or select take place the vblank
2052                  * after being written.
2053                  */
2054                 if (WARN_ON(crtc == NULL)) {
2055                         /* We should never try to disable a port without a crtc
2056                          * attached. For paranoia keep the code around for a
2057                          * bit. */
2058                         POSTING_READ(intel_dp->output_reg);
2059                         msleep(50);
2060                 } else
2061                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2062         }
2063
2064         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2065         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2066         POSTING_READ(intel_dp->output_reg);
2067         msleep(intel_dp->panel_power_down_delay);
2068 }
2069
2070 static bool
2071 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2072 {
2073         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2074
2075         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2076                                            sizeof(intel_dp->dpcd)) == 0)
2077                 return false; /* aux transfer failed */
2078
2079         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2080                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2081         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2082
2083         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2084                 return false; /* DPCD not present */
2085
2086         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2087               DP_DWN_STRM_PORT_PRESENT))
2088                 return true; /* native DP sink */
2089
2090         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2091                 return true; /* no per-port downstream info */
2092
2093         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2094                                            intel_dp->downstream_ports,
2095                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2096                 return false; /* downstream port status fetch failed */
2097
2098         return true;
2099 }
2100
2101 static void
2102 intel_dp_probe_oui(struct intel_dp *intel_dp)
2103 {
2104         u8 buf[3];
2105
2106         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2107                 return;
2108
2109         ironlake_edp_panel_vdd_on(intel_dp);
2110
2111         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2112                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2113                               buf[0], buf[1], buf[2]);
2114
2115         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2116                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2117                               buf[0], buf[1], buf[2]);
2118
2119         ironlake_edp_panel_vdd_off(intel_dp, false);
2120 }
2121
2122 static bool
2123 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2124 {
2125         int ret;
2126
2127         ret = intel_dp_aux_native_read_retry(intel_dp,
2128                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2129                                              sink_irq_vector, 1);
2130         if (!ret)
2131                 return false;
2132
2133         return true;
2134 }
2135
2136 static void
2137 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2138 {
2139         /* NAK by default */
2140         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2141 }
2142
2143 /*
2144  * According to DP spec
2145  * 5.1.2:
2146  *  1. Read DPCD
2147  *  2. Configure link according to Receiver Capabilities
2148  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2149  *  4. Check link status on receipt of hot-plug interrupt
2150  */
2151
2152 void
2153 intel_dp_check_link_status(struct intel_dp *intel_dp)
2154 {
2155         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2156         u8 sink_irq_vector;
2157         u8 link_status[DP_LINK_STATUS_SIZE];
2158
2159         if (!intel_encoder->connectors_active)
2160                 return;
2161
2162         if (WARN_ON(!intel_encoder->base.crtc))
2163                 return;
2164
2165         /* Try to read receiver status if the link appears to be up */
2166         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2167                 intel_dp_link_down(intel_dp);
2168                 return;
2169         }
2170
2171         /* Now read the DPCD to see if it's actually running */
2172         if (!intel_dp_get_dpcd(intel_dp)) {
2173                 intel_dp_link_down(intel_dp);
2174                 return;
2175         }
2176
2177         /* Try to read the source of the interrupt */
2178         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2179             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2180                 /* Clear interrupt source */
2181                 intel_dp_aux_native_write_1(intel_dp,
2182                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2183                                             sink_irq_vector);
2184
2185                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2186                         intel_dp_handle_test_request(intel_dp);
2187                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2188                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2189         }
2190
2191         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2192                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2193                               drm_get_encoder_name(&intel_encoder->base));
2194                 intel_dp_start_link_train(intel_dp);
2195                 intel_dp_complete_link_train(intel_dp);
2196                 intel_dp_stop_link_train(intel_dp);
2197         }
2198 }
2199
2200 /* XXX this is probably wrong for multiple downstream ports */
2201 static enum drm_connector_status
2202 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2203 {
2204         uint8_t *dpcd = intel_dp->dpcd;
2205         bool hpd;
2206         uint8_t type;
2207
2208         if (!intel_dp_get_dpcd(intel_dp))
2209                 return connector_status_disconnected;
2210
2211         /* if there's no downstream port, we're done */
2212         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2213                 return connector_status_connected;
2214
2215         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2216         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2217         if (hpd) {
2218                 uint8_t reg;
2219                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2220                                                     &reg, 1))
2221                         return connector_status_unknown;
2222                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2223                                               : connector_status_disconnected;
2224         }
2225
2226         /* If no HPD, poke DDC gently */
2227         if (drm_probe_ddc(&intel_dp->adapter))
2228                 return connector_status_connected;
2229
2230         /* Well we tried, say unknown for unreliable port types */
2231         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2232         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2233                 return connector_status_unknown;
2234
2235         /* Anything else is out of spec, warn and ignore */
2236         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2237         return connector_status_disconnected;
2238 }
2239
2240 static enum drm_connector_status
2241 ironlake_dp_detect(struct intel_dp *intel_dp)
2242 {
2243         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2246         enum drm_connector_status status;
2247
2248         /* Can't disconnect eDP, but you can close the lid... */
2249         if (is_edp(intel_dp)) {
2250                 status = intel_panel_detect(dev);
2251                 if (status == connector_status_unknown)
2252                         status = connector_status_connected;
2253                 return status;
2254         }
2255
2256         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2257                 return connector_status_disconnected;
2258
2259         return intel_dp_detect_dpcd(intel_dp);
2260 }
2261
2262 static enum drm_connector_status
2263 g4x_dp_detect(struct intel_dp *intel_dp)
2264 {
2265         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2268         uint32_t bit;
2269
2270         /* Can't disconnect eDP, but you can close the lid... */
2271         if (is_edp(intel_dp)) {
2272                 enum drm_connector_status status;
2273
2274                 status = intel_panel_detect(dev);
2275                 if (status == connector_status_unknown)
2276                         status = connector_status_connected;
2277                 return status;
2278         }
2279
2280         if (IS_VALLEYVIEW(dev)) {
2281                 switch (intel_dig_port->port) {
2282                 case PORT_B:
2283                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
2284                         break;
2285                 case PORT_C:
2286                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
2287                         break;
2288                 case PORT_D:
2289                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
2290                         break;
2291                 default:
2292                         return connector_status_unknown;
2293                 }
2294         } else {
2295                 switch (intel_dig_port->port) {
2296                 case PORT_B:
2297                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
2298                         break;
2299                 case PORT_C:
2300                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
2301                         break;
2302                 case PORT_D:
2303                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
2304                         break;
2305                 default:
2306                         return connector_status_unknown;
2307                 }
2308         }
2309
2310         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2311                 return connector_status_disconnected;
2312
2313         return intel_dp_detect_dpcd(intel_dp);
2314 }
2315
2316 static struct edid *
2317 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2318 {
2319         struct intel_connector *intel_connector = to_intel_connector(connector);
2320
2321         /* use cached edid if we have one */
2322         if (intel_connector->edid) {
2323                 struct edid *edid;
2324                 int size;
2325
2326                 /* invalid edid */
2327                 if (IS_ERR(intel_connector->edid))
2328                         return NULL;
2329
2330                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2331                 edid = kmalloc(size, GFP_KERNEL);
2332                 if (!edid)
2333                         return NULL;
2334
2335                 memcpy(edid, intel_connector->edid, size);
2336                 return edid;
2337         }
2338
2339         return drm_get_edid(connector, adapter);
2340 }
2341
2342 static int
2343 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2344 {
2345         struct intel_connector *intel_connector = to_intel_connector(connector);
2346
2347         /* use cached edid if we have one */
2348         if (intel_connector->edid) {
2349                 /* invalid edid */
2350                 if (IS_ERR(intel_connector->edid))
2351                         return 0;
2352
2353                 return intel_connector_update_modes(connector,
2354                                                     intel_connector->edid);
2355         }
2356
2357         return intel_ddc_get_modes(connector, adapter);
2358 }
2359
2360 static enum drm_connector_status
2361 intel_dp_detect(struct drm_connector *connector, bool force)
2362 {
2363         struct intel_dp *intel_dp = intel_attached_dp(connector);
2364         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2365         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2366         struct drm_device *dev = connector->dev;
2367         enum drm_connector_status status;
2368         struct edid *edid = NULL;
2369
2370         intel_dp->has_audio = false;
2371
2372         if (HAS_PCH_SPLIT(dev))
2373                 status = ironlake_dp_detect(intel_dp);
2374         else
2375                 status = g4x_dp_detect(intel_dp);
2376
2377         if (status != connector_status_connected)
2378                 return status;
2379
2380         intel_dp_probe_oui(intel_dp);
2381
2382         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2383                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2384         } else {
2385                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2386                 if (edid) {
2387                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2388                         kfree(edid);
2389                 }
2390         }
2391
2392         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2393                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2394         return connector_status_connected;
2395 }
2396
2397 static int intel_dp_get_modes(struct drm_connector *connector)
2398 {
2399         struct intel_dp *intel_dp = intel_attached_dp(connector);
2400         struct intel_connector *intel_connector = to_intel_connector(connector);
2401         struct drm_device *dev = connector->dev;
2402         int ret;
2403
2404         /* We should parse the EDID data and find out if it has an audio sink
2405          */
2406
2407         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2408         if (ret)
2409                 return ret;
2410
2411         /* if eDP has no EDID, fall back to fixed mode */
2412         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2413                 struct drm_display_mode *mode;
2414                 mode = drm_mode_duplicate(dev,
2415                                           intel_connector->panel.fixed_mode);
2416                 if (mode) {
2417                         drm_mode_probed_add(connector, mode);
2418                         return 1;
2419                 }
2420         }
2421         return 0;
2422 }
2423
2424 static bool
2425 intel_dp_detect_audio(struct drm_connector *connector)
2426 {
2427         struct intel_dp *intel_dp = intel_attached_dp(connector);
2428         struct edid *edid;
2429         bool has_audio = false;
2430
2431         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2432         if (edid) {
2433                 has_audio = drm_detect_monitor_audio(edid);
2434                 kfree(edid);
2435         }
2436
2437         return has_audio;
2438 }
2439
2440 static int
2441 intel_dp_set_property(struct drm_connector *connector,
2442                       struct drm_property *property,
2443                       uint64_t val)
2444 {
2445         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2446         struct intel_connector *intel_connector = to_intel_connector(connector);
2447         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2448         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2449         int ret;
2450
2451         ret = drm_object_property_set_value(&connector->base, property, val);
2452         if (ret)
2453                 return ret;
2454
2455         if (property == dev_priv->force_audio_property) {
2456                 int i = val;
2457                 bool has_audio;
2458
2459                 if (i == intel_dp->force_audio)
2460                         return 0;
2461
2462                 intel_dp->force_audio = i;
2463
2464                 if (i == HDMI_AUDIO_AUTO)
2465                         has_audio = intel_dp_detect_audio(connector);
2466                 else
2467                         has_audio = (i == HDMI_AUDIO_ON);
2468
2469                 if (has_audio == intel_dp->has_audio)
2470                         return 0;
2471
2472                 intel_dp->has_audio = has_audio;
2473                 goto done;
2474         }
2475
2476         if (property == dev_priv->broadcast_rgb_property) {
2477                 bool old_auto = intel_dp->color_range_auto;
2478                 uint32_t old_range = intel_dp->color_range;
2479
2480                 switch (val) {
2481                 case INTEL_BROADCAST_RGB_AUTO:
2482                         intel_dp->color_range_auto = true;
2483                         break;
2484                 case INTEL_BROADCAST_RGB_FULL:
2485                         intel_dp->color_range_auto = false;
2486                         intel_dp->color_range = 0;
2487                         break;
2488                 case INTEL_BROADCAST_RGB_LIMITED:
2489                         intel_dp->color_range_auto = false;
2490                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2491                         break;
2492                 default:
2493                         return -EINVAL;
2494                 }
2495
2496                 if (old_auto == intel_dp->color_range_auto &&
2497                     old_range == intel_dp->color_range)
2498                         return 0;
2499
2500                 goto done;
2501         }
2502
2503         if (is_edp(intel_dp) &&
2504             property == connector->dev->mode_config.scaling_mode_property) {
2505                 if (val == DRM_MODE_SCALE_NONE) {
2506                         DRM_DEBUG_KMS("no scaling not supported\n");
2507                         return -EINVAL;
2508                 }
2509
2510                 if (intel_connector->panel.fitting_mode == val) {
2511                         /* the eDP scaling property is not changed */
2512                         return 0;
2513                 }
2514                 intel_connector->panel.fitting_mode = val;
2515
2516                 goto done;
2517         }
2518
2519         return -EINVAL;
2520
2521 done:
2522         if (intel_encoder->base.crtc)
2523                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2524
2525         return 0;
2526 }
2527
2528 static void
2529 intel_dp_destroy(struct drm_connector *connector)
2530 {
2531         struct intel_dp *intel_dp = intel_attached_dp(connector);
2532         struct intel_connector *intel_connector = to_intel_connector(connector);
2533
2534         if (!IS_ERR_OR_NULL(intel_connector->edid))
2535                 kfree(intel_connector->edid);
2536
2537         if (is_edp(intel_dp))
2538                 intel_panel_fini(&intel_connector->panel);
2539
2540         drm_sysfs_connector_remove(connector);
2541         drm_connector_cleanup(connector);
2542         kfree(connector);
2543 }
2544
2545 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2546 {
2547         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2548         struct intel_dp *intel_dp = &intel_dig_port->dp;
2549         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2550
2551         i2c_del_adapter(&intel_dp->adapter);
2552         drm_encoder_cleanup(encoder);
2553         if (is_edp(intel_dp)) {
2554                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2555                 mutex_lock(&dev->mode_config.mutex);
2556                 ironlake_panel_vdd_off_sync(intel_dp);
2557                 mutex_unlock(&dev->mode_config.mutex);
2558         }
2559         kfree(intel_dig_port);
2560 }
2561
2562 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2563         .mode_set = intel_dp_mode_set,
2564 };
2565
2566 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2567         .dpms = intel_connector_dpms,
2568         .detect = intel_dp_detect,
2569         .fill_modes = drm_helper_probe_single_connector_modes,
2570         .set_property = intel_dp_set_property,
2571         .destroy = intel_dp_destroy,
2572 };
2573
2574 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2575         .get_modes = intel_dp_get_modes,
2576         .mode_valid = intel_dp_mode_valid,
2577         .best_encoder = intel_best_encoder,
2578 };
2579
2580 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2581         .destroy = intel_dp_encoder_destroy,
2582 };
2583
2584 static void
2585 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2586 {
2587         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2588
2589         intel_dp_check_link_status(intel_dp);
2590 }
2591
2592 /* Return which DP Port should be selected for Transcoder DP control */
2593 int
2594 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2595 {
2596         struct drm_device *dev = crtc->dev;
2597         struct intel_encoder *intel_encoder;
2598         struct intel_dp *intel_dp;
2599
2600         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2601                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2602
2603                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2604                     intel_encoder->type == INTEL_OUTPUT_EDP)
2605                         return intel_dp->output_reg;
2606         }
2607
2608         return -1;
2609 }
2610
2611 /* check the VBT to see whether the eDP is on DP-D port */
2612 bool intel_dpd_is_edp(struct drm_device *dev)
2613 {
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct child_device_config *p_child;
2616         int i;
2617
2618         if (!dev_priv->child_dev_num)
2619                 return false;
2620
2621         for (i = 0; i < dev_priv->child_dev_num; i++) {
2622                 p_child = dev_priv->child_dev + i;
2623
2624                 if (p_child->dvo_port == PORT_IDPD &&
2625                     p_child->device_type == DEVICE_TYPE_eDP)
2626                         return true;
2627         }
2628         return false;
2629 }
2630
2631 static void
2632 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2633 {
2634         struct intel_connector *intel_connector = to_intel_connector(connector);
2635
2636         intel_attach_force_audio_property(connector);
2637         intel_attach_broadcast_rgb_property(connector);
2638         intel_dp->color_range_auto = true;
2639
2640         if (is_edp(intel_dp)) {
2641                 drm_mode_create_scaling_mode_property(connector->dev);
2642                 drm_object_attach_property(
2643                         &connector->base,
2644                         connector->dev->mode_config.scaling_mode_property,
2645                         DRM_MODE_SCALE_ASPECT);
2646                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2647         }
2648 }
2649
2650 static void
2651 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2652                                     struct intel_dp *intel_dp,
2653                                     struct edp_power_seq *out)
2654 {
2655         struct drm_i915_private *dev_priv = dev->dev_private;
2656         struct edp_power_seq cur, vbt, spec, final;
2657         u32 pp_on, pp_off, pp_div, pp;
2658         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2659
2660         if (HAS_PCH_SPLIT(dev)) {
2661                 pp_control_reg = PCH_PP_CONTROL;
2662                 pp_on_reg = PCH_PP_ON_DELAYS;
2663                 pp_off_reg = PCH_PP_OFF_DELAYS;
2664                 pp_div_reg = PCH_PP_DIVISOR;
2665         } else {
2666                 pp_control_reg = PIPEA_PP_CONTROL;
2667                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2668                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2669                 pp_div_reg = PIPEA_PP_DIVISOR;
2670         }
2671
2672         /* Workaround: Need to write PP_CONTROL with the unlock key as
2673          * the very first thing. */
2674         pp = ironlake_get_pp_control(intel_dp);
2675         I915_WRITE(pp_control_reg, pp);
2676
2677         pp_on = I915_READ(pp_on_reg);
2678         pp_off = I915_READ(pp_off_reg);
2679         pp_div = I915_READ(pp_div_reg);
2680
2681         /* Pull timing values out of registers */
2682         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2683                 PANEL_POWER_UP_DELAY_SHIFT;
2684
2685         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2686                 PANEL_LIGHT_ON_DELAY_SHIFT;
2687
2688         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2689                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2690
2691         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2692                 PANEL_POWER_DOWN_DELAY_SHIFT;
2693
2694         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2695                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2696
2697         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2698                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2699
2700         vbt = dev_priv->edp.pps;
2701
2702         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2703          * our hw here, which are all in 100usec. */
2704         spec.t1_t3 = 210 * 10;
2705         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2706         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2707         spec.t10 = 500 * 10;
2708         /* This one is special and actually in units of 100ms, but zero
2709          * based in the hw (so we need to add 100 ms). But the sw vbt
2710          * table multiplies it with 1000 to make it in units of 100usec,
2711          * too. */
2712         spec.t11_t12 = (510 + 100) * 10;
2713
2714         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2715                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2716
2717         /* Use the max of the register settings and vbt. If both are
2718          * unset, fall back to the spec limits. */
2719 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2720                                        spec.field : \
2721                                        max(cur.field, vbt.field))
2722         assign_final(t1_t3);
2723         assign_final(t8);
2724         assign_final(t9);
2725         assign_final(t10);
2726         assign_final(t11_t12);
2727 #undef assign_final
2728
2729 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2730         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2731         intel_dp->backlight_on_delay = get_delay(t8);
2732         intel_dp->backlight_off_delay = get_delay(t9);
2733         intel_dp->panel_power_down_delay = get_delay(t10);
2734         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2735 #undef get_delay
2736
2737         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2738                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2739                       intel_dp->panel_power_cycle_delay);
2740
2741         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2742                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2743
2744         if (out)
2745                 *out = final;
2746 }
2747
2748 static void
2749 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2750                                               struct intel_dp *intel_dp,
2751                                               struct edp_power_seq *seq)
2752 {
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754         u32 pp_on, pp_off, pp_div, port_sel = 0;
2755         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2756         int pp_on_reg, pp_off_reg, pp_div_reg;
2757
2758         if (HAS_PCH_SPLIT(dev)) {
2759                 pp_on_reg = PCH_PP_ON_DELAYS;
2760                 pp_off_reg = PCH_PP_OFF_DELAYS;
2761                 pp_div_reg = PCH_PP_DIVISOR;
2762         } else {
2763                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2764                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2765                 pp_div_reg = PIPEA_PP_DIVISOR;
2766         }
2767
2768         if (IS_VALLEYVIEW(dev))
2769                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2770
2771         /* And finally store the new values in the power sequencer. */
2772         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2773                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2774         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2775                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2776         /* Compute the divisor for the pp clock, simply match the Bspec
2777          * formula. */
2778         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2779         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2780                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2781
2782         /* Haswell doesn't have any port selection bits for the panel
2783          * power sequencer any more. */
2784         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2785                 if (is_cpu_edp(intel_dp))
2786                         port_sel = PANEL_POWER_PORT_DP_A;
2787                 else
2788                         port_sel = PANEL_POWER_PORT_DP_D;
2789         }
2790
2791         pp_on |= port_sel;
2792
2793         I915_WRITE(pp_on_reg, pp_on);
2794         I915_WRITE(pp_off_reg, pp_off);
2795         I915_WRITE(pp_div_reg, pp_div);
2796
2797         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2798                       I915_READ(pp_on_reg),
2799                       I915_READ(pp_off_reg),
2800                       I915_READ(pp_div_reg));
2801 }
2802
2803 void
2804 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2805                         struct intel_connector *intel_connector)
2806 {
2807         struct drm_connector *connector = &intel_connector->base;
2808         struct intel_dp *intel_dp = &intel_dig_port->dp;
2809         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2810         struct drm_device *dev = intel_encoder->base.dev;
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         struct drm_display_mode *fixed_mode = NULL;
2813         struct edp_power_seq power_seq = { 0 };
2814         enum port port = intel_dig_port->port;
2815         const char *name = NULL;
2816         int type;
2817
2818         /* Preserve the current hw state. */
2819         intel_dp->DP = I915_READ(intel_dp->output_reg);
2820         intel_dp->attached_connector = intel_connector;
2821
2822         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2823                 if (intel_dpd_is_edp(dev))
2824                         intel_dp->is_pch_edp = true;
2825
2826         /*
2827          * FIXME : We need to initialize built-in panels before external panels.
2828          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2829          */
2830         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2831                 type = DRM_MODE_CONNECTOR_eDP;
2832                 intel_encoder->type = INTEL_OUTPUT_EDP;
2833         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2834                 type = DRM_MODE_CONNECTOR_eDP;
2835                 intel_encoder->type = INTEL_OUTPUT_EDP;
2836         } else {
2837                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2838                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2839                  * rewrite it.
2840                  */
2841                 type = DRM_MODE_CONNECTOR_DisplayPort;
2842         }
2843
2844         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2845         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2846
2847         connector->interlace_allowed = true;
2848         connector->doublescan_allowed = 0;
2849
2850         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2851                           ironlake_panel_vdd_work);
2852
2853         intel_connector_attach_encoder(intel_connector, intel_encoder);
2854         drm_sysfs_connector_add(connector);
2855
2856         if (HAS_DDI(dev))
2857                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2858         else
2859                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2860
2861         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2862         if (HAS_DDI(dev)) {
2863                 switch (intel_dig_port->port) {
2864                 case PORT_A:
2865                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2866                         break;
2867                 case PORT_B:
2868                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2869                         break;
2870                 case PORT_C:
2871                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2872                         break;
2873                 case PORT_D:
2874                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2875                         break;
2876                 default:
2877                         BUG();
2878                 }
2879         }
2880
2881         /* Set up the DDC bus. */
2882         switch (port) {
2883         case PORT_A:
2884                 intel_encoder->hpd_pin = HPD_PORT_A;
2885                 name = "DPDDC-A";
2886                 break;
2887         case PORT_B:
2888                 intel_encoder->hpd_pin = HPD_PORT_B;
2889                 name = "DPDDC-B";
2890                 break;
2891         case PORT_C:
2892                 intel_encoder->hpd_pin = HPD_PORT_C;
2893                 name = "DPDDC-C";
2894                 break;
2895         case PORT_D:
2896                 intel_encoder->hpd_pin = HPD_PORT_D;
2897                 name = "DPDDC-D";
2898                 break;
2899         default:
2900                 BUG();
2901         }
2902
2903         if (is_edp(intel_dp))
2904                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2905
2906         intel_dp_i2c_init(intel_dp, intel_connector, name);
2907
2908         /* Cache DPCD and EDID for edp. */
2909         if (is_edp(intel_dp)) {
2910                 bool ret;
2911                 struct drm_display_mode *scan;
2912                 struct edid *edid;
2913
2914                 ironlake_edp_panel_vdd_on(intel_dp);
2915                 ret = intel_dp_get_dpcd(intel_dp);
2916                 ironlake_edp_panel_vdd_off(intel_dp, false);
2917
2918                 if (ret) {
2919                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2920                                 dev_priv->no_aux_handshake =
2921                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2922                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2923                 } else {
2924                         /* if this fails, presume the device is a ghost */
2925                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2926                         intel_dp_encoder_destroy(&intel_encoder->base);
2927                         intel_dp_destroy(connector);
2928                         return;
2929                 }
2930
2931                 /* We now know it's not a ghost, init power sequence regs. */
2932                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2933                                                               &power_seq);
2934
2935                 ironlake_edp_panel_vdd_on(intel_dp);
2936                 edid = drm_get_edid(connector, &intel_dp->adapter);
2937                 if (edid) {
2938                         if (drm_add_edid_modes(connector, edid)) {
2939                                 drm_mode_connector_update_edid_property(connector, edid);
2940                                 drm_edid_to_eld(connector, edid);
2941                         } else {
2942                                 kfree(edid);
2943                                 edid = ERR_PTR(-EINVAL);
2944                         }
2945                 } else {
2946                         edid = ERR_PTR(-ENOENT);
2947                 }
2948                 intel_connector->edid = edid;
2949
2950                 /* prefer fixed mode from EDID if available */
2951                 list_for_each_entry(scan, &connector->probed_modes, head) {
2952                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2953                                 fixed_mode = drm_mode_duplicate(dev, scan);
2954                                 break;
2955                         }
2956                 }
2957
2958                 /* fallback to VBT if available for eDP */
2959                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2960                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2961                         if (fixed_mode)
2962                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2963                 }
2964
2965                 ironlake_edp_panel_vdd_off(intel_dp, false);
2966         }
2967
2968         if (is_edp(intel_dp)) {
2969                 intel_panel_init(&intel_connector->panel, fixed_mode);
2970                 intel_panel_setup_backlight(connector);
2971         }
2972
2973         intel_dp_add_properties(intel_dp, connector);
2974
2975         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2976          * 0xd.  Failure to do so will result in spurious interrupts being
2977          * generated on the port when a cable is not attached.
2978          */
2979         if (IS_G4X(dev) && !IS_GM45(dev)) {
2980                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2981                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2982         }
2983 }
2984
2985 void
2986 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2987 {
2988         struct intel_digital_port *intel_dig_port;
2989         struct intel_encoder *intel_encoder;
2990         struct drm_encoder *encoder;
2991         struct intel_connector *intel_connector;
2992
2993         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2994         if (!intel_dig_port)
2995                 return;
2996
2997         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2998         if (!intel_connector) {
2999                 kfree(intel_dig_port);
3000                 return;
3001         }
3002
3003         intel_encoder = &intel_dig_port->base;
3004         encoder = &intel_encoder->base;
3005
3006         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3007                          DRM_MODE_ENCODER_TMDS);
3008         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3009
3010         intel_encoder->compute_config = intel_dp_compute_config;
3011         intel_encoder->enable = intel_enable_dp;
3012         intel_encoder->pre_enable = intel_pre_enable_dp;
3013         intel_encoder->disable = intel_disable_dp;
3014         intel_encoder->post_disable = intel_post_disable_dp;
3015         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3016
3017         intel_dig_port->port = port;
3018         intel_dig_port->dp.output_reg = output_reg;
3019
3020         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3021         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3022         intel_encoder->cloneable = false;
3023         intel_encoder->hot_plug = intel_dp_hot_plug;
3024
3025         intel_dp_init_connector(intel_dig_port, intel_connector);
3026 }