drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 8, .max = 18 },
 158         .m2 = { .min = 3, .max = 7 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 8, .max = 18 },
 172         .m2 = { .min = 3, .max = 7 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 420
 421         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 422                 DRM_ERROR("DPIO idle wait timed out\n");
 423                 return 0;
 424         }
 425
 426         I915_WRITE(DPIO_REG, reg);
 427         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 428                    DPIO_BYTE);
 429         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 430                 DRM_ERROR("DPIO read wait timed out\n");
 431                 return 0;
 432         }
 433
 434         return I915_READ(DPIO_DATA);
 435 }
 436
 437 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 438                              u32 val)
 439 {
 440         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 441
 442         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 443                 DRM_ERROR("DPIO idle wait timed out\n");
 444                 return;
 445         }
 446
 447         I915_WRITE(DPIO_DATA, val);
 448         I915_WRITE(DPIO_REG, reg);
 449         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 450                    DPIO_BYTE);
 451         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 452                 DRM_ERROR("DPIO write wait timed out\n");
 453 }
 454
 455 static void vlv_init_dpio(struct drm_device *dev)
 456 {
 457         struct drm_i915_private *dev_priv = dev->dev_private;
 458
 459         /* Reset the DPIO config */
 460         I915_WRITE(DPIO_CTL, 0);
 461         POSTING_READ(DPIO_CTL);
 462         I915_WRITE(DPIO_CTL, 1);
 463         POSTING_READ(DPIO_CTL);
 464 }
 465
 466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 467                                                 int refclk)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         const intel_limit_t *limit;
 471
 472         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 473                 if (intel_is_dual_link_lvds(dev)) {
 474                         /* LVDS dual channel */
 475                         if (refclk == 100000)
 476                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 477                         else
 478                                 limit = &intel_limits_ironlake_dual_lvds;
 479                 } else {
 480                         if (refclk == 100000)
 481                                 limit = &intel_limits_ironlake_single_lvds_100m;
 482                         else
 483                                 limit = &intel_limits_ironlake_single_lvds;
 484                 }
 485         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 486                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 487                 limit = &intel_limits_ironlake_display_port;
 488         else
 489                 limit = &intel_limits_ironlake_dac;
 490
 491         return limit;
 492 }
 493
 494 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         const intel_limit_t *limit;
 498
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 500                 if (intel_is_dual_link_lvds(dev))
 501                         /* LVDS with dual channel */
 502                         limit = &intel_limits_g4x_dual_channel_lvds;
 503                 else
 504                         /* LVDS with dual channel */
 505                         limit = &intel_limits_g4x_single_channel_lvds;
 506         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 507                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 508                 limit = &intel_limits_g4x_hdmi;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 510                 limit = &intel_limits_g4x_sdvo;
 511         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 512                 limit = &intel_limits_g4x_display_port;
 513         } else /* The option is for other outputs */
 514                 limit = &intel_limits_i9xx_sdvo;
 515
 516         return limit;
 517 }
 518
 519 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         const intel_limit_t *limit;
 523
 524         if (HAS_PCH_SPLIT(dev))
 525                 limit = intel_ironlake_limit(crtc, refclk);
 526         else if (IS_G4X(dev)) {
 527                 limit = intel_g4x_limit(crtc);
 528         } else if (IS_PINEVIEW(dev)) {
 529                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 530                         limit = &intel_limits_pineview_lvds;
 531                 else
 532                         limit = &intel_limits_pineview_sdvo;
 533         } else if (IS_VALLEYVIEW(dev)) {
 534                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 535                         limit = &intel_limits_vlv_dac;
 536                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 537                         limit = &intel_limits_vlv_hdmi;
 538                 else
 539                         limit = &intel_limits_vlv_dp;
 540         } else if (!IS_GEN2(dev)) {
 541                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i9xx_lvds;
 543                 else
 544                         limit = &intel_limits_i9xx_sdvo;
 545         } else {
 546                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits_i8xx_lvds;
 548                 else
 549                         limit = &intel_limits_i8xx_dvo;
 550         }
 551         return limit;
 552 }
 553
 554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 555 static void pineview_clock(int refclk, intel_clock_t *clock)
 556 {
 557         clock->m = clock->m2 + 2;
 558         clock->p = clock->p1 * clock->p2;
 559         clock->vco = refclk * clock->m / clock->n;
 560         clock->dot = clock->vco / clock->p;
 561 }
 562
 563 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 564 {
 565         if (IS_PINEVIEW(dev)) {
 566                 pineview_clock(refclk, clock);
 567                 return;
 568         }
 569         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 570         clock->p = clock->p1 * clock->p2;
 571         clock->vco = refclk * clock->m / (clock->n + 2);
 572         clock->dot = clock->vco / clock->p;
 573 }
 574
 575 /**
 576  * Returns whether any output on the specified pipe is of the specified type
 577  */
 578 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         struct intel_encoder *encoder;
 582
 583         for_each_encoder_on_crtc(dev, crtc, encoder)
 584                 if (encoder->type == type)
 585                         return true;
 586
 587         return false;
 588 }
 589
 590 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 591 /**
 592  * Returns whether the given set of divisors are valid for a given refclk with
 593  * the given connectors.
 594  */
 595
 596 static bool intel_PLL_is_valid(struct drm_device *dev,
 597                                const intel_limit_t *limit,
 598                                const intel_clock_t *clock)
 599 {
 600         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 601                 INTELPllInvalid("p1 out of range\n");
 602         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 603                 INTELPllInvalid("p out of range\n");
 604         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 605                 INTELPllInvalid("m2 out of range\n");
 606         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 607                 INTELPllInvalid("m1 out of range\n");
 608         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 609                 INTELPllInvalid("m1 <= m2\n");
 610         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 611                 INTELPllInvalid("m out of range\n");
 612         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 613                 INTELPllInvalid("n out of range\n");
 614         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 615                 INTELPllInvalid("vco out of range\n");
 616         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 617          * connector, etc., rather than just a single range.
 618          */
 619         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 620                 INTELPllInvalid("dot out of range\n");
 621
 622         return true;
 623 }
 624
 625 static bool
 626 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                     int target, int refclk, intel_clock_t *match_clock,
 628                     intel_clock_t *best_clock)
 629
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int err = target;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 /*
 637                  * For LVDS just rely on its current settings for dual-channel.
 638                  * We haven't figured out how to reliably set up different
 639                  * single/dual channel state, if we even can.
 640                  */
 641                 if (intel_is_dual_link_lvds(dev))
 642                         clock.p2 = limit->p2.p2_fast;
 643                 else
 644                         clock.p2 = limit->p2.p2_slow;
 645         } else {
 646                 if (target < limit->p2.dot_limit)
 647                         clock.p2 = limit->p2.p2_slow;
 648                 else
 649                         clock.p2 = limit->p2.p2_fast;
 650         }
 651
 652         memset(best_clock, 0, sizeof(*best_clock));
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         /* m1 is always 0 in Pineview */
 659                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 660                                 break;
 661                         for (clock.n = limit->n.min;
 662                              clock.n <= limit->n.max; clock.n++) {
 663                                 for (clock.p1 = limit->p1.min;
 664                                         clock.p1 <= limit->p1.max; clock.p1++) {
 665                                         int this_err;
 666
 667                                         intel_clock(dev, refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 static bool
 689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 690                         int target, int refclk, intel_clock_t *match_clock,
 691                         intel_clock_t *best_clock)
 692 {
 693         struct drm_device *dev = crtc->dev;
 694         intel_clock_t clock;
 695         int max_n;
 696         bool found;
 697         /* approximately equals target * 0.00585 */
 698         int err_most = (target >> 8) + (target >> 9);
 699         found = false;
 700
 701         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 702                 int lvds_reg;
 703
 704                 if (HAS_PCH_SPLIT(dev))
 705                         lvds_reg = PCH_LVDS;
 706                 else
 707                         lvds_reg = LVDS;
 708                 if (intel_is_dual_link_lvds(dev))
 709                         clock.p2 = limit->p2.p2_fast;
 710                 else
 711                         clock.p2 = limit->p2.p2_slow;
 712         } else {
 713                 if (target < limit->p2.dot_limit)
 714                         clock.p2 = limit->p2.p2_slow;
 715                 else
 716                         clock.p2 = limit->p2.p2_fast;
 717         }
 718
 719         memset(best_clock, 0, sizeof(*best_clock));
 720         max_n = limit->n.max;
 721         /* based on hardware requirement, prefer smaller n to precision */
 722         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 723                 /* based on hardware requirement, prefere larger m1,m2 */
 724                 for (clock.m1 = limit->m1.max;
 725                      clock.m1 >= limit->m1.min; clock.m1--) {
 726                         for (clock.m2 = limit->m2.max;
 727                              clock.m2 >= limit->m2.min; clock.m2--) {
 728                                 for (clock.p1 = limit->p1.max;
 729                                      clock.p1 >= limit->p1.min; clock.p1--) {
 730                                         int this_err;
 731
 732                                         intel_clock(dev, refclk, &clock);
 733                                         if (!intel_PLL_is_valid(dev, limit,
 734                                                                 &clock))
 735                                                 continue;
 736                                         if (match_clock &&
 737                                             clock.p != match_clock->p)
 738                                                 continue;
 739
 740                                         this_err = abs(clock.dot - target);
 741                                         if (this_err < err_most) {
 742                                                 *best_clock = clock;
 743                                                 err_most = this_err;
 744                                                 max_n = clock.n;
 745                                                 found = true;
 746                                         }
 747                                 }
 748                         }
 749                 }
 750         }
 751         return found;
 752 }
 753
 754 static bool
 755 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 756                            int target, int refclk, intel_clock_t *match_clock,
 757                            intel_clock_t *best_clock)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         intel_clock_t clock;
 761
 762         if (target < 200000) {
 763                 clock.n = 1;
 764                 clock.p1 = 2;
 765                 clock.p2 = 10;
 766                 clock.m1 = 12;
 767                 clock.m2 = 9;
 768         } else {
 769                 clock.n = 2;
 770                 clock.p1 = 1;
 771                 clock.p2 = 10;
 772                 clock.m1 = 14;
 773                 clock.m2 = 8;
 774         }
 775         intel_clock(dev, refclk, &clock);
 776         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 777         return true;
 778 }
 779
 780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 781 static bool
 782 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 783                       int target, int refclk, intel_clock_t *match_clock,
 784                       intel_clock_t *best_clock)
 785 {
 786         intel_clock_t clock;
 787         if (target < 200000) {
 788                 clock.p1 = 2;
 789                 clock.p2 = 10;
 790                 clock.n = 2;
 791                 clock.m1 = 23;
 792                 clock.m2 = 8;
 793         } else {
 794                 clock.p1 = 1;
 795                 clock.p2 = 10;
 796                 clock.n = 1;
 797                 clock.m1 = 14;
 798                 clock.m2 = 2;
 799         }
 800         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 801         clock.p = (clock.p1 * clock.p2);
 802         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 803         clock.vco = 0;
 804         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 805         return true;
 806 }
 807 static bool
 808 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 809                         int target, int refclk, intel_clock_t *match_clock,
 810                         intel_clock_t *best_clock)
 811 {
 812         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 813         u32 m, n, fastclk;
 814         u32 updrate, minupdate, fracbits, p;
 815         unsigned long bestppm, ppm, absppm;
 816         int dotclk, flag;
 817
 818         flag = 0;
 819         dotclk = target * 1000;
 820         bestppm = 1000000;
 821         ppm = absppm = 0;
 822         fastclk = dotclk / (2*100);
 823         updrate = 0;
 824         minupdate = 19200;
 825         fracbits = 1;
 826         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 827         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 828
 829         /* based on hardware requirement, prefer smaller n to precision */
 830         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 831                 updrate = refclk / n;
 832                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 833                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 834                                 if (p2 > 10)
 835                                         p2 = p2 - 1;
 836                                 p = p1 * p2;
 837                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 838                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 839                                         m2 = (((2*(fastclk * p * n / m1 )) +
 840                                                refclk) / (2*refclk));
 841                                         m = m1 * m2;
 842                                         vco = updrate * m;
 843                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 844                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 845                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 846                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 847                                                         bestppm = 0;
 848                                                         flag = 1;
 849                                                 }
 850                                                 if (absppm < bestppm - 10) {
 851                                                         bestppm = absppm;
 852                                                         flag = 1;
 853                                                 }
 854                                                 if (flag) {
 855                                                         bestn = n;
 856                                                         bestm1 = m1;
 857                                                         bestm2 = m2;
 858                                                         bestp1 = p1;
 859                                                         bestp2 = p2;
 860                                                         flag = 0;
 861                                                 }
 862                                         }
 863                                 }
 864                         }
 865                 }
 866         }
 867         best_clock->n = bestn;
 868         best_clock->m1 = bestm1;
 869         best_clock->m2 = bestm2;
 870         best_clock->p1 = bestp1;
 871         best_clock->p2 = bestp2;
 872
 873         return true;
 874 }
 875
 876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 877                                              enum pipe pipe)
 878 {
 879         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 881
 882         return intel_crtc->cpu_transcoder;
 883 }
 884
 885 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 886 {
 887         struct drm_i915_private *dev_priv = dev->dev_private;
 888         u32 frame, frame_reg = PIPEFRAME(pipe);
 889
 890         frame = I915_READ(frame_reg);
 891
 892         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 /**
 897  * intel_wait_for_vblank - wait for vblank on a given pipe
 898  * @dev: drm device
 899  * @pipe: pipe to wait for
 900  *
 901  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 902  * mode setting code.
 903  */
 904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 905 {
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         int pipestat_reg = PIPESTAT(pipe);
 908
 909         if (INTEL_INFO(dev)->gen >= 5) {
 910                 ironlake_wait_for_vblank(dev, pipe);
 911                 return;
 912         }
 913
 914         /* Clear existing vblank status. Note this will clear any other
 915          * sticky status fields as well.
 916          *
 917          * This races with i915_driver_irq_handler() with the result
 918          * that either function could miss a vblank event.  Here it is not
 919          * fatal, as we will either wait upon the next vblank interrupt or
 920          * timeout.  Generally speaking intel_wait_for_vblank() is only
 921          * called during modeset at which time the GPU should be idle and
 922          * should *not* be performing page flips and thus not waiting on
 923          * vblanks...
 924          * Currently, the result of us stealing a vblank from the irq
 925          * handler is that a single frame will be skipped during swapbuffers.
 926          */
 927         I915_WRITE(pipestat_reg,
 928                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 929
 930         /* Wait for vblank interrupt bit to set */
 931         if (wait_for(I915_READ(pipestat_reg) &
 932                      PIPE_VBLANK_INTERRUPT_STATUS,
 933                      50))
 934                 DRM_DEBUG_KMS("vblank wait timed out\n");
 935 }
 936
 937 /*
 938  * intel_wait_for_pipe_off - wait for pipe to turn off
 939  * @dev: drm device
 940  * @pipe: pipe to wait for
 941  *
 942  * After disabling a pipe, we can't wait for vblank in the usual way,
 943  * spinning on the vblank interrupt status bit, since we won't actually
 944  * see an interrupt when the pipe is disabled.
 945  *
 946  * On Gen4 and above:
 947  *   wait for the pipe register state bit to turn off
 948  *
 949  * Otherwise:
 950  *   wait for the display line value to settle (it usually
 951  *   ends up stopping at the start of the next frame).
 952  *
 953  */
 954 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 955 {
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 958                                                                       pipe);
 959
 960         if (INTEL_INFO(dev)->gen >= 4) {
 961                 int reg = PIPECONF(cpu_transcoder);
 962
 963                 /* Wait for the Pipe State to go off */
 964                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 965                              100))
 966                         WARN(1, "pipe_off wait timed out\n");
 967         } else {
 968                 u32 last_line, line_mask;
 969                 int reg = PIPEDSL(pipe);
 970                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 971
 972                 if (IS_GEN2(dev))
 973                         line_mask = DSL_LINEMASK_GEN2;
 974                 else
 975                         line_mask = DSL_LINEMASK_GEN3;
 976
 977                 /* Wait for the display line to settle */
 978                 do {
 979                         last_line = I915_READ(reg) & line_mask;
 980                         mdelay(5);
 981                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 982                          time_after(timeout, jiffies));
 983                 if (time_after(jiffies, timeout))
 984                         WARN(1, "pipe_off wait timed out\n");
 985         }
 986 }
 987
 988 /*
 989  * ibx_digital_port_connected - is the specified port connected?
 990  * @dev_priv: i915 private structure
 991  * @port: the port to test
 992  *
 993  * Returns true if @port is connected, false otherwise.
 994  */
 995 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 996                                 struct intel_digital_port *port)
 997 {
 998         u32 bit;
 999
1000         if (HAS_PCH_IBX(dev_priv->dev)) {
1001                 switch(port->port) {
1002                 case PORT_B:
1003                         bit = SDE_PORTB_HOTPLUG;
1004                         break;
1005                 case PORT_C:
1006                         bit = SDE_PORTC_HOTPLUG;
1007                         break;
1008                 case PORT_D:
1009                         bit = SDE_PORTD_HOTPLUG;
1010                         break;
1011                 default:
1012                         return true;
1013                 }
1014         } else {
1015                 switch(port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG_CPT;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG_CPT;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG_CPT;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         }
1029
1030         return I915_READ(SDEISR) & bit;
1031 }
1032
1033 static const char *state_string(bool enabled)
1034 {
1035         return enabled ? "on" : "off";
1036 }
1037
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = DPLL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & DPLL_VCO_ENABLE);
1049         WARN(cur_state != state,
1050              "PLL state assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
1056 /* For ILK+ */
1057 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058                            struct intel_pch_pll *pll,
1059                            struct intel_crtc *crtc,
1060                            bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         if (HAS_PCH_LPT(dev_priv->dev)) {
1066                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067                 return;
1068         }
1069
1070         if (WARN (!pll,
1071                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072                 return;
1073
1074         val = I915_READ(pll->pll_reg);
1075         cur_state = !!(val & DPLL_VCO_ENABLE);
1076         WARN(cur_state != state,
1077              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078              pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080         /* Make sure the selected PLL is correctly attached to the transcoder */
1081         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082                 u32 pch_dpll;
1083
1084                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1088                           cur_state, crtc->pipe, pch_dpll)) {
1089                         cur_state = !!(val >> (4*crtc->pipe + 3));
1090                         WARN(cur_state != state,
1091                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1092                              pll->pll_reg == _PCH_DPLL_B,
1093                              state_string(state),
1094                              crtc->pipe,
1095                              val);
1096                 }
1097         }
1098 }
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109                                                                       pipe);
1110
1111         if (HAS_DDI(dev_priv->dev)) {
1112                 /* DDI does not have a specific FDI_TX register */
1113                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1116         } else {
1117                 reg = FDI_TX_CTL(pipe);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & FDI_TX_ENABLE);
1120         }
1121         WARN(cur_state != state,
1122              "FDI TX state assertion failure (expected %s, current %s)\n",
1123              state_string(state), state_string(cur_state));
1124 }
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         int reg;
1132         u32 val;
1133         bool cur_state;
1134
1135         reg = FDI_RX_CTL(pipe);
1136         val = I915_READ(reg);
1137         cur_state = !!(val & FDI_RX_ENABLE);
1138         WARN(cur_state != state,
1139              "FDI RX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146                                       enum pipe pipe)
1147 {
1148         int reg;
1149         u32 val;
1150
1151         /* ILK FDI PLL is always enabled */
1152         if (dev_priv->info->gen == 5)
1153                 return;
1154
1155         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156         if (HAS_DDI(dev_priv->dev))
1157                 return;
1158
1159         reg = FDI_TX_CTL(pipe);
1160         val = I915_READ(reg);
1161         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162 }
1163
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165                                       enum pipe pipe)
1166 {
1167         int reg;
1168         u32 val;
1169
1170         reg = FDI_RX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176                                   enum pipe pipe)
1177 {
1178         int pp_reg, lvds_reg;
1179         u32 val;
1180         enum pipe panel_pipe = PIPE_A;
1181         bool locked = true;
1182
1183         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184                 pp_reg = PCH_PP_CONTROL;
1185                 lvds_reg = PCH_LVDS;
1186         } else {
1187                 pp_reg = PP_CONTROL;
1188                 lvds_reg = LVDS;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197                 panel_pipe = PIPE_B;
1198
1199         WARN(panel_pipe == pipe && locked,
1200              "panel assertion failure, pipe %c regs locked\n",
1201              pipe_name(pipe));
1202 }
1203
1204 void assert_pipe(struct drm_i915_private *dev_priv,
1205                  enum pipe pipe, bool state)
1206 {
1207         int reg;
1208         u32 val;
1209         bool cur_state;
1210         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211                                                                       pipe);
1212
1213         /* if we need the pipe A quirk it must be always on */
1214         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215                 state = true;
1216
1217         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219                 cur_state = false;
1220         } else {
1221                 reg = PIPECONF(cpu_transcoder);
1222                 val = I915_READ(reg);
1223                 cur_state = !!(val & PIPECONF_ENABLE);
1224         }
1225
1226         WARN(cur_state != state,
1227              "pipe %c assertion failure (expected %s, current %s)\n",
1228              pipe_name(pipe), state_string(state), state_string(cur_state));
1229 }
1230
1231 static void assert_plane(struct drm_i915_private *dev_priv,
1232                          enum plane plane, bool state)
1233 {
1234         int reg;
1235         u32 val;
1236         bool cur_state;
1237
1238         reg = DSPCNTR(plane);
1239         val = I915_READ(reg);
1240         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241         WARN(cur_state != state,
1242              "plane %c assertion failure (expected %s, current %s)\n",
1243              plane_name(plane), state_string(state), state_string(cur_state));
1244 }
1245
1246 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
1249 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250                                    enum pipe pipe)
1251 {
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Planes are fixed to pipes on ILK+ */
1257         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN((val & DISPLAY_PLANE_ENABLE),
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for (i = 0; i < 2; i++) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279 {
1280         u32 val;
1281         bool enabled;
1282
1283         if (HAS_PCH_LPT(dev_priv->dev)) {
1284                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285                 return;
1286         }
1287
1288         val = I915_READ(PCH_DREF_CONTROL);
1289         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290                             DREF_SUPERSPREAD_SOURCE_MASK));
1291         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292 }
1293
1294 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                        enum pipe pipe)
1296 {
1297         int reg;
1298         u32 val;
1299         bool enabled;
1300
1301         reg = TRANSCONF(pipe);
1302         val = I915_READ(reg);
1303         enabled = !!(val & TRANS_ENABLE);
1304         WARN(enabled,
1305              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310                             enum pipe pipe, u32 port_sel, u32 val)
1311 {
1312         if ((val & DP_PORT_EN) == 0)
1313                 return false;
1314
1315         if (HAS_PCH_CPT(dev_priv->dev)) {
1316                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & PORT_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv->dev)) {
1334                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335                         return false;
1336         } else {
1337                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338                         return false;
1339         }
1340         return true;
1341 }
1342
1343 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344                               enum pipe pipe, u32 val)
1345 {
1346         if ((val & LVDS_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & ADPA_DAC_ENABLE) == 0)
1363                 return false;
1364         if (HAS_PCH_CPT(dev_priv->dev)) {
1365                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366                         return false;
1367         } else {
1368                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369                         return false;
1370         }
1371         return true;
1372 }
1373
1374 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1375                                    enum pipe pipe, int reg, u32 port_sel)
1376 {
1377         u32 val = I915_READ(reg);
1378         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1379              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1380              reg, pipe_name(pipe));
1381
1382         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383              && (val & DP_PIPEB_SELECT),
1384              "IBX PCH dp port still using transcoder B\n");
1385 }
1386
1387 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388                                      enum pipe pipe, int reg)
1389 {
1390         u32 val = I915_READ(reg);
1391         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1392              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1393              reg, pipe_name(pipe));
1394
1395         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396              && (val & SDVO_PIPE_B_SELECT),
1397              "IBX PCH hdmi port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401                                       enum pipe pipe)
1402 {
1403         int reg;
1404         u32 val;
1405
1406         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1409
1410         reg = PCH_ADPA;
1411         val = I915_READ(reg);
1412         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1413              "PCH VGA enabled on transcoder %c, should be disabled\n",
1414              pipe_name(pipe));
1415
1416         reg = PCH_LVDS;
1417         val = I915_READ(reg);
1418         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1420              pipe_name(pipe));
1421
1422         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 }
1426
1427 /**
1428  * intel_enable_pll - enable a PLL
1429  * @dev_priv: i915 private structure
1430  * @pipe: pipe PLL to enable
1431  *
1432  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1433  * make sure the PLL reg is writable first though, since the panel write
1434  * protect mechanism may be enabled.
1435  *
1436  * Note!  This is for pre-ILK only.
1437  *
1438  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1439  */
1440 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441 {
1442         int reg;
1443         u32 val;
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450                 assert_panel_unlocked(dev_priv, pipe);
1451
1452         reg = DPLL(pipe);
1453         val = I915_READ(reg);
1454         val |= DPLL_VCO_ENABLE;
1455
1456         /* We do this three times for luck */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463         I915_WRITE(reg, val);
1464         POSTING_READ(reg);
1465         udelay(150); /* wait for warmup */
1466 }
1467
1468 /**
1469  * intel_disable_pll - disable a PLL
1470  * @dev_priv: i915 private structure
1471  * @pipe: pipe PLL to disable
1472  *
1473  * Disable the PLL for @pipe, making sure the pipe is off first.
1474  *
1475  * Note!  This is for pre-ILK only.
1476  */
1477 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478 {
1479         int reg;
1480         u32 val;
1481
1482         /* Don't disable pipe A or pipe A PLLs if needed */
1483         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484                 return;
1485
1486         /* Make sure the pipe isn't still relying on us */
1487         assert_pipe_disabled(dev_priv, pipe);
1488
1489         reg = DPLL(pipe);
1490         val = I915_READ(reg);
1491         val &= ~DPLL_VCO_ENABLE;
1492         I915_WRITE(reg, val);
1493         POSTING_READ(reg);
1494 }
1495
1496 /* SBI access */
1497 static void
1498 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499                 enum intel_sbi_destination destination)
1500 {
1501         u32 tmp;
1502
1503         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1504
1505         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1506                                 100)) {
1507                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1508                 return;
1509         }
1510
1511         I915_WRITE(SBI_ADDR, (reg << 16));
1512         I915_WRITE(SBI_DATA, value);
1513
1514         if (destination == SBI_ICLK)
1515                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516         else
1517                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1519
1520         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1521                                 100)) {
1522                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1523                 return;
1524         }
1525 }
1526
1527 static u32
1528 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529                enum intel_sbi_destination destination)
1530 {
1531         u32 value = 0;
1532         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1533
1534         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1535                                 100)) {
1536                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537                 return 0;
1538         }
1539
1540         I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542         if (destination == SBI_ICLK)
1543                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544         else
1545                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1547
1548         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1549                                 100)) {
1550                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1551                 return 0;
1552         }
1553
1554         return I915_READ(SBI_DATA);
1555 }
1556
1557 /**
1558  * ironlake_enable_pch_pll - enable PCH PLL
1559  * @dev_priv: i915 private structure
1560  * @pipe: pipe PLL to enable
1561  *
1562  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563  * drives the transcoder clock.
1564  */
1565 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH PLLs only available on ILK, SNB and IVB */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         pll = intel_crtc->pch_pll;
1575         if (pll == NULL)
1576                 return;
1577
1578         if (WARN_ON(pll->refcount == 0))
1579                 return;
1580
1581         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582                       pll->pll_reg, pll->active, pll->on,
1583                       intel_crtc->base.base.id);
1584
1585         /* PCH refclock must be enabled first */
1586         assert_pch_refclk_enabled(dev_priv);
1587
1588         if (pll->active++ && pll->on) {
1589                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590                 return;
1591         }
1592
1593         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595         reg = pll->pll_reg;
1596         val = I915_READ(reg);
1597         val |= DPLL_VCO_ENABLE;
1598         I915_WRITE(reg, val);
1599         POSTING_READ(reg);
1600         udelay(200);
1601
1602         pll->on = true;
1603 }
1604
1605 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 {
1607         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609         int reg;
1610         u32 val;
1611
1612         /* PCH only available on ILK+ */
1613         BUG_ON(dev_priv->info->gen < 5);
1614         if (pll == NULL)
1615                return;
1616
1617         if (WARN_ON(pll->refcount == 0))
1618                 return;
1619
1620         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621                       pll->pll_reg, pll->active, pll->on,
1622                       intel_crtc->base.base.id);
1623
1624         if (WARN_ON(pll->active == 0)) {
1625                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         if (--pll->active) {
1630                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631                 return;
1632         }
1633
1634         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636         /* Make sure transcoder isn't still depending on us */
1637         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1638
1639         reg = pll->pll_reg;
1640         val = I915_READ(reg);
1641         val &= ~DPLL_VCO_ENABLE;
1642         I915_WRITE(reg, val);
1643         POSTING_READ(reg);
1644         udelay(200);
1645
1646         pll->on = false;
1647 }
1648
1649 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650                                            enum pipe pipe)
1651 {
1652         struct drm_device *dev = dev_priv->dev;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654         uint32_t reg, val, pipeconf_val;
1655
1656         /* PCH only available on ILK+ */
1657         BUG_ON(dev_priv->info->gen < 5);
1658
1659         /* Make sure PCH DPLL is enabled */
1660         assert_pch_pll_enabled(dev_priv,
1661                                to_intel_crtc(crtc)->pch_pll,
1662                                to_intel_crtc(crtc));
1663
1664         /* FDI must be feeding us bits for PCH ports */
1665         assert_fdi_tx_enabled(dev_priv, pipe);
1666         assert_fdi_rx_enabled(dev_priv, pipe);
1667
1668         if (HAS_PCH_CPT(dev)) {
1669                 /* Workaround: Set the timing override bit before enabling the
1670                  * pch transcoder. */
1671                 reg = TRANS_CHICKEN2(pipe);
1672                 val = I915_READ(reg);
1673                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674                 I915_WRITE(reg, val);
1675         }
1676
1677         reg = TRANSCONF(pipe);
1678         val = I915_READ(reg);
1679         pipeconf_val = I915_READ(PIPECONF(pipe));
1680
1681         if (HAS_PCH_IBX(dev_priv->dev)) {
1682                 /*
1683                  * make the BPC in transcoder be consistent with
1684                  * that in pipeconf reg.
1685                  */
1686                 val &= ~PIPECONF_BPC_MASK;
1687                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1688         }
1689
1690         val &= ~TRANS_INTERLACE_MASK;
1691         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1692                 if (HAS_PCH_IBX(dev_priv->dev) &&
1693                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694                         val |= TRANS_LEGACY_INTERLACED_ILK;
1695                 else
1696                         val |= TRANS_INTERLACED;
1697         else
1698                 val |= TRANS_PROGRESSIVE;
1699
1700         I915_WRITE(reg, val | TRANS_ENABLE);
1701         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703 }
1704
1705 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706                                       enum transcoder cpu_transcoder)
1707 {
1708         u32 val, pipeconf_val;
1709
1710         /* PCH only available on ILK+ */
1711         BUG_ON(dev_priv->info->gen < 5);
1712
1713         /* FDI must be feeding us bits for PCH ports */
1714         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1716
1717         /* Workaround: set timing override bit. */
1718         val = I915_READ(_TRANSA_CHICKEN2);
1719         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720         I915_WRITE(_TRANSA_CHICKEN2, val);
1721
1722         val = TRANS_ENABLE;
1723         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1724
1725         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726             PIPECONF_INTERLACED_ILK)
1727                 val |= TRANS_INTERLACED;
1728         else
1729                 val |= TRANS_PROGRESSIVE;
1730
1731         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1732         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733                 DRM_ERROR("Failed to enable PCH transcoder\n");
1734 }
1735
1736 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737                                             enum pipe pipe)
1738 {
1739         struct drm_device *dev = dev_priv->dev;
1740         uint32_t reg, val;
1741
1742         /* FDI relies on the transcoder */
1743         assert_fdi_tx_disabled(dev_priv, pipe);
1744         assert_fdi_rx_disabled(dev_priv, pipe);
1745
1746         /* Ports must be off as well */
1747         assert_pch_ports_disabled(dev_priv, pipe);
1748
1749         reg = TRANSCONF(pipe);
1750         val = I915_READ(reg);
1751         val &= ~TRANS_ENABLE;
1752         I915_WRITE(reg, val);
1753         /* wait for PCH transcoder off, transcoder state */
1754         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1755                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1756
1757         if (!HAS_PCH_IBX(dev)) {
1758                 /* Workaround: Clear the timing override chicken bit again. */
1759                 reg = TRANS_CHICKEN2(pipe);
1760                 val = I915_READ(reg);
1761                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762                 I915_WRITE(reg, val);
1763         }
1764 }
1765
1766 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1767 {
1768         u32 val;
1769
1770         val = I915_READ(_TRANSACONF);
1771         val &= ~TRANS_ENABLE;
1772         I915_WRITE(_TRANSACONF, val);
1773         /* wait for PCH transcoder off, transcoder state */
1774         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775                 DRM_ERROR("Failed to disable PCH transcoder\n");
1776
1777         /* Workaround: clear timing override bit. */
1778         val = I915_READ(_TRANSA_CHICKEN2);
1779         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1780         I915_WRITE(_TRANSA_CHICKEN2, val);
1781 }
1782
1783 /**
1784  * intel_enable_pipe - enable a pipe, asserting requirements
1785  * @dev_priv: i915 private structure
1786  * @pipe: pipe to enable
1787  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1788  *
1789  * Enable @pipe, making sure that various hardware specific requirements
1790  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791  *
1792  * @pipe should be %PIPE_A or %PIPE_B.
1793  *
1794  * Will wait until the pipe is actually running (i.e. first vblank) before
1795  * returning.
1796  */
1797 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798                               bool pch_port)
1799 {
1800         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801                                                                       pipe);
1802         enum pipe pch_transcoder;
1803         int reg;
1804         u32 val;
1805
1806         if (HAS_PCH_LPT(dev_priv->dev))
1807                 pch_transcoder = TRANSCODER_A;
1808         else
1809                 pch_transcoder = pipe;
1810
1811         /*
1812          * A pipe without a PLL won't actually be able to drive bits from
1813          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1814          * need the check.
1815          */
1816         if (!HAS_PCH_SPLIT(dev_priv->dev))
1817                 assert_pll_enabled(dev_priv, pipe);
1818         else {
1819                 if (pch_port) {
1820                         /* if driving the PCH, we need FDI enabled */
1821                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1822                         assert_fdi_tx_pll_enabled(dev_priv,
1823                                                   (enum pipe) cpu_transcoder);
1824                 }
1825                 /* FIXME: assert CPU port conditions for SNB+ */
1826         }
1827
1828         reg = PIPECONF(cpu_transcoder);
1829         val = I915_READ(reg);
1830         if (val & PIPECONF_ENABLE)
1831                 return;
1832
1833         I915_WRITE(reg, val | PIPECONF_ENABLE);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_pipe - disable a pipe, asserting requirements
1839  * @dev_priv: i915 private structure
1840  * @pipe: pipe to disable
1841  *
1842  * Disable @pipe, making sure that various hardware specific requirements
1843  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844  *
1845  * @pipe should be %PIPE_A or %PIPE_B.
1846  *
1847  * Will wait until the pipe has shut down before returning.
1848  */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850                                enum pipe pipe)
1851 {
1852         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853                                                                       pipe);
1854         int reg;
1855         u32 val;
1856
1857         /*
1858          * Make sure planes won't keep trying to pump pixels to us,
1859          * or we might hang the display.
1860          */
1861         assert_planes_disabled(dev_priv, pipe);
1862
1863         /* Don't disable pipe A or pipe A PLLs if needed */
1864         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865                 return;
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if ((val & PIPECONF_ENABLE) == 0)
1870                 return;
1871
1872         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877  * Plane regs are double buffered, going from enabled->disabled needs a
1878  * trigger in order to latch.  The display address reg provides this.
1879  */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881                                       enum plane plane)
1882 {
1883         if (dev_priv->info->gen >= 4)
1884                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885         else
1886                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890  * intel_enable_plane - enable a display plane on a given pipe
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to enable
1893  * @pipe: pipe being fed
1894  *
1895  * Enable @plane on @pipe, making sure that @pipe is running first.
1896  */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898                                enum plane plane, enum pipe pipe)
1899 {
1900         int reg;
1901         u32 val;
1902
1903         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904         assert_pipe_enabled(dev_priv, pipe);
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if (val & DISPLAY_PLANE_ENABLE)
1909                 return;
1910
1911         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912         intel_flush_display_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917  * intel_disable_plane - disable a display plane
1918  * @dev_priv: i915 private structure
1919  * @plane: plane to disable
1920  * @pipe: pipe consuming the data
1921  *
1922  * Disable @plane; should be an independent operation.
1923  */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925                                 enum plane plane, enum pipe pipe)
1926 {
1927         int reg;
1928         u32 val;
1929
1930         reg = DSPCNTR(plane);
1931         val = I915_READ(reg);
1932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933                 return;
1934
1935         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936         intel_flush_display_plane(dev_priv, plane);
1937         intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942                            struct drm_i915_gem_object *obj,
1943                            struct intel_ring_buffer *pipelined)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         u32 alignment;
1947         int ret;
1948
1949         switch (obj->tiling_mode) {
1950         case I915_TILING_NONE:
1951                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952                         alignment = 128 * 1024;
1953                 else if (INTEL_INFO(dev)->gen >= 4)
1954                         alignment = 4 * 1024;
1955                 else
1956                         alignment = 64 * 1024;
1957                 break;
1958         case I915_TILING_X:
1959                 /* pin() will align the object as required by fence */
1960                 alignment = 0;
1961                 break;
1962         case I915_TILING_Y:
1963                 /* FIXME: Is this true? */
1964                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965                 return -EINVAL;
1966         default:
1967                 BUG();
1968         }
1969
1970         dev_priv->mm.interruptible = false;
1971         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972         if (ret)
1973                 goto err_interruptible;
1974
1975         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976          * fence, whereas 965+ only requires a fence if using
1977          * framebuffer compression.  For simplicity, we always install
1978          * a fence as the cost is not that onerous.
1979          */
1980         ret = i915_gem_object_get_fence(obj);
1981         if (ret)
1982                 goto err_unpin;
1983
1984         i915_gem_object_pin_fence(obj);
1985
1986         dev_priv->mm.interruptible = true;
1987         return 0;
1988
1989 err_unpin:
1990         i915_gem_object_unpin(obj);
1991 err_interruptible:
1992         dev_priv->mm.interruptible = true;
1993         return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998         i915_gem_object_unpin_fence(obj);
1999         i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003  * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2005                                              unsigned int tiling_mode,
2006                                              unsigned int cpp,
2007                                              unsigned int pitch)
2008 {
2009         if (tiling_mode != I915_TILING_NONE) {
2010                 unsigned int tile_rows, tiles;
2011
2012                 tile_rows = *y / 8;
2013                 *y %= 8;
2014
2015                 tiles = *x / (512/cpp);
2016                 *x %= 512/cpp;
2017
2018                 return tile_rows * pitch * 8 + tiles * 4096;
2019         } else {
2020                 unsigned int offset;
2021
2022                 offset = *y * pitch + *x * cpp;
2023                 *y = 0;
2024                 *x = (offset & 4095) / cpp;
2025                 return offset & -4096;
2026         }
2027 }
2028
2029 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2030                              int x, int y)
2031 {
2032         struct drm_device *dev = crtc->dev;
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2035         struct intel_framebuffer *intel_fb;
2036         struct drm_i915_gem_object *obj;
2037         int plane = intel_crtc->plane;
2038         unsigned long linear_offset;
2039         u32 dspcntr;
2040         u32 reg;
2041
2042         switch (plane) {
2043         case 0:
2044         case 1:
2045                 break;
2046         default:
2047                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2048                 return -EINVAL;
2049         }
2050
2051         intel_fb = to_intel_framebuffer(fb);
2052         obj = intel_fb->obj;
2053
2054         reg = DSPCNTR(plane);
2055         dspcntr = I915_READ(reg);
2056         /* Mask out pixel format bits in case we change it */
2057         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2058         switch (fb->pixel_format) {
2059         case DRM_FORMAT_C8:
2060                 dspcntr |= DISPPLANE_8BPP;
2061                 break;
2062         case DRM_FORMAT_XRGB1555:
2063         case DRM_FORMAT_ARGB1555:
2064                 dspcntr |= DISPPLANE_BGRX555;
2065                 break;
2066         case DRM_FORMAT_RGB565:
2067                 dspcntr |= DISPPLANE_BGRX565;
2068                 break;
2069         case DRM_FORMAT_XRGB8888:
2070         case DRM_FORMAT_ARGB8888:
2071                 dspcntr |= DISPPLANE_BGRX888;
2072                 break;
2073         case DRM_FORMAT_XBGR8888:
2074         case DRM_FORMAT_ABGR8888:
2075                 dspcntr |= DISPPLANE_RGBX888;
2076                 break;
2077         case DRM_FORMAT_XRGB2101010:
2078         case DRM_FORMAT_ARGB2101010:
2079                 dspcntr |= DISPPLANE_BGRX101010;
2080                 break;
2081         case DRM_FORMAT_XBGR2101010:
2082         case DRM_FORMAT_ABGR2101010:
2083                 dspcntr |= DISPPLANE_RGBX101010;
2084                 break;
2085         default:
2086                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2087                 return -EINVAL;
2088         }
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 if (obj->tiling_mode != I915_TILING_NONE)
2092                         dspcntr |= DISPPLANE_TILED;
2093                 else
2094                         dspcntr &= ~DISPPLANE_TILED;
2095         }
2096
2097         I915_WRITE(reg, dspcntr);
2098
2099         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2100
2101         if (INTEL_INFO(dev)->gen >= 4) {
2102                 intel_crtc->dspaddr_offset =
2103                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2104                                                        fb->bits_per_pixel / 8,
2105                                                        fb->pitches[0]);
2106                 linear_offset -= intel_crtc->dspaddr_offset;
2107         } else {
2108                 intel_crtc->dspaddr_offset = linear_offset;
2109         }
2110
2111         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2112                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2113         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2114         if (INTEL_INFO(dev)->gen >= 4) {
2115                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2116                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2117                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2118                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2119         } else
2120                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2121         POSTING_READ(reg);
2122
2123         return 0;
2124 }
2125
2126 static int ironlake_update_plane(struct drm_crtc *crtc,
2127                                  struct drm_framebuffer *fb, int x, int y)
2128 {
2129         struct drm_device *dev = crtc->dev;
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132         struct intel_framebuffer *intel_fb;
2133         struct drm_i915_gem_object *obj;
2134         int plane = intel_crtc->plane;
2135         unsigned long linear_offset;
2136         u32 dspcntr;
2137         u32 reg;
2138
2139         switch (plane) {
2140         case 0:
2141         case 1:
2142         case 2:
2143                 break;
2144         default:
2145                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2146                 return -EINVAL;
2147         }
2148
2149         intel_fb = to_intel_framebuffer(fb);
2150         obj = intel_fb->obj;
2151
2152         reg = DSPCNTR(plane);
2153         dspcntr = I915_READ(reg);
2154         /* Mask out pixel format bits in case we change it */
2155         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2156         switch (fb->pixel_format) {
2157         case DRM_FORMAT_C8:
2158                 dspcntr |= DISPPLANE_8BPP;
2159                 break;
2160         case DRM_FORMAT_RGB565:
2161                 dspcntr |= DISPPLANE_BGRX565;
2162                 break;
2163         case DRM_FORMAT_XRGB8888:
2164         case DRM_FORMAT_ARGB8888:
2165                 dspcntr |= DISPPLANE_BGRX888;
2166                 break;
2167         case DRM_FORMAT_XBGR8888:
2168         case DRM_FORMAT_ABGR8888:
2169                 dspcntr |= DISPPLANE_RGBX888;
2170                 break;
2171         case DRM_FORMAT_XRGB2101010:
2172         case DRM_FORMAT_ARGB2101010:
2173                 dspcntr |= DISPPLANE_BGRX101010;
2174                 break;
2175         case DRM_FORMAT_XBGR2101010:
2176         case DRM_FORMAT_ABGR2101010:
2177                 dspcntr |= DISPPLANE_RGBX101010;
2178                 break;
2179         default:
2180                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2181                 return -EINVAL;
2182         }
2183
2184         if (obj->tiling_mode != I915_TILING_NONE)
2185                 dspcntr |= DISPPLANE_TILED;
2186         else
2187                 dspcntr &= ~DISPPLANE_TILED;
2188
2189         /* must disable */
2190         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2191
2192         I915_WRITE(reg, dspcntr);
2193
2194         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2195         intel_crtc->dspaddr_offset =
2196                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2197                                                fb->bits_per_pixel / 8,
2198                                                fb->pitches[0]);
2199         linear_offset -= intel_crtc->dspaddr_offset;
2200
2201         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2202                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2203         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2204         I915_MODIFY_DISPBASE(DSPSURF(plane),
2205                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2206         if (IS_HASWELL(dev)) {
2207                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208         } else {
2209                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211         }
2212         POSTING_READ(reg);
2213
2214         return 0;
2215 }
2216
2217 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2218 static int
2219 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220                            int x, int y, enum mode_set_atomic state)
2221 {
2222         struct drm_device *dev = crtc->dev;
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224
2225         if (dev_priv->display.disable_fbc)
2226                 dev_priv->display.disable_fbc(dev);
2227         intel_increase_pllclock(crtc);
2228
2229         return dev_priv->display.update_plane(crtc, fb, x, y);
2230 }
2231
2232 static int
2233 intel_finish_fb(struct drm_framebuffer *old_fb)
2234 {
2235         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2236         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2237         bool was_interruptible = dev_priv->mm.interruptible;
2238         int ret;
2239
2240         /* Big Hammer, we also need to ensure that any pending
2241          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2242          * current scanout is retired before unpinning the old
2243          * framebuffer.
2244          *
2245          * This should only fail upon a hung GPU, in which case we
2246          * can safely continue.
2247          */
2248         dev_priv->mm.interruptible = false;
2249         ret = i915_gem_object_finish_gpu(obj);
2250         dev_priv->mm.interruptible = was_interruptible;
2251
2252         return ret;
2253 }
2254
2255 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2256 {
2257         struct drm_device *dev = crtc->dev;
2258         struct drm_i915_master_private *master_priv;
2259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260
2261         if (!dev->primary->master)
2262                 return;
2263
2264         master_priv = dev->primary->master->driver_priv;
2265         if (!master_priv->sarea_priv)
2266                 return;
2267
2268         switch (intel_crtc->pipe) {
2269         case 0:
2270                 master_priv->sarea_priv->pipeA_x = x;
2271                 master_priv->sarea_priv->pipeA_y = y;
2272                 break;
2273         case 1:
2274                 master_priv->sarea_priv->pipeB_x = x;
2275                 master_priv->sarea_priv->pipeB_y = y;
2276                 break;
2277         default:
2278                 break;
2279         }
2280 }
2281
2282 static int
2283 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2284                     struct drm_framebuffer *fb)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         struct drm_framebuffer *old_fb;
2290         int ret;
2291
2292         /* no fb bound */
2293         if (!fb) {
2294                 DRM_ERROR("No FB bound\n");
2295                 return 0;
2296         }
2297
2298         if(intel_crtc->plane > dev_priv->num_pipe) {
2299                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2300                                 intel_crtc->plane,
2301                                 dev_priv->num_pipe);
2302                 return -EINVAL;
2303         }
2304
2305         mutex_lock(&dev->struct_mutex);
2306         ret = intel_pin_and_fence_fb_obj(dev,
2307                                          to_intel_framebuffer(fb)->obj,
2308                                          NULL);
2309         if (ret != 0) {
2310                 mutex_unlock(&dev->struct_mutex);
2311                 DRM_ERROR("pin & fence failed\n");
2312                 return ret;
2313         }
2314
2315         if (crtc->fb)
2316                 intel_finish_fb(crtc->fb);
2317
2318         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2319         if (ret) {
2320                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("failed to update base address\n");
2323                 return ret;
2324         }
2325
2326         old_fb = crtc->fb;
2327         crtc->fb = fb;
2328         crtc->x = x;
2329         crtc->y = y;
2330
2331         if (old_fb) {
2332                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2333                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2334         }
2335
2336         intel_update_fbc(dev);
2337         mutex_unlock(&dev->struct_mutex);
2338
2339         intel_crtc_update_sarea_pos(crtc, x, y);
2340
2341         return 0;
2342 }
2343
2344 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2345 {
2346         struct drm_device *dev = crtc->dev;
2347         struct drm_i915_private *dev_priv = dev->dev_private;
2348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2349         int pipe = intel_crtc->pipe;
2350         u32 reg, temp;
2351
2352         /* enable normal train */
2353         reg = FDI_TX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (IS_IVYBRIDGE(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2357                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2361         }
2362         I915_WRITE(reg, temp);
2363
2364         reg = FDI_RX_CTL(pipe);
2365         temp = I915_READ(reg);
2366         if (HAS_PCH_CPT(dev)) {
2367                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2368                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2369         } else {
2370                 temp &= ~FDI_LINK_TRAIN_NONE;
2371                 temp |= FDI_LINK_TRAIN_NONE;
2372         }
2373         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2374
2375         /* wait one idle pattern time */
2376         POSTING_READ(reg);
2377         udelay(1000);
2378
2379         /* IVB wants error correction enabled */
2380         if (IS_IVYBRIDGE(dev))
2381                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2382                            FDI_FE_ERRC_ENABLE);
2383 }
2384
2385 static void ivb_modeset_global_resources(struct drm_device *dev)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct intel_crtc *pipe_B_crtc =
2389                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2390         struct intel_crtc *pipe_C_crtc =
2391                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2392         uint32_t temp;
2393
2394         /* When everything is off disable fdi C so that we could enable fdi B
2395          * with all lanes. XXX: This misses the case where a pipe is not using
2396          * any pch resources and so doesn't need any fdi lanes. */
2397         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2398                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2399                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2400
2401                 temp = I915_READ(SOUTH_CHICKEN1);
2402                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2403                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2404                 I915_WRITE(SOUTH_CHICKEN1, temp);
2405         }
2406 }
2407
2408 /* The FDI link training functions for ILK/Ibexpeak. */
2409 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2410 {
2411         struct drm_device *dev = crtc->dev;
2412         struct drm_i915_private *dev_priv = dev->dev_private;
2413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414         int pipe = intel_crtc->pipe;
2415         int plane = intel_crtc->plane;
2416         u32 reg, temp, tries;
2417
2418         /* FDI needs bits from pipe & plane first */
2419         assert_pipe_enabled(dev_priv, pipe);
2420         assert_plane_enabled(dev_priv, plane);
2421
2422         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2423            for train result */
2424         reg = FDI_RX_IMR(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_RX_SYMBOL_LOCK;
2427         temp &= ~FDI_RX_BIT_LOCK;
2428         I915_WRITE(reg, temp);
2429         I915_READ(reg);
2430         udelay(150);
2431
2432         /* enable CPU FDI TX and PCH FDI RX */
2433         reg = FDI_TX_CTL(pipe);
2434         temp = I915_READ(reg);
2435         temp &= ~(7 << 19);
2436         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2437         temp &= ~FDI_LINK_TRAIN_NONE;
2438         temp |= FDI_LINK_TRAIN_PATTERN_1;
2439         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_LINK_TRAIN_NONE;
2444         temp |= FDI_LINK_TRAIN_PATTERN_1;
2445         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         /* Ironlake workaround, enable clock pointer after FDI enable*/
2451         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2452         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2453                    FDI_RX_PHASE_SYNC_POINTER_EN);
2454
2455         reg = FDI_RX_IIR(pipe);
2456         for (tries = 0; tries < 5; tries++) {
2457                 temp = I915_READ(reg);
2458                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460                 if ((temp & FDI_RX_BIT_LOCK)) {
2461                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2462                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2463                         break;
2464                 }
2465         }
2466         if (tries == 5)
2467                 DRM_ERROR("FDI train 1 fail!\n");
2468
2469         /* Train 2 */
2470         reg = FDI_TX_CTL(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_LINK_TRAIN_NONE;
2473         temp |= FDI_LINK_TRAIN_PATTERN_2;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_NONE;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         reg = FDI_RX_IIR(pipe);
2486         for (tries = 0; tries < 5; tries++) {
2487                 temp = I915_READ(reg);
2488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490                 if (temp & FDI_RX_SYMBOL_LOCK) {
2491                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2492                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2493                         break;
2494                 }
2495         }
2496         if (tries == 5)
2497                 DRM_ERROR("FDI train 2 fail!\n");
2498
2499         DRM_DEBUG_KMS("FDI train done\n");
2500
2501 }
2502
2503 static const int snb_b_fdi_train_param[] = {
2504         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508 };
2509
2510 /* The FDI link training functions for SNB/Cougarpoint. */
2511 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp, i, retry;
2518
2519         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520            for train result */
2521         reg = FDI_RX_IMR(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_RX_SYMBOL_LOCK;
2524         temp &= ~FDI_RX_BIT_LOCK;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         /* enable CPU FDI TX and PCH FDI RX */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         temp &= ~(7 << 19);
2534         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_1;
2537         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538         /* SNB-B */
2539         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2540         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2541
2542         I915_WRITE(FDI_RX_MISC(pipe),
2543                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
2545         reg = FDI_RX_CTL(pipe);
2546         temp = I915_READ(reg);
2547         if (HAS_PCH_CPT(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550         } else {
2551                 temp &= ~FDI_LINK_TRAIN_NONE;
2552                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553         }
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         for (i = 0; i < 4; i++) {
2560                 reg = FDI_TX_CTL(pipe);
2561                 temp = I915_READ(reg);
2562                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563                 temp |= snb_b_fdi_train_param[i];
2564                 I915_WRITE(reg, temp);
2565
2566                 POSTING_READ(reg);
2567                 udelay(500);
2568
2569                 for (retry = 0; retry < 5; retry++) {
2570                         reg = FDI_RX_IIR(pipe);
2571                         temp = I915_READ(reg);
2572                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2573                         if (temp & FDI_RX_BIT_LOCK) {
2574                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2575                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2576                                 break;
2577                         }
2578                         udelay(50);
2579                 }
2580                 if (retry < 5)
2581                         break;
2582         }
2583         if (i == 4)
2584                 DRM_ERROR("FDI train 1 fail!\n");
2585
2586         /* Train 2 */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~FDI_LINK_TRAIN_NONE;
2590         temp |= FDI_LINK_TRAIN_PATTERN_2;
2591         if (IS_GEN6(dev)) {
2592                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2593                 /* SNB-B */
2594                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595         }
2596         I915_WRITE(reg, temp);
2597
2598         reg = FDI_RX_CTL(pipe);
2599         temp = I915_READ(reg);
2600         if (HAS_PCH_CPT(dev)) {
2601                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2602                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2603         } else {
2604                 temp &= ~FDI_LINK_TRAIN_NONE;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2606         }
2607         I915_WRITE(reg, temp);
2608
2609         POSTING_READ(reg);
2610         udelay(150);
2611
2612         for (i = 0; i < 4; i++) {
2613                 reg = FDI_TX_CTL(pipe);
2614                 temp = I915_READ(reg);
2615                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616                 temp |= snb_b_fdi_train_param[i];
2617                 I915_WRITE(reg, temp);
2618
2619                 POSTING_READ(reg);
2620                 udelay(500);
2621
2622                 for (retry = 0; retry < 5; retry++) {
2623                         reg = FDI_RX_IIR(pipe);
2624                         temp = I915_READ(reg);
2625                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626                         if (temp & FDI_RX_SYMBOL_LOCK) {
2627                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2628                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2629                                 break;
2630                         }
2631                         udelay(50);
2632                 }
2633                 if (retry < 5)
2634                         break;
2635         }
2636         if (i == 4)
2637                 DRM_ERROR("FDI train 2 fail!\n");
2638
2639         DRM_DEBUG_KMS("FDI train done.\n");
2640 }
2641
2642 /* Manual link training for Ivy Bridge A0 parts */
2643 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2644 {
2645         struct drm_device *dev = crtc->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648         int pipe = intel_crtc->pipe;
2649         u32 reg, temp, i;
2650
2651         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2652            for train result */
2653         reg = FDI_RX_IMR(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_RX_SYMBOL_LOCK;
2656         temp &= ~FDI_RX_BIT_LOCK;
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2663                       I915_READ(FDI_RX_IIR(pipe)));
2664
2665         /* enable CPU FDI TX and PCH FDI RX */
2666         reg = FDI_TX_CTL(pipe);
2667         temp = I915_READ(reg);
2668         temp &= ~(7 << 19);
2669         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2670         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2671         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2672         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674         temp |= FDI_COMPOSITE_SYNC;
2675         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2676
2677         I915_WRITE(FDI_RX_MISC(pipe),
2678                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2679
2680         reg = FDI_RX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         temp &= ~FDI_LINK_TRAIN_AUTO;
2683         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2685         temp |= FDI_COMPOSITE_SYNC;
2686         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2687
2688         POSTING_READ(reg);
2689         udelay(150);
2690
2691         for (i = 0; i < 4; i++) {
2692                 reg = FDI_TX_CTL(pipe);
2693                 temp = I915_READ(reg);
2694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695                 temp |= snb_b_fdi_train_param[i];
2696                 I915_WRITE(reg, temp);
2697
2698                 POSTING_READ(reg);
2699                 udelay(500);
2700
2701                 reg = FDI_RX_IIR(pipe);
2702                 temp = I915_READ(reg);
2703                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2704
2705                 if (temp & FDI_RX_BIT_LOCK ||
2706                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2707                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2708                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2709                         break;
2710                 }
2711         }
2712         if (i == 4)
2713                 DRM_ERROR("FDI train 1 fail!\n");
2714
2715         /* Train 2 */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2719         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2720         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2721         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2722         I915_WRITE(reg, temp);
2723
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2727         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2728         I915_WRITE(reg, temp);
2729
2730         POSTING_READ(reg);
2731         udelay(150);
2732
2733         for (i = 0; i < 4; i++) {
2734                 reg = FDI_TX_CTL(pipe);
2735                 temp = I915_READ(reg);
2736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737                 temp |= snb_b_fdi_train_param[i];
2738                 I915_WRITE(reg, temp);
2739
2740                 POSTING_READ(reg);
2741                 udelay(500);
2742
2743                 reg = FDI_RX_IIR(pipe);
2744                 temp = I915_READ(reg);
2745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747                 if (temp & FDI_RX_SYMBOL_LOCK) {
2748                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2749                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2750                         break;
2751                 }
2752         }
2753         if (i == 4)
2754                 DRM_ERROR("FDI train 2 fail!\n");
2755
2756         DRM_DEBUG_KMS("FDI train done.\n");
2757 }
2758
2759 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2760 {
2761         struct drm_device *dev = intel_crtc->base.dev;
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         int pipe = intel_crtc->pipe;
2764         u32 reg, temp;
2765
2766
2767         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         temp &= ~((0x7 << 19) | (0x7 << 16));
2771         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2772         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2773         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2774
2775         POSTING_READ(reg);
2776         udelay(200);
2777
2778         /* Switch from Rawclk to PCDclk */
2779         temp = I915_READ(reg);
2780         I915_WRITE(reg, temp | FDI_PCDCLK);
2781
2782         POSTING_READ(reg);
2783         udelay(200);
2784
2785         /* Enable CPU FDI TX PLL, always on for Ironlake */
2786         reg = FDI_TX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2789                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2790
2791                 POSTING_READ(reg);
2792                 udelay(100);
2793         }
2794 }
2795
2796 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2797 {
2798         struct drm_device *dev = intel_crtc->base.dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         int pipe = intel_crtc->pipe;
2801         u32 reg, temp;
2802
2803         /* Switch from PCDclk to Rawclk */
2804         reg = FDI_RX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2807
2808         /* Disable CPU FDI TX PLL */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2812
2813         POSTING_READ(reg);
2814         udelay(100);
2815
2816         reg = FDI_RX_CTL(pipe);
2817         temp = I915_READ(reg);
2818         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2819
2820         /* Wait for the clocks to turn off. */
2821         POSTING_READ(reg);
2822         udelay(100);
2823 }
2824
2825 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2826 {
2827         struct drm_device *dev = crtc->dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830         int pipe = intel_crtc->pipe;
2831         u32 reg, temp;
2832
2833         /* disable CPU FDI tx and PCH FDI rx */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2837         POSTING_READ(reg);
2838
2839         reg = FDI_RX_CTL(pipe);
2840         temp = I915_READ(reg);
2841         temp &= ~(0x7 << 16);
2842         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2843         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2844
2845         POSTING_READ(reg);
2846         udelay(100);
2847
2848         /* Ironlake workaround, disable clock pointer after downing FDI */
2849         if (HAS_PCH_IBX(dev)) {
2850                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2851         }
2852
2853         /* still set train pattern 1 */
2854         reg = FDI_TX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         temp &= ~FDI_LINK_TRAIN_NONE;
2857         temp |= FDI_LINK_TRAIN_PATTERN_1;
2858         I915_WRITE(reg, temp);
2859
2860         reg = FDI_RX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         if (HAS_PCH_CPT(dev)) {
2863                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2865         } else {
2866                 temp &= ~FDI_LINK_TRAIN_NONE;
2867                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2868         }
2869         /* BPC in FDI rx is consistent with that in PIPECONF */
2870         temp &= ~(0x07 << 16);
2871         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2872         I915_WRITE(reg, temp);
2873
2874         POSTING_READ(reg);
2875         udelay(100);
2876 }
2877
2878 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2879 {
2880         struct drm_device *dev = crtc->dev;
2881         struct drm_i915_private *dev_priv = dev->dev_private;
2882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2883         unsigned long flags;
2884         bool pending;
2885
2886         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2887             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2888                 return false;
2889
2890         spin_lock_irqsave(&dev->event_lock, flags);
2891         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2892         spin_unlock_irqrestore(&dev->event_lock, flags);
2893
2894         return pending;
2895 }
2896
2897 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2898 {
2899         struct drm_device *dev = crtc->dev;
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901
2902         if (crtc->fb == NULL)
2903                 return;
2904
2905         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2906
2907         wait_event(dev_priv->pending_flip_queue,
2908                    !intel_crtc_has_pending_flip(crtc));
2909
2910         mutex_lock(&dev->struct_mutex);
2911         intel_finish_fb(crtc->fb);
2912         mutex_unlock(&dev->struct_mutex);
2913 }
2914
2915 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2916 {
2917         struct drm_device *dev = crtc->dev;
2918         struct intel_encoder *intel_encoder;
2919
2920         /*
2921          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2922          * must be driven by its own crtc; no sharing is possible.
2923          */
2924         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2925                 switch (intel_encoder->type) {
2926                 case INTEL_OUTPUT_EDP:
2927                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2928                                 return false;
2929                         continue;
2930                 }
2931         }
2932
2933         return true;
2934 }
2935
2936 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2937 {
2938         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2939 }
2940
2941 /* Program iCLKIP clock to the desired frequency */
2942 static void lpt_program_iclkip(struct drm_crtc *crtc)
2943 {
2944         struct drm_device *dev = crtc->dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2947         u32 temp;
2948
2949         mutex_lock(&dev_priv->dpio_lock);
2950
2951         /* It is necessary to ungate the pixclk gate prior to programming
2952          * the divisors, and gate it back when it is done.
2953          */
2954         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2955
2956         /* Disable SSCCTL */
2957         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2958                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2959                                 SBI_SSCCTL_DISABLE,
2960                         SBI_ICLK);
2961
2962         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2963         if (crtc->mode.clock == 20000) {
2964                 auxdiv = 1;
2965                 divsel = 0x41;
2966                 phaseinc = 0x20;
2967         } else {
2968                 /* The iCLK virtual clock root frequency is in MHz,
2969                  * but the crtc->mode.clock in in KHz. To get the divisors,
2970                  * it is necessary to divide one by another, so we
2971                  * convert the virtual clock precision to KHz here for higher
2972                  * precision.
2973                  */
2974                 u32 iclk_virtual_root_freq = 172800 * 1000;
2975                 u32 iclk_pi_range = 64;
2976                 u32 desired_divisor, msb_divisor_value, pi_value;
2977
2978                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2979                 msb_divisor_value = desired_divisor / iclk_pi_range;
2980                 pi_value = desired_divisor % iclk_pi_range;
2981
2982                 auxdiv = 0;
2983                 divsel = msb_divisor_value - 2;
2984                 phaseinc = pi_value;
2985         }
2986
2987         /* This should not happen with any sane values */
2988         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2989                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2990         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2991                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2992
2993         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2994                         crtc->mode.clock,
2995                         auxdiv,
2996                         divsel,
2997                         phasedir,
2998                         phaseinc);
2999
3000         /* Program SSCDIVINTPHASE6 */
3001         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3002         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3003         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3004         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3005         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3006         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3007         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3008         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3009
3010         /* Program SSCAUXDIV */
3011         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3012         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3013         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3014         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3015
3016         /* Enable modulator and associated divider */
3017         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3018         temp &= ~SBI_SSCCTL_DISABLE;
3019         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3020
3021         /* Wait for initialization time */
3022         udelay(24);
3023
3024         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3025
3026         mutex_unlock(&dev_priv->dpio_lock);
3027 }
3028
3029 /*
3030  * Enable PCH resources required for PCH ports:
3031  *   - PCH PLLs
3032  *   - FDI training & RX/TX
3033  *   - update transcoder timings
3034  *   - DP transcoding bits
3035  *   - transcoder
3036  */
3037 static void ironlake_pch_enable(struct drm_crtc *crtc)
3038 {
3039         struct drm_device *dev = crtc->dev;
3040         struct drm_i915_private *dev_priv = dev->dev_private;
3041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042         int pipe = intel_crtc->pipe;
3043         u32 reg, temp;
3044
3045         assert_transcoder_disabled(dev_priv, pipe);
3046
3047         /* Write the TU size bits before fdi link training, so that error
3048          * detection works. */
3049         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3050                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3051
3052         /* For PCH output, training FDI link */
3053         dev_priv->display.fdi_link_train(crtc);
3054
3055         /* XXX: pch pll's can be enabled any time before we enable the PCH
3056          * transcoder, and we actually should do this to not upset any PCH
3057          * transcoder that already use the clock when we share it.
3058          *
3059          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3060          * unconditionally resets the pll - we need that to have the right LVDS
3061          * enable sequence. */
3062         ironlake_enable_pch_pll(intel_crtc);
3063
3064         if (HAS_PCH_CPT(dev)) {
3065                 u32 sel;
3066
3067                 temp = I915_READ(PCH_DPLL_SEL);
3068                 switch (pipe) {
3069                 default:
3070                 case 0:
3071                         temp |= TRANSA_DPLL_ENABLE;
3072                         sel = TRANSA_DPLLB_SEL;
3073                         break;
3074                 case 1:
3075                         temp |= TRANSB_DPLL_ENABLE;
3076                         sel = TRANSB_DPLLB_SEL;
3077                         break;
3078                 case 2:
3079                         temp |= TRANSC_DPLL_ENABLE;
3080                         sel = TRANSC_DPLLB_SEL;
3081                         break;
3082                 }
3083                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3084                         temp |= sel;
3085                 else
3086                         temp &= ~sel;
3087                 I915_WRITE(PCH_DPLL_SEL, temp);
3088         }
3089
3090         /* set transcoder timing, panel must allow it */
3091         assert_panel_unlocked(dev_priv, pipe);
3092         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3093         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3094         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3095
3096         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3097         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3098         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3099         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3100
3101         intel_fdi_normal_train(crtc);
3102
3103         /* For PCH DP, enable TRANS_DP_CTL */
3104         if (HAS_PCH_CPT(dev) &&
3105             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3106              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3107                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3108                 reg = TRANS_DP_CTL(pipe);
3109                 temp = I915_READ(reg);
3110                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3111                           TRANS_DP_SYNC_MASK |
3112                           TRANS_DP_BPC_MASK);
3113                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3114                          TRANS_DP_ENH_FRAMING);
3115                 temp |= bpc << 9; /* same format but at 11:9 */
3116
3117                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3118                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3119                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3120                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3121
3122                 switch (intel_trans_dp_port_sel(crtc)) {
3123                 case PCH_DP_B:
3124                         temp |= TRANS_DP_PORT_SEL_B;
3125                         break;
3126                 case PCH_DP_C:
3127                         temp |= TRANS_DP_PORT_SEL_C;
3128                         break;
3129                 case PCH_DP_D:
3130                         temp |= TRANS_DP_PORT_SEL_D;
3131                         break;
3132                 default:
3133                         BUG();
3134                 }
3135
3136                 I915_WRITE(reg, temp);
3137         }
3138
3139         ironlake_enable_pch_transcoder(dev_priv, pipe);
3140 }
3141
3142 static void lpt_pch_enable(struct drm_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3148
3149         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3150
3151         lpt_program_iclkip(crtc);
3152
3153         /* Set transcoder timing. */
3154         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3155         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3156         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3157
3158         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3159         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3160         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3161         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3162
3163         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3164 }
3165
3166 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3167 {
3168         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3169
3170         if (pll == NULL)
3171                 return;
3172
3173         if (pll->refcount == 0) {
3174                 WARN(1, "bad PCH PLL refcount\n");
3175                 return;
3176         }
3177
3178         --pll->refcount;
3179         intel_crtc->pch_pll = NULL;
3180 }
3181
3182 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3183 {
3184         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3185         struct intel_pch_pll *pll;
3186         int i;
3187
3188         pll = intel_crtc->pch_pll;
3189         if (pll) {
3190                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3191                               intel_crtc->base.base.id, pll->pll_reg);
3192                 goto prepare;
3193         }
3194
3195         if (HAS_PCH_IBX(dev_priv->dev)) {
3196                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3197                 i = intel_crtc->pipe;
3198                 pll = &dev_priv->pch_plls[i];
3199
3200                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3201                               intel_crtc->base.base.id, pll->pll_reg);
3202
3203                 goto found;
3204         }
3205
3206         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3207                 pll = &dev_priv->pch_plls[i];
3208
3209                 /* Only want to check enabled timings first */
3210                 if (pll->refcount == 0)
3211                         continue;
3212
3213                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3214                     fp == I915_READ(pll->fp0_reg)) {
3215                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3216                                       intel_crtc->base.base.id,
3217                                       pll->pll_reg, pll->refcount, pll->active);
3218
3219                         goto found;
3220                 }
3221         }
3222
3223         /* Ok no matching timings, maybe there's a free one? */
3224         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3225                 pll = &dev_priv->pch_plls[i];
3226                 if (pll->refcount == 0) {
3227                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3228                                       intel_crtc->base.base.id, pll->pll_reg);
3229                         goto found;
3230                 }
3231         }
3232
3233         return NULL;
3234
3235 found:
3236         intel_crtc->pch_pll = pll;
3237         pll->refcount++;
3238         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3239 prepare: /* separate function? */
3240         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3241
3242         /* Wait for the clocks to stabilize before rewriting the regs */
3243         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3244         POSTING_READ(pll->pll_reg);
3245         udelay(150);
3246
3247         I915_WRITE(pll->fp0_reg, fp);
3248         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3249         pll->on = false;
3250         return pll;
3251 }
3252
3253 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3254 {
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         int dslreg = PIPEDSL(pipe);
3257         u32 temp;
3258
3259         temp = I915_READ(dslreg);
3260         udelay(500);
3261         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3262                 if (wait_for(I915_READ(dslreg) != temp, 5))
3263                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3264         }
3265 }
3266
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268 {
3269         struct drm_device *dev = crtc->dev;
3270         struct drm_i915_private *dev_priv = dev->dev_private;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         struct intel_encoder *encoder;
3273         int pipe = intel_crtc->pipe;
3274         int plane = intel_crtc->plane;
3275         u32 temp;
3276         bool is_pch_port;
3277
3278         WARN_ON(!crtc->enabled);
3279
3280         if (intel_crtc->active)
3281                 return;
3282
3283         intel_crtc->active = true;
3284         intel_update_watermarks(dev);
3285
3286         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3287                 temp = I915_READ(PCH_LVDS);
3288                 if ((temp & LVDS_PORT_EN) == 0)
3289                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3290         }
3291
3292         is_pch_port = ironlake_crtc_driving_pch(crtc);
3293
3294         if (is_pch_port) {
3295                 /* Note: FDI PLL enabling _must_ be done before we enable the
3296                  * cpu pipes, hence this is separate from all the other fdi/pch
3297                  * enabling. */
3298                 ironlake_fdi_pll_enable(intel_crtc);
3299         } else {
3300                 assert_fdi_tx_disabled(dev_priv, pipe);
3301                 assert_fdi_rx_disabled(dev_priv, pipe);
3302         }
3303
3304         for_each_encoder_on_crtc(dev, crtc, encoder)
3305                 if (encoder->pre_enable)
3306                         encoder->pre_enable(encoder);
3307
3308         /* Enable panel fitting for LVDS */
3309         if (dev_priv->pch_pf_size &&
3310             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3311              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3312                 /* Force use of hard-coded filter coefficients
3313                  * as some pre-programmed values are broken,
3314                  * e.g. x201.
3315                  */
3316                 if (IS_IVYBRIDGE(dev))
3317                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3318                                                  PF_PIPE_SEL_IVB(pipe));
3319                 else
3320                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3321                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3322                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3323         }
3324
3325         /*
3326          * On ILK+ LUT must be loaded before the pipe is running but with
3327          * clocks enabled
3328          */
3329         intel_crtc_load_lut(crtc);
3330
3331         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3332         intel_enable_plane(dev_priv, plane, pipe);
3333
3334         if (is_pch_port)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         intel_crtc_update_cursor(crtc, true);
3342
3343         for_each_encoder_on_crtc(dev, crtc, encoder)
3344                 encoder->enable(encoder);
3345
3346         if (HAS_PCH_CPT(dev))
3347                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3348
3349         /*
3350          * There seems to be a race in PCH platform hw (at least on some
3351          * outputs) where an enabled pipe still completes any pageflip right
3352          * away (as if the pipe is off) instead of waiting for vblank. As soon
3353          * as the first vblank happend, everything works as expected. Hence just
3354          * wait for one vblank before returning to avoid strange things
3355          * happening.
3356          */
3357         intel_wait_for_vblank(dev, intel_crtc->pipe);
3358 }
3359
3360 static void haswell_crtc_enable(struct drm_crtc *crtc)
3361 {
3362         struct drm_device *dev = crtc->dev;
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         struct intel_encoder *encoder;
3366         int pipe = intel_crtc->pipe;
3367         int plane = intel_crtc->plane;
3368         bool is_pch_port;
3369
3370         WARN_ON(!crtc->enabled);
3371
3372         if (intel_crtc->active)
3373                 return;
3374
3375         intel_crtc->active = true;
3376         intel_update_watermarks(dev);
3377
3378         is_pch_port = haswell_crtc_driving_pch(crtc);
3379
3380         if (is_pch_port)
3381                 dev_priv->display.fdi_link_train(crtc);
3382
3383         for_each_encoder_on_crtc(dev, crtc, encoder)
3384                 if (encoder->pre_enable)
3385                         encoder->pre_enable(encoder);
3386
3387         intel_ddi_enable_pipe_clock(intel_crtc);
3388
3389         /* Enable panel fitting for eDP */
3390         if (dev_priv->pch_pf_size &&
3391             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3392                 /* Force use of hard-coded filter coefficients
3393                  * as some pre-programmed values are broken,
3394                  * e.g. x201.
3395                  */
3396                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3397                                          PF_PIPE_SEL_IVB(pipe));
3398                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3400         }
3401
3402         /*
3403          * On ILK+ LUT must be loaded before the pipe is running but with
3404          * clocks enabled
3405          */
3406         intel_crtc_load_lut(crtc);
3407
3408         intel_ddi_set_pipe_settings(crtc);
3409         intel_ddi_enable_pipe_func(crtc);
3410
3411         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3412         intel_enable_plane(dev_priv, plane, pipe);
3413
3414         if (is_pch_port)
3415                 lpt_pch_enable(crtc);
3416
3417         mutex_lock(&dev->struct_mutex);
3418         intel_update_fbc(dev);
3419         mutex_unlock(&dev->struct_mutex);
3420
3421         intel_crtc_update_cursor(crtc, true);
3422
3423         for_each_encoder_on_crtc(dev, crtc, encoder)
3424                 encoder->enable(encoder);
3425
3426         /*
3427          * There seems to be a race in PCH platform hw (at least on some
3428          * outputs) where an enabled pipe still completes any pageflip right
3429          * away (as if the pipe is off) instead of waiting for vblank. As soon
3430          * as the first vblank happend, everything works as expected. Hence just
3431          * wait for one vblank before returning to avoid strange things
3432          * happening.
3433          */
3434         intel_wait_for_vblank(dev, intel_crtc->pipe);
3435 }
3436
3437 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442         struct intel_encoder *encoder;
3443         int pipe = intel_crtc->pipe;
3444         int plane = intel_crtc->plane;
3445         u32 reg, temp;
3446
3447
3448         if (!intel_crtc->active)
3449                 return;
3450
3451         for_each_encoder_on_crtc(dev, crtc, encoder)
3452                 encoder->disable(encoder);
3453
3454         intel_crtc_wait_for_pending_flips(crtc);
3455         drm_vblank_off(dev, pipe);
3456         intel_crtc_update_cursor(crtc, false);
3457
3458         intel_disable_plane(dev_priv, plane, pipe);
3459
3460         if (dev_priv->cfb_plane == plane)
3461                 intel_disable_fbc(dev);
3462
3463         intel_disable_pipe(dev_priv, pipe);
3464
3465         /* Disable PF */
3466         I915_WRITE(PF_CTL(pipe), 0);
3467         I915_WRITE(PF_WIN_SZ(pipe), 0);
3468
3469         for_each_encoder_on_crtc(dev, crtc, encoder)
3470                 if (encoder->post_disable)
3471                         encoder->post_disable(encoder);
3472
3473         ironlake_fdi_disable(crtc);
3474
3475         ironlake_disable_pch_transcoder(dev_priv, pipe);
3476
3477         if (HAS_PCH_CPT(dev)) {
3478                 /* disable TRANS_DP_CTL */
3479                 reg = TRANS_DP_CTL(pipe);
3480                 temp = I915_READ(reg);
3481                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3482                 temp |= TRANS_DP_PORT_SEL_NONE;
3483                 I915_WRITE(reg, temp);
3484
3485                 /* disable DPLL_SEL */
3486                 temp = I915_READ(PCH_DPLL_SEL);
3487                 switch (pipe) {
3488                 case 0:
3489                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3490                         break;
3491                 case 1:
3492                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3493                         break;
3494                 case 2:
3495                         /* C shares PLL A or B */
3496                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3497                         break;
3498                 default:
3499                         BUG(); /* wtf */
3500                 }
3501                 I915_WRITE(PCH_DPLL_SEL, temp);
3502         }
3503
3504         /* disable PCH DPLL */
3505         intel_disable_pch_pll(intel_crtc);
3506
3507         ironlake_fdi_pll_disable(intel_crtc);
3508
3509         intel_crtc->active = false;
3510         intel_update_watermarks(dev);
3511
3512         mutex_lock(&dev->struct_mutex);
3513         intel_update_fbc(dev);
3514         mutex_unlock(&dev->struct_mutex);
3515 }
3516
3517 static void haswell_crtc_disable(struct drm_crtc *crtc)
3518 {
3519         struct drm_device *dev = crtc->dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522         struct intel_encoder *encoder;
3523         int pipe = intel_crtc->pipe;
3524         int plane = intel_crtc->plane;
3525         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3526         bool is_pch_port;
3527
3528         if (!intel_crtc->active)
3529                 return;
3530
3531         is_pch_port = haswell_crtc_driving_pch(crtc);
3532
3533         for_each_encoder_on_crtc(dev, crtc, encoder)
3534                 encoder->disable(encoder);
3535
3536         intel_crtc_wait_for_pending_flips(crtc);
3537         drm_vblank_off(dev, pipe);
3538         intel_crtc_update_cursor(crtc, false);
3539
3540         intel_disable_plane(dev_priv, plane, pipe);
3541
3542         if (dev_priv->cfb_plane == plane)
3543                 intel_disable_fbc(dev);
3544
3545         intel_disable_pipe(dev_priv, pipe);
3546
3547         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3548
3549         /* Disable PF */
3550         I915_WRITE(PF_CTL(pipe), 0);
3551         I915_WRITE(PF_WIN_SZ(pipe), 0);
3552
3553         intel_ddi_disable_pipe_clock(intel_crtc);
3554
3555         for_each_encoder_on_crtc(dev, crtc, encoder)
3556                 if (encoder->post_disable)
3557                         encoder->post_disable(encoder);
3558
3559         if (is_pch_port) {
3560                 lpt_disable_pch_transcoder(dev_priv);
3561                 intel_ddi_fdi_disable(crtc);
3562         }
3563
3564         intel_crtc->active = false;
3565         intel_update_watermarks(dev);
3566
3567         mutex_lock(&dev->struct_mutex);
3568         intel_update_fbc(dev);
3569         mutex_unlock(&dev->struct_mutex);
3570 }
3571
3572 static void ironlake_crtc_off(struct drm_crtc *crtc)
3573 {
3574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575         intel_put_pch_pll(intel_crtc);
3576 }
3577
3578 static void haswell_crtc_off(struct drm_crtc *crtc)
3579 {
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581
3582         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3583          * start using it. */
3584         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3585
3586         intel_ddi_put_crtc_pll(crtc);
3587 }
3588
3589 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3590 {
3591         if (!enable && intel_crtc->overlay) {
3592                 struct drm_device *dev = intel_crtc->base.dev;
3593                 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595                 mutex_lock(&dev->struct_mutex);
3596                 dev_priv->mm.interruptible = false;
3597                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3598                 dev_priv->mm.interruptible = true;
3599                 mutex_unlock(&dev->struct_mutex);
3600         }
3601
3602         /* Let userspace switch the overlay on again. In most cases userspace
3603          * has to recompute where to put it anyway.
3604          */
3605 }
3606
3607 /**
3608  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3609  * cursor plane briefly if not already running after enabling the display
3610  * plane.
3611  * This workaround avoids occasional blank screens when self refresh is
3612  * enabled.
3613  */
3614 static void
3615 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3616 {
3617         u32 cntl = I915_READ(CURCNTR(pipe));
3618
3619         if ((cntl & CURSOR_MODE) == 0) {
3620                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3621
3622                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3623                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3624                 intel_wait_for_vblank(dev_priv->dev, pipe);
3625                 I915_WRITE(CURCNTR(pipe), cntl);
3626                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3627                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3628         }
3629 }
3630
3631 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3632 {
3633         struct drm_device *dev = crtc->dev;
3634         struct drm_i915_private *dev_priv = dev->dev_private;
3635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3636         struct intel_encoder *encoder;
3637         int pipe = intel_crtc->pipe;
3638         int plane = intel_crtc->plane;
3639
3640         WARN_ON(!crtc->enabled);
3641
3642         if (intel_crtc->active)
3643                 return;
3644
3645         intel_crtc->active = true;
3646         intel_update_watermarks(dev);
3647
3648         intel_enable_pll(dev_priv, pipe);
3649
3650         for_each_encoder_on_crtc(dev, crtc, encoder)
3651                 if (encoder->pre_enable)
3652                         encoder->pre_enable(encoder);
3653
3654         intel_enable_pipe(dev_priv, pipe, false);
3655         intel_enable_plane(dev_priv, plane, pipe);
3656         if (IS_G4X(dev))
3657                 g4x_fixup_plane(dev_priv, pipe);
3658
3659         intel_crtc_load_lut(crtc);
3660         intel_update_fbc(dev);
3661
3662         /* Give the overlay scaler a chance to enable if it's on this pipe */
3663         intel_crtc_dpms_overlay(intel_crtc, true);
3664         intel_crtc_update_cursor(crtc, true);
3665
3666         for_each_encoder_on_crtc(dev, crtc, encoder)
3667                 encoder->enable(encoder);
3668 }
3669
3670 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3671 {
3672         struct drm_device *dev = crtc->dev;
3673         struct drm_i915_private *dev_priv = dev->dev_private;
3674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675         struct intel_encoder *encoder;
3676         int pipe = intel_crtc->pipe;
3677         int plane = intel_crtc->plane;
3678         u32 pctl;
3679
3680
3681         if (!intel_crtc->active)
3682                 return;
3683
3684         for_each_encoder_on_crtc(dev, crtc, encoder)
3685                 encoder->disable(encoder);
3686
3687         /* Give the overlay scaler a chance to disable if it's on this pipe */
3688         intel_crtc_wait_for_pending_flips(crtc);
3689         drm_vblank_off(dev, pipe);
3690         intel_crtc_dpms_overlay(intel_crtc, false);
3691         intel_crtc_update_cursor(crtc, false);
3692
3693         if (dev_priv->cfb_plane == plane)
3694                 intel_disable_fbc(dev);
3695
3696         intel_disable_plane(dev_priv, plane, pipe);
3697         intel_disable_pipe(dev_priv, pipe);
3698
3699         /* Disable pannel fitter if it is on this pipe. */
3700         pctl = I915_READ(PFIT_CONTROL);
3701         if ((pctl & PFIT_ENABLE) &&
3702             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3703                 I915_WRITE(PFIT_CONTROL, 0);
3704
3705         intel_disable_pll(dev_priv, pipe);
3706
3707         intel_crtc->active = false;
3708         intel_update_fbc(dev);
3709         intel_update_watermarks(dev);
3710 }
3711
3712 static void i9xx_crtc_off(struct drm_crtc *crtc)
3713 {
3714 }
3715
3716 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3717                                     bool enabled)
3718 {
3719         struct drm_device *dev = crtc->dev;
3720         struct drm_i915_master_private *master_priv;
3721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3722         int pipe = intel_crtc->pipe;
3723
3724         if (!dev->primary->master)
3725                 return;
3726
3727         master_priv = dev->primary->master->driver_priv;
3728         if (!master_priv->sarea_priv)
3729                 return;
3730
3731         switch (pipe) {
3732         case 0:
3733                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3734                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3735                 break;
3736         case 1:
3737                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3738                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3739                 break;
3740         default:
3741                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3742                 break;
3743         }
3744 }
3745
3746 /**
3747  * Sets the power management mode of the pipe and plane.
3748  */
3749 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3750 {
3751         struct drm_device *dev = crtc->dev;
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         struct intel_encoder *intel_encoder;
3754         bool enable = false;
3755
3756         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3757                 enable |= intel_encoder->connectors_active;
3758
3759         if (enable)
3760                 dev_priv->display.crtc_enable(crtc);
3761         else
3762                 dev_priv->display.crtc_disable(crtc);
3763
3764         intel_crtc_update_sarea(crtc, enable);
3765 }
3766
3767 static void intel_crtc_disable(struct drm_crtc *crtc)
3768 {
3769         struct drm_device *dev = crtc->dev;
3770         struct drm_connector *connector;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773
3774         /* crtc should still be enabled when we disable it. */
3775         WARN_ON(!crtc->enabled);
3776
3777         intel_crtc->eld_vld = false;
3778         dev_priv->display.crtc_disable(crtc);
3779         intel_crtc_update_sarea(crtc, false);
3780         dev_priv->display.off(crtc);
3781
3782         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3783         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3784
3785         if (crtc->fb) {
3786                 mutex_lock(&dev->struct_mutex);
3787                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3788                 mutex_unlock(&dev->struct_mutex);
3789                 crtc->fb = NULL;
3790         }
3791
3792         /* Update computed state. */
3793         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3794                 if (!connector->encoder || !connector->encoder->crtc)
3795                         continue;
3796
3797                 if (connector->encoder->crtc != crtc)
3798                         continue;
3799
3800                 connector->dpms = DRM_MODE_DPMS_OFF;
3801                 to_intel_encoder(connector->encoder)->connectors_active = false;
3802         }
3803 }
3804
3805 void intel_modeset_disable(struct drm_device *dev)
3806 {
3807         struct drm_crtc *crtc;
3808
3809         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3810                 if (crtc->enabled)
3811                         intel_crtc_disable(crtc);
3812         }
3813 }
3814
3815 void intel_encoder_destroy(struct drm_encoder *encoder)
3816 {
3817         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3818
3819         drm_encoder_cleanup(encoder);
3820         kfree(intel_encoder);
3821 }
3822
3823 /* Simple dpms helper for encodres with just one connector, no cloning and only
3824  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3825  * state of the entire output pipe. */
3826 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3827 {
3828         if (mode == DRM_MODE_DPMS_ON) {
3829                 encoder->connectors_active = true;
3830
3831                 intel_crtc_update_dpms(encoder->base.crtc);
3832         } else {
3833                 encoder->connectors_active = false;
3834
3835                 intel_crtc_update_dpms(encoder->base.crtc);
3836         }
3837 }
3838
3839 /* Cross check the actual hw state with our own modeset state tracking (and it's
3840  * internal consistency). */
3841 static void intel_connector_check_state(struct intel_connector *connector)
3842 {
3843         if (connector->get_hw_state(connector)) {
3844                 struct intel_encoder *encoder = connector->encoder;
3845                 struct drm_crtc *crtc;
3846                 bool encoder_enabled;
3847                 enum pipe pipe;
3848
3849                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3850                               connector->base.base.id,
3851                               drm_get_connector_name(&connector->base));
3852
3853                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3854                      "wrong connector dpms state\n");
3855                 WARN(connector->base.encoder != &encoder->base,
3856                      "active connector not linked to encoder\n");
3857                 WARN(!encoder->connectors_active,
3858                      "encoder->connectors_active not set\n");
3859
3860                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3861                 WARN(!encoder_enabled, "encoder not enabled\n");
3862                 if (WARN_ON(!encoder->base.crtc))
3863                         return;
3864
3865                 crtc = encoder->base.crtc;
3866
3867                 WARN(!crtc->enabled, "crtc not enabled\n");
3868                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3869                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3870                      "encoder active on the wrong pipe\n");
3871         }
3872 }
3873
3874 /* Even simpler default implementation, if there's really no special case to
3875  * consider. */
3876 void intel_connector_dpms(struct drm_connector *connector, int mode)
3877 {
3878         struct intel_encoder *encoder = intel_attached_encoder(connector);
3879
3880         /* All the simple cases only support two dpms states. */
3881         if (mode != DRM_MODE_DPMS_ON)
3882                 mode = DRM_MODE_DPMS_OFF;
3883
3884         if (mode == connector->dpms)
3885                 return;
3886
3887         connector->dpms = mode;
3888
3889         /* Only need to change hw state when actually enabled */
3890         if (encoder->base.crtc)
3891                 intel_encoder_dpms(encoder, mode);
3892         else
3893                 WARN_ON(encoder->connectors_active != false);
3894
3895         intel_modeset_check_state(connector->dev);
3896 }
3897
3898 /* Simple connector->get_hw_state implementation for encoders that support only
3899  * one connector and no cloning and hence the encoder state determines the state
3900  * of the connector. */
3901 bool intel_connector_get_hw_state(struct intel_connector *connector)
3902 {
3903         enum pipe pipe = 0;
3904         struct intel_encoder *encoder = connector->encoder;
3905
3906         return encoder->get_hw_state(encoder, &pipe);
3907 }
3908
3909 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3910                                   const struct drm_display_mode *mode,
3911                                   struct drm_display_mode *adjusted_mode)
3912 {
3913         struct drm_device *dev = crtc->dev;
3914
3915         if (HAS_PCH_SPLIT(dev)) {
3916                 /* FDI link clock is fixed at 2.7G */
3917                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3918                         return false;
3919         }
3920
3921         /* All interlaced capable intel hw wants timings in frames. Note though
3922          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3923          * timings, so we need to be careful not to clobber these.*/
3924         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3925                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3926
3927         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3928          * with a hsync front porch of 0.
3929          */
3930         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3931                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3932                 return false;
3933
3934         return true;
3935 }
3936
3937 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3938 {
3939         return 400000; /* FIXME */
3940 }
3941
3942 static int i945_get_display_clock_speed(struct drm_device *dev)
3943 {
3944         return 400000;
3945 }
3946
3947 static int i915_get_display_clock_speed(struct drm_device *dev)
3948 {
3949         return 333000;
3950 }
3951
3952 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3953 {
3954         return 200000;
3955 }
3956
3957 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3958 {
3959         u16 gcfgc = 0;
3960
3961         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3962
3963         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3964                 return 133000;
3965         else {
3966                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3967                 case GC_DISPLAY_CLOCK_333_MHZ:
3968                         return 333000;
3969                 default:
3970                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3971                         return 190000;
3972                 }
3973         }
3974 }
3975
3976 static int i865_get_display_clock_speed(struct drm_device *dev)
3977 {
3978         return 266000;
3979 }
3980
3981 static int i855_get_display_clock_speed(struct drm_device *dev)
3982 {
3983         u16 hpllcc = 0;
3984         /* Assume that the hardware is in the high speed state.  This
3985          * should be the default.
3986          */
3987         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3988         case GC_CLOCK_133_200:
3989         case GC_CLOCK_100_200:
3990                 return 200000;
3991         case GC_CLOCK_166_250:
3992                 return 250000;
3993         case GC_CLOCK_100_133:
3994                 return 133000;
3995         }
3996
3997         /* Shouldn't happen */
3998         return 0;
3999 }
4000
4001 static int i830_get_display_clock_speed(struct drm_device *dev)
4002 {
4003         return 133000;
4004 }
4005
4006 static void
4007 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4008 {
4009         while (*num > 0xffffff || *den > 0xffffff) {
4010                 *num >>= 1;
4011                 *den >>= 1;
4012         }
4013 }
4014
4015 void
4016 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4017                        int pixel_clock, int link_clock,
4018                        struct intel_link_m_n *m_n)
4019 {
4020         m_n->tu = 64;
4021         m_n->gmch_m = bits_per_pixel * pixel_clock;
4022         m_n->gmch_n = link_clock * nlanes * 8;
4023         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4024         m_n->link_m = pixel_clock;
4025         m_n->link_n = link_clock;
4026         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4027 }
4028
4029 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4030 {
4031         if (i915_panel_use_ssc >= 0)
4032                 return i915_panel_use_ssc != 0;
4033         return dev_priv->lvds_use_ssc
4034                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4035 }
4036
4037 /**
4038  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4039  * @crtc: CRTC structure
4040  * @mode: requested mode
4041  *
4042  * A pipe may be connected to one or more outputs.  Based on the depth of the
4043  * attached framebuffer, choose a good color depth to use on the pipe.
4044  *
4045  * If possible, match the pipe depth to the fb depth.  In some cases, this
4046  * isn't ideal, because the connected output supports a lesser or restricted
4047  * set of depths.  Resolve that here:
4048  *    LVDS typically supports only 6bpc, so clamp down in that case
4049  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4050  *    Displays may support a restricted set as well, check EDID and clamp as
4051  *      appropriate.
4052  *    DP may want to dither down to 6bpc to fit larger modes
4053  *
4054  * RETURNS:
4055  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4056  * true if they don't match).
4057  */
4058 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4059                                          struct drm_framebuffer *fb,
4060                                          unsigned int *pipe_bpp,
4061                                          struct drm_display_mode *mode)
4062 {
4063         struct drm_device *dev = crtc->dev;
4064         struct drm_i915_private *dev_priv = dev->dev_private;
4065         struct drm_connector *connector;
4066         struct intel_encoder *intel_encoder;
4067         unsigned int display_bpc = UINT_MAX, bpc;
4068
4069         /* Walk the encoders & connectors on this crtc, get min bpc */
4070         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4071
4072                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4073                         unsigned int lvds_bpc;
4074
4075                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4076                             LVDS_A3_POWER_UP)
4077                                 lvds_bpc = 8;
4078                         else
4079                                 lvds_bpc = 6;
4080
4081                         if (lvds_bpc < display_bpc) {
4082                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4083                                 display_bpc = lvds_bpc;
4084                         }
4085                         continue;
4086                 }
4087
4088                 /* Not one of the known troublemakers, check the EDID */
4089                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4090                                     head) {
4091                         if (connector->encoder != &intel_encoder->base)
4092                                 continue;
4093
4094                         /* Don't use an invalid EDID bpc value */
4095                         if (connector->display_info.bpc &&
4096                             connector->display_info.bpc < display_bpc) {
4097                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4098                                 display_bpc = connector->display_info.bpc;
4099                         }
4100                 }
4101
4102                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4103                         /* Use VBT settings if we have an eDP panel */
4104                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4105
4106                         if (edp_bpc && edp_bpc < display_bpc) {
4107                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4108                                 display_bpc = edp_bpc;
4109                         }
4110                         continue;
4111                 }
4112
4113                 /*
4114                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4115                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4116                  */
4117                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4118                         if (display_bpc > 8 && display_bpc < 12) {
4119                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4120                                 display_bpc = 12;
4121                         } else {
4122                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4123                                 display_bpc = 8;
4124                         }
4125                 }
4126         }
4127
4128         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4129                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4130                 display_bpc = 6;
4131         }
4132
4133         /*
4134          * We could just drive the pipe at the highest bpc all the time and
4135          * enable dithering as needed, but that costs bandwidth.  So choose
4136          * the minimum value that expresses the full color range of the fb but
4137          * also stays within the max display bpc discovered above.
4138          */
4139
4140         switch (fb->depth) {
4141         case 8:
4142                 bpc = 8; /* since we go through a colormap */
4143                 break;
4144         case 15:
4145         case 16:
4146                 bpc = 6; /* min is 18bpp */
4147                 break;
4148         case 24:
4149                 bpc = 8;
4150                 break;
4151         case 30:
4152                 bpc = 10;
4153                 break;
4154         case 48:
4155                 bpc = 12;
4156                 break;
4157         default:
4158                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4159                 bpc = min((unsigned int)8, display_bpc);
4160                 break;
4161         }
4162
4163         display_bpc = min(display_bpc, bpc);
4164
4165         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4166                       bpc, display_bpc);
4167
4168         *pipe_bpp = display_bpc * 3;
4169
4170         return display_bpc != bpc;
4171 }
4172
4173 static int vlv_get_refclk(struct drm_crtc *crtc)
4174 {
4175         struct drm_device *dev = crtc->dev;
4176         struct drm_i915_private *dev_priv = dev->dev_private;
4177         int refclk = 27000; /* for DP & HDMI */
4178
4179         return 100000; /* only one validated so far */
4180
4181         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4182                 refclk = 96000;
4183         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4184                 if (intel_panel_use_ssc(dev_priv))
4185                         refclk = 100000;
4186                 else
4187                         refclk = 96000;
4188         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4189                 refclk = 100000;
4190         }
4191
4192         return refclk;
4193 }
4194
4195 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4196 {
4197         struct drm_device *dev = crtc->dev;
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199         int refclk;
4200
4201         if (IS_VALLEYVIEW(dev)) {
4202                 refclk = vlv_get_refclk(crtc);
4203         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4204             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4205                 refclk = dev_priv->lvds_ssc_freq * 1000;
4206                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4207                               refclk / 1000);
4208         } else if (!IS_GEN2(dev)) {
4209                 refclk = 96000;
4210         } else {
4211                 refclk = 48000;
4212         }
4213
4214         return refclk;
4215 }
4216
4217 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4218                                       intel_clock_t *clock)
4219 {
4220         /* SDVO TV has fixed PLL values depend on its clock range,
4221            this mirrors vbios setting. */
4222         if (adjusted_mode->clock >= 100000
4223             && adjusted_mode->clock < 140500) {
4224                 clock->p1 = 2;
4225                 clock->p2 = 10;
4226                 clock->n = 3;
4227                 clock->m1 = 16;
4228                 clock->m2 = 8;
4229         } else if (adjusted_mode->clock >= 140500
4230                    && adjusted_mode->clock <= 200000) {
4231                 clock->p1 = 1;
4232                 clock->p2 = 10;
4233                 clock->n = 6;
4234                 clock->m1 = 12;
4235                 clock->m2 = 8;
4236         }
4237 }
4238
4239 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4240                                      intel_clock_t *clock,
4241                                      intel_clock_t *reduced_clock)
4242 {
4243         struct drm_device *dev = crtc->dev;
4244         struct drm_i915_private *dev_priv = dev->dev_private;
4245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4246         int pipe = intel_crtc->pipe;
4247         u32 fp, fp2 = 0;
4248
4249         if (IS_PINEVIEW(dev)) {
4250                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4251                 if (reduced_clock)
4252                         fp2 = (1 << reduced_clock->n) << 16 |
4253                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4254         } else {
4255                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4256                 if (reduced_clock)
4257                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4258                                 reduced_clock->m2;
4259         }
4260
4261         I915_WRITE(FP0(pipe), fp);
4262
4263         intel_crtc->lowfreq_avail = false;
4264         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4265             reduced_clock && i915_powersave) {
4266                 I915_WRITE(FP1(pipe), fp2);
4267                 intel_crtc->lowfreq_avail = true;
4268         } else {
4269                 I915_WRITE(FP1(pipe), fp);
4270         }
4271 }
4272
4273 static void vlv_update_pll(struct drm_crtc *crtc,
4274                            struct drm_display_mode *mode,
4275                            struct drm_display_mode *adjusted_mode,
4276                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4277                            int num_connectors)
4278 {
4279         struct drm_device *dev = crtc->dev;
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4282         int pipe = intel_crtc->pipe;
4283         u32 dpll, mdiv, pdiv;
4284         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4285         bool is_sdvo;
4286         u32 temp;
4287
4288         mutex_lock(&dev_priv->dpio_lock);
4289
4290         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4291                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4292
4293         dpll = DPLL_VGA_MODE_DIS;
4294         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4295         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4296         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4297
4298         I915_WRITE(DPLL(pipe), dpll);
4299         POSTING_READ(DPLL(pipe));
4300
4301         bestn = clock->n;
4302         bestm1 = clock->m1;
4303         bestm2 = clock->m2;
4304         bestp1 = clock->p1;
4305         bestp2 = clock->p2;
4306
4307         /*
4308          * In Valleyview PLL and program lane counter registers are exposed
4309          * through DPIO interface
4310          */
4311         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4312         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4313         mdiv |= ((bestn << DPIO_N_SHIFT));
4314         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4315         mdiv |= (1 << DPIO_K_SHIFT);
4316         mdiv |= DPIO_ENABLE_CALIBRATION;
4317         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4318
4319         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4320
4321         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4322                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4323                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4324                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4325         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4326
4327         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4328
4329         dpll |= DPLL_VCO_ENABLE;
4330         I915_WRITE(DPLL(pipe), dpll);
4331         POSTING_READ(DPLL(pipe));
4332         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4333                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4334
4335         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4336
4337         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4338                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4339
4340         I915_WRITE(DPLL(pipe), dpll);
4341
4342         /* Wait for the clocks to stabilize. */
4343         POSTING_READ(DPLL(pipe));
4344         udelay(150);
4345
4346         temp = 0;
4347         if (is_sdvo) {
4348                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4349                 if (temp > 1)
4350                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4351                 else
4352                         temp = 0;
4353         }
4354         I915_WRITE(DPLL_MD(pipe), temp);
4355         POSTING_READ(DPLL_MD(pipe));
4356
4357         /* Now program lane control registers */
4358         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4359                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4360         {
4361                 temp = 0x1000C4;
4362                 if(pipe == 1)
4363                         temp |= (1 << 21);
4364                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4365         }
4366         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4367         {
4368                 temp = 0x1000C4;
4369                 if(pipe == 1)
4370                         temp |= (1 << 21);
4371                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4372         }
4373
4374         mutex_unlock(&dev_priv->dpio_lock);
4375 }
4376
4377 static void i9xx_update_pll(struct drm_crtc *crtc,
4378                             struct drm_display_mode *mode,
4379                             struct drm_display_mode *adjusted_mode,
4380                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4381                             int num_connectors)
4382 {
4383         struct drm_device *dev = crtc->dev;
4384         struct drm_i915_private *dev_priv = dev->dev_private;
4385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386         struct intel_encoder *encoder;
4387         int pipe = intel_crtc->pipe;
4388         u32 dpll;
4389         bool is_sdvo;
4390
4391         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4392
4393         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4394                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4395
4396         dpll = DPLL_VGA_MODE_DIS;
4397
4398         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4399                 dpll |= DPLLB_MODE_LVDS;
4400         else
4401                 dpll |= DPLLB_MODE_DAC_SERIAL;
4402         if (is_sdvo) {
4403                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4404                 if (pixel_multiplier > 1) {
4405                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4406                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4407                 }
4408                 dpll |= DPLL_DVO_HIGH_SPEED;
4409         }
4410         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4411                 dpll |= DPLL_DVO_HIGH_SPEED;
4412
4413         /* compute bitmask from p1 value */
4414         if (IS_PINEVIEW(dev))
4415                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4416         else {
4417                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4418                 if (IS_G4X(dev) && reduced_clock)
4419                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4420         }
4421         switch (clock->p2) {
4422         case 5:
4423                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4424                 break;
4425         case 7:
4426                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4427                 break;
4428         case 10:
4429                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4430                 break;
4431         case 14:
4432                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4433                 break;
4434         }
4435         if (INTEL_INFO(dev)->gen >= 4)
4436                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4437
4438         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4439                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4440         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4441                 /* XXX: just matching BIOS for now */
4442                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4443                 dpll |= 3;
4444         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4445                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4446                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4447         else
4448                 dpll |= PLL_REF_INPUT_DREFCLK;
4449
4450         dpll |= DPLL_VCO_ENABLE;
4451         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4452         POSTING_READ(DPLL(pipe));
4453         udelay(150);
4454
4455         for_each_encoder_on_crtc(dev, crtc, encoder)
4456                 if (encoder->pre_pll_enable)
4457                         encoder->pre_pll_enable(encoder);
4458
4459         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4460                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4461
4462         I915_WRITE(DPLL(pipe), dpll);
4463
4464         /* Wait for the clocks to stabilize. */
4465         POSTING_READ(DPLL(pipe));
4466         udelay(150);
4467
4468         if (INTEL_INFO(dev)->gen >= 4) {
4469                 u32 temp = 0;
4470                 if (is_sdvo) {
4471                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4472                         if (temp > 1)
4473                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4474                         else
4475                                 temp = 0;
4476                 }
4477                 I915_WRITE(DPLL_MD(pipe), temp);
4478         } else {
4479                 /* The pixel multiplier can only be updated once the
4480                  * DPLL is enabled and the clocks are stable.
4481                  *
4482                  * So write it again.
4483                  */
4484                 I915_WRITE(DPLL(pipe), dpll);
4485         }
4486 }
4487
4488 static void i8xx_update_pll(struct drm_crtc *crtc,
4489                             struct drm_display_mode *adjusted_mode,
4490                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4491                             int num_connectors)
4492 {
4493         struct drm_device *dev = crtc->dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496         struct intel_encoder *encoder;
4497         int pipe = intel_crtc->pipe;
4498         u32 dpll;
4499
4500         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4501
4502         dpll = DPLL_VGA_MODE_DIS;
4503
4504         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4505                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4506         } else {
4507                 if (clock->p1 == 2)
4508                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4509                 else
4510                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4511                 if (clock->p2 == 4)
4512                         dpll |= PLL_P2_DIVIDE_BY_4;
4513         }
4514
4515         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4516                 /* XXX: just matching BIOS for now */
4517                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4518                 dpll |= 3;
4519         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4520                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4521                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4522         else
4523                 dpll |= PLL_REF_INPUT_DREFCLK;
4524
4525         dpll |= DPLL_VCO_ENABLE;
4526         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4527         POSTING_READ(DPLL(pipe));
4528         udelay(150);
4529
4530         for_each_encoder_on_crtc(dev, crtc, encoder)
4531                 if (encoder->pre_pll_enable)
4532                         encoder->pre_pll_enable(encoder);
4533
4534         I915_WRITE(DPLL(pipe), dpll);
4535
4536         /* Wait for the clocks to stabilize. */
4537         POSTING_READ(DPLL(pipe));
4538         udelay(150);
4539
4540         /* The pixel multiplier can only be updated once the
4541          * DPLL is enabled and the clocks are stable.
4542          *
4543          * So write it again.
4544          */
4545         I915_WRITE(DPLL(pipe), dpll);
4546 }
4547
4548 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4549                                    struct drm_display_mode *mode,
4550                                    struct drm_display_mode *adjusted_mode)
4551 {
4552         struct drm_device *dev = intel_crtc->base.dev;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         enum pipe pipe = intel_crtc->pipe;
4555         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4556         uint32_t vsyncshift;
4557
4558         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4559                 /* the chip adds 2 halflines automatically */
4560                 adjusted_mode->crtc_vtotal -= 1;
4561                 adjusted_mode->crtc_vblank_end -= 1;
4562                 vsyncshift = adjusted_mode->crtc_hsync_start
4563                              - adjusted_mode->crtc_htotal / 2;
4564         } else {
4565                 vsyncshift = 0;
4566         }
4567
4568         if (INTEL_INFO(dev)->gen > 3)
4569                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4570
4571         I915_WRITE(HTOTAL(cpu_transcoder),
4572                    (adjusted_mode->crtc_hdisplay - 1) |
4573                    ((adjusted_mode->crtc_htotal - 1) << 16));
4574         I915_WRITE(HBLANK(cpu_transcoder),
4575                    (adjusted_mode->crtc_hblank_start - 1) |
4576                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4577         I915_WRITE(HSYNC(cpu_transcoder),
4578                    (adjusted_mode->crtc_hsync_start - 1) |
4579                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4580
4581         I915_WRITE(VTOTAL(cpu_transcoder),
4582                    (adjusted_mode->crtc_vdisplay - 1) |
4583                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4584         I915_WRITE(VBLANK(cpu_transcoder),
4585                    (adjusted_mode->crtc_vblank_start - 1) |
4586                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4587         I915_WRITE(VSYNC(cpu_transcoder),
4588                    (adjusted_mode->crtc_vsync_start - 1) |
4589                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4590
4591         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4592          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4593          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4594          * bits. */
4595         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4596             (pipe == PIPE_B || pipe == PIPE_C))
4597                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4598
4599         /* pipesrc controls the size that is scaled from, which should
4600          * always be the user's requested size.
4601          */
4602         I915_WRITE(PIPESRC(pipe),
4603                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4604 }
4605
4606 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4607                               struct drm_display_mode *mode,
4608                               struct drm_display_mode *adjusted_mode,
4609                               int x, int y,
4610                               struct drm_framebuffer *fb)
4611 {
4612         struct drm_device *dev = crtc->dev;
4613         struct drm_i915_private *dev_priv = dev->dev_private;
4614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4615         int pipe = intel_crtc->pipe;
4616         int plane = intel_crtc->plane;
4617         int refclk, num_connectors = 0;
4618         intel_clock_t clock, reduced_clock;
4619         u32 dspcntr, pipeconf;
4620         bool ok, has_reduced_clock = false, is_sdvo = false;
4621         bool is_lvds = false, is_tv = false, is_dp = false;
4622         struct intel_encoder *encoder;
4623         const intel_limit_t *limit;
4624         int ret;
4625
4626         for_each_encoder_on_crtc(dev, crtc, encoder) {
4627                 switch (encoder->type) {
4628                 case INTEL_OUTPUT_LVDS:
4629                         is_lvds = true;
4630                         break;
4631                 case INTEL_OUTPUT_SDVO:
4632                 case INTEL_OUTPUT_HDMI:
4633                         is_sdvo = true;
4634                         if (encoder->needs_tv_clock)
4635                                 is_tv = true;
4636                         break;
4637                 case INTEL_OUTPUT_TVOUT:
4638                         is_tv = true;
4639                         break;
4640                 case INTEL_OUTPUT_DISPLAYPORT:
4641                         is_dp = true;
4642                         break;
4643                 }
4644
4645                 num_connectors++;
4646         }
4647
4648         refclk = i9xx_get_refclk(crtc, num_connectors);
4649
4650         /*
4651          * Returns a set of divisors for the desired target clock with the given
4652          * refclk, or FALSE.  The returned values represent the clock equation:
4653          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4654          */
4655         limit = intel_limit(crtc, refclk);
4656         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4657                              &clock);
4658         if (!ok) {
4659                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4660                 return -EINVAL;
4661         }
4662
4663         /* Ensure that the cursor is valid for the new mode before changing... */
4664         intel_crtc_update_cursor(crtc, true);
4665
4666         if (is_lvds && dev_priv->lvds_downclock_avail) {
4667                 /*
4668                  * Ensure we match the reduced clock's P to the target clock.
4669                  * If the clocks don't match, we can't switch the display clock
4670                  * by using the FP0/FP1. In such case we will disable the LVDS
4671                  * downclock feature.
4672                 */
4673                 has_reduced_clock = limit->find_pll(limit, crtc,
4674                                                     dev_priv->lvds_downclock,
4675                                                     refclk,
4676                                                     &clock,
4677                                                     &reduced_clock);
4678         }
4679
4680         if (is_sdvo && is_tv)
4681                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4682
4683         if (IS_GEN2(dev))
4684                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4685                                 has_reduced_clock ? &reduced_clock : NULL,
4686                                 num_connectors);
4687         else if (IS_VALLEYVIEW(dev))
4688                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4689                                 has_reduced_clock ? &reduced_clock : NULL,
4690                                 num_connectors);
4691         else
4692                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4693                                 has_reduced_clock ? &reduced_clock : NULL,
4694                                 num_connectors);
4695
4696         /* setup pipeconf */
4697         pipeconf = I915_READ(PIPECONF(pipe));
4698
4699         /* Set up the display plane register */
4700         dspcntr = DISPPLANE_GAMMA_ENABLE;
4701
4702         if (pipe == 0)
4703                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4704         else
4705                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4706
4707         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4708                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4709                  * core speed.
4710                  *
4711                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4712                  * pipe == 0 check?
4713                  */
4714                 if (mode->clock >
4715                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4716                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4717                 else
4718                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4719         }
4720
4721         /* default to 8bpc */
4722         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4723         if (is_dp) {
4724                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4725                         pipeconf |= PIPECONF_6BPC |
4726                                     PIPECONF_DITHER_EN |
4727                                     PIPECONF_DITHER_TYPE_SP;
4728                 }
4729         }
4730
4731         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4732                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4733                         pipeconf |= PIPECONF_6BPC |
4734                                         PIPECONF_ENABLE |
4735                                         I965_PIPECONF_ACTIVE;
4736                 }
4737         }
4738
4739         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4740         drm_mode_debug_printmodeline(mode);
4741
4742         if (HAS_PIPE_CXSR(dev)) {
4743                 if (intel_crtc->lowfreq_avail) {
4744                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4745                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4746                 } else {
4747                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4748                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4749                 }
4750         }
4751
4752         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4753         if (!IS_GEN2(dev) &&
4754             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4755                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4756         else
4757                 pipeconf |= PIPECONF_PROGRESSIVE;
4758
4759         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4760
4761         /* pipesrc and dspsize control the size that is scaled from,
4762          * which should always be the user's requested size.
4763          */
4764         I915_WRITE(DSPSIZE(plane),
4765                    ((mode->vdisplay - 1) << 16) |
4766                    (mode->hdisplay - 1));
4767         I915_WRITE(DSPPOS(plane), 0);
4768
4769         I915_WRITE(PIPECONF(pipe), pipeconf);
4770         POSTING_READ(PIPECONF(pipe));
4771         intel_enable_pipe(dev_priv, pipe, false);
4772
4773         intel_wait_for_vblank(dev, pipe);
4774
4775         I915_WRITE(DSPCNTR(plane), dspcntr);
4776         POSTING_READ(DSPCNTR(plane));
4777
4778         ret = intel_pipe_set_base(crtc, x, y, fb);
4779
4780         intel_update_watermarks(dev);
4781
4782         return ret;
4783 }
4784
4785 static void ironlake_init_pch_refclk(struct drm_device *dev)
4786 {
4787         struct drm_i915_private *dev_priv = dev->dev_private;
4788         struct drm_mode_config *mode_config = &dev->mode_config;
4789         struct intel_encoder *encoder;
4790         u32 temp;
4791         bool has_lvds = false;
4792         bool has_cpu_edp = false;
4793         bool has_pch_edp = false;
4794         bool has_panel = false;
4795         bool has_ck505 = false;
4796         bool can_ssc = false;
4797
4798         /* We need to take the global config into account */
4799         list_for_each_entry(encoder, &mode_config->encoder_list,
4800                             base.head) {
4801                 switch (encoder->type) {
4802                 case INTEL_OUTPUT_LVDS:
4803                         has_panel = true;
4804                         has_lvds = true;
4805                         break;
4806                 case INTEL_OUTPUT_EDP:
4807                         has_panel = true;
4808                         if (intel_encoder_is_pch_edp(&encoder->base))
4809                                 has_pch_edp = true;
4810                         else
4811                                 has_cpu_edp = true;
4812                         break;
4813                 }
4814         }
4815
4816         if (HAS_PCH_IBX(dev)) {
4817                 has_ck505 = dev_priv->display_clock_mode;
4818                 can_ssc = has_ck505;
4819         } else {
4820                 has_ck505 = false;
4821                 can_ssc = true;
4822         }
4823
4824         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4825                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4826                       has_ck505);
4827
4828         /* Ironlake: try to setup display ref clock before DPLL
4829          * enabling. This is only under driver's control after
4830          * PCH B stepping, previous chipset stepping should be
4831          * ignoring this setting.
4832          */
4833         temp = I915_READ(PCH_DREF_CONTROL);
4834         /* Always enable nonspread source */
4835         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4836
4837         if (has_ck505)
4838                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4839         else
4840                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4841
4842         if (has_panel) {
4843                 temp &= ~DREF_SSC_SOURCE_MASK;
4844                 temp |= DREF_SSC_SOURCE_ENABLE;
4845
4846                 /* SSC must be turned on before enabling the CPU output  */
4847                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4848                         DRM_DEBUG_KMS("Using SSC on panel\n");
4849                         temp |= DREF_SSC1_ENABLE;
4850                 } else
4851                         temp &= ~DREF_SSC1_ENABLE;
4852
4853                 /* Get SSC going before enabling the outputs */
4854                 I915_WRITE(PCH_DREF_CONTROL, temp);
4855                 POSTING_READ(PCH_DREF_CONTROL);
4856                 udelay(200);
4857
4858                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4859
4860                 /* Enable CPU source on CPU attached eDP */
4861                 if (has_cpu_edp) {
4862                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4863                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4864                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4865                         }
4866                         else
4867                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4868                 } else
4869                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4870
4871                 I915_WRITE(PCH_DREF_CONTROL, temp);
4872                 POSTING_READ(PCH_DREF_CONTROL);
4873                 udelay(200);
4874         } else {
4875                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4876
4877                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4878
4879                 /* Turn off CPU output */
4880                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4881
4882                 I915_WRITE(PCH_DREF_CONTROL, temp);
4883                 POSTING_READ(PCH_DREF_CONTROL);
4884                 udelay(200);
4885
4886                 /* Turn off the SSC source */
4887                 temp &= ~DREF_SSC_SOURCE_MASK;
4888                 temp |= DREF_SSC_SOURCE_DISABLE;
4889
4890                 /* Turn off SSC1 */
4891                 temp &= ~ DREF_SSC1_ENABLE;
4892
4893                 I915_WRITE(PCH_DREF_CONTROL, temp);
4894                 POSTING_READ(PCH_DREF_CONTROL);
4895                 udelay(200);
4896         }
4897 }
4898
4899 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4900 static void lpt_init_pch_refclk(struct drm_device *dev)
4901 {
4902         struct drm_i915_private *dev_priv = dev->dev_private;
4903         struct drm_mode_config *mode_config = &dev->mode_config;
4904         struct intel_encoder *encoder;
4905         bool has_vga = false;
4906         bool is_sdv = false;
4907         u32 tmp;
4908
4909         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4910                 switch (encoder->type) {
4911                 case INTEL_OUTPUT_ANALOG:
4912                         has_vga = true;
4913                         break;
4914                 }
4915         }
4916
4917         if (!has_vga)
4918                 return;
4919
4920         mutex_lock(&dev_priv->dpio_lock);
4921
4922         /* XXX: Rip out SDV support once Haswell ships for real. */
4923         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4924                 is_sdv = true;
4925
4926         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4927         tmp &= ~SBI_SSCCTL_DISABLE;
4928         tmp |= SBI_SSCCTL_PATHALT;
4929         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4930
4931         udelay(24);
4932
4933         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4934         tmp &= ~SBI_SSCCTL_PATHALT;
4935         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4936
4937         if (!is_sdv) {
4938                 tmp = I915_READ(SOUTH_CHICKEN2);
4939                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4940                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4941
4942                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4943                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4944                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4945
4946                 tmp = I915_READ(SOUTH_CHICKEN2);
4947                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4948                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4949
4950                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4951                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4952                                        100))
4953                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4954         }
4955
4956         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4957         tmp &= ~(0xFF << 24);
4958         tmp |= (0x12 << 24);
4959         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4960
4961         if (!is_sdv) {
4962                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4963                 tmp &= ~(0x3 << 6);
4964                 tmp |= (1 << 6) | (1 << 0);
4965                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4966         }
4967
4968         if (is_sdv) {
4969                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4970                 tmp |= 0x7FFF;
4971                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4972         }
4973
4974         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4975         tmp |= (1 << 11);
4976         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4977
4978         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4979         tmp |= (1 << 11);
4980         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4981
4982         if (is_sdv) {
4983                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4984                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4985                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4986
4987                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4988                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4989                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4990
4991                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4992                 tmp |= (0x3F << 8);
4993                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4994
4995                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4996                 tmp |= (0x3F << 8);
4997                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4998         }
4999
5000         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5001         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5002         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5003
5004         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5005         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5006         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5007
5008         if (!is_sdv) {
5009                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5010                 tmp &= ~(7 << 13);
5011                 tmp |= (5 << 13);
5012                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5013
5014                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5015                 tmp &= ~(7 << 13);
5016                 tmp |= (5 << 13);
5017                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5018         }
5019
5020         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5021         tmp &= ~0xFF;
5022         tmp |= 0x1C;
5023         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5024
5025         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5026         tmp &= ~0xFF;
5027         tmp |= 0x1C;
5028         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5029
5030         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5031         tmp &= ~(0xFF << 16);
5032         tmp |= (0x1C << 16);
5033         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5034
5035         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5036         tmp &= ~(0xFF << 16);
5037         tmp |= (0x1C << 16);
5038         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5039
5040         if (!is_sdv) {
5041                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5042                 tmp |= (1 << 27);
5043                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5044
5045                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5046                 tmp |= (1 << 27);
5047                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5048
5049                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5050                 tmp &= ~(0xF << 28);
5051                 tmp |= (4 << 28);
5052                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5053
5054                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5055                 tmp &= ~(0xF << 28);
5056                 tmp |= (4 << 28);
5057                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5058         }
5059
5060         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5061         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5062         tmp |= SBI_DBUFF0_ENABLE;
5063         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5064
5065         mutex_unlock(&dev_priv->dpio_lock);
5066 }
5067
5068 /*
5069  * Initialize reference clocks when the driver loads
5070  */
5071 void intel_init_pch_refclk(struct drm_device *dev)
5072 {
5073         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5074                 ironlake_init_pch_refclk(dev);
5075         else if (HAS_PCH_LPT(dev))
5076                 lpt_init_pch_refclk(dev);
5077 }
5078
5079 static int ironlake_get_refclk(struct drm_crtc *crtc)
5080 {
5081         struct drm_device *dev = crtc->dev;
5082         struct drm_i915_private *dev_priv = dev->dev_private;
5083         struct intel_encoder *encoder;
5084         struct intel_encoder *edp_encoder = NULL;
5085         int num_connectors = 0;
5086         bool is_lvds = false;
5087
5088         for_each_encoder_on_crtc(dev, crtc, encoder) {
5089                 switch (encoder->type) {
5090                 case INTEL_OUTPUT_LVDS:
5091                         is_lvds = true;
5092                         break;
5093                 case INTEL_OUTPUT_EDP:
5094                         edp_encoder = encoder;
5095                         break;
5096                 }
5097                 num_connectors++;
5098         }
5099
5100         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5101                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5102                               dev_priv->lvds_ssc_freq);
5103                 return dev_priv->lvds_ssc_freq * 1000;
5104         }
5105
5106         return 120000;
5107 }
5108
5109 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5110                                   struct drm_display_mode *adjusted_mode,
5111                                   bool dither)
5112 {
5113         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115         int pipe = intel_crtc->pipe;
5116         uint32_t val;
5117
5118         val = I915_READ(PIPECONF(pipe));
5119
5120         val &= ~PIPECONF_BPC_MASK;
5121         switch (intel_crtc->bpp) {
5122         case 18:
5123                 val |= PIPECONF_6BPC;
5124                 break;
5125         case 24:
5126                 val |= PIPECONF_8BPC;
5127                 break;
5128         case 30:
5129                 val |= PIPECONF_10BPC;
5130                 break;
5131         case 36:
5132                 val |= PIPECONF_12BPC;
5133                 break;
5134         default:
5135                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5136                 BUG();
5137         }
5138
5139         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5140         if (dither)
5141                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5142
5143         val &= ~PIPECONF_INTERLACE_MASK;
5144         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5145                 val |= PIPECONF_INTERLACED_ILK;
5146         else
5147                 val |= PIPECONF_PROGRESSIVE;
5148
5149         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5150                 val |= PIPECONF_COLOR_RANGE_SELECT;
5151         else
5152                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5153
5154         I915_WRITE(PIPECONF(pipe), val);
5155         POSTING_READ(PIPECONF(pipe));
5156 }
5157
5158 /*
5159  * Set up the pipe CSC unit.
5160  *
5161  * Currently only full range RGB to limited range RGB conversion
5162  * is supported, but eventually this should handle various
5163  * RGB<->YCbCr scenarios as well.
5164  */
5165 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5166                                const struct drm_display_mode *adjusted_mode)
5167 {
5168         struct drm_device *dev = crtc->dev;
5169         struct drm_i915_private *dev_priv = dev->dev_private;
5170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5171         int pipe = intel_crtc->pipe;
5172         uint16_t coeff = 0x7800; /* 1.0 */
5173
5174         /*
5175          * TODO: Check what kind of values actually come out of the pipe
5176          * with these coeff/postoff values and adjust to get the best
5177          * accuracy. Perhaps we even need to take the bpc value into
5178          * consideration.
5179          */
5180
5181         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5182                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5183
5184         /*
5185          * GY/GU and RY/RU should be the other way around according
5186          * to BSpec, but reality doesn't agree. Just set them up in
5187          * a way that results in the correct picture.
5188          */
5189         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5190         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5191
5192         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5193         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5194
5195         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5196         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5197
5198         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5199         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5200         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5201
5202         if (INTEL_INFO(dev)->gen > 6) {
5203                 uint16_t postoff = 0;
5204
5205                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5206                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5207
5208                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5209                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5210                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5211
5212                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5213         } else {
5214                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5215
5216                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5217                         mode |= CSC_BLACK_SCREEN_OFFSET;
5218
5219                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5220         }
5221 }
5222
5223 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5224                                  struct drm_display_mode *adjusted_mode,
5225                                  bool dither)
5226 {
5227         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5230         uint32_t val;
5231
5232         val = I915_READ(PIPECONF(cpu_transcoder));
5233
5234         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5235         if (dither)
5236                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5237
5238         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5239         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5240                 val |= PIPECONF_INTERLACED_ILK;
5241         else
5242                 val |= PIPECONF_PROGRESSIVE;
5243
5244         I915_WRITE(PIPECONF(cpu_transcoder), val);
5245         POSTING_READ(PIPECONF(cpu_transcoder));
5246 }
5247
5248 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5249                                     struct drm_display_mode *adjusted_mode,
5250                                     intel_clock_t *clock,
5251                                     bool *has_reduced_clock,
5252                                     intel_clock_t *reduced_clock)
5253 {
5254         struct drm_device *dev = crtc->dev;
5255         struct drm_i915_private *dev_priv = dev->dev_private;
5256         struct intel_encoder *intel_encoder;
5257         int refclk;
5258         const intel_limit_t *limit;
5259         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5260
5261         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5262                 switch (intel_encoder->type) {
5263                 case INTEL_OUTPUT_LVDS:
5264                         is_lvds = true;
5265                         break;
5266                 case INTEL_OUTPUT_SDVO:
5267                 case INTEL_OUTPUT_HDMI:
5268                         is_sdvo = true;
5269                         if (intel_encoder->needs_tv_clock)
5270                                 is_tv = true;
5271                         break;
5272                 case INTEL_OUTPUT_TVOUT:
5273                         is_tv = true;
5274                         break;
5275                 }
5276         }
5277
5278         refclk = ironlake_get_refclk(crtc);
5279
5280         /*
5281          * Returns a set of divisors for the desired target clock with the given
5282          * refclk, or FALSE.  The returned values represent the clock equation:
5283          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5284          */
5285         limit = intel_limit(crtc, refclk);
5286         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5287                               clock);
5288         if (!ret)
5289                 return false;
5290
5291         if (is_lvds && dev_priv->lvds_downclock_avail) {
5292                 /*
5293                  * Ensure we match the reduced clock's P to the target clock.
5294                  * If the clocks don't match, we can't switch the display clock
5295                  * by using the FP0/FP1. In such case we will disable the LVDS
5296                  * downclock feature.
5297                 */
5298                 *has_reduced_clock = limit->find_pll(limit, crtc,
5299                                                      dev_priv->lvds_downclock,
5300                                                      refclk,
5301                                                      clock,
5302                                                      reduced_clock);
5303         }
5304
5305         if (is_sdvo && is_tv)
5306                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5307
5308         return true;
5309 }
5310
5311 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5312 {
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         uint32_t temp;
5315
5316         temp = I915_READ(SOUTH_CHICKEN1);
5317         if (temp & FDI_BC_BIFURCATION_SELECT)
5318                 return;
5319
5320         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5321         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5322
5323         temp |= FDI_BC_BIFURCATION_SELECT;
5324         DRM_DEBUG_KMS("enabling fdi C rx\n");
5325         I915_WRITE(SOUTH_CHICKEN1, temp);
5326         POSTING_READ(SOUTH_CHICKEN1);
5327 }
5328
5329 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5330 {
5331         struct drm_device *dev = intel_crtc->base.dev;
5332         struct drm_i915_private *dev_priv = dev->dev_private;
5333         struct intel_crtc *pipe_B_crtc =
5334                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5335
5336         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5337                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5338         if (intel_crtc->fdi_lanes > 4) {
5339                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5340                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5341                 /* Clamp lanes to avoid programming the hw with bogus values. */
5342                 intel_crtc->fdi_lanes = 4;
5343
5344                 return false;
5345         }
5346
5347         if (dev_priv->num_pipe == 2)
5348                 return true;
5349
5350         switch (intel_crtc->pipe) {
5351         case PIPE_A:
5352                 return true;
5353         case PIPE_B:
5354                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5355                     intel_crtc->fdi_lanes > 2) {
5356                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5357                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5358                         /* Clamp lanes to avoid programming the hw with bogus values. */
5359                         intel_crtc->fdi_lanes = 2;
5360
5361                         return false;
5362                 }
5363
5364                 if (intel_crtc->fdi_lanes > 2)
5365                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5366                 else
5367                         cpt_enable_fdi_bc_bifurcation(dev);
5368
5369                 return true;
5370         case PIPE_C:
5371                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5372                         if (intel_crtc->fdi_lanes > 2) {
5373                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5374                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5375                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5376                                 intel_crtc->fdi_lanes = 2;
5377
5378                                 return false;
5379                         }
5380                 } else {
5381                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5382                         return false;
5383                 }
5384
5385                 cpt_enable_fdi_bc_bifurcation(dev);
5386
5387                 return true;
5388         default:
5389                 BUG();
5390         }
5391 }
5392
5393 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5394 {
5395         /*
5396          * Account for spread spectrum to avoid
5397          * oversubscribing the link. Max center spread
5398          * is 2.5%; use 5% for safety's sake.
5399          */
5400         u32 bps = target_clock * bpp * 21 / 20;
5401         return bps / (link_bw * 8) + 1;
5402 }
5403
5404 static void ironlake_set_m_n(struct drm_crtc *crtc,
5405                              struct drm_display_mode *mode,
5406                              struct drm_display_mode *adjusted_mode)
5407 {
5408         struct drm_device *dev = crtc->dev;
5409         struct drm_i915_private *dev_priv = dev->dev_private;
5410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5412         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5413         struct intel_link_m_n m_n = {0};
5414         int target_clock, pixel_multiplier, lane, link_bw;
5415         bool is_dp = false, is_cpu_edp = false;
5416
5417         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5418                 switch (intel_encoder->type) {
5419                 case INTEL_OUTPUT_DISPLAYPORT:
5420                         is_dp = true;
5421                         break;
5422                 case INTEL_OUTPUT_EDP:
5423                         is_dp = true;
5424                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5425                                 is_cpu_edp = true;
5426                         edp_encoder = intel_encoder;
5427                         break;
5428                 }
5429         }
5430
5431         /* FDI link */
5432         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5433         lane = 0;
5434         /* CPU eDP doesn't require FDI link, so just set DP M/N
5435            according to current link config */
5436         if (is_cpu_edp) {
5437                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5438         } else {
5439                 /* FDI is a binary signal running at ~2.7GHz, encoding
5440                  * each output octet as 10 bits. The actual frequency
5441                  * is stored as a divider into a 100MHz clock, and the
5442                  * mode pixel clock is stored in units of 1KHz.
5443                  * Hence the bw of each lane in terms of the mode signal
5444                  * is:
5445                  */
5446                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5447         }
5448
5449         /* [e]DP over FDI requires target mode clock instead of link clock. */
5450         if (edp_encoder)
5451                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5452         else if (is_dp)
5453                 target_clock = mode->clock;
5454         else
5455                 target_clock = adjusted_mode->clock;
5456
5457         if (!lane)
5458                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5459                                                    intel_crtc->bpp);
5460
5461         intel_crtc->fdi_lanes = lane;
5462
5463         if (pixel_multiplier > 1)
5464                 link_bw *= pixel_multiplier;
5465         intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5466
5467         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5468         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5469         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5470         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5471 }
5472
5473 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5474                                       struct drm_display_mode *adjusted_mode,
5475                                       intel_clock_t *clock, u32 fp)
5476 {
5477         struct drm_crtc *crtc = &intel_crtc->base;
5478         struct drm_device *dev = crtc->dev;
5479         struct drm_i915_private *dev_priv = dev->dev_private;
5480         struct intel_encoder *intel_encoder;
5481         uint32_t dpll;
5482         int factor, pixel_multiplier, num_connectors = 0;
5483         bool is_lvds = false, is_sdvo = false, is_tv = false;
5484         bool is_dp = false, is_cpu_edp = false;
5485
5486         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5487                 switch (intel_encoder->type) {
5488                 case INTEL_OUTPUT_LVDS:
5489                         is_lvds = true;
5490                         break;
5491                 case INTEL_OUTPUT_SDVO:
5492                 case INTEL_OUTPUT_HDMI:
5493                         is_sdvo = true;
5494                         if (intel_encoder->needs_tv_clock)
5495                                 is_tv = true;
5496                         break;
5497                 case INTEL_OUTPUT_TVOUT:
5498                         is_tv = true;
5499                         break;
5500                 case INTEL_OUTPUT_DISPLAYPORT:
5501                         is_dp = true;
5502                         break;
5503                 case INTEL_OUTPUT_EDP:
5504                         is_dp = true;
5505                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5506                                 is_cpu_edp = true;
5507                         break;
5508                 }
5509
5510                 num_connectors++;
5511         }
5512
5513         /* Enable autotuning of the PLL clock (if permissible) */
5514         factor = 21;
5515         if (is_lvds) {
5516                 if ((intel_panel_use_ssc(dev_priv) &&
5517                      dev_priv->lvds_ssc_freq == 100) ||
5518                     intel_is_dual_link_lvds(dev))
5519                         factor = 25;
5520         } else if (is_sdvo && is_tv)
5521                 factor = 20;
5522
5523         if (clock->m < factor * clock->n)
5524                 fp |= FP_CB_TUNE;
5525
5526         dpll = 0;
5527
5528         if (is_lvds)
5529                 dpll |= DPLLB_MODE_LVDS;
5530         else
5531                 dpll |= DPLLB_MODE_DAC_SERIAL;
5532         if (is_sdvo) {
5533                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5534                 if (pixel_multiplier > 1) {
5535                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5536                 }
5537                 dpll |= DPLL_DVO_HIGH_SPEED;
5538         }
5539         if (is_dp && !is_cpu_edp)
5540                 dpll |= DPLL_DVO_HIGH_SPEED;
5541
5542         /* compute bitmask from p1 value */
5543         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5544         /* also FPA1 */
5545         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5546
5547         switch (clock->p2) {
5548         case 5:
5549                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5550                 break;
5551         case 7:
5552                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5553                 break;
5554         case 10:
5555                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5556                 break;
5557         case 14:
5558                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5559                 break;
5560         }
5561
5562         if (is_sdvo && is_tv)
5563                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5564         else if (is_tv)
5565                 /* XXX: just matching BIOS for now */
5566                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5567                 dpll |= 3;
5568         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5569                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5570         else
5571                 dpll |= PLL_REF_INPUT_DREFCLK;
5572
5573         return dpll;
5574 }
5575
5576 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5577                                   struct drm_display_mode *mode,
5578                                   struct drm_display_mode *adjusted_mode,
5579                                   int x, int y,
5580                                   struct drm_framebuffer *fb)
5581 {
5582         struct drm_device *dev = crtc->dev;
5583         struct drm_i915_private *dev_priv = dev->dev_private;
5584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5585         int pipe = intel_crtc->pipe;
5586         int plane = intel_crtc->plane;
5587         int num_connectors = 0;
5588         intel_clock_t clock, reduced_clock;
5589         u32 dpll, fp = 0, fp2 = 0;
5590         bool ok, has_reduced_clock = false;
5591         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5592         struct intel_encoder *encoder;
5593         int ret;
5594         bool dither, fdi_config_ok;
5595
5596         for_each_encoder_on_crtc(dev, crtc, encoder) {
5597                 switch (encoder->type) {
5598                 case INTEL_OUTPUT_LVDS:
5599                         is_lvds = true;
5600                         break;
5601                 case INTEL_OUTPUT_DISPLAYPORT:
5602                         is_dp = true;
5603                         break;
5604                 case INTEL_OUTPUT_EDP:
5605                         is_dp = true;
5606                         if (!intel_encoder_is_pch_edp(&encoder->base))
5607                                 is_cpu_edp = true;
5608                         break;
5609                 }
5610
5611                 num_connectors++;
5612         }
5613
5614         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5615              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5616
5617         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5618                                      &has_reduced_clock, &reduced_clock);
5619         if (!ok) {
5620                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5621                 return -EINVAL;
5622         }
5623
5624         /* Ensure that the cursor is valid for the new mode before changing... */
5625         intel_crtc_update_cursor(crtc, true);
5626
5627         /* determine panel color depth */
5628         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5629                                               adjusted_mode);
5630         if (is_lvds && dev_priv->lvds_dither)
5631                 dither = true;
5632
5633         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5634         if (has_reduced_clock)
5635                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5636                         reduced_clock.m2;
5637
5638         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5639
5640         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5641         drm_mode_debug_printmodeline(mode);
5642
5643         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5644         if (!is_cpu_edp) {
5645                 struct intel_pch_pll *pll;
5646
5647                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5648                 if (pll == NULL) {
5649                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5650                                          pipe);
5651                         return -EINVAL;
5652                 }
5653         } else
5654                 intel_put_pch_pll(intel_crtc);
5655
5656         if (is_dp && !is_cpu_edp)
5657                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5658
5659         for_each_encoder_on_crtc(dev, crtc, encoder)
5660                 if (encoder->pre_pll_enable)
5661                         encoder->pre_pll_enable(encoder);
5662
5663         if (intel_crtc->pch_pll) {
5664                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5665
5666                 /* Wait for the clocks to stabilize. */
5667                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5668                 udelay(150);
5669
5670                 /* The pixel multiplier can only be updated once the
5671                  * DPLL is enabled and the clocks are stable.
5672                  *
5673                  * So write it again.
5674                  */
5675                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5676         }
5677
5678         intel_crtc->lowfreq_avail = false;
5679         if (intel_crtc->pch_pll) {
5680                 if (is_lvds && has_reduced_clock && i915_powersave) {
5681                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5682                         intel_crtc->lowfreq_avail = true;
5683                 } else {
5684                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5685                 }
5686         }
5687
5688         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5689
5690         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5691          * ironlake_check_fdi_lanes. */
5692         ironlake_set_m_n(crtc, mode, adjusted_mode);
5693
5694         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5695
5696         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5697
5698         intel_wait_for_vblank(dev, pipe);
5699
5700         /* Set up the display plane register */
5701         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5702         POSTING_READ(DSPCNTR(plane));
5703
5704         ret = intel_pipe_set_base(crtc, x, y, fb);
5705
5706         intel_update_watermarks(dev);
5707
5708         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5709
5710         return fdi_config_ok ? ret : -EINVAL;
5711 }
5712
5713 static void haswell_modeset_global_resources(struct drm_device *dev)
5714 {
5715         struct drm_i915_private *dev_priv = dev->dev_private;
5716         bool enable = false;
5717         struct intel_crtc *crtc;
5718         struct intel_encoder *encoder;
5719
5720         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5721                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5722                         enable = true;
5723                 /* XXX: Should check for edp transcoder here, but thanks to init
5724                  * sequence that's not yet available. Just in case desktop eDP
5725                  * on PORT D is possible on haswell, too. */
5726         }
5727
5728         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5729                             base.head) {
5730                 if (encoder->type != INTEL_OUTPUT_EDP &&
5731                     encoder->connectors_active)
5732                         enable = true;
5733         }
5734
5735         /* Even the eDP panel fitter is outside the always-on well. */
5736         if (dev_priv->pch_pf_size)
5737                 enable = true;
5738
5739         intel_set_power_well(dev, enable);
5740 }
5741
5742 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5743                                  struct drm_display_mode *mode,
5744                                  struct drm_display_mode *adjusted_mode,
5745                                  int x, int y,
5746                                  struct drm_framebuffer *fb)
5747 {
5748         struct drm_device *dev = crtc->dev;
5749         struct drm_i915_private *dev_priv = dev->dev_private;
5750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5751         int pipe = intel_crtc->pipe;
5752         int plane = intel_crtc->plane;
5753         int num_connectors = 0;
5754         bool is_dp = false, is_cpu_edp = false;
5755         struct intel_encoder *encoder;
5756         int ret;
5757         bool dither;
5758
5759         for_each_encoder_on_crtc(dev, crtc, encoder) {
5760                 switch (encoder->type) {
5761                 case INTEL_OUTPUT_DISPLAYPORT:
5762                         is_dp = true;
5763                         break;
5764                 case INTEL_OUTPUT_EDP:
5765                         is_dp = true;
5766                         if (!intel_encoder_is_pch_edp(&encoder->base))
5767                                 is_cpu_edp = true;
5768                         break;
5769                 }
5770
5771                 num_connectors++;
5772         }
5773
5774         /* We are not sure yet this won't happen. */
5775         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5776              INTEL_PCH_TYPE(dev));
5777
5778         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5779              num_connectors, pipe_name(pipe));
5780
5781         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5782                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5783
5784         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5785
5786         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5787                 return -EINVAL;
5788
5789         /* Ensure that the cursor is valid for the new mode before changing... */
5790         intel_crtc_update_cursor(crtc, true);
5791
5792         /* determine panel color depth */
5793         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5794                                               adjusted_mode);
5795
5796         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5797         drm_mode_debug_printmodeline(mode);
5798
5799         if (is_dp && !is_cpu_edp)
5800                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5801
5802         intel_crtc->lowfreq_avail = false;
5803
5804         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5805
5806         if (!is_dp || is_cpu_edp)
5807                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5808
5809         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5810
5811         intel_set_pipe_csc(crtc, adjusted_mode);
5812
5813         /* Set up the display plane register */
5814         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5815         POSTING_READ(DSPCNTR(plane));
5816
5817         ret = intel_pipe_set_base(crtc, x, y, fb);
5818
5819         intel_update_watermarks(dev);
5820
5821         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5822
5823         return ret;
5824 }
5825
5826 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5827                                struct drm_display_mode *mode,
5828                                struct drm_display_mode *adjusted_mode,
5829                                int x, int y,
5830                                struct drm_framebuffer *fb)
5831 {
5832         struct drm_device *dev = crtc->dev;
5833         struct drm_i915_private *dev_priv = dev->dev_private;
5834         struct drm_encoder_helper_funcs *encoder_funcs;
5835         struct intel_encoder *encoder;
5836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837         int pipe = intel_crtc->pipe;
5838         int ret;
5839
5840         if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5841                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5842         else
5843                 intel_crtc->cpu_transcoder = pipe;
5844
5845         drm_vblank_pre_modeset(dev, pipe);
5846
5847         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5848                                               x, y, fb);
5849         drm_vblank_post_modeset(dev, pipe);
5850
5851         if (ret != 0)
5852                 return ret;
5853
5854         for_each_encoder_on_crtc(dev, crtc, encoder) {
5855                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5856                         encoder->base.base.id,
5857                         drm_get_encoder_name(&encoder->base),
5858                         mode->base.id, mode->name);
5859                 encoder_funcs = encoder->base.helper_private;
5860                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5861         }
5862
5863         return 0;
5864 }
5865
5866 static bool intel_eld_uptodate(struct drm_connector *connector,
5867                                int reg_eldv, uint32_t bits_eldv,
5868                                int reg_elda, uint32_t bits_elda,
5869                                int reg_edid)
5870 {
5871         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5872         uint8_t *eld = connector->eld;
5873         uint32_t i;
5874
5875         i = I915_READ(reg_eldv);
5876         i &= bits_eldv;
5877
5878         if (!eld[0])
5879                 return !i;
5880
5881         if (!i)
5882                 return false;
5883
5884         i = I915_READ(reg_elda);
5885         i &= ~bits_elda;
5886         I915_WRITE(reg_elda, i);
5887
5888         for (i = 0; i < eld[2]; i++)
5889                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5890                         return false;
5891
5892         return true;
5893 }
5894
5895 static void g4x_write_eld(struct drm_connector *connector,
5896                           struct drm_crtc *crtc)
5897 {
5898         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5899         uint8_t *eld = connector->eld;
5900         uint32_t eldv;
5901         uint32_t len;
5902         uint32_t i;
5903
5904         i = I915_READ(G4X_AUD_VID_DID);
5905
5906         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5907                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5908         else
5909                 eldv = G4X_ELDV_DEVCTG;
5910
5911         if (intel_eld_uptodate(connector,
5912                                G4X_AUD_CNTL_ST, eldv,
5913                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5914                                G4X_HDMIW_HDMIEDID))
5915                 return;
5916
5917         i = I915_READ(G4X_AUD_CNTL_ST);
5918         i &= ~(eldv | G4X_ELD_ADDR);
5919         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5920         I915_WRITE(G4X_AUD_CNTL_ST, i);
5921
5922         if (!eld[0])
5923                 return;
5924
5925         len = min_t(uint8_t, eld[2], len);
5926         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5927         for (i = 0; i < len; i++)
5928                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5929
5930         i = I915_READ(G4X_AUD_CNTL_ST);
5931         i |= eldv;
5932         I915_WRITE(G4X_AUD_CNTL_ST, i);
5933 }
5934
5935 static void haswell_write_eld(struct drm_connector *connector,
5936                                      struct drm_crtc *crtc)
5937 {
5938         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5939         uint8_t *eld = connector->eld;
5940         struct drm_device *dev = crtc->dev;
5941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5942         uint32_t eldv;
5943         uint32_t i;
5944         int len;
5945         int pipe = to_intel_crtc(crtc)->pipe;
5946         int tmp;
5947
5948         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5949         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5950         int aud_config = HSW_AUD_CFG(pipe);
5951         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5952
5953
5954         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5955
5956         /* Audio output enable */
5957         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5958         tmp = I915_READ(aud_cntrl_st2);
5959         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5960         I915_WRITE(aud_cntrl_st2, tmp);
5961
5962         /* Wait for 1 vertical blank */
5963         intel_wait_for_vblank(dev, pipe);
5964
5965         /* Set ELD valid state */
5966         tmp = I915_READ(aud_cntrl_st2);
5967         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5968         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5969         I915_WRITE(aud_cntrl_st2, tmp);
5970         tmp = I915_READ(aud_cntrl_st2);
5971         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5972
5973         /* Enable HDMI mode */
5974         tmp = I915_READ(aud_config);
5975         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5976         /* clear N_programing_enable and N_value_index */
5977         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5978         I915_WRITE(aud_config, tmp);
5979
5980         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5981
5982         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5983         intel_crtc->eld_vld = true;
5984
5985         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5986                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5987                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5988                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5989         } else
5990                 I915_WRITE(aud_config, 0);
5991
5992         if (intel_eld_uptodate(connector,
5993                                aud_cntrl_st2, eldv,
5994                                aud_cntl_st, IBX_ELD_ADDRESS,
5995                                hdmiw_hdmiedid))
5996                 return;
5997
5998         i = I915_READ(aud_cntrl_st2);
5999         i &= ~eldv;
6000         I915_WRITE(aud_cntrl_st2, i);
6001
6002         if (!eld[0])
6003                 return;
6004
6005         i = I915_READ(aud_cntl_st);
6006         i &= ~IBX_ELD_ADDRESS;
6007         I915_WRITE(aud_cntl_st, i);
6008         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6009         DRM_DEBUG_DRIVER("port num:%d\n", i);
6010
6011         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6012         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6013         for (i = 0; i < len; i++)
6014                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6015
6016         i = I915_READ(aud_cntrl_st2);
6017         i |= eldv;
6018         I915_WRITE(aud_cntrl_st2, i);
6019
6020 }
6021
6022 static void ironlake_write_eld(struct drm_connector *connector,
6023                                      struct drm_crtc *crtc)
6024 {
6025         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6026         uint8_t *eld = connector->eld;
6027         uint32_t eldv;
6028         uint32_t i;
6029         int len;
6030         int hdmiw_hdmiedid;
6031         int aud_config;
6032         int aud_cntl_st;
6033         int aud_cntrl_st2;
6034         int pipe = to_intel_crtc(crtc)->pipe;
6035
6036         if (HAS_PCH_IBX(connector->dev)) {
6037                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6038                 aud_config = IBX_AUD_CFG(pipe);
6039                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6040                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6041         } else {
6042                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6043                 aud_config = CPT_AUD_CFG(pipe);
6044                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6045                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6046         }
6047
6048         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6049
6050         i = I915_READ(aud_cntl_st);
6051         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6052         if (!i) {
6053                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6054                 /* operate blindly on all ports */
6055                 eldv = IBX_ELD_VALIDB;
6056                 eldv |= IBX_ELD_VALIDB << 4;
6057                 eldv |= IBX_ELD_VALIDB << 8;
6058         } else {
6059                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6060                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6061         }
6062
6063         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6064                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6065                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6066                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6067         } else
6068                 I915_WRITE(aud_config, 0);
6069
6070         if (intel_eld_uptodate(connector,
6071                                aud_cntrl_st2, eldv,
6072                                aud_cntl_st, IBX_ELD_ADDRESS,
6073                                hdmiw_hdmiedid))
6074                 return;
6075
6076         i = I915_READ(aud_cntrl_st2);
6077         i &= ~eldv;
6078         I915_WRITE(aud_cntrl_st2, i);
6079
6080         if (!eld[0])
6081                 return;
6082
6083         i = I915_READ(aud_cntl_st);
6084         i &= ~IBX_ELD_ADDRESS;
6085         I915_WRITE(aud_cntl_st, i);
6086
6087         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6088         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6089         for (i = 0; i < len; i++)
6090                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6091
6092         i = I915_READ(aud_cntrl_st2);
6093         i |= eldv;
6094         I915_WRITE(aud_cntrl_st2, i);
6095 }
6096
6097 void intel_write_eld(struct drm_encoder *encoder,
6098                      struct drm_display_mode *mode)
6099 {
6100         struct drm_crtc *crtc = encoder->crtc;
6101         struct drm_connector *connector;
6102         struct drm_device *dev = encoder->dev;
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104
6105         connector = drm_select_eld(encoder, mode);
6106         if (!connector)
6107                 return;
6108
6109         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6110                          connector->base.id,
6111                          drm_get_connector_name(connector),
6112                          connector->encoder->base.id,
6113                          drm_get_encoder_name(connector->encoder));
6114
6115         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6116
6117         if (dev_priv->display.write_eld)
6118                 dev_priv->display.write_eld(connector, crtc);
6119 }
6120
6121 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6122 void intel_crtc_load_lut(struct drm_crtc *crtc)
6123 {
6124         struct drm_device *dev = crtc->dev;
6125         struct drm_i915_private *dev_priv = dev->dev_private;
6126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6127         int palreg = PALETTE(intel_crtc->pipe);
6128         int i;
6129
6130         /* The clocks have to be on to load the palette. */
6131         if (!crtc->enabled || !intel_crtc->active)
6132                 return;
6133
6134         /* use legacy palette for Ironlake */
6135         if (HAS_PCH_SPLIT(dev))
6136                 palreg = LGC_PALETTE(intel_crtc->pipe);
6137
6138         for (i = 0; i < 256; i++) {
6139                 I915_WRITE(palreg + 4 * i,
6140                            (intel_crtc->lut_r[i] << 16) |
6141                            (intel_crtc->lut_g[i] << 8) |
6142                            intel_crtc->lut_b[i]);
6143         }
6144 }
6145
6146 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6147 {
6148         struct drm_device *dev = crtc->dev;
6149         struct drm_i915_private *dev_priv = dev->dev_private;
6150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6151         bool visible = base != 0;
6152         u32 cntl;
6153
6154         if (intel_crtc->cursor_visible == visible)
6155                 return;
6156
6157         cntl = I915_READ(_CURACNTR);
6158         if (visible) {
6159                 /* On these chipsets we can only modify the base whilst
6160                  * the cursor is disabled.
6161                  */
6162                 I915_WRITE(_CURABASE, base);
6163
6164                 cntl &= ~(CURSOR_FORMAT_MASK);
6165                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6166                 cntl |= CURSOR_ENABLE |
6167                         CURSOR_GAMMA_ENABLE |
6168                         CURSOR_FORMAT_ARGB;
6169         } else
6170                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6171         I915_WRITE(_CURACNTR, cntl);
6172
6173         intel_crtc->cursor_visible = visible;
6174 }
6175
6176 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6177 {
6178         struct drm_device *dev = crtc->dev;
6179         struct drm_i915_private *dev_priv = dev->dev_private;
6180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181         int pipe = intel_crtc->pipe;
6182         bool visible = base != 0;
6183
6184         if (intel_crtc->cursor_visible != visible) {
6185                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6186                 if (base) {
6187                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6188                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6189                         cntl |= pipe << 28; /* Connect to correct pipe */
6190                 } else {
6191                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6192                         cntl |= CURSOR_MODE_DISABLE;
6193                 }
6194                 I915_WRITE(CURCNTR(pipe), cntl);
6195
6196                 intel_crtc->cursor_visible = visible;
6197         }
6198         /* and commit changes on next vblank */
6199         I915_WRITE(CURBASE(pipe), base);
6200 }
6201
6202 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6203 {
6204         struct drm_device *dev = crtc->dev;
6205         struct drm_i915_private *dev_priv = dev->dev_private;
6206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207         int pipe = intel_crtc->pipe;
6208         bool visible = base != 0;
6209
6210         if (intel_crtc->cursor_visible != visible) {
6211                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6212                 if (base) {
6213                         cntl &= ~CURSOR_MODE;
6214                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6215                 } else {
6216                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6217                         cntl |= CURSOR_MODE_DISABLE;
6218                 }
6219                 if (IS_HASWELL(dev))
6220                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6221                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6222
6223                 intel_crtc->cursor_visible = visible;
6224         }
6225         /* and commit changes on next vblank */
6226         I915_WRITE(CURBASE_IVB(pipe), base);
6227 }
6228
6229 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6230 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6231                                      bool on)
6232 {
6233         struct drm_device *dev = crtc->dev;
6234         struct drm_i915_private *dev_priv = dev->dev_private;
6235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6236         int pipe = intel_crtc->pipe;
6237         int x = intel_crtc->cursor_x;
6238         int y = intel_crtc->cursor_y;
6239         u32 base, pos;
6240         bool visible;
6241
6242         pos = 0;
6243
6244         if (on && crtc->enabled && crtc->fb) {
6245                 base = intel_crtc->cursor_addr;
6246                 if (x > (int) crtc->fb->width)
6247                         base = 0;
6248
6249                 if (y > (int) crtc->fb->height)
6250                         base = 0;
6251         } else
6252                 base = 0;
6253
6254         if (x < 0) {
6255                 if (x + intel_crtc->cursor_width < 0)
6256                         base = 0;
6257
6258                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6259                 x = -x;
6260         }
6261         pos |= x << CURSOR_X_SHIFT;
6262
6263         if (y < 0) {
6264                 if (y + intel_crtc->cursor_height < 0)
6265                         base = 0;
6266
6267                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6268                 y = -y;
6269         }
6270         pos |= y << CURSOR_Y_SHIFT;
6271
6272         visible = base != 0;
6273         if (!visible && !intel_crtc->cursor_visible)
6274                 return;
6275
6276         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6277                 I915_WRITE(CURPOS_IVB(pipe), pos);
6278                 ivb_update_cursor(crtc, base);
6279         } else {
6280                 I915_WRITE(CURPOS(pipe), pos);
6281                 if (IS_845G(dev) || IS_I865G(dev))
6282                         i845_update_cursor(crtc, base);
6283                 else
6284                         i9xx_update_cursor(crtc, base);
6285         }
6286 }
6287
6288 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6289                                  struct drm_file *file,
6290                                  uint32_t handle,
6291                                  uint32_t width, uint32_t height)
6292 {
6293         struct drm_device *dev = crtc->dev;
6294         struct drm_i915_private *dev_priv = dev->dev_private;
6295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6296         struct drm_i915_gem_object *obj;
6297         uint32_t addr;
6298         int ret;
6299
6300         /* if we want to turn off the cursor ignore width and height */
6301         if (!handle) {
6302                 DRM_DEBUG_KMS("cursor off\n");
6303                 addr = 0;
6304                 obj = NULL;
6305                 mutex_lock(&dev->struct_mutex);
6306                 goto finish;
6307         }
6308
6309         /* Currently we only support 64x64 cursors */
6310         if (width != 64 || height != 64) {
6311                 DRM_ERROR("we currently only support 64x64 cursors\n");
6312                 return -EINVAL;
6313         }
6314
6315         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6316         if (&obj->base == NULL)
6317                 return -ENOENT;
6318
6319         if (obj->base.size < width * height * 4) {
6320                 DRM_ERROR("buffer is to small\n");
6321                 ret = -ENOMEM;
6322                 goto fail;
6323         }
6324
6325         /* we only need to pin inside GTT if cursor is non-phy */
6326         mutex_lock(&dev->struct_mutex);
6327         if (!dev_priv->info->cursor_needs_physical) {
6328                 if (obj->tiling_mode) {
6329                         DRM_ERROR("cursor cannot be tiled\n");
6330                         ret = -EINVAL;
6331                         goto fail_locked;
6332                 }
6333
6334                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6335                 if (ret) {
6336                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6337                         goto fail_locked;
6338                 }
6339
6340                 ret = i915_gem_object_put_fence(obj);
6341                 if (ret) {
6342                         DRM_ERROR("failed to release fence for cursor");
6343                         goto fail_unpin;
6344                 }
6345
6346                 addr = obj->gtt_offset;
6347         } else {
6348                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6349                 ret = i915_gem_attach_phys_object(dev, obj,
6350                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6351                                                   align);
6352                 if (ret) {
6353                         DRM_ERROR("failed to attach phys object\n");
6354                         goto fail_locked;
6355                 }
6356                 addr = obj->phys_obj->handle->busaddr;
6357         }
6358
6359         if (IS_GEN2(dev))
6360                 I915_WRITE(CURSIZE, (height << 12) | width);
6361
6362  finish:
6363         if (intel_crtc->cursor_bo) {
6364                 if (dev_priv->info->cursor_needs_physical) {
6365                         if (intel_crtc->cursor_bo != obj)
6366                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6367                 } else
6368                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6369                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6370         }
6371
6372         mutex_unlock(&dev->struct_mutex);
6373
6374         intel_crtc->cursor_addr = addr;
6375         intel_crtc->cursor_bo = obj;
6376         intel_crtc->cursor_width = width;
6377         intel_crtc->cursor_height = height;
6378
6379         intel_crtc_update_cursor(crtc, true);
6380
6381         return 0;
6382 fail_unpin:
6383         i915_gem_object_unpin(obj);
6384 fail_locked:
6385         mutex_unlock(&dev->struct_mutex);
6386 fail:
6387         drm_gem_object_unreference_unlocked(&obj->base);
6388         return ret;
6389 }
6390
6391 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6392 {
6393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394
6395         intel_crtc->cursor_x = x;
6396         intel_crtc->cursor_y = y;
6397
6398         intel_crtc_update_cursor(crtc, true);
6399
6400         return 0;
6401 }
6402
6403 /** Sets the color ramps on behalf of RandR */
6404 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6405                                  u16 blue, int regno)
6406 {
6407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6408
6409         intel_crtc->lut_r[regno] = red >> 8;
6410         intel_crtc->lut_g[regno] = green >> 8;
6411         intel_crtc->lut_b[regno] = blue >> 8;
6412 }
6413
6414 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6415                              u16 *blue, int regno)
6416 {
6417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418
6419         *red = intel_crtc->lut_r[regno] << 8;
6420         *green = intel_crtc->lut_g[regno] << 8;
6421         *blue = intel_crtc->lut_b[regno] << 8;
6422 }
6423
6424 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6425                                  u16 *blue, uint32_t start, uint32_t size)
6426 {
6427         int end = (start + size > 256) ? 256 : start + size, i;
6428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6429
6430         for (i = start; i < end; i++) {
6431                 intel_crtc->lut_r[i] = red[i] >> 8;
6432                 intel_crtc->lut_g[i] = green[i] >> 8;
6433                 intel_crtc->lut_b[i] = blue[i] >> 8;
6434         }
6435
6436         intel_crtc_load_lut(crtc);
6437 }
6438
6439 /**
6440  * Get a pipe with a simple mode set on it for doing load-based monitor
6441  * detection.
6442  *
6443  * It will be up to the load-detect code to adjust the pipe as appropriate for
6444  * its requirements.  The pipe will be connected to no other encoders.
6445  *
6446  * Currently this code will only succeed if there is a pipe with no encoders
6447  * configured for it.  In the future, it could choose to temporarily disable
6448  * some outputs to free up a pipe for its use.
6449  *
6450  * \return crtc, or NULL if no pipes are available.
6451  */
6452
6453 /* VESA 640x480x72Hz mode to set on the pipe */
6454 static struct drm_display_mode load_detect_mode = {
6455         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6456                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6457 };
6458
6459 static struct drm_framebuffer *
6460 intel_framebuffer_create(struct drm_device *dev,
6461                          struct drm_mode_fb_cmd2 *mode_cmd,
6462                          struct drm_i915_gem_object *obj)
6463 {
6464         struct intel_framebuffer *intel_fb;
6465         int ret;
6466
6467         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6468         if (!intel_fb) {
6469                 drm_gem_object_unreference_unlocked(&obj->base);
6470                 return ERR_PTR(-ENOMEM);
6471         }
6472
6473         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6474         if (ret) {
6475                 drm_gem_object_unreference_unlocked(&obj->base);
6476                 kfree(intel_fb);
6477                 return ERR_PTR(ret);
6478         }
6479
6480         return &intel_fb->base;
6481 }
6482
6483 static u32
6484 intel_framebuffer_pitch_for_width(int width, int bpp)
6485 {
6486         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6487         return ALIGN(pitch, 64);
6488 }
6489
6490 static u32
6491 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6492 {
6493         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6494         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6495 }
6496
6497 static struct drm_framebuffer *
6498 intel_framebuffer_create_for_mode(struct drm_device *dev,
6499                                   struct drm_display_mode *mode,
6500                                   int depth, int bpp)
6501 {
6502         struct drm_i915_gem_object *obj;
6503         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6504
6505         obj = i915_gem_alloc_object(dev,
6506                                     intel_framebuffer_size_for_mode(mode, bpp));
6507         if (obj == NULL)
6508                 return ERR_PTR(-ENOMEM);
6509
6510         mode_cmd.width = mode->hdisplay;
6511         mode_cmd.height = mode->vdisplay;
6512         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6513                                                                 bpp);
6514         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6515
6516         return intel_framebuffer_create(dev, &mode_cmd, obj);
6517 }
6518
6519 static struct drm_framebuffer *
6520 mode_fits_in_fbdev(struct drm_device *dev,
6521                    struct drm_display_mode *mode)
6522 {
6523         struct drm_i915_private *dev_priv = dev->dev_private;
6524         struct drm_i915_gem_object *obj;
6525         struct drm_framebuffer *fb;
6526
6527         if (dev_priv->fbdev == NULL)
6528                 return NULL;
6529
6530         obj = dev_priv->fbdev->ifb.obj;
6531         if (obj == NULL)
6532                 return NULL;
6533
6534         fb = &dev_priv->fbdev->ifb.base;
6535         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6536                                                                fb->bits_per_pixel))
6537                 return NULL;
6538
6539         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6540                 return NULL;
6541
6542         return fb;
6543 }
6544
6545 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6546                                 struct drm_display_mode *mode,
6547                                 struct intel_load_detect_pipe *old)
6548 {
6549         struct intel_crtc *intel_crtc;
6550         struct intel_encoder *intel_encoder =
6551                 intel_attached_encoder(connector);
6552         struct drm_crtc *possible_crtc;
6553         struct drm_encoder *encoder = &intel_encoder->base;
6554         struct drm_crtc *crtc = NULL;
6555         struct drm_device *dev = encoder->dev;
6556         struct drm_framebuffer *fb;
6557         int i = -1;
6558
6559         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6560                       connector->base.id, drm_get_connector_name(connector),
6561                       encoder->base.id, drm_get_encoder_name(encoder));
6562
6563         /*
6564          * Algorithm gets a little messy:
6565          *
6566          *   - if the connector already has an assigned crtc, use it (but make
6567          *     sure it's on first)
6568          *
6569          *   - try to find the first unused crtc that can drive this connector,
6570          *     and use that if we find one
6571          */
6572
6573         /* See if we already have a CRTC for this connector */
6574         if (encoder->crtc) {
6575                 crtc = encoder->crtc;
6576
6577                 mutex_lock(&crtc->mutex);
6578
6579                 old->dpms_mode = connector->dpms;
6580                 old->load_detect_temp = false;
6581
6582                 /* Make sure the crtc and connector are running */
6583                 if (connector->dpms != DRM_MODE_DPMS_ON)
6584                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6585
6586                 return true;
6587         }
6588
6589         /* Find an unused one (if possible) */
6590         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6591                 i++;
6592                 if (!(encoder->possible_crtcs & (1 << i)))
6593                         continue;
6594                 if (!possible_crtc->enabled) {
6595                         crtc = possible_crtc;
6596                         break;
6597                 }
6598         }
6599
6600         /*
6601          * If we didn't find an unused CRTC, don't use any.
6602          */
6603         if (!crtc) {
6604                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6605                 return false;
6606         }
6607
6608         mutex_lock(&crtc->mutex);
6609         intel_encoder->new_crtc = to_intel_crtc(crtc);
6610         to_intel_connector(connector)->new_encoder = intel_encoder;
6611
6612         intel_crtc = to_intel_crtc(crtc);
6613         old->dpms_mode = connector->dpms;
6614         old->load_detect_temp = true;
6615         old->release_fb = NULL;
6616
6617         if (!mode)
6618                 mode = &load_detect_mode;
6619
6620         /* We need a framebuffer large enough to accommodate all accesses
6621          * that the plane may generate whilst we perform load detection.
6622          * We can not rely on the fbcon either being present (we get called
6623          * during its initialisation to detect all boot displays, or it may
6624          * not even exist) or that it is large enough to satisfy the
6625          * requested mode.
6626          */
6627         fb = mode_fits_in_fbdev(dev, mode);
6628         if (fb == NULL) {
6629                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6630                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6631                 old->release_fb = fb;
6632         } else
6633                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6634         if (IS_ERR(fb)) {
6635                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6636                 mutex_unlock(&crtc->mutex);
6637                 return false;
6638         }
6639
6640         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6641                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6642                 if (old->release_fb)
6643                         old->release_fb->funcs->destroy(old->release_fb);
6644                 mutex_unlock(&crtc->mutex);
6645                 return false;
6646         }
6647
6648         /* let the connector get through one full cycle before testing */
6649         intel_wait_for_vblank(dev, intel_crtc->pipe);
6650         return true;
6651 }
6652
6653 void intel_release_load_detect_pipe(struct drm_connector *connector,
6654                                     struct intel_load_detect_pipe *old)
6655 {
6656         struct intel_encoder *intel_encoder =
6657                 intel_attached_encoder(connector);
6658         struct drm_encoder *encoder = &intel_encoder->base;
6659         struct drm_crtc *crtc = encoder->crtc;
6660
6661         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6662                       connector->base.id, drm_get_connector_name(connector),
6663                       encoder->base.id, drm_get_encoder_name(encoder));
6664
6665         if (old->load_detect_temp) {
6666                 to_intel_connector(connector)->new_encoder = NULL;
6667                 intel_encoder->new_crtc = NULL;
6668                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6669
6670                 if (old->release_fb) {
6671                         drm_framebuffer_unregister_private(old->release_fb);
6672                         drm_framebuffer_unreference(old->release_fb);
6673                 }
6674
6675                 mutex_unlock(&crtc->mutex);
6676                 return;
6677         }
6678
6679         /* Switch crtc and encoder back off if necessary */
6680         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6681                 connector->funcs->dpms(connector, old->dpms_mode);
6682
6683         mutex_unlock(&crtc->mutex);
6684 }
6685
6686 /* Returns the clock of the currently programmed mode of the given pipe. */
6687 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6688 {
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691         int pipe = intel_crtc->pipe;
6692         u32 dpll = I915_READ(DPLL(pipe));
6693         u32 fp;
6694         intel_clock_t clock;
6695
6696         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6697                 fp = I915_READ(FP0(pipe));
6698         else
6699                 fp = I915_READ(FP1(pipe));
6700
6701         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6702         if (IS_PINEVIEW(dev)) {
6703                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6704                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6705         } else {
6706                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6707                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6708         }
6709
6710         if (!IS_GEN2(dev)) {
6711                 if (IS_PINEVIEW(dev))
6712                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6713                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6714                 else
6715                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6716                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6717
6718                 switch (dpll & DPLL_MODE_MASK) {
6719                 case DPLLB_MODE_DAC_SERIAL:
6720                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6721                                 5 : 10;
6722                         break;
6723                 case DPLLB_MODE_LVDS:
6724                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6725                                 7 : 14;
6726                         break;
6727                 default:
6728                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6729                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6730                         return 0;
6731                 }
6732
6733                 /* XXX: Handle the 100Mhz refclk */
6734                 intel_clock(dev, 96000, &clock);
6735         } else {
6736                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6737
6738                 if (is_lvds) {
6739                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6740                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6741                         clock.p2 = 14;
6742
6743                         if ((dpll & PLL_REF_INPUT_MASK) ==
6744                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6745                                 /* XXX: might not be 66MHz */
6746                                 intel_clock(dev, 66000, &clock);
6747                         } else
6748                                 intel_clock(dev, 48000, &clock);
6749                 } else {
6750                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6751                                 clock.p1 = 2;
6752                         else {
6753                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6754                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6755                         }
6756                         if (dpll & PLL_P2_DIVIDE_BY_4)
6757                                 clock.p2 = 4;
6758                         else
6759                                 clock.p2 = 2;
6760
6761                         intel_clock(dev, 48000, &clock);
6762                 }
6763         }
6764
6765         /* XXX: It would be nice to validate the clocks, but we can't reuse
6766          * i830PllIsValid() because it relies on the xf86_config connector
6767          * configuration being accurate, which it isn't necessarily.
6768          */
6769
6770         return clock.dot;
6771 }
6772
6773 /** Returns the currently programmed mode of the given pipe. */
6774 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6775                                              struct drm_crtc *crtc)
6776 {
6777         struct drm_i915_private *dev_priv = dev->dev_private;
6778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6779         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6780         struct drm_display_mode *mode;
6781         int htot = I915_READ(HTOTAL(cpu_transcoder));
6782         int hsync = I915_READ(HSYNC(cpu_transcoder));
6783         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6784         int vsync = I915_READ(VSYNC(cpu_transcoder));
6785
6786         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6787         if (!mode)
6788                 return NULL;
6789
6790         mode->clock = intel_crtc_clock_get(dev, crtc);
6791         mode->hdisplay = (htot & 0xffff) + 1;
6792         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6793         mode->hsync_start = (hsync & 0xffff) + 1;
6794         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6795         mode->vdisplay = (vtot & 0xffff) + 1;
6796         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6797         mode->vsync_start = (vsync & 0xffff) + 1;
6798         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6799
6800         drm_mode_set_name(mode);
6801
6802         return mode;
6803 }
6804
6805 static void intel_increase_pllclock(struct drm_crtc *crtc)
6806 {
6807         struct drm_device *dev = crtc->dev;
6808         drm_i915_private_t *dev_priv = dev->dev_private;
6809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810         int pipe = intel_crtc->pipe;
6811         int dpll_reg = DPLL(pipe);
6812         int dpll;
6813
6814         if (HAS_PCH_SPLIT(dev))
6815                 return;
6816
6817         if (!dev_priv->lvds_downclock_avail)
6818                 return;
6819
6820         dpll = I915_READ(dpll_reg);
6821         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6822                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6823
6824                 assert_panel_unlocked(dev_priv, pipe);
6825
6826                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6827                 I915_WRITE(dpll_reg, dpll);
6828                 intel_wait_for_vblank(dev, pipe);
6829
6830                 dpll = I915_READ(dpll_reg);
6831                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6832                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6833         }
6834 }
6835
6836 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6837 {
6838         struct drm_device *dev = crtc->dev;
6839         drm_i915_private_t *dev_priv = dev->dev_private;
6840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6841
6842         if (HAS_PCH_SPLIT(dev))
6843                 return;
6844
6845         if (!dev_priv->lvds_downclock_avail)
6846                 return;
6847
6848         /*
6849          * Since this is called by a timer, we should never get here in
6850          * the manual case.
6851          */
6852         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6853                 int pipe = intel_crtc->pipe;
6854                 int dpll_reg = DPLL(pipe);
6855                 int dpll;
6856
6857                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6858
6859                 assert_panel_unlocked(dev_priv, pipe);
6860
6861                 dpll = I915_READ(dpll_reg);
6862                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6863                 I915_WRITE(dpll_reg, dpll);
6864                 intel_wait_for_vblank(dev, pipe);
6865                 dpll = I915_READ(dpll_reg);
6866                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6867                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6868         }
6869
6870 }
6871
6872 void intel_mark_busy(struct drm_device *dev)
6873 {
6874         i915_update_gfx_val(dev->dev_private);
6875 }
6876
6877 void intel_mark_idle(struct drm_device *dev)
6878 {
6879         struct drm_crtc *crtc;
6880
6881         if (!i915_powersave)
6882                 return;
6883
6884         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6885                 if (!crtc->fb)
6886                         continue;
6887
6888                 intel_decrease_pllclock(crtc);
6889         }
6890 }
6891
6892 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6893 {
6894         struct drm_device *dev = obj->base.dev;
6895         struct drm_crtc *crtc;
6896
6897         if (!i915_powersave)
6898                 return;
6899
6900         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6901                 if (!crtc->fb)
6902                         continue;
6903
6904                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6905                         intel_increase_pllclock(crtc);
6906         }
6907 }
6908
6909 static void intel_crtc_destroy(struct drm_crtc *crtc)
6910 {
6911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912         struct drm_device *dev = crtc->dev;
6913         struct intel_unpin_work *work;
6914         unsigned long flags;
6915
6916         spin_lock_irqsave(&dev->event_lock, flags);
6917         work = intel_crtc->unpin_work;
6918         intel_crtc->unpin_work = NULL;
6919         spin_unlock_irqrestore(&dev->event_lock, flags);
6920
6921         if (work) {
6922                 cancel_work_sync(&work->work);
6923                 kfree(work);
6924         }
6925
6926         drm_crtc_cleanup(crtc);
6927
6928         kfree(intel_crtc);
6929 }
6930
6931 static void intel_unpin_work_fn(struct work_struct *__work)
6932 {
6933         struct intel_unpin_work *work =
6934                 container_of(__work, struct intel_unpin_work, work);
6935         struct drm_device *dev = work->crtc->dev;
6936
6937         mutex_lock(&dev->struct_mutex);
6938         intel_unpin_fb_obj(work->old_fb_obj);
6939         drm_gem_object_unreference(&work->pending_flip_obj->base);
6940         drm_gem_object_unreference(&work->old_fb_obj->base);
6941
6942         intel_update_fbc(dev);
6943         mutex_unlock(&dev->struct_mutex);
6944
6945         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6946         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6947
6948         kfree(work);
6949 }
6950
6951 static void do_intel_finish_page_flip(struct drm_device *dev,
6952                                       struct drm_crtc *crtc)
6953 {
6954         drm_i915_private_t *dev_priv = dev->dev_private;
6955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6956         struct intel_unpin_work *work;
6957         struct drm_i915_gem_object *obj;
6958         unsigned long flags;
6959
6960         /* Ignore early vblank irqs */
6961         if (intel_crtc == NULL)
6962                 return;
6963
6964         spin_lock_irqsave(&dev->event_lock, flags);
6965         work = intel_crtc->unpin_work;
6966
6967         /* Ensure we don't miss a work->pending update ... */
6968         smp_rmb();
6969
6970         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6971                 spin_unlock_irqrestore(&dev->event_lock, flags);
6972                 return;
6973         }
6974
6975         /* and that the unpin work is consistent wrt ->pending. */
6976         smp_rmb();
6977
6978         intel_crtc->unpin_work = NULL;
6979
6980         if (work->event)
6981                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6982
6983         drm_vblank_put(dev, intel_crtc->pipe);
6984
6985         spin_unlock_irqrestore(&dev->event_lock, flags);
6986
6987         obj = work->old_fb_obj;
6988
6989         wake_up_all(&dev_priv->pending_flip_queue);
6990
6991         queue_work(dev_priv->wq, &work->work);
6992
6993         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6994 }
6995
6996 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6997 {
6998         drm_i915_private_t *dev_priv = dev->dev_private;
6999         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7000
7001         do_intel_finish_page_flip(dev, crtc);
7002 }
7003
7004 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7005 {
7006         drm_i915_private_t *dev_priv = dev->dev_private;
7007         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7008
7009         do_intel_finish_page_flip(dev, crtc);
7010 }
7011
7012 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7013 {
7014         drm_i915_private_t *dev_priv = dev->dev_private;
7015         struct intel_crtc *intel_crtc =
7016                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7017         unsigned long flags;
7018
7019         /* NB: An MMIO update of the plane base pointer will also
7020          * generate a page-flip completion irq, i.e. every modeset
7021          * is also accompanied by a spurious intel_prepare_page_flip().
7022          */
7023         spin_lock_irqsave(&dev->event_lock, flags);
7024         if (intel_crtc->unpin_work)
7025                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7026         spin_unlock_irqrestore(&dev->event_lock, flags);
7027 }
7028
7029 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7030 {
7031         /* Ensure that the work item is consistent when activating it ... */
7032         smp_wmb();
7033         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7034         /* and that it is marked active as soon as the irq could fire. */
7035         smp_wmb();
7036 }
7037
7038 static int intel_gen2_queue_flip(struct drm_device *dev,
7039                                  struct drm_crtc *crtc,
7040                                  struct drm_framebuffer *fb,
7041                                  struct drm_i915_gem_object *obj)
7042 {
7043         struct drm_i915_private *dev_priv = dev->dev_private;
7044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7045         u32 flip_mask;
7046         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7047         int ret;
7048
7049         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7050         if (ret)
7051                 goto err;
7052
7053         ret = intel_ring_begin(ring, 6);
7054         if (ret)
7055                 goto err_unpin;
7056
7057         /* Can't queue multiple flips, so wait for the previous
7058          * one to finish before executing the next.
7059          */
7060         if (intel_crtc->plane)
7061                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7062         else
7063                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7064         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7065         intel_ring_emit(ring, MI_NOOP);
7066         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7067                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7068         intel_ring_emit(ring, fb->pitches[0]);
7069         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7070         intel_ring_emit(ring, 0); /* aux display base address, unused */
7071
7072         intel_mark_page_flip_active(intel_crtc);
7073         intel_ring_advance(ring);
7074         return 0;
7075
7076 err_unpin:
7077         intel_unpin_fb_obj(obj);
7078 err:
7079         return ret;
7080 }
7081
7082 static int intel_gen3_queue_flip(struct drm_device *dev,
7083                                  struct drm_crtc *crtc,
7084                                  struct drm_framebuffer *fb,
7085                                  struct drm_i915_gem_object *obj)
7086 {
7087         struct drm_i915_private *dev_priv = dev->dev_private;
7088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089         u32 flip_mask;
7090         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7091         int ret;
7092
7093         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7094         if (ret)
7095                 goto err;
7096
7097         ret = intel_ring_begin(ring, 6);
7098         if (ret)
7099                 goto err_unpin;
7100
7101         if (intel_crtc->plane)
7102                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7103         else
7104                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7105         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7106         intel_ring_emit(ring, MI_NOOP);
7107         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7108                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7109         intel_ring_emit(ring, fb->pitches[0]);
7110         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7111         intel_ring_emit(ring, MI_NOOP);
7112
7113         intel_mark_page_flip_active(intel_crtc);
7114         intel_ring_advance(ring);
7115         return 0;
7116
7117 err_unpin:
7118         intel_unpin_fb_obj(obj);
7119 err:
7120         return ret;
7121 }
7122
7123 static int intel_gen4_queue_flip(struct drm_device *dev,
7124                                  struct drm_crtc *crtc,
7125                                  struct drm_framebuffer *fb,
7126                                  struct drm_i915_gem_object *obj)
7127 {
7128         struct drm_i915_private *dev_priv = dev->dev_private;
7129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7130         uint32_t pf, pipesrc;
7131         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7132         int ret;
7133
7134         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7135         if (ret)
7136                 goto err;
7137
7138         ret = intel_ring_begin(ring, 4);
7139         if (ret)
7140                 goto err_unpin;
7141
7142         /* i965+ uses the linear or tiled offsets from the
7143          * Display Registers (which do not change across a page-flip)
7144          * so we need only reprogram the base address.
7145          */
7146         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7147                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7148         intel_ring_emit(ring, fb->pitches[0]);
7149         intel_ring_emit(ring,
7150                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7151                         obj->tiling_mode);
7152
7153         /* XXX Enabling the panel-fitter across page-flip is so far
7154          * untested on non-native modes, so ignore it for now.
7155          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7156          */
7157         pf = 0;
7158         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7159         intel_ring_emit(ring, pf | pipesrc);
7160
7161         intel_mark_page_flip_active(intel_crtc);
7162         intel_ring_advance(ring);
7163         return 0;
7164
7165 err_unpin:
7166         intel_unpin_fb_obj(obj);
7167 err:
7168         return ret;
7169 }
7170
7171 static int intel_gen6_queue_flip(struct drm_device *dev,
7172                                  struct drm_crtc *crtc,
7173                                  struct drm_framebuffer *fb,
7174                                  struct drm_i915_gem_object *obj)
7175 {
7176         struct drm_i915_private *dev_priv = dev->dev_private;
7177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7178         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7179         uint32_t pf, pipesrc;
7180         int ret;
7181
7182         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7183         if (ret)
7184                 goto err;
7185
7186         ret = intel_ring_begin(ring, 4);
7187         if (ret)
7188                 goto err_unpin;
7189
7190         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7191                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7192         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7193         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7194
7195         /* Contrary to the suggestions in the documentation,
7196          * "Enable Panel Fitter" does not seem to be required when page
7197          * flipping with a non-native mode, and worse causes a normal
7198          * modeset to fail.
7199          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7200          */
7201         pf = 0;
7202         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7203         intel_ring_emit(ring, pf | pipesrc);
7204
7205         intel_mark_page_flip_active(intel_crtc);
7206         intel_ring_advance(ring);
7207         return 0;
7208
7209 err_unpin:
7210         intel_unpin_fb_obj(obj);
7211 err:
7212         return ret;
7213 }
7214
7215 /*
7216  * On gen7 we currently use the blit ring because (in early silicon at least)
7217  * the render ring doesn't give us interrpts for page flip completion, which
7218  * means clients will hang after the first flip is queued.  Fortunately the
7219  * blit ring generates interrupts properly, so use it instead.
7220  */
7221 static int intel_gen7_queue_flip(struct drm_device *dev,
7222                                  struct drm_crtc *crtc,
7223                                  struct drm_framebuffer *fb,
7224                                  struct drm_i915_gem_object *obj)
7225 {
7226         struct drm_i915_private *dev_priv = dev->dev_private;
7227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7228         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7229         uint32_t plane_bit = 0;
7230         int ret;
7231
7232         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7233         if (ret)
7234                 goto err;
7235
7236         switch(intel_crtc->plane) {
7237         case PLANE_A:
7238                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7239                 break;
7240         case PLANE_B:
7241                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7242                 break;
7243         case PLANE_C:
7244                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7245                 break;
7246         default:
7247                 WARN_ONCE(1, "unknown plane in flip command\n");
7248                 ret = -ENODEV;
7249                 goto err_unpin;
7250         }
7251
7252         ret = intel_ring_begin(ring, 4);
7253         if (ret)
7254                 goto err_unpin;
7255
7256         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7257         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7258         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7259         intel_ring_emit(ring, (MI_NOOP));
7260
7261         intel_mark_page_flip_active(intel_crtc);
7262         intel_ring_advance(ring);
7263         return 0;
7264
7265 err_unpin:
7266         intel_unpin_fb_obj(obj);
7267 err:
7268         return ret;
7269 }
7270
7271 static int intel_default_queue_flip(struct drm_device *dev,
7272                                     struct drm_crtc *crtc,
7273                                     struct drm_framebuffer *fb,
7274                                     struct drm_i915_gem_object *obj)
7275 {
7276         return -ENODEV;
7277 }
7278
7279 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7280                                 struct drm_framebuffer *fb,
7281                                 struct drm_pending_vblank_event *event)
7282 {
7283         struct drm_device *dev = crtc->dev;
7284         struct drm_i915_private *dev_priv = dev->dev_private;
7285         struct drm_framebuffer *old_fb = crtc->fb;
7286         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7288         struct intel_unpin_work *work;
7289         unsigned long flags;
7290         int ret;
7291
7292         /* Can't change pixel format via MI display flips. */
7293         if (fb->pixel_format != crtc->fb->pixel_format)
7294                 return -EINVAL;
7295
7296         /*
7297          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7298          * Note that pitch changes could also affect these register.
7299          */
7300         if (INTEL_INFO(dev)->gen > 3 &&
7301             (fb->offsets[0] != crtc->fb->offsets[0] ||
7302              fb->pitches[0] != crtc->fb->pitches[0]))
7303                 return -EINVAL;
7304
7305         work = kzalloc(sizeof *work, GFP_KERNEL);
7306         if (work == NULL)
7307                 return -ENOMEM;
7308
7309         work->event = event;
7310         work->crtc = crtc;
7311         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7312         INIT_WORK(&work->work, intel_unpin_work_fn);
7313
7314         ret = drm_vblank_get(dev, intel_crtc->pipe);
7315         if (ret)
7316                 goto free_work;
7317
7318         /* We borrow the event spin lock for protecting unpin_work */
7319         spin_lock_irqsave(&dev->event_lock, flags);
7320         if (intel_crtc->unpin_work) {
7321                 spin_unlock_irqrestore(&dev->event_lock, flags);
7322                 kfree(work);
7323                 drm_vblank_put(dev, intel_crtc->pipe);
7324
7325                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7326                 return -EBUSY;
7327         }
7328         intel_crtc->unpin_work = work;
7329         spin_unlock_irqrestore(&dev->event_lock, flags);
7330
7331         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7332                 flush_workqueue(dev_priv->wq);
7333
7334         ret = i915_mutex_lock_interruptible(dev);
7335         if (ret)
7336                 goto cleanup;
7337
7338         /* Reference the objects for the scheduled work. */
7339         drm_gem_object_reference(&work->old_fb_obj->base);
7340         drm_gem_object_reference(&obj->base);
7341
7342         crtc->fb = fb;
7343
7344         work->pending_flip_obj = obj;
7345
7346         work->enable_stall_check = true;
7347
7348         atomic_inc(&intel_crtc->unpin_work_count);
7349         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7350
7351         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7352         if (ret)
7353                 goto cleanup_pending;
7354
7355         intel_disable_fbc(dev);
7356         intel_mark_fb_busy(obj);
7357         mutex_unlock(&dev->struct_mutex);
7358
7359         trace_i915_flip_request(intel_crtc->plane, obj);
7360
7361         return 0;
7362
7363 cleanup_pending:
7364         atomic_dec(&intel_crtc->unpin_work_count);
7365         crtc->fb = old_fb;
7366         drm_gem_object_unreference(&work->old_fb_obj->base);
7367         drm_gem_object_unreference(&obj->base);
7368         mutex_unlock(&dev->struct_mutex);
7369
7370 cleanup:
7371         spin_lock_irqsave(&dev->event_lock, flags);
7372         intel_crtc->unpin_work = NULL;
7373         spin_unlock_irqrestore(&dev->event_lock, flags);
7374
7375         drm_vblank_put(dev, intel_crtc->pipe);
7376 free_work:
7377         kfree(work);
7378
7379         return ret;
7380 }
7381
7382 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7383         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7384         .load_lut = intel_crtc_load_lut,
7385 };
7386
7387 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7388 {
7389         struct intel_encoder *other_encoder;
7390         struct drm_crtc *crtc = &encoder->new_crtc->base;
7391
7392         if (WARN_ON(!crtc))
7393                 return false;
7394
7395         list_for_each_entry(other_encoder,
7396                             &crtc->dev->mode_config.encoder_list,
7397                             base.head) {
7398
7399                 if (&other_encoder->new_crtc->base != crtc ||
7400                     encoder == other_encoder)
7401                         continue;
7402                 else
7403                         return true;
7404         }
7405
7406         return false;
7407 }
7408
7409 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7410                                   struct drm_crtc *crtc)
7411 {
7412         struct drm_device *dev;
7413         struct drm_crtc *tmp;
7414         int crtc_mask = 1;
7415
7416         WARN(!crtc, "checking null crtc?\n");
7417
7418         dev = crtc->dev;
7419
7420         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7421                 if (tmp == crtc)
7422                         break;
7423                 crtc_mask <<= 1;
7424         }
7425
7426         if (encoder->possible_crtcs & crtc_mask)
7427                 return true;
7428         return false;
7429 }
7430
7431 /**
7432  * intel_modeset_update_staged_output_state
7433  *
7434  * Updates the staged output configuration state, e.g. after we've read out the
7435  * current hw state.
7436  */
7437 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7438 {
7439         struct intel_encoder *encoder;
7440         struct intel_connector *connector;
7441
7442         list_for_each_entry(connector, &dev->mode_config.connector_list,
7443                             base.head) {
7444                 connector->new_encoder =
7445                         to_intel_encoder(connector->base.encoder);
7446         }
7447
7448         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7449                             base.head) {
7450                 encoder->new_crtc =
7451                         to_intel_crtc(encoder->base.crtc);
7452         }
7453 }
7454
7455 /**
7456  * intel_modeset_commit_output_state
7457  *
7458  * This function copies the stage display pipe configuration to the real one.
7459  */
7460 static void intel_modeset_commit_output_state(struct drm_device *dev)
7461 {
7462         struct intel_encoder *encoder;
7463         struct intel_connector *connector;
7464
7465         list_for_each_entry(connector, &dev->mode_config.connector_list,
7466                             base.head) {
7467                 connector->base.encoder = &connector->new_encoder->base;
7468         }
7469
7470         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7471                             base.head) {
7472                 encoder->base.crtc = &encoder->new_crtc->base;
7473         }
7474 }
7475
7476 static struct drm_display_mode *
7477 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7478                             struct drm_display_mode *mode)
7479 {
7480         struct drm_device *dev = crtc->dev;
7481         struct drm_display_mode *adjusted_mode;
7482         struct drm_encoder_helper_funcs *encoder_funcs;
7483         struct intel_encoder *encoder;
7484
7485         adjusted_mode = drm_mode_duplicate(dev, mode);
7486         if (!adjusted_mode)
7487                 return ERR_PTR(-ENOMEM);
7488
7489         /* Pass our mode to the connectors and the CRTC to give them a chance to
7490          * adjust it according to limitations or connector properties, and also
7491          * a chance to reject the mode entirely.
7492          */
7493         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7494                             base.head) {
7495
7496                 if (&encoder->new_crtc->base != crtc)
7497                         continue;
7498                 encoder_funcs = encoder->base.helper_private;
7499                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7500                                                 adjusted_mode))) {
7501                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7502                         goto fail;
7503                 }
7504         }
7505
7506         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7507                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7508                 goto fail;
7509         }
7510         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7511
7512         return adjusted_mode;
7513 fail:
7514         drm_mode_destroy(dev, adjusted_mode);
7515         return ERR_PTR(-EINVAL);
7516 }
7517
7518 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7519  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7520 static void
7521 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7522                              unsigned *prepare_pipes, unsigned *disable_pipes)
7523 {
7524         struct intel_crtc *intel_crtc;
7525         struct drm_device *dev = crtc->dev;
7526         struct intel_encoder *encoder;
7527         struct intel_connector *connector;
7528         struct drm_crtc *tmp_crtc;
7529
7530         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7531
7532         /* Check which crtcs have changed outputs connected to them, these need
7533          * to be part of the prepare_pipes mask. We don't (yet) support global
7534          * modeset across multiple crtcs, so modeset_pipes will only have one
7535          * bit set at most. */
7536         list_for_each_entry(connector, &dev->mode_config.connector_list,
7537                             base.head) {
7538                 if (connector->base.encoder == &connector->new_encoder->base)
7539                         continue;
7540
7541                 if (connector->base.encoder) {
7542                         tmp_crtc = connector->base.encoder->crtc;
7543
7544                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7545                 }
7546
7547                 if (connector->new_encoder)
7548                         *prepare_pipes |=
7549                                 1 << connector->new_encoder->new_crtc->pipe;
7550         }
7551
7552         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7553                             base.head) {
7554                 if (encoder->base.crtc == &encoder->new_crtc->base)
7555                         continue;
7556
7557                 if (encoder->base.crtc) {
7558                         tmp_crtc = encoder->base.crtc;
7559
7560                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7561                 }
7562
7563                 if (encoder->new_crtc)
7564                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7565         }
7566
7567         /* Check for any pipes that will be fully disabled ... */
7568         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7569                             base.head) {
7570                 bool used = false;
7571
7572                 /* Don't try to disable disabled crtcs. */
7573                 if (!intel_crtc->base.enabled)
7574                         continue;
7575
7576                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7577                                     base.head) {
7578                         if (encoder->new_crtc == intel_crtc)
7579                                 used = true;
7580                 }
7581
7582                 if (!used)
7583                         *disable_pipes |= 1 << intel_crtc->pipe;
7584         }
7585
7586
7587         /* set_mode is also used to update properties on life display pipes. */
7588         intel_crtc = to_intel_crtc(crtc);
7589         if (crtc->enabled)
7590                 *prepare_pipes |= 1 << intel_crtc->pipe;
7591
7592         /* We only support modeset on one single crtc, hence we need to do that
7593          * only for the passed in crtc iff we change anything else than just
7594          * disable crtcs.
7595          *
7596          * This is actually not true, to be fully compatible with the old crtc
7597          * helper we automatically disable _any_ output (i.e. doesn't need to be
7598          * connected to the crtc we're modesetting on) if it's disconnected.
7599          * Which is a rather nutty api (since changed the output configuration
7600          * without userspace's explicit request can lead to confusion), but
7601          * alas. Hence we currently need to modeset on all pipes we prepare. */
7602         if (*prepare_pipes)
7603                 *modeset_pipes = *prepare_pipes;
7604
7605         /* ... and mask these out. */
7606         *modeset_pipes &= ~(*disable_pipes);
7607         *prepare_pipes &= ~(*disable_pipes);
7608 }
7609
7610 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7611 {
7612         struct drm_encoder *encoder;
7613         struct drm_device *dev = crtc->dev;
7614
7615         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7616                 if (encoder->crtc == crtc)
7617                         return true;
7618
7619         return false;
7620 }
7621
7622 static void
7623 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7624 {
7625         struct intel_encoder *intel_encoder;
7626         struct intel_crtc *intel_crtc;
7627         struct drm_connector *connector;
7628
7629         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7630                             base.head) {
7631                 if (!intel_encoder->base.crtc)
7632                         continue;
7633
7634                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7635
7636                 if (prepare_pipes & (1 << intel_crtc->pipe))
7637                         intel_encoder->connectors_active = false;
7638         }
7639
7640         intel_modeset_commit_output_state(dev);
7641
7642         /* Update computed state. */
7643         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7644                             base.head) {
7645                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7646         }
7647
7648         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7649                 if (!connector->encoder || !connector->encoder->crtc)
7650                         continue;
7651
7652                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7653
7654                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7655                         struct drm_property *dpms_property =
7656                                 dev->mode_config.dpms_property;
7657
7658                         connector->dpms = DRM_MODE_DPMS_ON;
7659                         drm_object_property_set_value(&connector->base,
7660                                                          dpms_property,
7661                                                          DRM_MODE_DPMS_ON);
7662
7663                         intel_encoder = to_intel_encoder(connector->encoder);
7664                         intel_encoder->connectors_active = true;
7665                 }
7666         }
7667
7668 }
7669
7670 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7671         list_for_each_entry((intel_crtc), \
7672                             &(dev)->mode_config.crtc_list, \
7673                             base.head) \
7674                 if (mask & (1 <<(intel_crtc)->pipe)) \
7675
7676 void
7677 intel_modeset_check_state(struct drm_device *dev)
7678 {
7679         struct intel_crtc *crtc;
7680         struct intel_encoder *encoder;
7681         struct intel_connector *connector;
7682
7683         list_for_each_entry(connector, &dev->mode_config.connector_list,
7684                             base.head) {
7685                 /* This also checks the encoder/connector hw state with the
7686                  * ->get_hw_state callbacks. */
7687                 intel_connector_check_state(connector);
7688
7689                 WARN(&connector->new_encoder->base != connector->base.encoder,
7690                      "connector's staged encoder doesn't match current encoder\n");
7691         }
7692
7693         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7694                             base.head) {
7695                 bool enabled = false;
7696                 bool active = false;
7697                 enum pipe pipe, tracked_pipe;
7698
7699                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7700                               encoder->base.base.id,
7701                               drm_get_encoder_name(&encoder->base));
7702
7703                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7704                      "encoder's stage crtc doesn't match current crtc\n");
7705                 WARN(encoder->connectors_active && !encoder->base.crtc,
7706                      "encoder's active_connectors set, but no crtc\n");
7707
7708                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7709                                     base.head) {
7710                         if (connector->base.encoder != &encoder->base)
7711                                 continue;
7712                         enabled = true;
7713                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7714                                 active = true;
7715                 }
7716                 WARN(!!encoder->base.crtc != enabled,
7717                      "encoder's enabled state mismatch "
7718                      "(expected %i, found %i)\n",
7719                      !!encoder->base.crtc, enabled);
7720                 WARN(active && !encoder->base.crtc,
7721                      "active encoder with no crtc\n");
7722
7723                 WARN(encoder->connectors_active != active,
7724                      "encoder's computed active state doesn't match tracked active state "
7725                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7726
7727                 active = encoder->get_hw_state(encoder, &pipe);
7728                 WARN(active != encoder->connectors_active,
7729                      "encoder's hw state doesn't match sw tracking "
7730                      "(expected %i, found %i)\n",
7731                      encoder->connectors_active, active);
7732
7733                 if (!encoder->base.crtc)
7734                         continue;
7735
7736                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7737                 WARN(active && pipe != tracked_pipe,
7738                      "active encoder's pipe doesn't match"
7739                      "(expected %i, found %i)\n",
7740                      tracked_pipe, pipe);
7741
7742         }
7743
7744         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7745                             base.head) {
7746                 bool enabled = false;
7747                 bool active = false;
7748
7749                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7750                               crtc->base.base.id);
7751
7752                 WARN(crtc->active && !crtc->base.enabled,
7753                      "active crtc, but not enabled in sw tracking\n");
7754
7755                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7756                                     base.head) {
7757                         if (encoder->base.crtc != &crtc->base)
7758                                 continue;
7759                         enabled = true;
7760                         if (encoder->connectors_active)
7761                                 active = true;
7762                 }
7763                 WARN(active != crtc->active,
7764                      "crtc's computed active state doesn't match tracked active state "
7765                      "(expected %i, found %i)\n", active, crtc->active);
7766                 WARN(enabled != crtc->base.enabled,
7767                      "crtc's computed enabled state doesn't match tracked enabled state "
7768                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7769
7770                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7771         }
7772 }
7773
7774 int intel_set_mode(struct drm_crtc *crtc,
7775                    struct drm_display_mode *mode,
7776                    int x, int y, struct drm_framebuffer *fb)
7777 {
7778         struct drm_device *dev = crtc->dev;
7779         drm_i915_private_t *dev_priv = dev->dev_private;
7780         struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7781         struct intel_crtc *intel_crtc;
7782         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7783         int ret = 0;
7784
7785         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7786         if (!saved_mode)
7787                 return -ENOMEM;
7788         saved_hwmode = saved_mode + 1;
7789
7790         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7791                                      &prepare_pipes, &disable_pipes);
7792
7793         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7794                       modeset_pipes, prepare_pipes, disable_pipes);
7795
7796         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7797                 intel_crtc_disable(&intel_crtc->base);
7798
7799         *saved_hwmode = crtc->hwmode;
7800         *saved_mode = crtc->mode;
7801
7802         /* Hack: Because we don't (yet) support global modeset on multiple
7803          * crtcs, we don't keep track of the new mode for more than one crtc.
7804          * Hence simply check whether any bit is set in modeset_pipes in all the
7805          * pieces of code that are not yet converted to deal with mutliple crtcs
7806          * changing their mode at the same time. */
7807         adjusted_mode = NULL;
7808         if (modeset_pipes) {
7809                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7810                 if (IS_ERR(adjusted_mode)) {
7811                         ret = PTR_ERR(adjusted_mode);
7812                         goto out;
7813                 }
7814         }
7815
7816         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7817                 if (intel_crtc->base.enabled)
7818                         dev_priv->display.crtc_disable(&intel_crtc->base);
7819         }
7820
7821         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7822          * to set it here already despite that we pass it down the callchain.
7823          */
7824         if (modeset_pipes)
7825                 crtc->mode = *mode;
7826
7827         /* Only after disabling all output pipelines that will be changed can we
7828          * update the the output configuration. */
7829         intel_modeset_update_state(dev, prepare_pipes);
7830
7831         if (dev_priv->display.modeset_global_resources)
7832                 dev_priv->display.modeset_global_resources(dev);
7833
7834         /* Set up the DPLL and any encoders state that needs to adjust or depend
7835          * on the DPLL.
7836          */
7837         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7838                 ret = intel_crtc_mode_set(&intel_crtc->base,
7839                                           mode, adjusted_mode,
7840                                           x, y, fb);
7841                 if (ret)
7842                         goto done;
7843         }
7844
7845         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7846         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7847                 dev_priv->display.crtc_enable(&intel_crtc->base);
7848
7849         if (modeset_pipes) {
7850                 /* Store real post-adjustment hardware mode. */
7851                 crtc->hwmode = *adjusted_mode;
7852
7853                 /* Calculate and store various constants which
7854                  * are later needed by vblank and swap-completion
7855                  * timestamping. They are derived from true hwmode.
7856                  */
7857                 drm_calc_timestamping_constants(crtc);
7858         }
7859
7860         /* FIXME: add subpixel order */
7861 done:
7862         drm_mode_destroy(dev, adjusted_mode);
7863         if (ret && crtc->enabled) {
7864                 crtc->hwmode = *saved_hwmode;
7865                 crtc->mode = *saved_mode;
7866         } else {
7867                 intel_modeset_check_state(dev);
7868         }
7869
7870 out:
7871         kfree(saved_mode);
7872         return ret;
7873 }
7874
7875 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7876 {
7877         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7878 }
7879
7880 #undef for_each_intel_crtc_masked
7881
7882 static void intel_set_config_free(struct intel_set_config *config)
7883 {
7884         if (!config)
7885                 return;
7886
7887         kfree(config->save_connector_encoders);
7888         kfree(config->save_encoder_crtcs);
7889         kfree(config);
7890 }
7891
7892 static int intel_set_config_save_state(struct drm_device *dev,
7893                                        struct intel_set_config *config)
7894 {
7895         struct drm_encoder *encoder;
7896         struct drm_connector *connector;
7897         int count;
7898
7899         config->save_encoder_crtcs =
7900                 kcalloc(dev->mode_config.num_encoder,
7901                         sizeof(struct drm_crtc *), GFP_KERNEL);
7902         if (!config->save_encoder_crtcs)
7903                 return -ENOMEM;
7904
7905         config->save_connector_encoders =
7906                 kcalloc(dev->mode_config.num_connector,
7907                         sizeof(struct drm_encoder *), GFP_KERNEL);
7908         if (!config->save_connector_encoders)
7909                 return -ENOMEM;
7910
7911         /* Copy data. Note that driver private data is not affected.
7912          * Should anything bad happen only the expected state is
7913          * restored, not the drivers personal bookkeeping.
7914          */
7915         count = 0;
7916         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7917                 config->save_encoder_crtcs[count++] = encoder->crtc;
7918         }
7919
7920         count = 0;
7921         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7922                 config->save_connector_encoders[count++] = connector->encoder;
7923         }
7924
7925         return 0;
7926 }
7927
7928 static void intel_set_config_restore_state(struct drm_device *dev,
7929                                            struct intel_set_config *config)
7930 {
7931         struct intel_encoder *encoder;
7932         struct intel_connector *connector;
7933         int count;
7934
7935         count = 0;
7936         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7937                 encoder->new_crtc =
7938                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7939         }
7940
7941         count = 0;
7942         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7943                 connector->new_encoder =
7944                         to_intel_encoder(config->save_connector_encoders[count++]);
7945         }
7946 }
7947
7948 static void
7949 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7950                                       struct intel_set_config *config)
7951 {
7952
7953         /* We should be able to check here if the fb has the same properties
7954          * and then just flip_or_move it */
7955         if (set->crtc->fb != set->fb) {
7956                 /* If we have no fb then treat it as a full mode set */
7957                 if (set->crtc->fb == NULL) {
7958                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7959                         config->mode_changed = true;
7960                 } else if (set->fb == NULL) {
7961                         config->mode_changed = true;
7962                 } else if (set->fb->depth != set->crtc->fb->depth) {
7963                         config->mode_changed = true;
7964                 } else if (set->fb->bits_per_pixel !=
7965                            set->crtc->fb->bits_per_pixel) {
7966                         config->mode_changed = true;
7967                 } else
7968                         config->fb_changed = true;
7969         }
7970
7971         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7972                 config->fb_changed = true;
7973
7974         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7975                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7976                 drm_mode_debug_printmodeline(&set->crtc->mode);
7977                 drm_mode_debug_printmodeline(set->mode);
7978                 config->mode_changed = true;
7979         }
7980 }
7981
7982 static int
7983 intel_modeset_stage_output_state(struct drm_device *dev,
7984                                  struct drm_mode_set *set,
7985                                  struct intel_set_config *config)
7986 {
7987         struct drm_crtc *new_crtc;
7988         struct intel_connector *connector;
7989         struct intel_encoder *encoder;
7990         int count, ro;
7991
7992         /* The upper layers ensure that we either disable a crtc or have a list
7993          * of connectors. For paranoia, double-check this. */
7994         WARN_ON(!set->fb && (set->num_connectors != 0));
7995         WARN_ON(set->fb && (set->num_connectors == 0));
7996
7997         count = 0;
7998         list_for_each_entry(connector, &dev->mode_config.connector_list,
7999                             base.head) {
8000                 /* Otherwise traverse passed in connector list and get encoders
8001                  * for them. */
8002                 for (ro = 0; ro < set->num_connectors; ro++) {
8003                         if (set->connectors[ro] == &connector->base) {
8004                                 connector->new_encoder = connector->encoder;
8005                                 break;
8006                         }
8007                 }
8008
8009                 /* If we disable the crtc, disable all its connectors. Also, if
8010                  * the connector is on the changing crtc but not on the new
8011                  * connector list, disable it. */
8012                 if ((!set->fb || ro == set->num_connectors) &&
8013                     connector->base.encoder &&
8014                     connector->base.encoder->crtc == set->crtc) {
8015                         connector->new_encoder = NULL;
8016
8017                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8018                                 connector->base.base.id,
8019                                 drm_get_connector_name(&connector->base));
8020                 }
8021
8022
8023                 if (&connector->new_encoder->base != connector->base.encoder) {
8024                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8025                         config->mode_changed = true;
8026                 }
8027         }
8028         /* connector->new_encoder is now updated for all connectors. */
8029
8030         /* Update crtc of enabled connectors. */
8031         count = 0;
8032         list_for_each_entry(connector, &dev->mode_config.connector_list,
8033                             base.head) {
8034                 if (!connector->new_encoder)
8035                         continue;
8036
8037                 new_crtc = connector->new_encoder->base.crtc;
8038
8039                 for (ro = 0; ro < set->num_connectors; ro++) {
8040                         if (set->connectors[ro] == &connector->base)
8041                                 new_crtc = set->crtc;
8042                 }
8043
8044                 /* Make sure the new CRTC will work with the encoder */
8045                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8046                                            new_crtc)) {
8047                         return -EINVAL;
8048                 }
8049                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8050
8051                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8052                         connector->base.base.id,
8053                         drm_get_connector_name(&connector->base),
8054                         new_crtc->base.id);
8055         }
8056
8057         /* Check for any encoders that needs to be disabled. */
8058         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8059                             base.head) {
8060                 list_for_each_entry(connector,
8061                                     &dev->mode_config.connector_list,
8062                                     base.head) {
8063                         if (connector->new_encoder == encoder) {
8064                                 WARN_ON(!connector->new_encoder->new_crtc);
8065
8066                                 goto next_encoder;
8067                         }
8068                 }
8069                 encoder->new_crtc = NULL;
8070 next_encoder:
8071                 /* Only now check for crtc changes so we don't miss encoders
8072                  * that will be disabled. */
8073                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8074                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8075                         config->mode_changed = true;
8076                 }
8077         }
8078         /* Now we've also updated encoder->new_crtc for all encoders. */
8079
8080         return 0;
8081 }
8082
8083 static int intel_crtc_set_config(struct drm_mode_set *set)
8084 {
8085         struct drm_device *dev;
8086         struct drm_mode_set save_set;
8087         struct intel_set_config *config;
8088         int ret;
8089
8090         BUG_ON(!set);
8091         BUG_ON(!set->crtc);
8092         BUG_ON(!set->crtc->helper_private);
8093
8094         /* Enforce sane interface api - has been abused by the fb helper. */
8095         BUG_ON(!set->mode && set->fb);
8096         BUG_ON(set->fb && set->num_connectors == 0);
8097
8098         if (set->fb) {
8099                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8100                                 set->crtc->base.id, set->fb->base.id,
8101                                 (int)set->num_connectors, set->x, set->y);
8102         } else {
8103                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8104         }
8105
8106         dev = set->crtc->dev;
8107
8108         ret = -ENOMEM;
8109         config = kzalloc(sizeof(*config), GFP_KERNEL);
8110         if (!config)
8111                 goto out_config;
8112
8113         ret = intel_set_config_save_state(dev, config);
8114         if (ret)
8115                 goto out_config;
8116
8117         save_set.crtc = set->crtc;
8118         save_set.mode = &set->crtc->mode;
8119         save_set.x = set->crtc->x;
8120         save_set.y = set->crtc->y;
8121         save_set.fb = set->crtc->fb;
8122
8123         /* Compute whether we need a full modeset, only an fb base update or no
8124          * change at all. In the future we might also check whether only the
8125          * mode changed, e.g. for LVDS where we only change the panel fitter in
8126          * such cases. */
8127         intel_set_config_compute_mode_changes(set, config);
8128
8129         ret = intel_modeset_stage_output_state(dev, set, config);
8130         if (ret)
8131                 goto fail;
8132
8133         if (config->mode_changed) {
8134                 if (set->mode) {
8135                         DRM_DEBUG_KMS("attempting to set mode from"
8136                                         " userspace\n");
8137                         drm_mode_debug_printmodeline(set->mode);
8138                 }
8139
8140                 ret = intel_set_mode(set->crtc, set->mode,
8141                                      set->x, set->y, set->fb);
8142                 if (ret) {
8143                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8144                                   set->crtc->base.id, ret);
8145                         goto fail;
8146                 }
8147         } else if (config->fb_changed) {
8148                 ret = intel_pipe_set_base(set->crtc,
8149                                           set->x, set->y, set->fb);
8150         }
8151
8152         intel_set_config_free(config);
8153
8154         return 0;
8155
8156 fail:
8157         intel_set_config_restore_state(dev, config);
8158
8159         /* Try to restore the config */
8160         if (config->mode_changed &&
8161             intel_set_mode(save_set.crtc, save_set.mode,
8162                            save_set.x, save_set.y, save_set.fb))
8163                 DRM_ERROR("failed to restore config after modeset failure\n");
8164
8165 out_config:
8166         intel_set_config_free(config);
8167         return ret;
8168 }
8169
8170 static const struct drm_crtc_funcs intel_crtc_funcs = {
8171         .cursor_set = intel_crtc_cursor_set,
8172         .cursor_move = intel_crtc_cursor_move,
8173         .gamma_set = intel_crtc_gamma_set,
8174         .set_config = intel_crtc_set_config,
8175         .destroy = intel_crtc_destroy,
8176         .page_flip = intel_crtc_page_flip,
8177 };
8178
8179 static void intel_cpu_pll_init(struct drm_device *dev)
8180 {
8181         if (HAS_DDI(dev))
8182                 intel_ddi_pll_init(dev);
8183 }
8184
8185 static void intel_pch_pll_init(struct drm_device *dev)
8186 {
8187         drm_i915_private_t *dev_priv = dev->dev_private;
8188         int i;
8189
8190         if (dev_priv->num_pch_pll == 0) {
8191                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8192                 return;
8193         }
8194
8195         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8196                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8197                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8198                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8199         }
8200 }
8201
8202 static void intel_crtc_init(struct drm_device *dev, int pipe)
8203 {
8204         drm_i915_private_t *dev_priv = dev->dev_private;
8205         struct intel_crtc *intel_crtc;
8206         int i;
8207
8208         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8209         if (intel_crtc == NULL)
8210                 return;
8211
8212         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8213
8214         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8215         for (i = 0; i < 256; i++) {
8216                 intel_crtc->lut_r[i] = i;
8217                 intel_crtc->lut_g[i] = i;
8218                 intel_crtc->lut_b[i] = i;
8219         }
8220
8221         /* Swap pipes & planes for FBC on pre-965 */
8222         intel_crtc->pipe = pipe;
8223         intel_crtc->plane = pipe;
8224         intel_crtc->cpu_transcoder = pipe;
8225         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8226                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8227                 intel_crtc->plane = !pipe;
8228         }
8229
8230         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8231                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8232         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8233         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8234
8235         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8236
8237         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8238 }
8239
8240 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8241                                 struct drm_file *file)
8242 {
8243         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8244         struct drm_mode_object *drmmode_obj;
8245         struct intel_crtc *crtc;
8246
8247         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8248                 return -ENODEV;
8249
8250         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8251                         DRM_MODE_OBJECT_CRTC);
8252
8253         if (!drmmode_obj) {
8254                 DRM_ERROR("no such CRTC id\n");
8255                 return -EINVAL;
8256         }
8257
8258         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8259         pipe_from_crtc_id->pipe = crtc->pipe;
8260
8261         return 0;
8262 }
8263
8264 static int intel_encoder_clones(struct intel_encoder *encoder)
8265 {
8266         struct drm_device *dev = encoder->base.dev;
8267         struct intel_encoder *source_encoder;
8268         int index_mask = 0;
8269         int entry = 0;
8270
8271         list_for_each_entry(source_encoder,
8272                             &dev->mode_config.encoder_list, base.head) {
8273
8274                 if (encoder == source_encoder)
8275                         index_mask |= (1 << entry);
8276
8277                 /* Intel hw has only one MUX where enocoders could be cloned. */
8278                 if (encoder->cloneable && source_encoder->cloneable)
8279                         index_mask |= (1 << entry);
8280
8281                 entry++;
8282         }
8283
8284         return index_mask;
8285 }
8286
8287 static bool has_edp_a(struct drm_device *dev)
8288 {
8289         struct drm_i915_private *dev_priv = dev->dev_private;
8290
8291         if (!IS_MOBILE(dev))
8292                 return false;
8293
8294         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8295                 return false;
8296
8297         if (IS_GEN5(dev) &&
8298             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8299                 return false;
8300
8301         return true;
8302 }
8303
8304 static void intel_setup_outputs(struct drm_device *dev)
8305 {
8306         struct drm_i915_private *dev_priv = dev->dev_private;
8307         struct intel_encoder *encoder;
8308         bool dpd_is_edp = false;
8309         bool has_lvds;
8310
8311         has_lvds = intel_lvds_init(dev);
8312         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8313                 /* disable the panel fitter on everything but LVDS */
8314                 I915_WRITE(PFIT_CONTROL, 0);
8315         }
8316
8317         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8318                 intel_crt_init(dev);
8319
8320         if (HAS_DDI(dev)) {
8321                 int found;
8322
8323                 /* Haswell uses DDI functions to detect digital outputs */
8324                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8325                 /* DDI A only supports eDP */
8326                 if (found)
8327                         intel_ddi_init(dev, PORT_A);
8328
8329                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8330                  * register */
8331                 found = I915_READ(SFUSE_STRAP);
8332
8333                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8334                         intel_ddi_init(dev, PORT_B);
8335                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8336                         intel_ddi_init(dev, PORT_C);
8337                 if (found & SFUSE_STRAP_DDID_DETECTED)
8338                         intel_ddi_init(dev, PORT_D);
8339         } else if (HAS_PCH_SPLIT(dev)) {
8340                 int found;
8341                 dpd_is_edp = intel_dpd_is_edp(dev);
8342
8343                 if (has_edp_a(dev))
8344                         intel_dp_init(dev, DP_A, PORT_A);
8345
8346                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8347                         /* PCH SDVOB multiplex with HDMIB */
8348                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8349                         if (!found)
8350                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8351                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8352                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8353                 }
8354
8355                 if (I915_READ(HDMIC) & PORT_DETECTED)
8356                         intel_hdmi_init(dev, HDMIC, PORT_C);
8357
8358                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8359                         intel_hdmi_init(dev, HDMID, PORT_D);
8360
8361                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8362                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8363
8364                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8365                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8366         } else if (IS_VALLEYVIEW(dev)) {
8367                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8368                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8369                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8370
8371                 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8372                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8373                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8374                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8375                 }
8376
8377                 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8378                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8379
8380         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8381                 bool found = false;
8382
8383                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8384                         DRM_DEBUG_KMS("probing SDVOB\n");
8385                         found = intel_sdvo_init(dev, SDVOB, true);
8386                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8387                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8388                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8389                         }
8390
8391                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8392                                 DRM_DEBUG_KMS("probing DP_B\n");
8393                                 intel_dp_init(dev, DP_B, PORT_B);
8394                         }
8395                 }
8396
8397                 /* Before G4X SDVOC doesn't have its own detect register */
8398
8399                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8400                         DRM_DEBUG_KMS("probing SDVOC\n");
8401                         found = intel_sdvo_init(dev, SDVOC, false);
8402                 }
8403
8404                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8405
8406                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8407                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8408                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8409                         }
8410                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8411                                 DRM_DEBUG_KMS("probing DP_C\n");
8412                                 intel_dp_init(dev, DP_C, PORT_C);
8413                         }
8414                 }
8415
8416                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8417                     (I915_READ(DP_D) & DP_DETECTED)) {
8418                         DRM_DEBUG_KMS("probing DP_D\n");
8419                         intel_dp_init(dev, DP_D, PORT_D);
8420                 }
8421         } else if (IS_GEN2(dev))
8422                 intel_dvo_init(dev);
8423
8424         if (SUPPORTS_TV(dev))
8425                 intel_tv_init(dev);
8426
8427         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8428                 encoder->base.possible_crtcs = encoder->crtc_mask;
8429                 encoder->base.possible_clones =
8430                         intel_encoder_clones(encoder);
8431         }
8432
8433         intel_init_pch_refclk(dev);
8434
8435         drm_helper_move_panel_connectors_to_head(dev);
8436 }
8437
8438 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8439 {
8440         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8441
8442         drm_framebuffer_cleanup(fb);
8443         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8444
8445         kfree(intel_fb);
8446 }
8447
8448 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8449                                                 struct drm_file *file,
8450                                                 unsigned int *handle)
8451 {
8452         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8453         struct drm_i915_gem_object *obj = intel_fb->obj;
8454
8455         return drm_gem_handle_create(file, &obj->base, handle);
8456 }
8457
8458 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8459         .destroy = intel_user_framebuffer_destroy,
8460         .create_handle = intel_user_framebuffer_create_handle,
8461 };
8462
8463 int intel_framebuffer_init(struct drm_device *dev,
8464                            struct intel_framebuffer *intel_fb,
8465                            struct drm_mode_fb_cmd2 *mode_cmd,
8466                            struct drm_i915_gem_object *obj)
8467 {
8468         int ret;
8469
8470         if (obj->tiling_mode == I915_TILING_Y) {
8471                 DRM_DEBUG("hardware does not support tiling Y\n");
8472                 return -EINVAL;
8473         }
8474
8475         if (mode_cmd->pitches[0] & 63) {
8476                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8477                           mode_cmd->pitches[0]);
8478                 return -EINVAL;
8479         }
8480
8481         /* FIXME <= Gen4 stride limits are bit unclear */
8482         if (mode_cmd->pitches[0] > 32768) {
8483                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8484                           mode_cmd->pitches[0]);
8485                 return -EINVAL;
8486         }
8487
8488         if (obj->tiling_mode != I915_TILING_NONE &&
8489             mode_cmd->pitches[0] != obj->stride) {
8490                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8491                           mode_cmd->pitches[0], obj->stride);
8492                 return -EINVAL;
8493         }
8494
8495         /* Reject formats not supported by any plane early. */
8496         switch (mode_cmd->pixel_format) {
8497         case DRM_FORMAT_C8:
8498         case DRM_FORMAT_RGB565:
8499         case DRM_FORMAT_XRGB8888:
8500         case DRM_FORMAT_ARGB8888:
8501                 break;
8502         case DRM_FORMAT_XRGB1555:
8503         case DRM_FORMAT_ARGB1555:
8504                 if (INTEL_INFO(dev)->gen > 3) {
8505                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8506                         return -EINVAL;
8507                 }
8508                 break;
8509         case DRM_FORMAT_XBGR8888:
8510         case DRM_FORMAT_ABGR8888:
8511         case DRM_FORMAT_XRGB2101010:
8512         case DRM_FORMAT_ARGB2101010:
8513         case DRM_FORMAT_XBGR2101010:
8514         case DRM_FORMAT_ABGR2101010:
8515                 if (INTEL_INFO(dev)->gen < 4) {
8516                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8517                         return -EINVAL;
8518                 }
8519                 break;
8520         case DRM_FORMAT_YUYV:
8521         case DRM_FORMAT_UYVY:
8522         case DRM_FORMAT_YVYU:
8523         case DRM_FORMAT_VYUY:
8524                 if (INTEL_INFO(dev)->gen < 5) {
8525                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8526                         return -EINVAL;
8527                 }
8528                 break;
8529         default:
8530                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8531                 return -EINVAL;
8532         }
8533
8534         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8535         if (mode_cmd->offsets[0] != 0)
8536                 return -EINVAL;
8537
8538         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8539         intel_fb->obj = obj;
8540
8541         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8542         if (ret) {
8543                 DRM_ERROR("framebuffer init failed %d\n", ret);
8544                 return ret;
8545         }
8546
8547         return 0;
8548 }
8549
8550 static struct drm_framebuffer *
8551 intel_user_framebuffer_create(struct drm_device *dev,
8552                               struct drm_file *filp,
8553                               struct drm_mode_fb_cmd2 *mode_cmd)
8554 {
8555         struct drm_i915_gem_object *obj;
8556
8557         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8558                                                 mode_cmd->handles[0]));
8559         if (&obj->base == NULL)
8560                 return ERR_PTR(-ENOENT);
8561
8562         return intel_framebuffer_create(dev, mode_cmd, obj);
8563 }
8564
8565 static const struct drm_mode_config_funcs intel_mode_funcs = {
8566         .fb_create = intel_user_framebuffer_create,
8567         .output_poll_changed = intel_fb_output_poll_changed,
8568 };
8569
8570 /* Set up chip specific display functions */
8571 static void intel_init_display(struct drm_device *dev)
8572 {
8573         struct drm_i915_private *dev_priv = dev->dev_private;
8574
8575         /* We always want a DPMS function */
8576         if (HAS_DDI(dev)) {
8577                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8578                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8579                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8580                 dev_priv->display.off = haswell_crtc_off;
8581                 dev_priv->display.update_plane = ironlake_update_plane;
8582         } else if (HAS_PCH_SPLIT(dev)) {
8583                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8584                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8585                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8586                 dev_priv->display.off = ironlake_crtc_off;
8587                 dev_priv->display.update_plane = ironlake_update_plane;
8588         } else {
8589                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8590                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8591                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8592                 dev_priv->display.off = i9xx_crtc_off;
8593                 dev_priv->display.update_plane = i9xx_update_plane;
8594         }
8595
8596         /* Returns the core display clock speed */
8597         if (IS_VALLEYVIEW(dev))
8598                 dev_priv->display.get_display_clock_speed =
8599                         valleyview_get_display_clock_speed;
8600         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8601                 dev_priv->display.get_display_clock_speed =
8602                         i945_get_display_clock_speed;
8603         else if (IS_I915G(dev))
8604                 dev_priv->display.get_display_clock_speed =
8605                         i915_get_display_clock_speed;
8606         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8607                 dev_priv->display.get_display_clock_speed =
8608                         i9xx_misc_get_display_clock_speed;
8609         else if (IS_I915GM(dev))
8610                 dev_priv->display.get_display_clock_speed =
8611                         i915gm_get_display_clock_speed;
8612         else if (IS_I865G(dev))
8613                 dev_priv->display.get_display_clock_speed =
8614                         i865_get_display_clock_speed;
8615         else if (IS_I85X(dev))
8616                 dev_priv->display.get_display_clock_speed =
8617                         i855_get_display_clock_speed;
8618         else /* 852, 830 */
8619                 dev_priv->display.get_display_clock_speed =
8620                         i830_get_display_clock_speed;
8621
8622         if (HAS_PCH_SPLIT(dev)) {
8623                 if (IS_GEN5(dev)) {
8624                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8625                         dev_priv->display.write_eld = ironlake_write_eld;
8626                 } else if (IS_GEN6(dev)) {
8627                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8628                         dev_priv->display.write_eld = ironlake_write_eld;
8629                 } else if (IS_IVYBRIDGE(dev)) {
8630                         /* FIXME: detect B0+ stepping and use auto training */
8631                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8632                         dev_priv->display.write_eld = ironlake_write_eld;
8633                         dev_priv->display.modeset_global_resources =
8634                                 ivb_modeset_global_resources;
8635                 } else if (IS_HASWELL(dev)) {
8636                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8637                         dev_priv->display.write_eld = haswell_write_eld;
8638                         dev_priv->display.modeset_global_resources =
8639                                 haswell_modeset_global_resources;
8640                 }
8641         } else if (IS_G4X(dev)) {
8642                 dev_priv->display.write_eld = g4x_write_eld;
8643         }
8644
8645         /* Default just returns -ENODEV to indicate unsupported */
8646         dev_priv->display.queue_flip = intel_default_queue_flip;
8647
8648         switch (INTEL_INFO(dev)->gen) {
8649         case 2:
8650                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8651                 break;
8652
8653         case 3:
8654                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8655                 break;
8656
8657         case 4:
8658         case 5:
8659                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8660                 break;
8661
8662         case 6:
8663                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8664                 break;
8665         case 7:
8666                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8667                 break;
8668         }
8669 }
8670
8671 /*
8672  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8673  * resume, or other times.  This quirk makes sure that's the case for
8674  * affected systems.
8675  */
8676 static void quirk_pipea_force(struct drm_device *dev)
8677 {
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679
8680         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8681         DRM_INFO("applying pipe a force quirk\n");
8682 }
8683
8684 /*
8685  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8686  */
8687 static void quirk_ssc_force_disable(struct drm_device *dev)
8688 {
8689         struct drm_i915_private *dev_priv = dev->dev_private;
8690         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8691         DRM_INFO("applying lvds SSC disable quirk\n");
8692 }
8693
8694 /*
8695  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8696  * brightness value
8697  */
8698 static void quirk_invert_brightness(struct drm_device *dev)
8699 {
8700         struct drm_i915_private *dev_priv = dev->dev_private;
8701         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8702         DRM_INFO("applying inverted panel brightness quirk\n");
8703 }
8704
8705 struct intel_quirk {
8706         int device;
8707         int subsystem_vendor;
8708         int subsystem_device;
8709         void (*hook)(struct drm_device *dev);
8710 };
8711
8712 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8713 struct intel_dmi_quirk {
8714         void (*hook)(struct drm_device *dev);
8715         const struct dmi_system_id (*dmi_id_list)[];
8716 };
8717
8718 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8719 {
8720         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8721         return 1;
8722 }
8723
8724 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8725         {
8726                 .dmi_id_list = &(const struct dmi_system_id[]) {
8727                         {
8728                                 .callback = intel_dmi_reverse_brightness,
8729                                 .ident = "NCR Corporation",
8730                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8731                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8732                                 },
8733                         },
8734                         { }  /* terminating entry */
8735                 },
8736                 .hook = quirk_invert_brightness,
8737         },
8738 };
8739
8740 static struct intel_quirk intel_quirks[] = {
8741         /* HP Mini needs pipe A force quirk (LP: #322104) */
8742         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8743
8744         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8745         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8746
8747         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8748         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8749
8750         /* 830/845 need to leave pipe A & dpll A up */
8751         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8752         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8753
8754         /* Lenovo U160 cannot use SSC on LVDS */
8755         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8756
8757         /* Sony Vaio Y cannot use SSC on LVDS */
8758         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8759
8760         /* Acer Aspire 5734Z must invert backlight brightness */
8761         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8762
8763         /* Acer/eMachines G725 */
8764         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8765
8766         /* Acer/eMachines e725 */
8767         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8768
8769         /* Acer/Packard Bell NCL20 */
8770         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8771
8772         /* Acer Aspire 4736Z */
8773         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8774 };
8775
8776 static void intel_init_quirks(struct drm_device *dev)
8777 {
8778         struct pci_dev *d = dev->pdev;
8779         int i;
8780
8781         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8782                 struct intel_quirk *q = &intel_quirks[i];
8783
8784                 if (d->device == q->device &&
8785                     (d->subsystem_vendor == q->subsystem_vendor ||
8786                      q->subsystem_vendor == PCI_ANY_ID) &&
8787                     (d->subsystem_device == q->subsystem_device ||
8788                      q->subsystem_device == PCI_ANY_ID))
8789                         q->hook(dev);
8790         }
8791         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8792                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8793                         intel_dmi_quirks[i].hook(dev);
8794         }
8795 }
8796
8797 /* Disable the VGA plane that we never use */
8798 static void i915_disable_vga(struct drm_device *dev)
8799 {
8800         struct drm_i915_private *dev_priv = dev->dev_private;
8801         u8 sr1;
8802         u32 vga_reg = i915_vgacntrl_reg(dev);
8803
8804         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8805         outb(SR01, VGA_SR_INDEX);
8806         sr1 = inb(VGA_SR_DATA);
8807         outb(sr1 | 1<<5, VGA_SR_DATA);
8808         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8809         udelay(300);
8810
8811         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8812         POSTING_READ(vga_reg);
8813 }
8814
8815 void intel_modeset_init_hw(struct drm_device *dev)
8816 {
8817         intel_init_power_well(dev);
8818
8819         intel_prepare_ddi(dev);
8820
8821         intel_init_clock_gating(dev);
8822
8823         mutex_lock(&dev->struct_mutex);
8824         intel_enable_gt_powersave(dev);
8825         mutex_unlock(&dev->struct_mutex);
8826 }
8827
8828 void intel_modeset_init(struct drm_device *dev)
8829 {
8830         struct drm_i915_private *dev_priv = dev->dev_private;
8831         int i, ret;
8832
8833         drm_mode_config_init(dev);
8834
8835         dev->mode_config.min_width = 0;
8836         dev->mode_config.min_height = 0;
8837
8838         dev->mode_config.preferred_depth = 24;
8839         dev->mode_config.prefer_shadow = 1;
8840
8841         dev->mode_config.funcs = &intel_mode_funcs;
8842
8843         intel_init_quirks(dev);
8844
8845         intel_init_pm(dev);
8846
8847         intel_init_display(dev);
8848
8849         if (IS_GEN2(dev)) {
8850                 dev->mode_config.max_width = 2048;
8851                 dev->mode_config.max_height = 2048;
8852         } else if (IS_GEN3(dev)) {
8853                 dev->mode_config.max_width = 4096;
8854                 dev->mode_config.max_height = 4096;
8855         } else {
8856                 dev->mode_config.max_width = 8192;
8857                 dev->mode_config.max_height = 8192;
8858         }
8859         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8860
8861         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8862                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8863
8864         for (i = 0; i < dev_priv->num_pipe; i++) {
8865                 intel_crtc_init(dev, i);
8866                 ret = intel_plane_init(dev, i);
8867                 if (ret)
8868                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8869         }
8870
8871         intel_cpu_pll_init(dev);
8872         intel_pch_pll_init(dev);
8873
8874         /* Just disable it once at startup */
8875         i915_disable_vga(dev);
8876         intel_setup_outputs(dev);
8877
8878         /* Just in case the BIOS is doing something questionable. */
8879         intel_disable_fbc(dev);
8880 }
8881
8882 static void
8883 intel_connector_break_all_links(struct intel_connector *connector)
8884 {
8885         connector->base.dpms = DRM_MODE_DPMS_OFF;
8886         connector->base.encoder = NULL;
8887         connector->encoder->connectors_active = false;
8888         connector->encoder->base.crtc = NULL;
8889 }
8890
8891 static void intel_enable_pipe_a(struct drm_device *dev)
8892 {
8893         struct intel_connector *connector;
8894         struct drm_connector *crt = NULL;
8895         struct intel_load_detect_pipe load_detect_temp;
8896
8897         /* We can't just switch on the pipe A, we need to set things up with a
8898          * proper mode and output configuration. As a gross hack, enable pipe A
8899          * by enabling the load detect pipe once. */
8900         list_for_each_entry(connector,
8901                             &dev->mode_config.connector_list,
8902                             base.head) {
8903                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8904                         crt = &connector->base;
8905                         break;
8906                 }
8907         }
8908
8909         if (!crt)
8910                 return;
8911
8912         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8913                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8914
8915
8916 }
8917
8918 static bool
8919 intel_check_plane_mapping(struct intel_crtc *crtc)
8920 {
8921         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8922         u32 reg, val;
8923
8924         if (dev_priv->num_pipe == 1)
8925                 return true;
8926
8927         reg = DSPCNTR(!crtc->plane);
8928         val = I915_READ(reg);
8929
8930         if ((val & DISPLAY_PLANE_ENABLE) &&
8931             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8932                 return false;
8933
8934         return true;
8935 }
8936
8937 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8938 {
8939         struct drm_device *dev = crtc->base.dev;
8940         struct drm_i915_private *dev_priv = dev->dev_private;
8941         u32 reg;
8942
8943         /* Clear any frame start delays used for debugging left by the BIOS */
8944         reg = PIPECONF(crtc->cpu_transcoder);
8945         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8946
8947         /* We need to sanitize the plane -> pipe mapping first because this will
8948          * disable the crtc (and hence change the state) if it is wrong. Note
8949          * that gen4+ has a fixed plane -> pipe mapping.  */
8950         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8951                 struct intel_connector *connector;
8952                 bool plane;
8953
8954                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8955                               crtc->base.base.id);
8956
8957                 /* Pipe has the wrong plane attached and the plane is active.
8958                  * Temporarily change the plane mapping and disable everything
8959                  * ...  */
8960                 plane = crtc->plane;
8961                 crtc->plane = !plane;
8962                 dev_priv->display.crtc_disable(&crtc->base);
8963                 crtc->plane = plane;
8964
8965                 /* ... and break all links. */
8966                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8967                                     base.head) {
8968                         if (connector->encoder->base.crtc != &crtc->base)
8969                                 continue;
8970
8971                         intel_connector_break_all_links(connector);
8972                 }
8973
8974                 WARN_ON(crtc->active);
8975                 crtc->base.enabled = false;
8976         }
8977
8978         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8979             crtc->pipe == PIPE_A && !crtc->active) {
8980                 /* BIOS forgot to enable pipe A, this mostly happens after
8981                  * resume. Force-enable the pipe to fix this, the update_dpms
8982                  * call below we restore the pipe to the right state, but leave
8983                  * the required bits on. */
8984                 intel_enable_pipe_a(dev);
8985         }
8986
8987         /* Adjust the state of the output pipe according to whether we
8988          * have active connectors/encoders. */
8989         intel_crtc_update_dpms(&crtc->base);
8990
8991         if (crtc->active != crtc->base.enabled) {
8992                 struct intel_encoder *encoder;
8993
8994                 /* This can happen either due to bugs in the get_hw_state
8995                  * functions or because the pipe is force-enabled due to the
8996                  * pipe A quirk. */
8997                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8998                               crtc->base.base.id,
8999                               crtc->base.enabled ? "enabled" : "disabled",
9000                               crtc->active ? "enabled" : "disabled");
9001
9002                 crtc->base.enabled = crtc->active;
9003
9004                 /* Because we only establish the connector -> encoder ->
9005                  * crtc links if something is active, this means the
9006                  * crtc is now deactivated. Break the links. connector
9007                  * -> encoder links are only establish when things are
9008                  *  actually up, hence no need to break them. */
9009                 WARN_ON(crtc->active);
9010
9011                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9012                         WARN_ON(encoder->connectors_active);
9013                         encoder->base.crtc = NULL;
9014                 }
9015         }
9016 }
9017
9018 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9019 {
9020         struct intel_connector *connector;
9021         struct drm_device *dev = encoder->base.dev;
9022
9023         /* We need to check both for a crtc link (meaning that the
9024          * encoder is active and trying to read from a pipe) and the
9025          * pipe itself being active. */
9026         bool has_active_crtc = encoder->base.crtc &&
9027                 to_intel_crtc(encoder->base.crtc)->active;
9028
9029         if (encoder->connectors_active && !has_active_crtc) {
9030                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9031                               encoder->base.base.id,
9032                               drm_get_encoder_name(&encoder->base));
9033
9034                 /* Connector is active, but has no active pipe. This is
9035                  * fallout from our resume register restoring. Disable
9036                  * the encoder manually again. */
9037                 if (encoder->base.crtc) {
9038                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9039                                       encoder->base.base.id,
9040                                       drm_get_encoder_name(&encoder->base));
9041                         encoder->disable(encoder);
9042                 }
9043
9044                 /* Inconsistent output/port/pipe state happens presumably due to
9045                  * a bug in one of the get_hw_state functions. Or someplace else
9046                  * in our code, like the register restore mess on resume. Clamp
9047                  * things to off as a safer default. */
9048                 list_for_each_entry(connector,
9049                                     &dev->mode_config.connector_list,
9050                                     base.head) {
9051                         if (connector->encoder != encoder)
9052                                 continue;
9053
9054                         intel_connector_break_all_links(connector);
9055                 }
9056         }
9057         /* Enabled encoders without active connectors will be fixed in
9058          * the crtc fixup. */
9059 }
9060
9061 void i915_redisable_vga(struct drm_device *dev)
9062 {
9063         struct drm_i915_private *dev_priv = dev->dev_private;
9064         u32 vga_reg = i915_vgacntrl_reg(dev);
9065
9066         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9067                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9068                 i915_disable_vga(dev);
9069         }
9070 }
9071
9072 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9073  * and i915 state tracking structures. */
9074 void intel_modeset_setup_hw_state(struct drm_device *dev,
9075                                   bool force_restore)
9076 {
9077         struct drm_i915_private *dev_priv = dev->dev_private;
9078         enum pipe pipe;
9079         u32 tmp;
9080         struct intel_crtc *crtc;
9081         struct intel_encoder *encoder;
9082         struct intel_connector *connector;
9083
9084         if (HAS_DDI(dev)) {
9085                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9086
9087                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9088                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9089                         case TRANS_DDI_EDP_INPUT_A_ON:
9090                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9091                                 pipe = PIPE_A;
9092                                 break;
9093                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9094                                 pipe = PIPE_B;
9095                                 break;
9096                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9097                                 pipe = PIPE_C;
9098                                 break;
9099                         }
9100
9101                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9102                         crtc->cpu_transcoder = TRANSCODER_EDP;
9103
9104                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9105                                       pipe_name(pipe));
9106                 }
9107         }
9108
9109         for_each_pipe(pipe) {
9110                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9111
9112                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9113                 if (tmp & PIPECONF_ENABLE)
9114                         crtc->active = true;
9115                 else
9116                         crtc->active = false;
9117
9118                 crtc->base.enabled = crtc->active;
9119
9120                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9121                               crtc->base.base.id,
9122                               crtc->active ? "enabled" : "disabled");
9123         }
9124
9125         if (HAS_DDI(dev))
9126                 intel_ddi_setup_hw_pll_state(dev);
9127
9128         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9129                             base.head) {
9130                 pipe = 0;
9131
9132                 if (encoder->get_hw_state(encoder, &pipe)) {
9133                         encoder->base.crtc =
9134                                 dev_priv->pipe_to_crtc_mapping[pipe];
9135                 } else {
9136                         encoder->base.crtc = NULL;
9137                 }
9138
9139                 encoder->connectors_active = false;
9140                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9141                               encoder->base.base.id,
9142                               drm_get_encoder_name(&encoder->base),
9143                               encoder->base.crtc ? "enabled" : "disabled",
9144                               pipe);
9145         }
9146
9147         list_for_each_entry(connector, &dev->mode_config.connector_list,
9148                             base.head) {
9149                 if (connector->get_hw_state(connector)) {
9150                         connector->base.dpms = DRM_MODE_DPMS_ON;
9151                         connector->encoder->connectors_active = true;
9152                         connector->base.encoder = &connector->encoder->base;
9153                 } else {
9154                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9155                         connector->base.encoder = NULL;
9156                 }
9157                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9158                               connector->base.base.id,
9159                               drm_get_connector_name(&connector->base),
9160                               connector->base.encoder ? "enabled" : "disabled");
9161         }
9162
9163         /* HW state is read out, now we need to sanitize this mess. */
9164         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9165                             base.head) {
9166                 intel_sanitize_encoder(encoder);
9167         }
9168
9169         for_each_pipe(pipe) {
9170                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9171                 intel_sanitize_crtc(crtc);
9172         }
9173
9174         if (force_restore) {
9175                 for_each_pipe(pipe) {
9176                         intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9177                 }
9178
9179                 i915_redisable_vga(dev);
9180         } else {
9181                 intel_modeset_update_staged_output_state(dev);
9182         }
9183
9184         intel_modeset_check_state(dev);
9185
9186         drm_mode_config_reset(dev);
9187 }
9188
9189 void intel_modeset_gem_init(struct drm_device *dev)
9190 {
9191         intel_modeset_init_hw(dev);
9192
9193         intel_setup_overlay(dev);
9194
9195         intel_modeset_setup_hw_state(dev, false);
9196 }
9197
9198 void intel_modeset_cleanup(struct drm_device *dev)
9199 {
9200         struct drm_i915_private *dev_priv = dev->dev_private;
9201         struct drm_crtc *crtc;
9202         struct intel_crtc *intel_crtc;
9203
9204         drm_kms_helper_poll_fini(dev);
9205         mutex_lock(&dev->struct_mutex);
9206
9207         intel_unregister_dsm_handler();
9208
9209
9210         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9211                 /* Skip inactive CRTCs */
9212                 if (!crtc->fb)
9213                         continue;
9214
9215                 intel_crtc = to_intel_crtc(crtc);
9216                 intel_increase_pllclock(crtc);
9217         }
9218
9219         intel_disable_fbc(dev);
9220
9221         intel_disable_gt_powersave(dev);
9222
9223         ironlake_teardown_rc6(dev);
9224
9225         if (IS_VALLEYVIEW(dev))
9226                 vlv_init_dpio(dev);
9227
9228         mutex_unlock(&dev->struct_mutex);
9229
9230         /* Disable the irq before mode object teardown, for the irq might
9231          * enqueue unpin/hotplug work. */
9232         drm_irq_uninstall(dev);
9233         cancel_work_sync(&dev_priv->hotplug_work);
9234         cancel_work_sync(&dev_priv->rps.work);
9235
9236         /* flush any delayed tasks or pending work */
9237         flush_scheduled_work();
9238
9239         drm_mode_config_cleanup(dev);
9240
9241         intel_cleanup_overlay(dev);
9242 }
9243
9244 /*
9245  * Return which encoder is currently attached for connector.
9246  */
9247 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9248 {
9249         return &intel_attached_encoder(connector)->base;
9250 }
9251
9252 void intel_connector_attach_encoder(struct intel_connector *connector,
9253                                     struct intel_encoder *encoder)
9254 {
9255         connector->encoder = encoder;
9256         drm_mode_connector_attach_encoder(&connector->base,
9257                                           &encoder->base);
9258 }
9259
9260 /*
9261  * set vga decode state - true == enable VGA decode
9262  */
9263 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9264 {
9265         struct drm_i915_private *dev_priv = dev->dev_private;
9266         u16 gmch_ctrl;
9267
9268         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9269         if (state)
9270                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9271         else
9272                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9273         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9274         return 0;
9275 }
9276
9277 #ifdef CONFIG_DEBUG_FS
9278 #include <linux/seq_file.h>
9279
9280 struct intel_display_error_state {
9281         struct intel_cursor_error_state {
9282                 u32 control;
9283                 u32 position;
9284                 u32 base;
9285                 u32 size;
9286         } cursor[I915_MAX_PIPES];
9287
9288         struct intel_pipe_error_state {
9289                 u32 conf;
9290                 u32 source;
9291
9292                 u32 htotal;
9293                 u32 hblank;
9294                 u32 hsync;
9295                 u32 vtotal;
9296                 u32 vblank;
9297                 u32 vsync;
9298         } pipe[I915_MAX_PIPES];
9299
9300         struct intel_plane_error_state {
9301                 u32 control;
9302                 u32 stride;
9303                 u32 size;
9304                 u32 pos;
9305                 u32 addr;
9306                 u32 surface;
9307                 u32 tile_offset;
9308         } plane[I915_MAX_PIPES];
9309 };
9310
9311 struct intel_display_error_state *
9312 intel_display_capture_error_state(struct drm_device *dev)
9313 {
9314         drm_i915_private_t *dev_priv = dev->dev_private;
9315         struct intel_display_error_state *error;
9316         enum transcoder cpu_transcoder;
9317         int i;
9318
9319         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9320         if (error == NULL)
9321                 return NULL;
9322
9323         for_each_pipe(i) {
9324                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9325
9326                 error->cursor[i].control = I915_READ(CURCNTR(i));
9327                 error->cursor[i].position = I915_READ(CURPOS(i));
9328                 error->cursor[i].base = I915_READ(CURBASE(i));
9329
9330                 error->plane[i].control = I915_READ(DSPCNTR(i));
9331                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9332                 error->plane[i].size = I915_READ(DSPSIZE(i));
9333                 error->plane[i].pos = I915_READ(DSPPOS(i));
9334                 error->plane[i].addr = I915_READ(DSPADDR(i));
9335                 if (INTEL_INFO(dev)->gen >= 4) {
9336                         error->plane[i].surface = I915_READ(DSPSURF(i));
9337                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9338                 }
9339
9340                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9341                 error->pipe[i].source = I915_READ(PIPESRC(i));
9342                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9343                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9344                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9345                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9346                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9347                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9348         }
9349
9350         return error;
9351 }
9352
9353 void
9354 intel_display_print_error_state(struct seq_file *m,
9355                                 struct drm_device *dev,
9356                                 struct intel_display_error_state *error)
9357 {
9358         drm_i915_private_t *dev_priv = dev->dev_private;
9359         int i;
9360
9361         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9362         for_each_pipe(i) {
9363                 seq_printf(m, "Pipe [%d]:\n", i);
9364                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9365                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9366                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9367                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9368                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9369                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9370                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9371                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9372
9373                 seq_printf(m, "Plane [%d]:\n", i);
9374                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9375                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9376                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9377                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9378                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9379                 if (INTEL_INFO(dev)->gen >= 4) {
9380                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9381                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9382                 }
9383
9384                 seq_printf(m, "Cursor [%d]:\n", i);
9385                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9386                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9387                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9388         }
9389 }
9390 #endif