drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <acpi/video.h>
  45 #include <asm/pat.h>
  46
  47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  48
  49 #define BEGIN_LP_RING(n) \
  50         intel_ring_begin(LP_RING(dev_priv), (n))
  51
  52 #define OUT_RING(x) \
  53         intel_ring_emit(LP_RING(dev_priv), x)
  54
  55 #define ADVANCE_LP_RING() \
  56         intel_ring_advance(LP_RING(dev_priv))
  57
  58 /**
  59  * Lock test for when it's just for synchronization of ring access.
  60  *
  61  * In that case, we don't need to do it when GEM is initialized as nobody else
  62  * has access to the ring.
  63  */
  64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  65         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  66                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  67 } while (0)
  68
  69 static inline u32
  70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  71 {
  72         if (I915_NEED_GFX_HWS(dev_priv->dev))
  73                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  74         else
  75                 return intel_read_status_page(LP_RING(dev_priv), reg);
  76 }
  77
  78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  80 #define I915_BREADCRUMB_INDEX           0x21
  81
  82 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  83 {
  84         drm_i915_private_t *dev_priv = dev->dev_private;
  85         struct drm_i915_master_private *master_priv;
  86
  87         /*
  88          * The dri breadcrumb update races against the drm master disappearing.
  89          * Instead of trying to fix this (this is by far not the only ums issue)
  90          * just don't do the update in kms mode.
  91          */
  92         if (drm_core_check_feature(dev, DRIVER_MODESET))
  93                 return;
  94
  95         if (dev->primary->master) {
  96                 master_priv = dev->primary->master->driver_priv;
  97                 if (master_priv->sarea_priv)
  98                         master_priv->sarea_priv->last_dispatch =
  99                                 READ_BREADCRUMB(dev_priv);
 100         }
 101 }
 102
 103 static void i915_write_hws_pga(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         u32 addr;
 107
 108         addr = dev_priv->status_page_dmah->busaddr;
 109         if (INTEL_INFO(dev)->gen >= 4)
 110                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 111         I915_WRITE(HWS_PGA, addr);
 112 }
 113
 114 /**
 115  * Frees the hardware status page, whether it's a physical address or a virtual
 116  * address set up by the X Server.
 117  */
 118 static void i915_free_hws(struct drm_device *dev)
 119 {
 120         drm_i915_private_t *dev_priv = dev->dev_private;
 121         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 122
 123         if (dev_priv->status_page_dmah) {
 124                 drm_pci_free(dev, dev_priv->status_page_dmah);
 125                 dev_priv->status_page_dmah = NULL;
 126         }
 127
 128         if (ring->status_page.gfx_addr) {
 129                 ring->status_page.gfx_addr = 0;
 130                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 131         }
 132
 133         /* Need to rewrite hardware status page */
 134         I915_WRITE(HWS_PGA, 0x1ffff000);
 135 }
 136
 137 void i915_kernel_lost_context(struct drm_device * dev)
 138 {
 139         drm_i915_private_t *dev_priv = dev->dev_private;
 140         struct drm_i915_master_private *master_priv;
 141         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 142
 143         /*
 144          * We should never lose context on the ring with modesetting
 145          * as we don't expose it to userspace
 146          */
 147         if (drm_core_check_feature(dev, DRIVER_MODESET))
 148                 return;
 149
 150         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 151         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 152         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 153         if (ring->space < 0)
 154                 ring->space += ring->size;
 155
 156         if (!dev->primary->master)
 157                 return;
 158
 159         master_priv = dev->primary->master->driver_priv;
 160         if (ring->head == ring->tail && master_priv->sarea_priv)
 161                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 162 }
 163
 164 static int i915_dma_cleanup(struct drm_device * dev)
 165 {
 166         drm_i915_private_t *dev_priv = dev->dev_private;
 167         int i;
 168
 169         /* Make sure interrupts are disabled here because the uninstall ioctl
 170          * may not have been called from userspace and after dev_private
 171          * is freed, it's too late.
 172          */
 173         if (dev->irq_enabled)
 174                 drm_irq_uninstall(dev);
 175
 176         mutex_lock(&dev->struct_mutex);
 177         for (i = 0; i < I915_NUM_RINGS; i++)
 178                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 179         mutex_unlock(&dev->struct_mutex);
 180
 181         /* Clear the HWS virtual address at teardown */
 182         if (I915_NEED_GFX_HWS(dev))
 183                 i915_free_hws(dev);
 184
 185         return 0;
 186 }
 187
 188 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 189 {
 190         drm_i915_private_t *dev_priv = dev->dev_private;
 191         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 192         int ret;
 193
 194         master_priv->sarea = drm_getsarea(dev);
 195         if (master_priv->sarea) {
 196                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 197                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 198         } else {
 199                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 200         }
 201
 202         if (init->ring_size != 0) {
 203                 if (LP_RING(dev_priv)->obj != NULL) {
 204                         i915_dma_cleanup(dev);
 205                         DRM_ERROR("Client tried to initialize ringbuffer in "
 206                                   "GEM mode\n");
 207                         return -EINVAL;
 208                 }
 209
 210                 ret = intel_render_ring_init_dri(dev,
 211                                                  init->ring_start,
 212                                                  init->ring_size);
 213                 if (ret) {
 214                         i915_dma_cleanup(dev);
 215                         return ret;
 216                 }
 217         }
 218
 219         dev_priv->dri1.cpp = init->cpp;
 220         dev_priv->dri1.back_offset = init->back_offset;
 221         dev_priv->dri1.front_offset = init->front_offset;
 222         dev_priv->dri1.current_page = 0;
 223         if (master_priv->sarea_priv)
 224                 master_priv->sarea_priv->pf_current_page = 0;
 225
 226         /* Allow hardware batchbuffers unless told otherwise.
 227          */
 228         dev_priv->dri1.allow_batchbuffer = 1;
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_resume(struct drm_device * dev)
 234 {
 235         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 236         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 237
 238         DRM_DEBUG_DRIVER("%s\n", __func__);
 239
 240         if (ring->virtual_start == NULL) {
 241                 DRM_ERROR("can not ioremap virtual address for"
 242                           " ring buffer\n");
 243                 return -ENOMEM;
 244         }
 245
 246         /* Program Hardware Status Page */
 247         if (!ring->status_page.page_addr) {
 248                 DRM_ERROR("Can not find hardware status page\n");
 249                 return -EINVAL;
 250         }
 251         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 252                                 ring->status_page.page_addr);
 253         if (ring->status_page.gfx_addr != 0)
 254                 intel_ring_setup_status_page(ring);
 255         else
 256                 i915_write_hws_pga(dev);
 257
 258         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 259
 260         return 0;
 261 }
 262
 263 static int i915_dma_init(struct drm_device *dev, void *data,
 264                          struct drm_file *file_priv)
 265 {
 266         drm_i915_init_t *init = data;
 267         int retcode = 0;
 268
 269         if (drm_core_check_feature(dev, DRIVER_MODESET))
 270                 return -ENODEV;
 271
 272         switch (init->func) {
 273         case I915_INIT_DMA:
 274                 retcode = i915_initialize(dev, init);
 275                 break;
 276         case I915_CLEANUP_DMA:
 277                 retcode = i915_dma_cleanup(dev);
 278                 break;
 279         case I915_RESUME_DMA:
 280                 retcode = i915_dma_resume(dev);
 281                 break;
 282         default:
 283                 retcode = -EINVAL;
 284                 break;
 285         }
 286
 287         return retcode;
 288 }
 289
 290 /* Implement basically the same security restrictions as hardware does
 291  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 292  *
 293  * Most of the calculations below involve calculating the size of a
 294  * particular instruction.  It's important to get the size right as
 295  * that tells us where the next instruction to check is.  Any illegal
 296  * instruction detected will be given a size of zero, which is a
 297  * signal to abort the rest of the buffer.
 298  */
 299 static int validate_cmd(int cmd)
 300 {
 301         switch (((cmd >> 29) & 0x7)) {
 302         case 0x0:
 303                 switch ((cmd >> 23) & 0x3f) {
 304                 case 0x0:
 305                         return 1;       /* MI_NOOP */
 306                 case 0x4:
 307                         return 1;       /* MI_FLUSH */
 308                 default:
 309                         return 0;       /* disallow everything else */
 310                 }
 311                 break;
 312         case 0x1:
 313                 return 0;       /* reserved */
 314         case 0x2:
 315                 return (cmd & 0xff) + 2;        /* 2d commands */
 316         case 0x3:
 317                 if (((cmd >> 24) & 0x1f) <= 0x18)
 318                         return 1;
 319
 320                 switch ((cmd >> 24) & 0x1f) {
 321                 case 0x1c:
 322                         return 1;
 323                 case 0x1d:
 324                         switch ((cmd >> 16) & 0xff) {
 325                         case 0x3:
 326                                 return (cmd & 0x1f) + 2;
 327                         case 0x4:
 328                                 return (cmd & 0xf) + 2;
 329                         default:
 330                                 return (cmd & 0xffff) + 2;
 331                         }
 332                 case 0x1e:
 333                         if (cmd & (1 << 23))
 334                                 return (cmd & 0xffff) + 1;
 335                         else
 336                                 return 1;
 337                 case 0x1f:
 338                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 339                                 return (cmd & 0x1ffff) + 2;
 340                         else if (cmd & (1 << 17))       /* indirect random */
 341                                 if ((cmd & 0xffff) == 0)
 342                                         return 0;       /* unknown length, too hard */
 343                                 else
 344                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 345                         else
 346                                 return 2;       /* indirect sequential */
 347                 default:
 348                         return 0;
 349                 }
 350         default:
 351                 return 0;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 358 {
 359         drm_i915_private_t *dev_priv = dev->dev_private;
 360         int i, ret;
 361
 362         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 363                 return -EINVAL;
 364
 365         for (i = 0; i < dwords;) {
 366                 int sz = validate_cmd(buffer[i]);
 367                 if (sz == 0 || i + sz > dwords)
 368                         return -EINVAL;
 369                 i += sz;
 370         }
 371
 372         ret = BEGIN_LP_RING((dwords+1)&~1);
 373         if (ret)
 374                 return ret;
 375
 376         for (i = 0; i < dwords; i++)
 377                 OUT_RING(buffer[i]);
 378         if (dwords & 1)
 379                 OUT_RING(0);
 380
 381         ADVANCE_LP_RING();
 382
 383         return 0;
 384 }
 385
 386 int
 387 i915_emit_box(struct drm_device *dev,
 388               struct drm_clip_rect *box,
 389               int DR1, int DR4)
 390 {
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         int ret;
 393
 394         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 395             box->y2 <= 0 || box->x2 <= 0) {
 396                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 397                           box->x1, box->y1, box->x2, box->y2);
 398                 return -EINVAL;
 399         }
 400
 401         if (INTEL_INFO(dev)->gen >= 4) {
 402                 ret = BEGIN_LP_RING(4);
 403                 if (ret)
 404                         return ret;
 405
 406                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 407                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 408                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 409                 OUT_RING(DR4);
 410         } else {
 411                 ret = BEGIN_LP_RING(6);
 412                 if (ret)
 413                         return ret;
 414
 415                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 416                 OUT_RING(DR1);
 417                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 418                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 419                 OUT_RING(DR4);
 420                 OUT_RING(0);
 421         }
 422         ADVANCE_LP_RING();
 423
 424         return 0;
 425 }
 426
 427 /* XXX: Emitting the counter should really be moved to part of the IRQ
 428  * emit. For now, do it in both places:
 429  */
 430
 431 static void i915_emit_breadcrumb(struct drm_device *dev)
 432 {
 433         drm_i915_private_t *dev_priv = dev->dev_private;
 434         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 435
 436         dev_priv->dri1.counter++;
 437         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 438                 dev_priv->dri1.counter = 0;
 439         if (master_priv->sarea_priv)
 440                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 441
 442         if (BEGIN_LP_RING(4) == 0) {
 443                 OUT_RING(MI_STORE_DWORD_INDEX);
 444                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 445                 OUT_RING(dev_priv->dri1.counter);
 446                 OUT_RING(0);
 447                 ADVANCE_LP_RING();
 448         }
 449 }
 450
 451 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 452                                    drm_i915_cmdbuffer_t *cmd,
 453                                    struct drm_clip_rect *cliprects,
 454                                    void *cmdbuf)
 455 {
 456         int nbox = cmd->num_cliprects;
 457         int i = 0, count, ret;
 458
 459         if (cmd->sz & 0x3) {
 460                 DRM_ERROR("alignment");
 461                 return -EINVAL;
 462         }
 463
 464         i915_kernel_lost_context(dev);
 465
 466         count = nbox ? nbox : 1;
 467
 468         for (i = 0; i < count; i++) {
 469                 if (i < nbox) {
 470                         ret = i915_emit_box(dev, &cliprects[i],
 471                                             cmd->DR1, cmd->DR4);
 472                         if (ret)
 473                                 return ret;
 474                 }
 475
 476                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 477                 if (ret)
 478                         return ret;
 479         }
 480
 481         i915_emit_breadcrumb(dev);
 482         return 0;
 483 }
 484
 485 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 486                                      drm_i915_batchbuffer_t * batch,
 487                                      struct drm_clip_rect *cliprects)
 488 {
 489         struct drm_i915_private *dev_priv = dev->dev_private;
 490         int nbox = batch->num_cliprects;
 491         int i, count, ret;
 492
 493         if ((batch->start | batch->used) & 0x7) {
 494                 DRM_ERROR("alignment");
 495                 return -EINVAL;
 496         }
 497
 498         i915_kernel_lost_context(dev);
 499
 500         count = nbox ? nbox : 1;
 501         for (i = 0; i < count; i++) {
 502                 if (i < nbox) {
 503                         ret = i915_emit_box(dev, &cliprects[i],
 504                                             batch->DR1, batch->DR4);
 505                         if (ret)
 506                                 return ret;
 507                 }
 508
 509                 if (!IS_I830(dev) && !IS_845G(dev)) {
 510                         ret = BEGIN_LP_RING(2);
 511                         if (ret)
 512                                 return ret;
 513
 514                         if (INTEL_INFO(dev)->gen >= 4) {
 515                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 516                                 OUT_RING(batch->start);
 517                         } else {
 518                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 519                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 520                         }
 521                 } else {
 522                         ret = BEGIN_LP_RING(4);
 523                         if (ret)
 524                                 return ret;
 525
 526                         OUT_RING(MI_BATCH_BUFFER);
 527                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 528                         OUT_RING(batch->start + batch->used - 4);
 529                         OUT_RING(0);
 530                 }
 531                 ADVANCE_LP_RING();
 532         }
 533
 534
 535         if (IS_G4X(dev) || IS_GEN5(dev)) {
 536                 if (BEGIN_LP_RING(2) == 0) {
 537                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 538                         OUT_RING(MI_NOOP);
 539                         ADVANCE_LP_RING();
 540                 }
 541         }
 542
 543         i915_emit_breadcrumb(dev);
 544         return 0;
 545 }
 546
 547 static int i915_dispatch_flip(struct drm_device * dev)
 548 {
 549         drm_i915_private_t *dev_priv = dev->dev_private;
 550         struct drm_i915_master_private *master_priv =
 551                 dev->primary->master->driver_priv;
 552         int ret;
 553
 554         if (!master_priv->sarea_priv)
 555                 return -EINVAL;
 556
 557         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 558                           __func__,
 559                          dev_priv->dri1.current_page,
 560                          master_priv->sarea_priv->pf_current_page);
 561
 562         i915_kernel_lost_context(dev);
 563
 564         ret = BEGIN_LP_RING(10);
 565         if (ret)
 566                 return ret;
 567
 568         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 569         OUT_RING(0);
 570
 571         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 572         OUT_RING(0);
 573         if (dev_priv->dri1.current_page == 0) {
 574                 OUT_RING(dev_priv->dri1.back_offset);
 575                 dev_priv->dri1.current_page = 1;
 576         } else {
 577                 OUT_RING(dev_priv->dri1.front_offset);
 578                 dev_priv->dri1.current_page = 0;
 579         }
 580         OUT_RING(0);
 581
 582         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 583         OUT_RING(0);
 584
 585         ADVANCE_LP_RING();
 586
 587         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 588
 589         if (BEGIN_LP_RING(4) == 0) {
 590                 OUT_RING(MI_STORE_DWORD_INDEX);
 591                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 592                 OUT_RING(dev_priv->dri1.counter);
 593                 OUT_RING(0);
 594                 ADVANCE_LP_RING();
 595         }
 596
 597         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 598         return 0;
 599 }
 600
 601 static int i915_quiescent(struct drm_device *dev)
 602 {
 603         i915_kernel_lost_context(dev);
 604         return intel_ring_idle(LP_RING(dev->dev_private));
 605 }
 606
 607 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 608                             struct drm_file *file_priv)
 609 {
 610         int ret;
 611
 612         if (drm_core_check_feature(dev, DRIVER_MODESET))
 613                 return -ENODEV;
 614
 615         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 616
 617         mutex_lock(&dev->struct_mutex);
 618         ret = i915_quiescent(dev);
 619         mutex_unlock(&dev->struct_mutex);
 620
 621         return ret;
 622 }
 623
 624 static int i915_batchbuffer(struct drm_device *dev, void *data,
 625                             struct drm_file *file_priv)
 626 {
 627         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 628         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 629         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 630             master_priv->sarea_priv;
 631         drm_i915_batchbuffer_t *batch = data;
 632         int ret;
 633         struct drm_clip_rect *cliprects = NULL;
 634
 635         if (drm_core_check_feature(dev, DRIVER_MODESET))
 636                 return -ENODEV;
 637
 638         if (!dev_priv->dri1.allow_batchbuffer) {
 639                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 640                 return -EINVAL;
 641         }
 642
 643         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 644                         batch->start, batch->used, batch->num_cliprects);
 645
 646         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 647
 648         if (batch->num_cliprects < 0)
 649                 return -EINVAL;
 650
 651         if (batch->num_cliprects) {
 652                 cliprects = kcalloc(batch->num_cliprects,
 653                                     sizeof(struct drm_clip_rect),
 654                                     GFP_KERNEL);
 655                 if (cliprects == NULL)
 656                         return -ENOMEM;
 657
 658                 ret = copy_from_user(cliprects, batch->cliprects,
 659                                      batch->num_cliprects *
 660                                      sizeof(struct drm_clip_rect));
 661                 if (ret != 0) {
 662                         ret = -EFAULT;
 663                         goto fail_free;
 664                 }
 665         }
 666
 667         mutex_lock(&dev->struct_mutex);
 668         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 669         mutex_unlock(&dev->struct_mutex);
 670
 671         if (sarea_priv)
 672                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 673
 674 fail_free:
 675         kfree(cliprects);
 676
 677         return ret;
 678 }
 679
 680 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 681                           struct drm_file *file_priv)
 682 {
 683         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 684         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 685         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 686             master_priv->sarea_priv;
 687         drm_i915_cmdbuffer_t *cmdbuf = data;
 688         struct drm_clip_rect *cliprects = NULL;
 689         void *batch_data;
 690         int ret;
 691
 692         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 693                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 694
 695         if (drm_core_check_feature(dev, DRIVER_MODESET))
 696                 return -ENODEV;
 697
 698         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 699
 700         if (cmdbuf->num_cliprects < 0)
 701                 return -EINVAL;
 702
 703         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 704         if (batch_data == NULL)
 705                 return -ENOMEM;
 706
 707         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 708         if (ret != 0) {
 709                 ret = -EFAULT;
 710                 goto fail_batch_free;
 711         }
 712
 713         if (cmdbuf->num_cliprects) {
 714                 cliprects = kcalloc(cmdbuf->num_cliprects,
 715                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 716                 if (cliprects == NULL) {
 717                         ret = -ENOMEM;
 718                         goto fail_batch_free;
 719                 }
 720
 721                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 722                                      cmdbuf->num_cliprects *
 723                                      sizeof(struct drm_clip_rect));
 724                 if (ret != 0) {
 725                         ret = -EFAULT;
 726                         goto fail_clip_free;
 727                 }
 728         }
 729
 730         mutex_lock(&dev->struct_mutex);
 731         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 732         mutex_unlock(&dev->struct_mutex);
 733         if (ret) {
 734                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 735                 goto fail_clip_free;
 736         }
 737
 738         if (sarea_priv)
 739                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 740
 741 fail_clip_free:
 742         kfree(cliprects);
 743 fail_batch_free:
 744         kfree(batch_data);
 745
 746         return ret;
 747 }
 748
 749 static int i915_emit_irq(struct drm_device * dev)
 750 {
 751         drm_i915_private_t *dev_priv = dev->dev_private;
 752         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 753
 754         i915_kernel_lost_context(dev);
 755
 756         DRM_DEBUG_DRIVER("\n");
 757
 758         dev_priv->dri1.counter++;
 759         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 760                 dev_priv->dri1.counter = 1;
 761         if (master_priv->sarea_priv)
 762                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 763
 764         if (BEGIN_LP_RING(4) == 0) {
 765                 OUT_RING(MI_STORE_DWORD_INDEX);
 766                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 767                 OUT_RING(dev_priv->dri1.counter);
 768                 OUT_RING(MI_USER_INTERRUPT);
 769                 ADVANCE_LP_RING();
 770         }
 771
 772         return dev_priv->dri1.counter;
 773 }
 774
 775 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 776 {
 777         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 778         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 779         int ret = 0;
 780         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 781
 782         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 783                   READ_BREADCRUMB(dev_priv));
 784
 785         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 786                 if (master_priv->sarea_priv)
 787                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 788                 return 0;
 789         }
 790
 791         if (master_priv->sarea_priv)
 792                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 793
 794         if (ring->irq_get(ring)) {
 795                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 796                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 797                 ring->irq_put(ring);
 798         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 799                 ret = -EBUSY;
 800
 801         if (ret == -EBUSY) {
 802                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 803                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 804         }
 805
 806         return ret;
 807 }
 808
 809 /* Needs the lock as it touches the ring.
 810  */
 811 static int i915_irq_emit(struct drm_device *dev, void *data,
 812                          struct drm_file *file_priv)
 813 {
 814         drm_i915_private_t *dev_priv = dev->dev_private;
 815         drm_i915_irq_emit_t *emit = data;
 816         int result;
 817
 818         if (drm_core_check_feature(dev, DRIVER_MODESET))
 819                 return -ENODEV;
 820
 821         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 822                 DRM_ERROR("called with no initialization\n");
 823                 return -EINVAL;
 824         }
 825
 826         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 827
 828         mutex_lock(&dev->struct_mutex);
 829         result = i915_emit_irq(dev);
 830         mutex_unlock(&dev->struct_mutex);
 831
 832         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 833                 DRM_ERROR("copy_to_user\n");
 834                 return -EFAULT;
 835         }
 836
 837         return 0;
 838 }
 839
 840 /* Doesn't need the hardware lock.
 841  */
 842 static int i915_irq_wait(struct drm_device *dev, void *data,
 843                          struct drm_file *file_priv)
 844 {
 845         drm_i915_private_t *dev_priv = dev->dev_private;
 846         drm_i915_irq_wait_t *irqwait = data;
 847
 848         if (drm_core_check_feature(dev, DRIVER_MODESET))
 849                 return -ENODEV;
 850
 851         if (!dev_priv) {
 852                 DRM_ERROR("called with no initialization\n");
 853                 return -EINVAL;
 854         }
 855
 856         return i915_wait_irq(dev, irqwait->irq_seq);
 857 }
 858
 859 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 860                          struct drm_file *file_priv)
 861 {
 862         drm_i915_private_t *dev_priv = dev->dev_private;
 863         drm_i915_vblank_pipe_t *pipe = data;
 864
 865         if (drm_core_check_feature(dev, DRIVER_MODESET))
 866                 return -ENODEV;
 867
 868         if (!dev_priv) {
 869                 DRM_ERROR("called with no initialization\n");
 870                 return -EINVAL;
 871         }
 872
 873         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 874
 875         return 0;
 876 }
 877
 878 /**
 879  * Schedule buffer swap at given vertical blank.
 880  */
 881 static int i915_vblank_swap(struct drm_device *dev, void *data,
 882                      struct drm_file *file_priv)
 883 {
 884         /* The delayed swap mechanism was fundamentally racy, and has been
 885          * removed.  The model was that the client requested a delayed flip/swap
 886          * from the kernel, then waited for vblank before continuing to perform
 887          * rendering.  The problem was that the kernel might wake the client
 888          * up before it dispatched the vblank swap (since the lock has to be
 889          * held while touching the ringbuffer), in which case the client would
 890          * clear and start the next frame before the swap occurred, and
 891          * flicker would occur in addition to likely missing the vblank.
 892          *
 893          * In the absence of this ioctl, userland falls back to a correct path
 894          * of waiting for a vblank, then dispatching the swap on its own.
 895          * Context switching to userland and back is plenty fast enough for
 896          * meeting the requirements of vblank swapping.
 897          */
 898         return -EINVAL;
 899 }
 900
 901 static int i915_flip_bufs(struct drm_device *dev, void *data,
 902                           struct drm_file *file_priv)
 903 {
 904         int ret;
 905
 906         if (drm_core_check_feature(dev, DRIVER_MODESET))
 907                 return -ENODEV;
 908
 909         DRM_DEBUG_DRIVER("%s\n", __func__);
 910
 911         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 912
 913         mutex_lock(&dev->struct_mutex);
 914         ret = i915_dispatch_flip(dev);
 915         mutex_unlock(&dev->struct_mutex);
 916
 917         return ret;
 918 }
 919
 920 static int i915_getparam(struct drm_device *dev, void *data,
 921                          struct drm_file *file_priv)
 922 {
 923         drm_i915_private_t *dev_priv = dev->dev_private;
 924         drm_i915_getparam_t *param = data;
 925         int value;
 926
 927         if (!dev_priv) {
 928                 DRM_ERROR("called with no initialization\n");
 929                 return -EINVAL;
 930         }
 931
 932         switch (param->param) {
 933         case I915_PARAM_IRQ_ACTIVE:
 934                 value = dev->pdev->irq ? 1 : 0;
 935                 break;
 936         case I915_PARAM_ALLOW_BATCHBUFFER:
 937                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 938                 break;
 939         case I915_PARAM_LAST_DISPATCH:
 940                 value = READ_BREADCRUMB(dev_priv);
 941                 break;
 942         case I915_PARAM_CHIPSET_ID:
 943                 value = dev->pci_device;
 944                 break;
 945         case I915_PARAM_HAS_GEM:
 946                 value = 1;
 947                 break;
 948         case I915_PARAM_NUM_FENCES_AVAIL:
 949                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 950                 break;
 951         case I915_PARAM_HAS_OVERLAY:
 952                 value = dev_priv->overlay ? 1 : 0;
 953                 break;
 954         case I915_PARAM_HAS_PAGEFLIPPING:
 955                 value = 1;
 956                 break;
 957         case I915_PARAM_HAS_EXECBUF2:
 958                 /* depends on GEM */
 959                 value = 1;
 960                 break;
 961         case I915_PARAM_HAS_BSD:
 962                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 963                 break;
 964         case I915_PARAM_HAS_BLT:
 965                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 966                 break;
 967         case I915_PARAM_HAS_RELAXED_FENCING:
 968                 value = 1;
 969                 break;
 970         case I915_PARAM_HAS_COHERENT_RINGS:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_HAS_EXEC_CONSTANTS:
 974                 value = INTEL_INFO(dev)->gen >= 4;
 975                 break;
 976         case I915_PARAM_HAS_RELAXED_DELTA:
 977                 value = 1;
 978                 break;
 979         case I915_PARAM_HAS_GEN7_SOL_RESET:
 980                 value = 1;
 981                 break;
 982         case I915_PARAM_HAS_LLC:
 983                 value = HAS_LLC(dev);
 984                 break;
 985         case I915_PARAM_HAS_ALIASING_PPGTT:
 986                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 987                 break;
 988         case I915_PARAM_HAS_WAIT_TIMEOUT:
 989                 value = 1;
 990                 break;
 991         case I915_PARAM_HAS_SEMAPHORES:
 992                 value = i915_semaphore_is_enabled(dev);
 993                 break;
 994         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 995                 value = 1;
 996                 break;
 997         case I915_PARAM_HAS_SECURE_BATCHES:
 998                 value = capable(CAP_SYS_ADMIN);
 999                 break;
1000         case I915_PARAM_HAS_PINNED_BATCHES:
1001                 value = 1;
1002                 break;
1003         case I915_PARAM_HAS_EXEC_NO_RELOC:
1004                 value = 1;
1005                 break;
1006         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1007                 value = 1;
1008                 break;
1009         default:
1010                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1011                                  param->param);
1012                 return -EINVAL;
1013         }
1014
1015         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1016                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1017                 return -EFAULT;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static int i915_setparam(struct drm_device *dev, void *data,
1024                          struct drm_file *file_priv)
1025 {
1026         drm_i915_private_t *dev_priv = dev->dev_private;
1027         drm_i915_setparam_t *param = data;
1028
1029         if (!dev_priv) {
1030                 DRM_ERROR("called with no initialization\n");
1031                 return -EINVAL;
1032         }
1033
1034         switch (param->param) {
1035         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1036                 break;
1037         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1038                 break;
1039         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1040                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1041                 break;
1042         case I915_SETPARAM_NUM_USED_FENCES:
1043                 if (param->value > dev_priv->num_fence_regs ||
1044                     param->value < 0)
1045                         return -EINVAL;
1046                 /* Userspace can use first N regs */
1047                 dev_priv->fence_reg_start = param->value;
1048                 break;
1049         default:
1050                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1051                                         param->param);
1052                 return -EINVAL;
1053         }
1054
1055         return 0;
1056 }
1057
1058 static int i915_set_status_page(struct drm_device *dev, void *data,
1059                                 struct drm_file *file_priv)
1060 {
1061         drm_i915_private_t *dev_priv = dev->dev_private;
1062         drm_i915_hws_addr_t *hws = data;
1063         struct intel_ring_buffer *ring;
1064
1065         if (drm_core_check_feature(dev, DRIVER_MODESET))
1066                 return -ENODEV;
1067
1068         if (!I915_NEED_GFX_HWS(dev))
1069                 return -EINVAL;
1070
1071         if (!dev_priv) {
1072                 DRM_ERROR("called with no initialization\n");
1073                 return -EINVAL;
1074         }
1075
1076         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1077                 WARN(1, "tried to set status page when mode setting active\n");
1078                 return 0;
1079         }
1080
1081         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1082
1083         ring = LP_RING(dev_priv);
1084         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1085
1086         dev_priv->dri1.gfx_hws_cpu_addr =
1087                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1088         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1089                 i915_dma_cleanup(dev);
1090                 ring->status_page.gfx_addr = 0;
1091                 DRM_ERROR("can not ioremap virtual address for"
1092                                 " G33 hw status page\n");
1093                 return -ENOMEM;
1094         }
1095
1096         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1097         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1098
1099         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1100                          ring->status_page.gfx_addr);
1101         DRM_DEBUG_DRIVER("load hws at %p\n",
1102                          ring->status_page.page_addr);
1103         return 0;
1104 }
1105
1106 static int i915_get_bridge_dev(struct drm_device *dev)
1107 {
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109
1110         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1111         if (!dev_priv->bridge_dev) {
1112                 DRM_ERROR("bridge device not found\n");
1113                 return -1;
1114         }
1115         return 0;
1116 }
1117
1118 #define MCHBAR_I915 0x44
1119 #define MCHBAR_I965 0x48
1120 #define MCHBAR_SIZE (4*4096)
1121
1122 #define DEVEN_REG 0x54
1123 #define   DEVEN_MCHBAR_EN (1 << 28)
1124
1125 /* Allocate space for the MCH regs if needed, return nonzero on error */
1126 static int
1127 intel_alloc_mchbar_resource(struct drm_device *dev)
1128 {
1129         drm_i915_private_t *dev_priv = dev->dev_private;
1130         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1131         u32 temp_lo, temp_hi = 0;
1132         u64 mchbar_addr;
1133         int ret;
1134
1135         if (INTEL_INFO(dev)->gen >= 4)
1136                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1137         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1138         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1139
1140         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1141 #ifdef CONFIG_PNP
1142         if (mchbar_addr &&
1143             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1144                 return 0;
1145 #endif
1146
1147         /* Get some space for it */
1148         dev_priv->mch_res.name = "i915 MCHBAR";
1149         dev_priv->mch_res.flags = IORESOURCE_MEM;
1150         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1151                                      &dev_priv->mch_res,
1152                                      MCHBAR_SIZE, MCHBAR_SIZE,
1153                                      PCIBIOS_MIN_MEM,
1154                                      0, pcibios_align_resource,
1155                                      dev_priv->bridge_dev);
1156         if (ret) {
1157                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1158                 dev_priv->mch_res.start = 0;
1159                 return ret;
1160         }
1161
1162         if (INTEL_INFO(dev)->gen >= 4)
1163                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1164                                        upper_32_bits(dev_priv->mch_res.start));
1165
1166         pci_write_config_dword(dev_priv->bridge_dev, reg,
1167                                lower_32_bits(dev_priv->mch_res.start));
1168         return 0;
1169 }
1170
1171 /* Setup MCHBAR if possible, return true if we should disable it again */
1172 static void
1173 intel_setup_mchbar(struct drm_device *dev)
1174 {
1175         drm_i915_private_t *dev_priv = dev->dev_private;
1176         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1177         u32 temp;
1178         bool enabled;
1179
1180         dev_priv->mchbar_need_disable = false;
1181
1182         if (IS_I915G(dev) || IS_I915GM(dev)) {
1183                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1184                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1185         } else {
1186                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1187                 enabled = temp & 1;
1188         }
1189
1190         /* If it's already enabled, don't have to do anything */
1191         if (enabled)
1192                 return;
1193
1194         if (intel_alloc_mchbar_resource(dev))
1195                 return;
1196
1197         dev_priv->mchbar_need_disable = true;
1198
1199         /* Space is allocated or reserved, so enable it. */
1200         if (IS_I915G(dev) || IS_I915GM(dev)) {
1201                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1202                                        temp | DEVEN_MCHBAR_EN);
1203         } else {
1204                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1205                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1206         }
1207 }
1208
1209 static void
1210 intel_teardown_mchbar(struct drm_device *dev)
1211 {
1212         drm_i915_private_t *dev_priv = dev->dev_private;
1213         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1214         u32 temp;
1215
1216         if (dev_priv->mchbar_need_disable) {
1217                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1218                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1219                         temp &= ~DEVEN_MCHBAR_EN;
1220                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1221                 } else {
1222                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1223                         temp &= ~1;
1224                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1225                 }
1226         }
1227
1228         if (dev_priv->mch_res.start)
1229                 release_resource(&dev_priv->mch_res);
1230 }
1231
1232 /* true = enable decode, false = disable decoder */
1233 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1234 {
1235         struct drm_device *dev = cookie;
1236
1237         intel_modeset_vga_set_state(dev, state);
1238         if (state)
1239                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1240                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1241         else
1242                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1243 }
1244
1245 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1246 {
1247         struct drm_device *dev = pci_get_drvdata(pdev);
1248         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1249         if (state == VGA_SWITCHEROO_ON) {
1250                 pr_info("switched on\n");
1251                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1252                 /* i915 resume handler doesn't set to D0 */
1253                 pci_set_power_state(dev->pdev, PCI_D0);
1254                 i915_resume(dev);
1255                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1256         } else {
1257                 pr_err("switched off\n");
1258                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1259                 i915_suspend(dev, pmm);
1260                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1261         }
1262 }
1263
1264 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1265 {
1266         struct drm_device *dev = pci_get_drvdata(pdev);
1267         bool can_switch;
1268
1269         spin_lock(&dev->count_lock);
1270         can_switch = (dev->open_count == 0);
1271         spin_unlock(&dev->count_lock);
1272         return can_switch;
1273 }
1274
1275 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1276         .set_gpu_state = i915_switcheroo_set_state,
1277         .reprobe = NULL,
1278         .can_switch = i915_switcheroo_can_switch,
1279 };
1280
1281 static int i915_load_modeset_init(struct drm_device *dev)
1282 {
1283         struct drm_i915_private *dev_priv = dev->dev_private;
1284         int ret;
1285
1286         ret = intel_parse_bios(dev);
1287         if (ret)
1288                 DRM_INFO("failed to find VBIOS tables\n");
1289
1290         /* If we have > 1 VGA cards, then we need to arbitrate access
1291          * to the common VGA resources.
1292          *
1293          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1294          * then we do not take part in VGA arbitration and the
1295          * vga_client_register() fails with -ENODEV.
1296          */
1297         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1298         if (ret && ret != -ENODEV)
1299                 goto out;
1300
1301         intel_register_dsm_handler();
1302
1303         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1304         if (ret)
1305                 goto cleanup_vga_client;
1306
1307         /* Initialise stolen first so that we may reserve preallocated
1308          * objects for the BIOS to KMS transition.
1309          */
1310         ret = i915_gem_init_stolen(dev);
1311         if (ret)
1312                 goto cleanup_vga_switcheroo;
1313
1314         ret = drm_irq_install(dev);
1315         if (ret)
1316                 goto cleanup_gem_stolen;
1317
1318         /* Important: The output setup functions called by modeset_init need
1319          * working irqs for e.g. gmbus and dp aux transfers. */
1320         intel_modeset_init(dev);
1321
1322         ret = i915_gem_init(dev);
1323         if (ret)
1324                 goto cleanup_irq;
1325
1326         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1327
1328         intel_modeset_gem_init(dev);
1329
1330         /* Always safe in the mode setting case. */
1331         /* FIXME: do pre/post-mode set stuff in core KMS code */
1332         dev->vblank_disable_allowed = 1;
1333         if (INTEL_INFO(dev)->num_pipes == 0) {
1334                 dev_priv->mm.suspended = 0;
1335                 return 0;
1336         }
1337
1338         ret = intel_fbdev_init(dev);
1339         if (ret)
1340                 goto cleanup_gem;
1341
1342         /* Only enable hotplug handling once the fbdev is fully set up. */
1343         intel_hpd_init(dev);
1344
1345         /*
1346          * Some ports require correctly set-up hpd registers for detection to
1347          * work properly (leading to ghost connected connector status), e.g. VGA
1348          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1349          * irqs are fully enabled. Now we should scan for the initial config
1350          * only once hotplug handling is enabled, but due to screwed-up locking
1351          * around kms/fbdev init we can't protect the fdbev initial config
1352          * scanning against hotplug events. Hence do this first and ignore the
1353          * tiny window where we will loose hotplug notifactions.
1354          */
1355         intel_fbdev_initial_config(dev);
1356
1357         /* Only enable hotplug handling once the fbdev is fully set up. */
1358         dev_priv->enable_hotplug_processing = true;
1359
1360         drm_kms_helper_poll_init(dev);
1361
1362         /* We're off and running w/KMS */
1363         dev_priv->mm.suspended = 0;
1364
1365         return 0;
1366
1367 cleanup_gem:
1368         mutex_lock(&dev->struct_mutex);
1369         i915_gem_cleanup_ringbuffer(dev);
1370         mutex_unlock(&dev->struct_mutex);
1371         i915_gem_cleanup_aliasing_ppgtt(dev);
1372 cleanup_irq:
1373         drm_irq_uninstall(dev);
1374 cleanup_gem_stolen:
1375         i915_gem_cleanup_stolen(dev);
1376 cleanup_vga_switcheroo:
1377         vga_switcheroo_unregister_client(dev->pdev);
1378 cleanup_vga_client:
1379         vga_client_register(dev->pdev, NULL, NULL, NULL);
1380 out:
1381         return ret;
1382 }
1383
1384 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1385 {
1386         struct drm_i915_master_private *master_priv;
1387
1388         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1389         if (!master_priv)
1390                 return -ENOMEM;
1391
1392         master->driver_priv = master_priv;
1393         return 0;
1394 }
1395
1396 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1397 {
1398         struct drm_i915_master_private *master_priv = master->driver_priv;
1399
1400         if (!master_priv)
1401                 return;
1402
1403         kfree(master_priv);
1404
1405         master->driver_priv = NULL;
1406 }
1407
1408 static void
1409 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1410                 unsigned long size)
1411 {
1412         dev_priv->mm.gtt_mtrr = -1;
1413
1414 #if defined(CONFIG_X86_PAT)
1415         if (cpu_has_pat)
1416                 return;
1417 #endif
1418
1419         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1420          * one would think, because the kernel disables PAT on first
1421          * generation Core chips because WC PAT gets overridden by a UC
1422          * MTRR if present.  Even if a UC MTRR isn't present.
1423          */
1424         dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1425         if (dev_priv->mm.gtt_mtrr < 0) {
1426                 DRM_INFO("MTRR allocation failed.  Graphics "
1427                          "performance may suffer.\n");
1428         }
1429 }
1430
1431 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1432 {
1433         struct apertures_struct *ap;
1434         struct pci_dev *pdev = dev_priv->dev->pdev;
1435         bool primary;
1436
1437         ap = alloc_apertures(1);
1438         if (!ap)
1439                 return;
1440
1441         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1442         ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1443
1444         primary =
1445                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1446
1447         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1448
1449         kfree(ap);
1450 }
1451
1452 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1453 {
1454         const struct intel_device_info *info = dev_priv->info;
1455
1456 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1457 #define DEV_INFO_SEP ,
1458         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1459                          "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1460                          info->gen,
1461                          dev_priv->dev->pdev->device,
1462                          DEV_INFO_FLAGS);
1463 #undef DEV_INFO_FLAG
1464 #undef DEV_INFO_SEP
1465 }
1466
1467 /**
1468  * intel_early_sanitize_regs - clean up BIOS state
1469  * @dev: DRM device
1470  *
1471  * This function must be called before we do any I915_READ or I915_WRITE. Its
1472  * purpose is to clean up any state left by the BIOS that may affect us when
1473  * reading and/or writing registers.
1474  */
1475 static void intel_early_sanitize_regs(struct drm_device *dev)
1476 {
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478
1479         if (IS_HASWELL(dev))
1480                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1481 }
1482
1483 /**
1484  * i915_driver_load - setup chip and create an initial config
1485  * @dev: DRM device
1486  * @flags: startup flags
1487  *
1488  * The driver load routine has to do several things:
1489  *   - drive output discovery via intel_modeset_init()
1490  *   - initialize the memory manager
1491  *   - allocate initial config memory
1492  *   - setup the DRM framebuffer with the allocated memory
1493  */
1494 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1495 {
1496         struct drm_i915_private *dev_priv;
1497         struct intel_device_info *info;
1498         int ret = 0, mmio_bar, mmio_size;
1499         uint32_t aperture_size;
1500
1501         info = (struct intel_device_info *) flags;
1502
1503         /* Refuse to load on gen6+ without kms enabled. */
1504         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1505                 return -ENODEV;
1506
1507         /* i915 has 4 more counters */
1508         dev->counters += 4;
1509         dev->types[6] = _DRM_STAT_IRQ;
1510         dev->types[7] = _DRM_STAT_PRIMARY;
1511         dev->types[8] = _DRM_STAT_SECONDARY;
1512         dev->types[9] = _DRM_STAT_DMA;
1513
1514         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1515         if (dev_priv == NULL)
1516                 return -ENOMEM;
1517
1518         dev->dev_private = (void *)dev_priv;
1519         dev_priv->dev = dev;
1520         dev_priv->info = info;
1521
1522         spin_lock_init(&dev_priv->irq_lock);
1523         spin_lock_init(&dev_priv->gpu_error.lock);
1524         spin_lock_init(&dev_priv->rps.lock);
1525         spin_lock_init(&dev_priv->gt_lock);
1526         mutex_init(&dev_priv->dpio_lock);
1527         mutex_init(&dev_priv->rps.hw_lock);
1528         mutex_init(&dev_priv->modeset_restore_lock);
1529
1530         i915_dump_device_info(dev_priv);
1531
1532         if (i915_get_bridge_dev(dev)) {
1533                 ret = -EIO;
1534                 goto free_priv;
1535         }
1536
1537         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1538         /* Before gen4, the registers and the GTT are behind different BARs.
1539          * However, from gen4 onwards, the registers and the GTT are shared
1540          * in the same BAR, so we want to restrict this ioremap from
1541          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1542          * the register BAR remains the same size for all the earlier
1543          * generations up to Ironlake.
1544          */
1545         if (info->gen < 5)
1546                 mmio_size = 512*1024;
1547         else
1548                 mmio_size = 2*1024*1024;
1549
1550         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1551         if (!dev_priv->regs) {
1552                 DRM_ERROR("failed to map registers\n");
1553                 ret = -EIO;
1554                 goto put_bridge;
1555         }
1556
1557         intel_early_sanitize_regs(dev);
1558
1559         ret = i915_gem_gtt_init(dev);
1560         if (ret)
1561                 goto put_bridge;
1562
1563         if (drm_core_check_feature(dev, DRIVER_MODESET))
1564                 i915_kick_out_firmware_fb(dev_priv);
1565
1566         pci_set_master(dev->pdev);
1567
1568         /* overlay on gen2 is broken and can't address above 1G */
1569         if (IS_GEN2(dev))
1570                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1571
1572         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1573          * using 32bit addressing, overwriting memory if HWS is located
1574          * above 4GB.
1575          *
1576          * The documentation also mentions an issue with undefined
1577          * behaviour if any general state is accessed within a page above 4GB,
1578          * which also needs to be handled carefully.
1579          */
1580         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1581                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1582
1583         aperture_size = dev_priv->gtt.mappable_end;
1584
1585         dev_priv->gtt.mappable =
1586                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1587                                      aperture_size);
1588         if (dev_priv->gtt.mappable == NULL) {
1589                 ret = -EIO;
1590                 goto out_rmmap;
1591         }
1592
1593         i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1594                         aperture_size);
1595
1596         /* The i915 workqueue is primarily used for batched retirement of
1597          * requests (and thus managing bo) once the task has been completed
1598          * by the GPU. i915_gem_retire_requests() is called directly when we
1599          * need high-priority retirement, such as waiting for an explicit
1600          * bo.
1601          *
1602          * It is also used for periodic low-priority events, such as
1603          * idle-timers and recording error state.
1604          *
1605          * All tasks on the workqueue are expected to acquire the dev mutex
1606          * so there is no point in running more than one instance of the
1607          * workqueue at any time.  Use an ordered one.
1608          */
1609         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1610         if (dev_priv->wq == NULL) {
1611                 DRM_ERROR("Failed to create our workqueue.\n");
1612                 ret = -ENOMEM;
1613                 goto out_mtrrfree;
1614         }
1615
1616         /* This must be called before any calls to HAS_PCH_* */
1617         intel_detect_pch(dev);
1618
1619         intel_irq_init(dev);
1620         intel_pm_init(dev);
1621         intel_gt_sanitize(dev);
1622         intel_gt_init(dev);
1623
1624         /* Try to make sure MCHBAR is enabled before poking at it */
1625         intel_setup_mchbar(dev);
1626         intel_setup_gmbus(dev);
1627         intel_opregion_setup(dev);
1628
1629         intel_setup_bios(dev);
1630
1631         i915_gem_load(dev);
1632
1633         /* On the 945G/GM, the chipset reports the MSI capability on the
1634          * integrated graphics even though the support isn't actually there
1635          * according to the published specs.  It doesn't appear to function
1636          * correctly in testing on 945G.
1637          * This may be a side effect of MSI having been made available for PEG
1638          * and the registers being closely associated.
1639          *
1640          * According to chipset errata, on the 965GM, MSI interrupts may
1641          * be lost or delayed, but we use them anyways to avoid
1642          * stuck interrupts on some machines.
1643          */
1644         if (!IS_I945G(dev) && !IS_I945GM(dev))
1645                 pci_enable_msi(dev->pdev);
1646
1647         dev_priv->num_plane = 1;
1648         if (IS_VALLEYVIEW(dev))
1649                 dev_priv->num_plane = 2;
1650
1651         if (INTEL_INFO(dev)->num_pipes) {
1652                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1653                 if (ret)
1654                         goto out_gem_unload;
1655         }
1656
1657         /* Start out suspended */
1658         dev_priv->mm.suspended = 1;
1659
1660         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1661                 ret = i915_load_modeset_init(dev);
1662                 if (ret < 0) {
1663                         DRM_ERROR("failed to init modeset\n");
1664                         goto out_gem_unload;
1665                 }
1666         }
1667
1668         i915_setup_sysfs(dev);
1669
1670         if (INTEL_INFO(dev)->num_pipes) {
1671                 /* Must be done after probing outputs */
1672                 intel_opregion_init(dev);
1673                 acpi_video_register();
1674         }
1675
1676         if (IS_GEN5(dev))
1677                 intel_gpu_ips_init(dev_priv);
1678
1679         return 0;
1680
1681 out_gem_unload:
1682         if (dev_priv->mm.inactive_shrinker.shrink)
1683                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1684
1685         if (dev->pdev->msi_enabled)
1686                 pci_disable_msi(dev->pdev);
1687
1688         intel_teardown_gmbus(dev);
1689         intel_teardown_mchbar(dev);
1690         pm_qos_remove_request(&dev_priv->pm_qos);
1691         destroy_workqueue(dev_priv->wq);
1692 out_mtrrfree:
1693         if (dev_priv->mm.gtt_mtrr >= 0) {
1694                 mtrr_del(dev_priv->mm.gtt_mtrr,
1695                          dev_priv->gtt.mappable_base,
1696                          aperture_size);
1697                 dev_priv->mm.gtt_mtrr = -1;
1698         }
1699         io_mapping_free(dev_priv->gtt.mappable);
1700         dev_priv->gtt.gtt_remove(dev);
1701 out_rmmap:
1702         pci_iounmap(dev->pdev, dev_priv->regs);
1703 put_bridge:
1704         pci_dev_put(dev_priv->bridge_dev);
1705 free_priv:
1706         kfree(dev_priv);
1707         return ret;
1708 }
1709
1710 int i915_driver_unload(struct drm_device *dev)
1711 {
1712         struct drm_i915_private *dev_priv = dev->dev_private;
1713         int ret;
1714
1715         intel_gpu_ips_teardown();
1716
1717         i915_teardown_sysfs(dev);
1718
1719         if (dev_priv->mm.inactive_shrinker.shrink)
1720                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1721
1722         mutex_lock(&dev->struct_mutex);
1723         ret = i915_gpu_idle(dev);
1724         if (ret)
1725                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1726         i915_gem_retire_requests(dev);
1727         mutex_unlock(&dev->struct_mutex);
1728
1729         /* Cancel the retire work handler, which should be idle now. */
1730         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1731
1732         io_mapping_free(dev_priv->gtt.mappable);
1733         if (dev_priv->mm.gtt_mtrr >= 0) {
1734                 mtrr_del(dev_priv->mm.gtt_mtrr,
1735                          dev_priv->gtt.mappable_base,
1736                          dev_priv->gtt.mappable_end);
1737                 dev_priv->mm.gtt_mtrr = -1;
1738         }
1739
1740         acpi_video_unregister();
1741
1742         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1743                 intel_fbdev_fini(dev);
1744                 intel_modeset_cleanup(dev);
1745                 cancel_work_sync(&dev_priv->console_resume_work);
1746
1747                 /*
1748                  * free the memory space allocated for the child device
1749                  * config parsed from VBT
1750                  */
1751                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1752                         kfree(dev_priv->child_dev);
1753                         dev_priv->child_dev = NULL;
1754                         dev_priv->child_dev_num = 0;
1755                 }
1756
1757                 vga_switcheroo_unregister_client(dev->pdev);
1758                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1759         }
1760
1761         /* Free error state after interrupts are fully disabled. */
1762         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1763         cancel_work_sync(&dev_priv->gpu_error.work);
1764         i915_destroy_error_state(dev);
1765
1766         if (dev->pdev->msi_enabled)
1767                 pci_disable_msi(dev->pdev);
1768
1769         intel_opregion_fini(dev);
1770
1771         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1772                 /* Flush any outstanding unpin_work. */
1773                 flush_workqueue(dev_priv->wq);
1774
1775                 mutex_lock(&dev->struct_mutex);
1776                 i915_gem_free_all_phys_object(dev);
1777                 i915_gem_cleanup_ringbuffer(dev);
1778                 i915_gem_context_fini(dev);
1779                 mutex_unlock(&dev->struct_mutex);
1780                 i915_gem_cleanup_aliasing_ppgtt(dev);
1781                 i915_gem_cleanup_stolen(dev);
1782
1783                 if (!I915_NEED_GFX_HWS(dev))
1784                         i915_free_hws(dev);
1785         }
1786
1787         if (dev_priv->regs != NULL)
1788                 pci_iounmap(dev->pdev, dev_priv->regs);
1789
1790         intel_teardown_gmbus(dev);
1791         intel_teardown_mchbar(dev);
1792
1793         destroy_workqueue(dev_priv->wq);
1794         pm_qos_remove_request(&dev_priv->pm_qos);
1795
1796         if (dev_priv->slab)
1797                 kmem_cache_destroy(dev_priv->slab);
1798
1799         pci_dev_put(dev_priv->bridge_dev);
1800         kfree(dev->dev_private);
1801
1802         return 0;
1803 }
1804
1805 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1806 {
1807         struct drm_i915_file_private *file_priv;
1808
1809         DRM_DEBUG_DRIVER("\n");
1810         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1811         if (!file_priv)
1812                 return -ENOMEM;
1813
1814         file->driver_priv = file_priv;
1815
1816         spin_lock_init(&file_priv->mm.lock);
1817         INIT_LIST_HEAD(&file_priv->mm.request_list);
1818
1819         idr_init(&file_priv->context_idr);
1820
1821         return 0;
1822 }
1823
1824 /**
1825  * i915_driver_lastclose - clean up after all DRM clients have exited
1826  * @dev: DRM device
1827  *
1828  * Take care of cleaning up after all DRM clients have exited.  In the
1829  * mode setting case, we want to restore the kernel's initial mode (just
1830  * in case the last client left us in a bad state).
1831  *
1832  * Additionally, in the non-mode setting case, we'll tear down the GTT
1833  * and DMA structures, since the kernel won't be using them, and clea
1834  * up any GEM state.
1835  */
1836 void i915_driver_lastclose(struct drm_device * dev)
1837 {
1838         drm_i915_private_t *dev_priv = dev->dev_private;
1839
1840         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1841          * goes right around and calls lastclose. Check for this and don't clean
1842          * up anything. */
1843         if (!dev_priv)
1844                 return;
1845
1846         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1847                 intel_fb_restore_mode(dev);
1848                 vga_switcheroo_process_delayed_switch();
1849                 return;
1850         }
1851
1852         i915_gem_lastclose(dev);
1853
1854         i915_dma_cleanup(dev);
1855 }
1856
1857 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1858 {
1859         mutex_lock(&dev->struct_mutex);
1860         i915_gem_context_close(dev, file_priv);
1861         i915_gem_release(dev, file_priv);
1862         mutex_unlock(&dev->struct_mutex);
1863 }
1864
1865 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1866 {
1867         struct drm_i915_file_private *file_priv = file->driver_priv;
1868
1869         kfree(file_priv);
1870 }
1871
1872 struct drm_ioctl_desc i915_ioctls[] = {
1873         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1874         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1875         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1876         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1877         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1878         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1879         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1880         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1881         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1882         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1883         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1884         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1885         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1886         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1887         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1888         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1889         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1890         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1891         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1892         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1893         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1894         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1895         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1896         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1897         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1898         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1899         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1900         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1901         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1902         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1903         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1904         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1905         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1906         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1907         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1908         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1909         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1910         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1911         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1912         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1913         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1914         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1915         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1916         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1917         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1918         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1919         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1920         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1921 };
1922
1923 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1924
1925 /*
1926  * This is really ugly: Because old userspace abused the linux agp interface to
1927  * manage the gtt, we need to claim that all intel devices are agp.  For
1928  * otherwise the drm core refuses to initialize the agp support code.
1929  */
1930 int i915_driver_device_is_agp(struct drm_device * dev)
1931 {
1932         return 1;
1933 }