2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v)
51 return v ? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor *minor,
61 struct drm_info_node *node;
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
71 node->info_ent = (void *) key;
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
80 static int i915_capabilities(struct seq_file *m, void *data)
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
107 switch (obj->tiling_mode) {
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
123 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
124 struct intel_engine_cs *ring;
125 struct i915_vma *vma;
129 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
131 obj->active ? "*" : " ",
133 get_tiling_flag(obj),
134 get_global_flag(obj),
135 obj->base.size / 1024,
136 obj->base.read_domains,
137 obj->base.write_domain);
138 for_each_ring(ring, dev_priv, i)
140 i915_gem_request_get_seqno(obj->last_read_req[i]));
141 seq_printf(m, "] %x %x%s%s%s",
142 i915_gem_request_get_seqno(obj->last_write_req),
143 i915_gem_request_get_seqno(obj->last_fenced_req),
144 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
145 obj->dirty ? " dirty" : "",
146 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
148 seq_printf(m, " (name: %d)", obj->base.name);
149 list_for_each_entry(vma, &obj->vma_list, vma_link) {
150 if (vma->pin_count > 0)
153 seq_printf(m, " (pinned x %d)", pin_count);
154 if (obj->pin_display)
155 seq_printf(m, " (display)");
156 if (obj->fence_reg != I915_FENCE_REG_NONE)
157 seq_printf(m, " (fence: %d)", obj->fence_reg);
158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
159 if (!i915_is_ggtt(vma->vm))
163 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
164 vma->node.start, vma->node.size,
165 vma->ggtt_view.type);
168 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
169 if (obj->pin_display || obj->fault_mappable) {
171 if (obj->pin_display)
173 if (obj->fault_mappable)
176 seq_printf(m, " (%s mappable)", s);
178 if (obj->last_write_req != NULL)
179 seq_printf(m, " (%s)",
180 i915_gem_request_get_ring(obj->last_write_req)->name);
181 if (obj->frontbuffer_bits)
182 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
185 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
187 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
188 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
192 static int i915_gem_object_list_info(struct seq_file *m, void *data)
194 struct drm_info_node *node = m->private;
195 uintptr_t list = (uintptr_t) node->info_ent->data;
196 struct list_head *head;
197 struct drm_device *dev = node->minor->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct i915_address_space *vm = &dev_priv->gtt.base;
200 struct i915_vma *vma;
201 size_t total_obj_size, total_gtt_size;
204 ret = mutex_lock_interruptible(&dev->struct_mutex);
208 /* FIXME: the user of this interface might want more than just GGTT */
211 seq_puts(m, "Active:\n");
212 head = &vm->active_list;
215 seq_puts(m, "Inactive:\n");
216 head = &vm->inactive_list;
219 mutex_unlock(&dev->struct_mutex);
223 total_obj_size = total_gtt_size = count = 0;
224 list_for_each_entry(vma, head, mm_list) {
226 describe_obj(m, vma->obj);
228 total_obj_size += vma->obj->base.size;
229 total_gtt_size += vma->node.size;
232 mutex_unlock(&dev->struct_mutex);
234 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
235 count, total_obj_size, total_gtt_size);
239 static int obj_rank_by_stolen(void *priv,
240 struct list_head *A, struct list_head *B)
242 struct drm_i915_gem_object *a =
243 container_of(A, struct drm_i915_gem_object, obj_exec_link);
244 struct drm_i915_gem_object *b =
245 container_of(B, struct drm_i915_gem_object, obj_exec_link);
247 return a->stolen->start - b->stolen->start;
250 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
252 struct drm_info_node *node = m->private;
253 struct drm_device *dev = node->minor->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct drm_i915_gem_object *obj;
256 size_t total_obj_size, total_gtt_size;
260 ret = mutex_lock_interruptible(&dev->struct_mutex);
264 total_obj_size = total_gtt_size = count = 0;
265 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
266 if (obj->stolen == NULL)
269 list_add(&obj->obj_exec_link, &stolen);
271 total_obj_size += obj->base.size;
272 total_gtt_size += i915_gem_obj_ggtt_size(obj);
275 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
276 if (obj->stolen == NULL)
279 list_add(&obj->obj_exec_link, &stolen);
281 total_obj_size += obj->base.size;
284 list_sort(NULL, &stolen, obj_rank_by_stolen);
285 seq_puts(m, "Stolen:\n");
286 while (!list_empty(&stolen)) {
287 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
289 describe_obj(m, obj);
291 list_del_init(&obj->obj_exec_link);
293 mutex_unlock(&dev->struct_mutex);
295 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
296 count, total_obj_size, total_gtt_size);
300 #define count_objects(list, member) do { \
301 list_for_each_entry(obj, list, member) { \
302 size += i915_gem_obj_ggtt_size(obj); \
304 if (obj->map_and_fenceable) { \
305 mappable_size += i915_gem_obj_ggtt_size(obj); \
312 struct drm_i915_file_private *file_priv;
314 size_t total, unbound;
315 size_t global, shared;
316 size_t active, inactive;
319 static int per_file_stats(int id, void *ptr, void *data)
321 struct drm_i915_gem_object *obj = ptr;
322 struct file_stats *stats = data;
323 struct i915_vma *vma;
326 stats->total += obj->base.size;
328 if (obj->base.name || obj->base.dma_buf)
329 stats->shared += obj->base.size;
331 if (USES_FULL_PPGTT(obj->base.dev)) {
332 list_for_each_entry(vma, &obj->vma_list, vma_link) {
333 struct i915_hw_ppgtt *ppgtt;
335 if (!drm_mm_node_allocated(&vma->node))
338 if (i915_is_ggtt(vma->vm)) {
339 stats->global += obj->base.size;
343 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
344 if (ppgtt->file_priv != stats->file_priv)
347 if (obj->active) /* XXX per-vma statistic */
348 stats->active += obj->base.size;
350 stats->inactive += obj->base.size;
355 if (i915_gem_obj_ggtt_bound(obj)) {
356 stats->global += obj->base.size;
358 stats->active += obj->base.size;
360 stats->inactive += obj->base.size;
365 if (!list_empty(&obj->global_list))
366 stats->unbound += obj->base.size;
371 #define print_file_stats(m, name, stats) do { \
373 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
384 static void print_batch_pool_stats(struct seq_file *m,
385 struct drm_i915_private *dev_priv)
387 struct drm_i915_gem_object *obj;
388 struct file_stats stats;
389 struct intel_engine_cs *ring;
392 memset(&stats, 0, sizeof(stats));
394 for_each_ring(ring, dev_priv, i) {
395 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
396 list_for_each_entry(obj,
397 &ring->batch_pool.cache_list[j],
399 per_file_stats(0, obj, &stats);
403 print_file_stats(m, "[k]batch pool", stats);
406 #define count_vmas(list, member) do { \
407 list_for_each_entry(vma, list, member) { \
408 size += i915_gem_obj_ggtt_size(vma->obj); \
410 if (vma->obj->map_and_fenceable) { \
411 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
417 static int i915_gem_object_info(struct seq_file *m, void* data)
419 struct drm_info_node *node = m->private;
420 struct drm_device *dev = node->minor->dev;
421 struct drm_i915_private *dev_priv = dev->dev_private;
422 u32 count, mappable_count, purgeable_count;
423 size_t size, mappable_size, purgeable_size;
424 struct drm_i915_gem_object *obj;
425 struct i915_address_space *vm = &dev_priv->gtt.base;
426 struct drm_file *file;
427 struct i915_vma *vma;
430 ret = mutex_lock_interruptible(&dev->struct_mutex);
434 seq_printf(m, "%u objects, %zu bytes\n",
435 dev_priv->mm.object_count,
436 dev_priv->mm.object_memory);
438 size = count = mappable_size = mappable_count = 0;
439 count_objects(&dev_priv->mm.bound_list, global_list);
440 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
441 count, mappable_count, size, mappable_size);
443 size = count = mappable_size = mappable_count = 0;
444 count_vmas(&vm->active_list, mm_list);
445 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
446 count, mappable_count, size, mappable_size);
448 size = count = mappable_size = mappable_count = 0;
449 count_vmas(&vm->inactive_list, mm_list);
450 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
451 count, mappable_count, size, mappable_size);
453 size = count = purgeable_size = purgeable_count = 0;
454 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
455 size += obj->base.size, ++count;
456 if (obj->madv == I915_MADV_DONTNEED)
457 purgeable_size += obj->base.size, ++purgeable_count;
459 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
461 size = count = mappable_size = mappable_count = 0;
462 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
463 if (obj->fault_mappable) {
464 size += i915_gem_obj_ggtt_size(obj);
467 if (obj->pin_display) {
468 mappable_size += i915_gem_obj_ggtt_size(obj);
471 if (obj->madv == I915_MADV_DONTNEED) {
472 purgeable_size += obj->base.size;
476 seq_printf(m, "%u purgeable objects, %zu bytes\n",
477 purgeable_count, purgeable_size);
478 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
479 mappable_count, mappable_size);
480 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
483 seq_printf(m, "%zu [%lu] gtt total\n",
484 dev_priv->gtt.base.total,
485 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
488 print_batch_pool_stats(m, dev_priv);
489 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
490 struct file_stats stats;
491 struct task_struct *task;
493 memset(&stats, 0, sizeof(stats));
494 stats.file_priv = file->driver_priv;
495 spin_lock(&file->table_lock);
496 idr_for_each(&file->object_idr, per_file_stats, &stats);
497 spin_unlock(&file->table_lock);
499 * Although we have a valid reference on file->pid, that does
500 * not guarantee that the task_struct who called get_pid() is
501 * still alive (e.g. get_pid(current) => fork() => exit()).
502 * Therefore, we need to protect this ->comm access using RCU.
505 task = pid_task(file->pid, PIDTYPE_PID);
506 print_file_stats(m, task ? task->comm : "<unknown>", stats);
510 mutex_unlock(&dev->struct_mutex);
515 static int i915_gem_gtt_info(struct seq_file *m, void *data)
517 struct drm_info_node *node = m->private;
518 struct drm_device *dev = node->minor->dev;
519 uintptr_t list = (uintptr_t) node->info_ent->data;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 struct drm_i915_gem_object *obj;
522 size_t total_obj_size, total_gtt_size;
525 ret = mutex_lock_interruptible(&dev->struct_mutex);
529 total_obj_size = total_gtt_size = count = 0;
530 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
531 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
535 describe_obj(m, obj);
537 total_obj_size += obj->base.size;
538 total_gtt_size += i915_gem_obj_ggtt_size(obj);
542 mutex_unlock(&dev->struct_mutex);
544 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
545 count, total_obj_size, total_gtt_size);
550 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
552 struct drm_info_node *node = m->private;
553 struct drm_device *dev = node->minor->dev;
554 struct drm_i915_private *dev_priv = dev->dev_private;
555 struct intel_crtc *crtc;
558 ret = mutex_lock_interruptible(&dev->struct_mutex);
562 for_each_intel_crtc(dev, crtc) {
563 const char pipe = pipe_name(crtc->pipe);
564 const char plane = plane_name(crtc->plane);
565 struct intel_unpin_work *work;
567 spin_lock_irq(&dev->event_lock);
568 work = crtc->unpin_work;
570 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
575 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
576 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
579 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
582 if (work->flip_queued_req) {
583 struct intel_engine_cs *ring =
584 i915_gem_request_get_ring(work->flip_queued_req);
586 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
588 i915_gem_request_get_seqno(work->flip_queued_req),
589 dev_priv->next_seqno,
590 ring->get_seqno(ring, true),
591 i915_gem_request_completed(work->flip_queued_req, true));
593 seq_printf(m, "Flip not associated with any ring\n");
594 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
595 work->flip_queued_vblank,
596 work->flip_ready_vblank,
597 drm_crtc_vblank_count(&crtc->base));
598 if (work->enable_stall_check)
599 seq_puts(m, "Stall check enabled, ");
601 seq_puts(m, "Stall check waiting for page flip ioctl, ");
602 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
604 if (INTEL_INFO(dev)->gen >= 4)
605 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
607 addr = I915_READ(DSPADDR(crtc->plane));
608 seq_printf(m, "Current scanout address 0x%08x\n", addr);
610 if (work->pending_flip_obj) {
611 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
612 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
615 spin_unlock_irq(&dev->event_lock);
618 mutex_unlock(&dev->struct_mutex);
623 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
625 struct drm_info_node *node = m->private;
626 struct drm_device *dev = node->minor->dev;
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 struct drm_i915_gem_object *obj;
629 struct intel_engine_cs *ring;
633 ret = mutex_lock_interruptible(&dev->struct_mutex);
637 for_each_ring(ring, dev_priv, i) {
638 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
642 list_for_each_entry(obj,
643 &ring->batch_pool.cache_list[j],
646 seq_printf(m, "%s cache[%d]: %d objects\n",
647 ring->name, j, count);
649 list_for_each_entry(obj,
650 &ring->batch_pool.cache_list[j],
653 describe_obj(m, obj);
661 seq_printf(m, "total: %d\n", total);
663 mutex_unlock(&dev->struct_mutex);
668 static int i915_gem_request_info(struct seq_file *m, void *data)
670 struct drm_info_node *node = m->private;
671 struct drm_device *dev = node->minor->dev;
672 struct drm_i915_private *dev_priv = dev->dev_private;
673 struct intel_engine_cs *ring;
674 struct drm_i915_gem_request *req;
677 ret = mutex_lock_interruptible(&dev->struct_mutex);
682 for_each_ring(ring, dev_priv, i) {
686 list_for_each_entry(req, &ring->request_list, list)
691 seq_printf(m, "%s requests: %d\n", ring->name, count);
692 list_for_each_entry(req, &ring->request_list, list) {
693 struct task_struct *task;
698 task = pid_task(req->pid, PIDTYPE_PID);
699 seq_printf(m, " %x @ %d: %s [%d]\n",
701 (int) (jiffies - req->emitted_jiffies),
702 task ? task->comm : "<unknown>",
703 task ? task->pid : -1);
709 mutex_unlock(&dev->struct_mutex);
712 seq_puts(m, "No requests\n");
717 static void i915_ring_seqno_info(struct seq_file *m,
718 struct intel_engine_cs *ring)
720 if (ring->get_seqno) {
721 seq_printf(m, "Current sequence (%s): %x\n",
722 ring->name, ring->get_seqno(ring, false));
726 static int i915_gem_seqno_info(struct seq_file *m, void *data)
728 struct drm_info_node *node = m->private;
729 struct drm_device *dev = node->minor->dev;
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 struct intel_engine_cs *ring;
734 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 intel_runtime_pm_get(dev_priv);
739 for_each_ring(ring, dev_priv, i)
740 i915_ring_seqno_info(m, ring);
742 intel_runtime_pm_put(dev_priv);
743 mutex_unlock(&dev->struct_mutex);
749 static int i915_interrupt_info(struct seq_file *m, void *data)
751 struct drm_info_node *node = m->private;
752 struct drm_device *dev = node->minor->dev;
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 struct intel_engine_cs *ring;
757 ret = mutex_lock_interruptible(&dev->struct_mutex);
760 intel_runtime_pm_get(dev_priv);
762 if (IS_CHERRYVIEW(dev)) {
763 seq_printf(m, "Master Interrupt Control:\t%08x\n",
764 I915_READ(GEN8_MASTER_IRQ));
766 seq_printf(m, "Display IER:\t%08x\n",
768 seq_printf(m, "Display IIR:\t%08x\n",
770 seq_printf(m, "Display IIR_RW:\t%08x\n",
771 I915_READ(VLV_IIR_RW));
772 seq_printf(m, "Display IMR:\t%08x\n",
774 for_each_pipe(dev_priv, pipe)
775 seq_printf(m, "Pipe %c stat:\t%08x\n",
777 I915_READ(PIPESTAT(pipe)));
779 seq_printf(m, "Port hotplug:\t%08x\n",
780 I915_READ(PORT_HOTPLUG_EN));
781 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
782 I915_READ(VLV_DPFLIPSTAT));
783 seq_printf(m, "DPINVGTT:\t%08x\n",
784 I915_READ(DPINVGTT));
786 for (i = 0; i < 4; i++) {
787 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
788 i, I915_READ(GEN8_GT_IMR(i)));
789 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
790 i, I915_READ(GEN8_GT_IIR(i)));
791 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
792 i, I915_READ(GEN8_GT_IER(i)));
795 seq_printf(m, "PCU interrupt mask:\t%08x\n",
796 I915_READ(GEN8_PCU_IMR));
797 seq_printf(m, "PCU interrupt identity:\t%08x\n",
798 I915_READ(GEN8_PCU_IIR));
799 seq_printf(m, "PCU interrupt enable:\t%08x\n",
800 I915_READ(GEN8_PCU_IER));
801 } else if (INTEL_INFO(dev)->gen >= 8) {
802 seq_printf(m, "Master Interrupt Control:\t%08x\n",
803 I915_READ(GEN8_MASTER_IRQ));
805 for (i = 0; i < 4; i++) {
806 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
807 i, I915_READ(GEN8_GT_IMR(i)));
808 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
809 i, I915_READ(GEN8_GT_IIR(i)));
810 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
811 i, I915_READ(GEN8_GT_IER(i)));
814 for_each_pipe(dev_priv, pipe) {
815 if (!intel_display_power_is_enabled(dev_priv,
816 POWER_DOMAIN_PIPE(pipe))) {
817 seq_printf(m, "Pipe %c power disabled\n",
821 seq_printf(m, "Pipe %c IMR:\t%08x\n",
823 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
824 seq_printf(m, "Pipe %c IIR:\t%08x\n",
826 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
827 seq_printf(m, "Pipe %c IER:\t%08x\n",
829 I915_READ(GEN8_DE_PIPE_IER(pipe)));
832 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
833 I915_READ(GEN8_DE_PORT_IMR));
834 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
835 I915_READ(GEN8_DE_PORT_IIR));
836 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
837 I915_READ(GEN8_DE_PORT_IER));
839 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
840 I915_READ(GEN8_DE_MISC_IMR));
841 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
842 I915_READ(GEN8_DE_MISC_IIR));
843 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
844 I915_READ(GEN8_DE_MISC_IER));
846 seq_printf(m, "PCU interrupt mask:\t%08x\n",
847 I915_READ(GEN8_PCU_IMR));
848 seq_printf(m, "PCU interrupt identity:\t%08x\n",
849 I915_READ(GEN8_PCU_IIR));
850 seq_printf(m, "PCU interrupt enable:\t%08x\n",
851 I915_READ(GEN8_PCU_IER));
852 } else if (IS_VALLEYVIEW(dev)) {
853 seq_printf(m, "Display IER:\t%08x\n",
855 seq_printf(m, "Display IIR:\t%08x\n",
857 seq_printf(m, "Display IIR_RW:\t%08x\n",
858 I915_READ(VLV_IIR_RW));
859 seq_printf(m, "Display IMR:\t%08x\n",
861 for_each_pipe(dev_priv, pipe)
862 seq_printf(m, "Pipe %c stat:\t%08x\n",
864 I915_READ(PIPESTAT(pipe)));
866 seq_printf(m, "Master IER:\t%08x\n",
867 I915_READ(VLV_MASTER_IER));
869 seq_printf(m, "Render IER:\t%08x\n",
871 seq_printf(m, "Render IIR:\t%08x\n",
873 seq_printf(m, "Render IMR:\t%08x\n",
876 seq_printf(m, "PM IER:\t\t%08x\n",
877 I915_READ(GEN6_PMIER));
878 seq_printf(m, "PM IIR:\t\t%08x\n",
879 I915_READ(GEN6_PMIIR));
880 seq_printf(m, "PM IMR:\t\t%08x\n",
881 I915_READ(GEN6_PMIMR));
883 seq_printf(m, "Port hotplug:\t%08x\n",
884 I915_READ(PORT_HOTPLUG_EN));
885 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
886 I915_READ(VLV_DPFLIPSTAT));
887 seq_printf(m, "DPINVGTT:\t%08x\n",
888 I915_READ(DPINVGTT));
890 } else if (!HAS_PCH_SPLIT(dev)) {
891 seq_printf(m, "Interrupt enable: %08x\n",
893 seq_printf(m, "Interrupt identity: %08x\n",
895 seq_printf(m, "Interrupt mask: %08x\n",
897 for_each_pipe(dev_priv, pipe)
898 seq_printf(m, "Pipe %c stat: %08x\n",
900 I915_READ(PIPESTAT(pipe)));
902 seq_printf(m, "North Display Interrupt enable: %08x\n",
904 seq_printf(m, "North Display Interrupt identity: %08x\n",
906 seq_printf(m, "North Display Interrupt mask: %08x\n",
908 seq_printf(m, "South Display Interrupt enable: %08x\n",
910 seq_printf(m, "South Display Interrupt identity: %08x\n",
912 seq_printf(m, "South Display Interrupt mask: %08x\n",
914 seq_printf(m, "Graphics Interrupt enable: %08x\n",
916 seq_printf(m, "Graphics Interrupt identity: %08x\n",
918 seq_printf(m, "Graphics Interrupt mask: %08x\n",
921 for_each_ring(ring, dev_priv, i) {
922 if (INTEL_INFO(dev)->gen >= 6) {
924 "Graphics Interrupt mask (%s): %08x\n",
925 ring->name, I915_READ_IMR(ring));
927 i915_ring_seqno_info(m, ring);
929 intel_runtime_pm_put(dev_priv);
930 mutex_unlock(&dev->struct_mutex);
935 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
937 struct drm_info_node *node = m->private;
938 struct drm_device *dev = node->minor->dev;
939 struct drm_i915_private *dev_priv = dev->dev_private;
942 ret = mutex_lock_interruptible(&dev->struct_mutex);
946 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
947 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
948 for (i = 0; i < dev_priv->num_fence_regs; i++) {
949 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
951 seq_printf(m, "Fence %d, pin count = %d, object = ",
952 i, dev_priv->fence_regs[i].pin_count);
954 seq_puts(m, "unused");
956 describe_obj(m, obj);
960 mutex_unlock(&dev->struct_mutex);
964 static int i915_hws_info(struct seq_file *m, void *data)
966 struct drm_info_node *node = m->private;
967 struct drm_device *dev = node->minor->dev;
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 struct intel_engine_cs *ring;
973 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
974 hws = ring->status_page.page_addr;
978 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
979 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
981 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
987 i915_error_state_write(struct file *filp,
988 const char __user *ubuf,
992 struct i915_error_state_file_priv *error_priv = filp->private_data;
993 struct drm_device *dev = error_priv->dev;
996 DRM_DEBUG_DRIVER("Resetting error state\n");
998 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 i915_destroy_error_state(dev);
1003 mutex_unlock(&dev->struct_mutex);
1008 static int i915_error_state_open(struct inode *inode, struct file *file)
1010 struct drm_device *dev = inode->i_private;
1011 struct i915_error_state_file_priv *error_priv;
1013 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1017 error_priv->dev = dev;
1019 i915_error_state_get(dev, error_priv);
1021 file->private_data = error_priv;
1026 static int i915_error_state_release(struct inode *inode, struct file *file)
1028 struct i915_error_state_file_priv *error_priv = file->private_data;
1030 i915_error_state_put(error_priv);
1036 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1037 size_t count, loff_t *pos)
1039 struct i915_error_state_file_priv *error_priv = file->private_data;
1040 struct drm_i915_error_state_buf error_str;
1042 ssize_t ret_count = 0;
1045 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1049 ret = i915_error_state_to_str(&error_str, error_priv);
1053 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1060 *pos = error_str.start + ret_count;
1062 i915_error_state_buf_release(&error_str);
1063 return ret ?: ret_count;
1066 static const struct file_operations i915_error_state_fops = {
1067 .owner = THIS_MODULE,
1068 .open = i915_error_state_open,
1069 .read = i915_error_state_read,
1070 .write = i915_error_state_write,
1071 .llseek = default_llseek,
1072 .release = i915_error_state_release,
1076 i915_next_seqno_get(void *data, u64 *val)
1078 struct drm_device *dev = data;
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1082 ret = mutex_lock_interruptible(&dev->struct_mutex);
1086 *val = dev_priv->next_seqno;
1087 mutex_unlock(&dev->struct_mutex);
1093 i915_next_seqno_set(void *data, u64 val)
1095 struct drm_device *dev = data;
1098 ret = mutex_lock_interruptible(&dev->struct_mutex);
1102 ret = i915_gem_set_seqno(dev, val);
1103 mutex_unlock(&dev->struct_mutex);
1108 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1109 i915_next_seqno_get, i915_next_seqno_set,
1112 static int i915_frequency_info(struct seq_file *m, void *unused)
1114 struct drm_info_node *node = m->private;
1115 struct drm_device *dev = node->minor->dev;
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1119 intel_runtime_pm_get(dev_priv);
1121 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1124 u16 rgvswctl = I915_READ16(MEMSWCTL);
1125 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1127 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1128 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1129 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1131 seq_printf(m, "Current P-state: %d\n",
1132 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1133 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1134 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1135 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1136 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1137 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1138 u32 rpmodectl, rpinclimit, rpdeclimit;
1139 u32 rpstat, cagf, reqf;
1140 u32 rpupei, rpcurup, rpprevup;
1141 u32 rpdownei, rpcurdown, rpprevdown;
1142 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1145 /* RPSTAT1 is in the GT power well */
1146 ret = mutex_lock_interruptible(&dev->struct_mutex);
1150 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1152 reqf = I915_READ(GEN6_RPNSWREQ);
1156 reqf &= ~GEN6_TURBO_DISABLE;
1157 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1162 reqf = intel_gpu_freq(dev_priv, reqf);
1164 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1165 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1166 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1168 rpstat = I915_READ(GEN6_RPSTAT1);
1169 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1170 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1171 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1172 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1173 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1174 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1176 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1177 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1178 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1180 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1181 cagf = intel_gpu_freq(dev_priv, cagf);
1183 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1184 mutex_unlock(&dev->struct_mutex);
1186 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1187 pm_ier = I915_READ(GEN6_PMIER);
1188 pm_imr = I915_READ(GEN6_PMIMR);
1189 pm_isr = I915_READ(GEN6_PMISR);
1190 pm_iir = I915_READ(GEN6_PMIIR);
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1193 pm_ier = I915_READ(GEN8_GT_IER(2));
1194 pm_imr = I915_READ(GEN8_GT_IMR(2));
1195 pm_isr = I915_READ(GEN8_GT_ISR(2));
1196 pm_iir = I915_READ(GEN8_GT_IIR(2));
1197 pm_mask = I915_READ(GEN6_PMINTRMSK);
1199 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1200 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1201 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1202 seq_printf(m, "Render p-state ratio: %d\n",
1203 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1204 seq_printf(m, "Render p-state VID: %d\n",
1205 gt_perf_status & 0xff);
1206 seq_printf(m, "Render p-state limit: %d\n",
1207 rp_state_limits & 0xff);
1208 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1209 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1210 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1211 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1212 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1213 seq_printf(m, "CAGF: %dMHz\n", cagf);
1214 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1215 GEN6_CURICONT_MASK);
1216 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1217 GEN6_CURBSYTAVG_MASK);
1218 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1219 GEN6_CURBSYTAVG_MASK);
1220 seq_printf(m, "Up threshold: %d%%\n",
1221 dev_priv->rps.up_threshold);
1223 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1225 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1226 GEN6_CURBSYTAVG_MASK);
1227 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1228 GEN6_CURBSYTAVG_MASK);
1229 seq_printf(m, "Down threshold: %d%%\n",
1230 dev_priv->rps.down_threshold);
1232 max_freq = (rp_state_cap & 0xff0000) >> 16;
1233 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1234 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1235 intel_gpu_freq(dev_priv, max_freq));
1237 max_freq = (rp_state_cap & 0xff00) >> 8;
1238 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1239 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1240 intel_gpu_freq(dev_priv, max_freq));
1242 max_freq = rp_state_cap & 0xff;
1243 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1244 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1245 intel_gpu_freq(dev_priv, max_freq));
1246 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1247 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1249 seq_printf(m, "Current freq: %d MHz\n",
1250 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1251 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1252 seq_printf(m, "Idle freq: %d MHz\n",
1253 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1254 seq_printf(m, "Min freq: %d MHz\n",
1255 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1256 seq_printf(m, "Max freq: %d MHz\n",
1257 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1259 "efficient (RPe) frequency: %d MHz\n",
1260 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1261 } else if (IS_VALLEYVIEW(dev)) {
1264 mutex_lock(&dev_priv->rps.hw_lock);
1265 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1266 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1267 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1269 seq_printf(m, "actual GPU freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1272 seq_printf(m, "current GPU freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1275 seq_printf(m, "max GPU freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1278 seq_printf(m, "min GPU freq: %d MHz\n",
1279 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281 seq_printf(m, "idle GPU freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1285 "efficient (RPe) frequency: %d MHz\n",
1286 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1287 mutex_unlock(&dev_priv->rps.hw_lock);
1289 seq_puts(m, "no P-state info available\n");
1293 intel_runtime_pm_put(dev_priv);
1297 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1299 struct drm_info_node *node = m->private;
1300 struct drm_device *dev = node->minor->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 struct intel_engine_cs *ring;
1303 u64 acthd[I915_NUM_RINGS];
1304 u32 seqno[I915_NUM_RINGS];
1307 if (!i915.enable_hangcheck) {
1308 seq_printf(m, "Hangcheck disabled\n");
1312 intel_runtime_pm_get(dev_priv);
1314 for_each_ring(ring, dev_priv, i) {
1315 seqno[i] = ring->get_seqno(ring, false);
1316 acthd[i] = intel_ring_get_active_head(ring);
1319 intel_runtime_pm_put(dev_priv);
1321 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1322 seq_printf(m, "Hangcheck active, fires in %dms\n",
1323 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1326 seq_printf(m, "Hangcheck inactive\n");
1328 for_each_ring(ring, dev_priv, i) {
1329 seq_printf(m, "%s:\n", ring->name);
1330 seq_printf(m, "\tseqno = %x [current %x]\n",
1331 ring->hangcheck.seqno, seqno[i]);
1332 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1333 (long long)ring->hangcheck.acthd,
1334 (long long)acthd[i]);
1335 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1336 (long long)ring->hangcheck.max_acthd);
1337 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1338 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1344 static int ironlake_drpc_info(struct seq_file *m)
1346 struct drm_info_node *node = m->private;
1347 struct drm_device *dev = node->minor->dev;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 u32 rgvmodectl, rstdbyctl;
1353 ret = mutex_lock_interruptible(&dev->struct_mutex);
1356 intel_runtime_pm_get(dev_priv);
1358 rgvmodectl = I915_READ(MEMMODECTL);
1359 rstdbyctl = I915_READ(RSTDBYCTL);
1360 crstandvid = I915_READ16(CRSTANDVID);
1362 intel_runtime_pm_put(dev_priv);
1363 mutex_unlock(&dev->struct_mutex);
1365 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1367 seq_printf(m, "Boost freq: %d\n",
1368 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1369 MEMMODE_BOOST_FREQ_SHIFT);
1370 seq_printf(m, "HW control enabled: %s\n",
1371 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1372 seq_printf(m, "SW control enabled: %s\n",
1373 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1374 seq_printf(m, "Gated voltage change: %s\n",
1375 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1376 seq_printf(m, "Starting frequency: P%d\n",
1377 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1378 seq_printf(m, "Max P-state: P%d\n",
1379 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1380 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1381 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1382 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1383 seq_printf(m, "Render standby enabled: %s\n",
1384 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1385 seq_puts(m, "Current RS state: ");
1386 switch (rstdbyctl & RSX_STATUS_MASK) {
1388 seq_puts(m, "on\n");
1390 case RSX_STATUS_RC1:
1391 seq_puts(m, "RC1\n");
1393 case RSX_STATUS_RC1E:
1394 seq_puts(m, "RC1E\n");
1396 case RSX_STATUS_RS1:
1397 seq_puts(m, "RS1\n");
1399 case RSX_STATUS_RS2:
1400 seq_puts(m, "RS2 (RC6)\n");
1402 case RSX_STATUS_RS3:
1403 seq_puts(m, "RC3 (RC6+)\n");
1406 seq_puts(m, "unknown\n");
1413 static int i915_forcewake_domains(struct seq_file *m, void *data)
1415 struct drm_info_node *node = m->private;
1416 struct drm_device *dev = node->minor->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct intel_uncore_forcewake_domain *fw_domain;
1421 spin_lock_irq(&dev_priv->uncore.lock);
1422 for_each_fw_domain(fw_domain, dev_priv, i) {
1423 seq_printf(m, "%s.wake_count = %u\n",
1424 intel_uncore_forcewake_domain_to_str(i),
1425 fw_domain->wake_count);
1427 spin_unlock_irq(&dev_priv->uncore.lock);
1432 static int vlv_drpc_info(struct seq_file *m)
1434 struct drm_info_node *node = m->private;
1435 struct drm_device *dev = node->minor->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 u32 rpmodectl1, rcctl1, pw_status;
1439 intel_runtime_pm_get(dev_priv);
1441 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1442 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1443 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1445 intel_runtime_pm_put(dev_priv);
1447 seq_printf(m, "Video Turbo Mode: %s\n",
1448 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1449 seq_printf(m, "Turbo enabled: %s\n",
1450 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1451 seq_printf(m, "HW control enabled: %s\n",
1452 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1453 seq_printf(m, "SW control enabled: %s\n",
1454 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1455 GEN6_RP_MEDIA_SW_MODE));
1456 seq_printf(m, "RC6 Enabled: %s\n",
1457 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1458 GEN6_RC_CTL_EI_MODE(1))));
1459 seq_printf(m, "Render Power Well: %s\n",
1460 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1461 seq_printf(m, "Media Power Well: %s\n",
1462 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1464 seq_printf(m, "Render RC6 residency since boot: %u\n",
1465 I915_READ(VLV_GT_RENDER_RC6));
1466 seq_printf(m, "Media RC6 residency since boot: %u\n",
1467 I915_READ(VLV_GT_MEDIA_RC6));
1469 return i915_forcewake_domains(m, NULL);
1472 static int gen6_drpc_info(struct seq_file *m)
1474 struct drm_info_node *node = m->private;
1475 struct drm_device *dev = node->minor->dev;
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1477 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1478 unsigned forcewake_count;
1481 ret = mutex_lock_interruptible(&dev->struct_mutex);
1484 intel_runtime_pm_get(dev_priv);
1486 spin_lock_irq(&dev_priv->uncore.lock);
1487 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1488 spin_unlock_irq(&dev_priv->uncore.lock);
1490 if (forcewake_count) {
1491 seq_puts(m, "RC information inaccurate because somebody "
1492 "holds a forcewake reference \n");
1494 /* NB: we cannot use forcewake, else we read the wrong values */
1495 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1497 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1500 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1501 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1503 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1504 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1505 mutex_unlock(&dev->struct_mutex);
1506 mutex_lock(&dev_priv->rps.hw_lock);
1507 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1508 mutex_unlock(&dev_priv->rps.hw_lock);
1510 intel_runtime_pm_put(dev_priv);
1512 seq_printf(m, "Video Turbo Mode: %s\n",
1513 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1514 seq_printf(m, "HW control enabled: %s\n",
1515 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1516 seq_printf(m, "SW control enabled: %s\n",
1517 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1518 GEN6_RP_MEDIA_SW_MODE));
1519 seq_printf(m, "RC1e Enabled: %s\n",
1520 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1521 seq_printf(m, "RC6 Enabled: %s\n",
1522 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1523 seq_printf(m, "Deep RC6 Enabled: %s\n",
1524 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1525 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1526 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1527 seq_puts(m, "Current RC state: ");
1528 switch (gt_core_status & GEN6_RCn_MASK) {
1530 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1531 seq_puts(m, "Core Power Down\n");
1533 seq_puts(m, "on\n");
1536 seq_puts(m, "RC3\n");
1539 seq_puts(m, "RC6\n");
1542 seq_puts(m, "RC7\n");
1545 seq_puts(m, "Unknown\n");
1549 seq_printf(m, "Core Power Down: %s\n",
1550 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1552 /* Not exactly sure what this is */
1553 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1554 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1555 seq_printf(m, "RC6 residency since boot: %u\n",
1556 I915_READ(GEN6_GT_GFX_RC6));
1557 seq_printf(m, "RC6+ residency since boot: %u\n",
1558 I915_READ(GEN6_GT_GFX_RC6p));
1559 seq_printf(m, "RC6++ residency since boot: %u\n",
1560 I915_READ(GEN6_GT_GFX_RC6pp));
1562 seq_printf(m, "RC6 voltage: %dmV\n",
1563 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1564 seq_printf(m, "RC6+ voltage: %dmV\n",
1565 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1566 seq_printf(m, "RC6++ voltage: %dmV\n",
1567 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1571 static int i915_drpc_info(struct seq_file *m, void *unused)
1573 struct drm_info_node *node = m->private;
1574 struct drm_device *dev = node->minor->dev;
1576 if (IS_VALLEYVIEW(dev))
1577 return vlv_drpc_info(m);
1578 else if (INTEL_INFO(dev)->gen >= 6)
1579 return gen6_drpc_info(m);
1581 return ironlake_drpc_info(m);
1584 static int i915_fbc_status(struct seq_file *m, void *unused)
1586 struct drm_info_node *node = m->private;
1587 struct drm_device *dev = node->minor->dev;
1588 struct drm_i915_private *dev_priv = dev->dev_private;
1590 if (!HAS_FBC(dev)) {
1591 seq_puts(m, "FBC unsupported on this chipset\n");
1595 intel_runtime_pm_get(dev_priv);
1597 if (intel_fbc_enabled(dev)) {
1598 seq_puts(m, "FBC enabled\n");
1600 seq_puts(m, "FBC disabled: ");
1601 switch (dev_priv->fbc.no_fbc_reason) {
1603 seq_puts(m, "FBC actived, but currently disabled in hardware");
1605 case FBC_UNSUPPORTED:
1606 seq_puts(m, "unsupported by this chipset");
1609 seq_puts(m, "no outputs");
1611 case FBC_STOLEN_TOO_SMALL:
1612 seq_puts(m, "not enough stolen memory");
1614 case FBC_UNSUPPORTED_MODE:
1615 seq_puts(m, "mode not supported");
1617 case FBC_MODE_TOO_LARGE:
1618 seq_puts(m, "mode too large");
1621 seq_puts(m, "FBC unsupported on plane");
1624 seq_puts(m, "scanout buffer not tiled");
1626 case FBC_MULTIPLE_PIPES:
1627 seq_puts(m, "multiple pipes are enabled");
1629 case FBC_MODULE_PARAM:
1630 seq_puts(m, "disabled per module param (default off)");
1632 case FBC_CHIP_DEFAULT:
1633 seq_puts(m, "disabled per chip default");
1636 seq_puts(m, "unknown reason");
1641 intel_runtime_pm_put(dev_priv);
1646 static int i915_fbc_fc_get(void *data, u64 *val)
1648 struct drm_device *dev = data;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1651 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1654 drm_modeset_lock_all(dev);
1655 *val = dev_priv->fbc.false_color;
1656 drm_modeset_unlock_all(dev);
1661 static int i915_fbc_fc_set(void *data, u64 val)
1663 struct drm_device *dev = data;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1667 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1670 drm_modeset_lock_all(dev);
1672 reg = I915_READ(ILK_DPFC_CONTROL);
1673 dev_priv->fbc.false_color = val;
1675 I915_WRITE(ILK_DPFC_CONTROL, val ?
1676 (reg | FBC_CTL_FALSE_COLOR) :
1677 (reg & ~FBC_CTL_FALSE_COLOR));
1679 drm_modeset_unlock_all(dev);
1683 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1684 i915_fbc_fc_get, i915_fbc_fc_set,
1687 static int i915_ips_status(struct seq_file *m, void *unused)
1689 struct drm_info_node *node = m->private;
1690 struct drm_device *dev = node->minor->dev;
1691 struct drm_i915_private *dev_priv = dev->dev_private;
1693 if (!HAS_IPS(dev)) {
1694 seq_puts(m, "not supported\n");
1698 intel_runtime_pm_get(dev_priv);
1700 seq_printf(m, "Enabled by kernel parameter: %s\n",
1701 yesno(i915.enable_ips));
1703 if (INTEL_INFO(dev)->gen >= 8) {
1704 seq_puts(m, "Currently: unknown\n");
1706 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1707 seq_puts(m, "Currently: enabled\n");
1709 seq_puts(m, "Currently: disabled\n");
1712 intel_runtime_pm_put(dev_priv);
1717 static int i915_sr_status(struct seq_file *m, void *unused)
1719 struct drm_info_node *node = m->private;
1720 struct drm_device *dev = node->minor->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 bool sr_enabled = false;
1724 intel_runtime_pm_get(dev_priv);
1726 if (HAS_PCH_SPLIT(dev))
1727 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1728 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1729 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1730 else if (IS_I915GM(dev))
1731 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1732 else if (IS_PINEVIEW(dev))
1733 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1735 intel_runtime_pm_put(dev_priv);
1737 seq_printf(m, "self-refresh: %s\n",
1738 sr_enabled ? "enabled" : "disabled");
1743 static int i915_emon_status(struct seq_file *m, void *unused)
1745 struct drm_info_node *node = m->private;
1746 struct drm_device *dev = node->minor->dev;
1747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 unsigned long temp, chipset, gfx;
1754 ret = mutex_lock_interruptible(&dev->struct_mutex);
1758 temp = i915_mch_val(dev_priv);
1759 chipset = i915_chipset_val(dev_priv);
1760 gfx = i915_gfx_val(dev_priv);
1761 mutex_unlock(&dev->struct_mutex);
1763 seq_printf(m, "GMCH temp: %ld\n", temp);
1764 seq_printf(m, "Chipset power: %ld\n", chipset);
1765 seq_printf(m, "GFX power: %ld\n", gfx);
1766 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1771 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1773 struct drm_info_node *node = m->private;
1774 struct drm_device *dev = node->minor->dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
1777 int gpu_freq, ia_freq;
1779 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1780 seq_puts(m, "unsupported on this chipset\n");
1784 intel_runtime_pm_get(dev_priv);
1786 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1788 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1792 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1794 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1795 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1798 sandybridge_pcode_read(dev_priv,
1799 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1801 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1802 intel_gpu_freq(dev_priv, gpu_freq),
1803 ((ia_freq >> 0) & 0xff) * 100,
1804 ((ia_freq >> 8) & 0xff) * 100);
1807 mutex_unlock(&dev_priv->rps.hw_lock);
1810 intel_runtime_pm_put(dev_priv);
1814 static int i915_opregion(struct seq_file *m, void *unused)
1816 struct drm_info_node *node = m->private;
1817 struct drm_device *dev = node->minor->dev;
1818 struct drm_i915_private *dev_priv = dev->dev_private;
1819 struct intel_opregion *opregion = &dev_priv->opregion;
1820 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1826 ret = mutex_lock_interruptible(&dev->struct_mutex);
1830 if (opregion->header) {
1831 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1832 seq_write(m, data, OPREGION_SIZE);
1835 mutex_unlock(&dev->struct_mutex);
1842 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1844 struct drm_info_node *node = m->private;
1845 struct drm_device *dev = node->minor->dev;
1846 struct intel_fbdev *ifbdev = NULL;
1847 struct intel_framebuffer *fb;
1849 #ifdef CONFIG_DRM_I915_FBDEV
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1852 ifbdev = dev_priv->fbdev;
1853 fb = to_intel_framebuffer(ifbdev->helper.fb);
1855 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1859 fb->base.bits_per_pixel,
1860 fb->base.modifier[0],
1861 atomic_read(&fb->base.refcount.refcount));
1862 describe_obj(m, fb->obj);
1866 mutex_lock(&dev->mode_config.fb_lock);
1867 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1868 if (ifbdev && &fb->base == ifbdev->helper.fb)
1871 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1875 fb->base.bits_per_pixel,
1876 fb->base.modifier[0],
1877 atomic_read(&fb->base.refcount.refcount));
1878 describe_obj(m, fb->obj);
1881 mutex_unlock(&dev->mode_config.fb_lock);
1886 static void describe_ctx_ringbuf(struct seq_file *m,
1887 struct intel_ringbuffer *ringbuf)
1889 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1890 ringbuf->space, ringbuf->head, ringbuf->tail,
1891 ringbuf->last_retired_head);
1894 static int i915_context_status(struct seq_file *m, void *unused)
1896 struct drm_info_node *node = m->private;
1897 struct drm_device *dev = node->minor->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_engine_cs *ring;
1900 struct intel_context *ctx;
1903 ret = mutex_lock_interruptible(&dev->struct_mutex);
1907 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1908 if (!i915.enable_execlists &&
1909 ctx->legacy_hw_ctx.rcs_state == NULL)
1912 seq_puts(m, "HW context ");
1913 describe_ctx(m, ctx);
1914 for_each_ring(ring, dev_priv, i) {
1915 if (ring->default_context == ctx)
1916 seq_printf(m, "(default context %s) ",
1920 if (i915.enable_execlists) {
1922 for_each_ring(ring, dev_priv, i) {
1923 struct drm_i915_gem_object *ctx_obj =
1924 ctx->engine[i].state;
1925 struct intel_ringbuffer *ringbuf =
1926 ctx->engine[i].ringbuf;
1928 seq_printf(m, "%s: ", ring->name);
1930 describe_obj(m, ctx_obj);
1932 describe_ctx_ringbuf(m, ringbuf);
1936 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1942 mutex_unlock(&dev->struct_mutex);
1947 static void i915_dump_lrc_obj(struct seq_file *m,
1948 struct intel_engine_cs *ring,
1949 struct drm_i915_gem_object *ctx_obj)
1952 uint32_t *reg_state;
1954 unsigned long ggtt_offset = 0;
1956 if (ctx_obj == NULL) {
1957 seq_printf(m, "Context on %s with no gem object\n",
1962 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1963 intel_execlists_ctx_id(ctx_obj));
1965 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1966 seq_puts(m, "\tNot bound in GGTT\n");
1968 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1970 if (i915_gem_object_get_pages(ctx_obj)) {
1971 seq_puts(m, "\tFailed to get pages for context object\n");
1975 page = i915_gem_object_get_page(ctx_obj, 1);
1976 if (!WARN_ON(page == NULL)) {
1977 reg_state = kmap_atomic(page);
1979 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1980 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1981 ggtt_offset + 4096 + (j * 4),
1982 reg_state[j], reg_state[j + 1],
1983 reg_state[j + 2], reg_state[j + 3]);
1985 kunmap_atomic(reg_state);
1991 static int i915_dump_lrc(struct seq_file *m, void *unused)
1993 struct drm_info_node *node = (struct drm_info_node *) m->private;
1994 struct drm_device *dev = node->minor->dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_engine_cs *ring;
1997 struct intel_context *ctx;
2000 if (!i915.enable_execlists) {
2001 seq_printf(m, "Logical Ring Contexts are disabled\n");
2005 ret = mutex_lock_interruptible(&dev->struct_mutex);
2009 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2010 for_each_ring(ring, dev_priv, i) {
2011 if (ring->default_context != ctx)
2012 i915_dump_lrc_obj(m, ring,
2013 ctx->engine[i].state);
2017 mutex_unlock(&dev->struct_mutex);
2022 static int i915_execlists(struct seq_file *m, void *data)
2024 struct drm_info_node *node = (struct drm_info_node *)m->private;
2025 struct drm_device *dev = node->minor->dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027 struct intel_engine_cs *ring;
2033 struct list_head *cursor;
2037 if (!i915.enable_execlists) {
2038 seq_puts(m, "Logical Ring Contexts are disabled\n");
2042 ret = mutex_lock_interruptible(&dev->struct_mutex);
2046 intel_runtime_pm_get(dev_priv);
2048 for_each_ring(ring, dev_priv, ring_id) {
2049 struct drm_i915_gem_request *head_req = NULL;
2051 unsigned long flags;
2053 seq_printf(m, "%s\n", ring->name);
2055 status = I915_READ(RING_EXECLIST_STATUS(ring));
2056 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2057 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2060 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2061 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2063 read_pointer = ring->next_context_status_buffer;
2064 write_pointer = status_pointer & 0x07;
2065 if (read_pointer > write_pointer)
2067 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2068 read_pointer, write_pointer);
2070 for (i = 0; i < 6; i++) {
2071 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2072 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2074 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2078 spin_lock_irqsave(&ring->execlist_lock, flags);
2079 list_for_each(cursor, &ring->execlist_queue)
2081 head_req = list_first_entry_or_null(&ring->execlist_queue,
2082 struct drm_i915_gem_request, execlist_link);
2083 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2085 seq_printf(m, "\t%d requests in queue\n", count);
2087 struct drm_i915_gem_object *ctx_obj;
2089 ctx_obj = head_req->ctx->engine[ring_id].state;
2090 seq_printf(m, "\tHead request id: %u\n",
2091 intel_execlists_ctx_id(ctx_obj));
2092 seq_printf(m, "\tHead request tail: %u\n",
2099 intel_runtime_pm_put(dev_priv);
2100 mutex_unlock(&dev->struct_mutex);
2105 static const char *swizzle_string(unsigned swizzle)
2108 case I915_BIT_6_SWIZZLE_NONE:
2110 case I915_BIT_6_SWIZZLE_9:
2112 case I915_BIT_6_SWIZZLE_9_10:
2113 return "bit9/bit10";
2114 case I915_BIT_6_SWIZZLE_9_11:
2115 return "bit9/bit11";
2116 case I915_BIT_6_SWIZZLE_9_10_11:
2117 return "bit9/bit10/bit11";
2118 case I915_BIT_6_SWIZZLE_9_17:
2119 return "bit9/bit17";
2120 case I915_BIT_6_SWIZZLE_9_10_17:
2121 return "bit9/bit10/bit17";
2122 case I915_BIT_6_SWIZZLE_UNKNOWN:
2129 static int i915_swizzle_info(struct seq_file *m, void *data)
2131 struct drm_info_node *node = m->private;
2132 struct drm_device *dev = node->minor->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2136 ret = mutex_lock_interruptible(&dev->struct_mutex);
2139 intel_runtime_pm_get(dev_priv);
2141 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2142 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2143 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2144 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2146 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2147 seq_printf(m, "DDC = 0x%08x\n",
2149 seq_printf(m, "DDC2 = 0x%08x\n",
2151 seq_printf(m, "C0DRB3 = 0x%04x\n",
2152 I915_READ16(C0DRB3));
2153 seq_printf(m, "C1DRB3 = 0x%04x\n",
2154 I915_READ16(C1DRB3));
2155 } else if (INTEL_INFO(dev)->gen >= 6) {
2156 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2157 I915_READ(MAD_DIMM_C0));
2158 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2159 I915_READ(MAD_DIMM_C1));
2160 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2161 I915_READ(MAD_DIMM_C2));
2162 seq_printf(m, "TILECTL = 0x%08x\n",
2163 I915_READ(TILECTL));
2164 if (INTEL_INFO(dev)->gen >= 8)
2165 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2166 I915_READ(GAMTARBMODE));
2168 seq_printf(m, "ARB_MODE = 0x%08x\n",
2169 I915_READ(ARB_MODE));
2170 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2171 I915_READ(DISP_ARB_CTL));
2174 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2175 seq_puts(m, "L-shaped memory detected\n");
2177 intel_runtime_pm_put(dev_priv);
2178 mutex_unlock(&dev->struct_mutex);
2183 static int per_file_ctx(int id, void *ptr, void *data)
2185 struct intel_context *ctx = ptr;
2186 struct seq_file *m = data;
2187 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2190 seq_printf(m, " no ppgtt for context %d\n",
2195 if (i915_gem_context_is_default(ctx))
2196 seq_puts(m, " default context:\n");
2198 seq_printf(m, " context %d:\n", ctx->user_handle);
2199 ppgtt->debug_dump(ppgtt, m);
2204 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2206 struct drm_i915_private *dev_priv = dev->dev_private;
2207 struct intel_engine_cs *ring;
2208 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2214 for_each_ring(ring, dev_priv, unused) {
2215 seq_printf(m, "%s\n", ring->name);
2216 for (i = 0; i < 4; i++) {
2217 u32 offset = 0x270 + i * 8;
2218 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2220 pdp |= I915_READ(ring->mmio_base + offset);
2221 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2226 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 struct intel_engine_cs *ring;
2230 struct drm_file *file;
2233 if (INTEL_INFO(dev)->gen == 6)
2234 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2236 for_each_ring(ring, dev_priv, i) {
2237 seq_printf(m, "%s\n", ring->name);
2238 if (INTEL_INFO(dev)->gen == 7)
2239 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2240 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2241 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2242 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2244 if (dev_priv->mm.aliasing_ppgtt) {
2245 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2247 seq_puts(m, "aliasing PPGTT:\n");
2248 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
2250 ppgtt->debug_dump(ppgtt, m);
2253 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2254 struct drm_i915_file_private *file_priv = file->driver_priv;
2256 seq_printf(m, "proc: %s\n",
2257 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2258 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2260 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2263 static int i915_ppgtt_info(struct seq_file *m, void *data)
2265 struct drm_info_node *node = m->private;
2266 struct drm_device *dev = node->minor->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2269 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2272 intel_runtime_pm_get(dev_priv);
2274 if (INTEL_INFO(dev)->gen >= 8)
2275 gen8_ppgtt_info(m, dev);
2276 else if (INTEL_INFO(dev)->gen >= 6)
2277 gen6_ppgtt_info(m, dev);
2279 intel_runtime_pm_put(dev_priv);
2280 mutex_unlock(&dev->struct_mutex);
2285 static int i915_rps_boost_info(struct seq_file *m, void *data)
2287 struct drm_info_node *node = m->private;
2288 struct drm_device *dev = node->minor->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct drm_file *file;
2293 ret = mutex_lock_interruptible(&dev->struct_mutex);
2297 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2301 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2302 struct drm_i915_file_private *file_priv = file->driver_priv;
2303 struct task_struct *task;
2306 task = pid_task(file->pid, PIDTYPE_PID);
2307 seq_printf(m, "%s [%d]: %d boosts%s\n",
2308 task ? task->comm : "<unknown>",
2309 task ? task->pid : -1,
2310 file_priv->rps_boosts,
2311 list_empty(&file_priv->rps_boost) ? "" : ", active");
2314 seq_printf(m, "Semaphore boosts: %d\n", dev_priv->rps.semaphores.rps_boosts);
2315 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2317 mutex_unlock(&dev_priv->rps.hw_lock);
2319 mutex_unlock(&dev->struct_mutex);
2324 static int i915_llc(struct seq_file *m, void *data)
2326 struct drm_info_node *node = m->private;
2327 struct drm_device *dev = node->minor->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2330 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2331 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2332 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2337 static int i915_edp_psr_status(struct seq_file *m, void *data)
2339 struct drm_info_node *node = m->private;
2340 struct drm_device *dev = node->minor->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2345 bool enabled = false;
2347 if (!HAS_PSR(dev)) {
2348 seq_puts(m, "PSR not supported\n");
2352 intel_runtime_pm_get(dev_priv);
2354 mutex_lock(&dev_priv->psr.lock);
2355 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2356 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2357 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2358 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2359 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2360 dev_priv->psr.busy_frontbuffer_bits);
2361 seq_printf(m, "Re-enable work scheduled: %s\n",
2362 yesno(work_busy(&dev_priv->psr.work.work)));
2365 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2367 for_each_pipe(dev_priv, pipe) {
2368 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2369 VLV_EDP_PSR_CURR_STATE_MASK;
2370 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2371 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2375 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2378 for_each_pipe(dev_priv, pipe) {
2379 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2380 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2381 seq_printf(m, " pipe %c", pipe_name(pipe));
2385 /* CHV PSR has no kind of performance counter */
2387 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2388 EDP_PSR_PERF_CNT_MASK;
2390 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2392 mutex_unlock(&dev_priv->psr.lock);
2394 intel_runtime_pm_put(dev_priv);
2398 static int i915_sink_crc(struct seq_file *m, void *data)
2400 struct drm_info_node *node = m->private;
2401 struct drm_device *dev = node->minor->dev;
2402 struct intel_encoder *encoder;
2403 struct intel_connector *connector;
2404 struct intel_dp *intel_dp = NULL;
2408 drm_modeset_lock_all(dev);
2409 for_each_intel_connector(dev, connector) {
2411 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2414 if (!connector->base.encoder)
2417 encoder = to_intel_encoder(connector->base.encoder);
2418 if (encoder->type != INTEL_OUTPUT_EDP)
2421 intel_dp = enc_to_intel_dp(&encoder->base);
2423 ret = intel_dp_sink_crc(intel_dp, crc);
2427 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2428 crc[0], crc[1], crc[2],
2429 crc[3], crc[4], crc[5]);
2434 drm_modeset_unlock_all(dev);
2438 static int i915_energy_uJ(struct seq_file *m, void *data)
2440 struct drm_info_node *node = m->private;
2441 struct drm_device *dev = node->minor->dev;
2442 struct drm_i915_private *dev_priv = dev->dev_private;
2446 if (INTEL_INFO(dev)->gen < 6)
2449 intel_runtime_pm_get(dev_priv);
2451 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2452 power = (power & 0x1f00) >> 8;
2453 units = 1000000 / (1 << power); /* convert to uJ */
2454 power = I915_READ(MCH_SECP_NRG_STTS);
2457 intel_runtime_pm_put(dev_priv);
2459 seq_printf(m, "%llu", (long long unsigned)power);
2464 static int i915_pc8_status(struct seq_file *m, void *unused)
2466 struct drm_info_node *node = m->private;
2467 struct drm_device *dev = node->minor->dev;
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2470 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2471 seq_puts(m, "not supported\n");
2475 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2476 seq_printf(m, "IRQs disabled: %s\n",
2477 yesno(!intel_irqs_enabled(dev_priv)));
2482 static const char *power_domain_str(enum intel_display_power_domain domain)
2485 case POWER_DOMAIN_PIPE_A:
2487 case POWER_DOMAIN_PIPE_B:
2489 case POWER_DOMAIN_PIPE_C:
2491 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2492 return "PIPE_A_PANEL_FITTER";
2493 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2494 return "PIPE_B_PANEL_FITTER";
2495 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2496 return "PIPE_C_PANEL_FITTER";
2497 case POWER_DOMAIN_TRANSCODER_A:
2498 return "TRANSCODER_A";
2499 case POWER_DOMAIN_TRANSCODER_B:
2500 return "TRANSCODER_B";
2501 case POWER_DOMAIN_TRANSCODER_C:
2502 return "TRANSCODER_C";
2503 case POWER_DOMAIN_TRANSCODER_EDP:
2504 return "TRANSCODER_EDP";
2505 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2506 return "PORT_DDI_A_2_LANES";
2507 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2508 return "PORT_DDI_A_4_LANES";
2509 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2510 return "PORT_DDI_B_2_LANES";
2511 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2512 return "PORT_DDI_B_4_LANES";
2513 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2514 return "PORT_DDI_C_2_LANES";
2515 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2516 return "PORT_DDI_C_4_LANES";
2517 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2518 return "PORT_DDI_D_2_LANES";
2519 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2520 return "PORT_DDI_D_4_LANES";
2521 case POWER_DOMAIN_PORT_DSI:
2523 case POWER_DOMAIN_PORT_CRT:
2525 case POWER_DOMAIN_PORT_OTHER:
2526 return "PORT_OTHER";
2527 case POWER_DOMAIN_VGA:
2529 case POWER_DOMAIN_AUDIO:
2531 case POWER_DOMAIN_PLLS:
2533 case POWER_DOMAIN_AUX_A:
2535 case POWER_DOMAIN_AUX_B:
2537 case POWER_DOMAIN_AUX_C:
2539 case POWER_DOMAIN_AUX_D:
2541 case POWER_DOMAIN_INIT:
2544 MISSING_CASE(domain);
2549 static int i915_power_domain_info(struct seq_file *m, void *unused)
2551 struct drm_info_node *node = m->private;
2552 struct drm_device *dev = node->minor->dev;
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2557 mutex_lock(&power_domains->lock);
2559 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2560 for (i = 0; i < power_domains->power_well_count; i++) {
2561 struct i915_power_well *power_well;
2562 enum intel_display_power_domain power_domain;
2564 power_well = &power_domains->power_wells[i];
2565 seq_printf(m, "%-25s %d\n", power_well->name,
2568 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2570 if (!(BIT(power_domain) & power_well->domains))
2573 seq_printf(m, " %-23s %d\n",
2574 power_domain_str(power_domain),
2575 power_domains->domain_use_count[power_domain]);
2579 mutex_unlock(&power_domains->lock);
2584 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2585 struct drm_display_mode *mode)
2589 for (i = 0; i < tabs; i++)
2592 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2593 mode->base.id, mode->name,
2594 mode->vrefresh, mode->clock,
2595 mode->hdisplay, mode->hsync_start,
2596 mode->hsync_end, mode->htotal,
2597 mode->vdisplay, mode->vsync_start,
2598 mode->vsync_end, mode->vtotal,
2599 mode->type, mode->flags);
2602 static void intel_encoder_info(struct seq_file *m,
2603 struct intel_crtc *intel_crtc,
2604 struct intel_encoder *intel_encoder)
2606 struct drm_info_node *node = m->private;
2607 struct drm_device *dev = node->minor->dev;
2608 struct drm_crtc *crtc = &intel_crtc->base;
2609 struct intel_connector *intel_connector;
2610 struct drm_encoder *encoder;
2612 encoder = &intel_encoder->base;
2613 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2614 encoder->base.id, encoder->name);
2615 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2616 struct drm_connector *connector = &intel_connector->base;
2617 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2620 drm_get_connector_status_name(connector->status));
2621 if (connector->status == connector_status_connected) {
2622 struct drm_display_mode *mode = &crtc->mode;
2623 seq_printf(m, ", mode:\n");
2624 intel_seq_print_mode(m, 2, mode);
2631 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2633 struct drm_info_node *node = m->private;
2634 struct drm_device *dev = node->minor->dev;
2635 struct drm_crtc *crtc = &intel_crtc->base;
2636 struct intel_encoder *intel_encoder;
2638 if (crtc->primary->fb)
2639 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2640 crtc->primary->fb->base.id, crtc->x, crtc->y,
2641 crtc->primary->fb->width, crtc->primary->fb->height);
2643 seq_puts(m, "\tprimary plane disabled\n");
2644 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2645 intel_encoder_info(m, intel_crtc, intel_encoder);
2648 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2650 struct drm_display_mode *mode = panel->fixed_mode;
2652 seq_printf(m, "\tfixed mode:\n");
2653 intel_seq_print_mode(m, 2, mode);
2656 static void intel_dp_info(struct seq_file *m,
2657 struct intel_connector *intel_connector)
2659 struct intel_encoder *intel_encoder = intel_connector->encoder;
2660 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2662 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2663 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2665 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2666 intel_panel_info(m, &intel_connector->panel);
2669 static void intel_hdmi_info(struct seq_file *m,
2670 struct intel_connector *intel_connector)
2672 struct intel_encoder *intel_encoder = intel_connector->encoder;
2673 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2675 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2679 static void intel_lvds_info(struct seq_file *m,
2680 struct intel_connector *intel_connector)
2682 intel_panel_info(m, &intel_connector->panel);
2685 static void intel_connector_info(struct seq_file *m,
2686 struct drm_connector *connector)
2688 struct intel_connector *intel_connector = to_intel_connector(connector);
2689 struct intel_encoder *intel_encoder = intel_connector->encoder;
2690 struct drm_display_mode *mode;
2692 seq_printf(m, "connector %d: type %s, status: %s\n",
2693 connector->base.id, connector->name,
2694 drm_get_connector_status_name(connector->status));
2695 if (connector->status == connector_status_connected) {
2696 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2697 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2698 connector->display_info.width_mm,
2699 connector->display_info.height_mm);
2700 seq_printf(m, "\tsubpixel order: %s\n",
2701 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2702 seq_printf(m, "\tCEA rev: %d\n",
2703 connector->display_info.cea_rev);
2705 if (intel_encoder) {
2706 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2707 intel_encoder->type == INTEL_OUTPUT_EDP)
2708 intel_dp_info(m, intel_connector);
2709 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2710 intel_hdmi_info(m, intel_connector);
2711 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2712 intel_lvds_info(m, intel_connector);
2715 seq_printf(m, "\tmodes:\n");
2716 list_for_each_entry(mode, &connector->modes, head)
2717 intel_seq_print_mode(m, 2, mode);
2720 static bool cursor_active(struct drm_device *dev, int pipe)
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2725 if (IS_845G(dev) || IS_I865G(dev))
2726 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2728 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2733 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2738 pos = I915_READ(CURPOS(pipe));
2740 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2741 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2744 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2745 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2748 return cursor_active(dev, pipe);
2751 static int i915_display_info(struct seq_file *m, void *unused)
2753 struct drm_info_node *node = m->private;
2754 struct drm_device *dev = node->minor->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *crtc;
2757 struct drm_connector *connector;
2759 intel_runtime_pm_get(dev_priv);
2760 drm_modeset_lock_all(dev);
2761 seq_printf(m, "CRTC info\n");
2762 seq_printf(m, "---------\n");
2763 for_each_intel_crtc(dev, crtc) {
2767 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2768 crtc->base.base.id, pipe_name(crtc->pipe),
2769 yesno(crtc->active), crtc->config->pipe_src_w,
2770 crtc->config->pipe_src_h);
2772 intel_crtc_info(m, crtc);
2774 active = cursor_position(dev, crtc->pipe, &x, &y);
2775 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2776 yesno(crtc->cursor_base),
2777 x, y, crtc->base.cursor->state->crtc_w,
2778 crtc->base.cursor->state->crtc_h,
2779 crtc->cursor_addr, yesno(active));
2782 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2783 yesno(!crtc->cpu_fifo_underrun_disabled),
2784 yesno(!crtc->pch_fifo_underrun_disabled));
2787 seq_printf(m, "\n");
2788 seq_printf(m, "Connector info\n");
2789 seq_printf(m, "--------------\n");
2790 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2791 intel_connector_info(m, connector);
2793 drm_modeset_unlock_all(dev);
2794 intel_runtime_pm_put(dev_priv);
2799 static int i915_semaphore_status(struct seq_file *m, void *unused)
2801 struct drm_info_node *node = (struct drm_info_node *) m->private;
2802 struct drm_device *dev = node->minor->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_engine_cs *ring;
2805 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2808 if (!i915_semaphore_is_enabled(dev)) {
2809 seq_puts(m, "Semaphores are disabled\n");
2813 ret = mutex_lock_interruptible(&dev->struct_mutex);
2816 intel_runtime_pm_get(dev_priv);
2818 if (IS_BROADWELL(dev)) {
2822 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2824 seqno = (uint64_t *)kmap_atomic(page);
2825 for_each_ring(ring, dev_priv, i) {
2828 seq_printf(m, "%s\n", ring->name);
2830 seq_puts(m, " Last signal:");
2831 for (j = 0; j < num_rings; j++) {
2832 offset = i * I915_NUM_RINGS + j;
2833 seq_printf(m, "0x%08llx (0x%02llx) ",
2834 seqno[offset], offset * 8);
2838 seq_puts(m, " Last wait: ");
2839 for (j = 0; j < num_rings; j++) {
2840 offset = i + (j * I915_NUM_RINGS);
2841 seq_printf(m, "0x%08llx (0x%02llx) ",
2842 seqno[offset], offset * 8);
2847 kunmap_atomic(seqno);
2849 seq_puts(m, " Last signal:");
2850 for_each_ring(ring, dev_priv, i)
2851 for (j = 0; j < num_rings; j++)
2852 seq_printf(m, "0x%08x\n",
2853 I915_READ(ring->semaphore.mbox.signal[j]));
2857 seq_puts(m, "\nSync seqno:\n");
2858 for_each_ring(ring, dev_priv, i) {
2859 for (j = 0; j < num_rings; j++) {
2860 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2866 intel_runtime_pm_put(dev_priv);
2867 mutex_unlock(&dev->struct_mutex);
2871 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2873 struct drm_info_node *node = (struct drm_info_node *) m->private;
2874 struct drm_device *dev = node->minor->dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2878 drm_modeset_lock_all(dev);
2879 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2880 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2882 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2883 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2884 pll->config.crtc_mask, pll->active, yesno(pll->on));
2885 seq_printf(m, " tracked hardware state:\n");
2886 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2887 seq_printf(m, " dpll_md: 0x%08x\n",
2888 pll->config.hw_state.dpll_md);
2889 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2890 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2891 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2893 drm_modeset_unlock_all(dev);
2898 static int i915_wa_registers(struct seq_file *m, void *unused)
2902 struct drm_info_node *node = (struct drm_info_node *) m->private;
2903 struct drm_device *dev = node->minor->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2906 ret = mutex_lock_interruptible(&dev->struct_mutex);
2910 intel_runtime_pm_get(dev_priv);
2912 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2913 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2914 u32 addr, mask, value, read;
2917 addr = dev_priv->workarounds.reg[i].addr;
2918 mask = dev_priv->workarounds.reg[i].mask;
2919 value = dev_priv->workarounds.reg[i].value;
2920 read = I915_READ(addr);
2921 ok = (value & mask) == (read & mask);
2922 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2923 addr, value, mask, read, ok ? "OK" : "FAIL");
2926 intel_runtime_pm_put(dev_priv);
2927 mutex_unlock(&dev->struct_mutex);
2932 static int i915_ddb_info(struct seq_file *m, void *unused)
2934 struct drm_info_node *node = m->private;
2935 struct drm_device *dev = node->minor->dev;
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 struct skl_ddb_allocation *ddb;
2938 struct skl_ddb_entry *entry;
2942 if (INTEL_INFO(dev)->gen < 9)
2945 drm_modeset_lock_all(dev);
2947 ddb = &dev_priv->wm.skl_hw.ddb;
2949 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2951 for_each_pipe(dev_priv, pipe) {
2952 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2954 for_each_plane(dev_priv, pipe, plane) {
2955 entry = &ddb->plane[pipe][plane];
2956 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2957 entry->start, entry->end,
2958 skl_ddb_entry_size(entry));
2961 entry = &ddb->cursor[pipe];
2962 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2963 entry->end, skl_ddb_entry_size(entry));
2966 drm_modeset_unlock_all(dev);
2971 static void drrs_status_per_crtc(struct seq_file *m,
2972 struct drm_device *dev, struct intel_crtc *intel_crtc)
2974 struct intel_encoder *intel_encoder;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 struct i915_drrs *drrs = &dev_priv->drrs;
2979 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2980 /* Encoder connected on this CRTC */
2981 switch (intel_encoder->type) {
2982 case INTEL_OUTPUT_EDP:
2983 seq_puts(m, "eDP:\n");
2985 case INTEL_OUTPUT_DSI:
2986 seq_puts(m, "DSI:\n");
2988 case INTEL_OUTPUT_HDMI:
2989 seq_puts(m, "HDMI:\n");
2991 case INTEL_OUTPUT_DISPLAYPORT:
2992 seq_puts(m, "DP:\n");
2995 seq_printf(m, "Other encoder (id=%d).\n",
2996 intel_encoder->type);
3001 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3002 seq_puts(m, "\tVBT: DRRS_type: Static");
3003 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3004 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3005 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3006 seq_puts(m, "\tVBT: DRRS_type: None");
3008 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3010 seq_puts(m, "\n\n");
3012 if (intel_crtc->config->has_drrs) {
3013 struct intel_panel *panel;
3015 mutex_lock(&drrs->mutex);
3016 /* DRRS Supported */
3017 seq_puts(m, "\tDRRS Supported: Yes\n");
3019 /* disable_drrs() will make drrs->dp NULL */
3021 seq_puts(m, "Idleness DRRS: Disabled");
3022 mutex_unlock(&drrs->mutex);
3026 panel = &drrs->dp->attached_connector->panel;
3027 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3028 drrs->busy_frontbuffer_bits);
3030 seq_puts(m, "\n\t\t");
3031 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3032 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3033 vrefresh = panel->fixed_mode->vrefresh;
3034 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3035 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3036 vrefresh = panel->downclock_mode->vrefresh;
3038 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3039 drrs->refresh_rate_type);
3040 mutex_unlock(&drrs->mutex);
3043 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3045 seq_puts(m, "\n\t\t");
3046 mutex_unlock(&drrs->mutex);
3048 /* DRRS not supported. Print the VBT parameter*/
3049 seq_puts(m, "\tDRRS Supported : No");
3054 static int i915_drrs_status(struct seq_file *m, void *unused)
3056 struct drm_info_node *node = m->private;
3057 struct drm_device *dev = node->minor->dev;
3058 struct intel_crtc *intel_crtc;
3059 int active_crtc_cnt = 0;
3061 for_each_intel_crtc(dev, intel_crtc) {
3062 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3064 if (intel_crtc->active) {
3066 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3068 drrs_status_per_crtc(m, dev, intel_crtc);
3071 drm_modeset_unlock(&intel_crtc->base.mutex);
3074 if (!active_crtc_cnt)
3075 seq_puts(m, "No active crtc found\n");
3080 struct pipe_crc_info {
3082 struct drm_device *dev;
3086 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3088 struct drm_info_node *node = (struct drm_info_node *) m->private;
3089 struct drm_device *dev = node->minor->dev;
3090 struct drm_encoder *encoder;
3091 struct intel_encoder *intel_encoder;
3092 struct intel_digital_port *intel_dig_port;
3093 drm_modeset_lock_all(dev);
3094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3095 intel_encoder = to_intel_encoder(encoder);
3096 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3098 intel_dig_port = enc_to_dig_port(encoder);
3099 if (!intel_dig_port->dp.can_mst)
3102 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3104 drm_modeset_unlock_all(dev);
3108 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3110 struct pipe_crc_info *info = inode->i_private;
3111 struct drm_i915_private *dev_priv = info->dev->dev_private;
3112 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3114 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3117 spin_lock_irq(&pipe_crc->lock);
3119 if (pipe_crc->opened) {
3120 spin_unlock_irq(&pipe_crc->lock);
3121 return -EBUSY; /* already open */
3124 pipe_crc->opened = true;
3125 filep->private_data = inode->i_private;
3127 spin_unlock_irq(&pipe_crc->lock);
3132 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3134 struct pipe_crc_info *info = inode->i_private;
3135 struct drm_i915_private *dev_priv = info->dev->dev_private;
3136 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3138 spin_lock_irq(&pipe_crc->lock);
3139 pipe_crc->opened = false;
3140 spin_unlock_irq(&pipe_crc->lock);
3145 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3146 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3147 /* account for \'0' */
3148 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3150 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3152 assert_spin_locked(&pipe_crc->lock);
3153 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3154 INTEL_PIPE_CRC_ENTRIES_NR);
3158 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3161 struct pipe_crc_info *info = filep->private_data;
3162 struct drm_device *dev = info->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3165 char buf[PIPE_CRC_BUFFER_LEN];
3170 * Don't allow user space to provide buffers not big enough to hold
3173 if (count < PIPE_CRC_LINE_LEN)
3176 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3179 /* nothing to read */
3180 spin_lock_irq(&pipe_crc->lock);
3181 while (pipe_crc_data_count(pipe_crc) == 0) {
3184 if (filep->f_flags & O_NONBLOCK) {
3185 spin_unlock_irq(&pipe_crc->lock);
3189 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3190 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3192 spin_unlock_irq(&pipe_crc->lock);
3197 /* We now have one or more entries to read */
3198 n_entries = count / PIPE_CRC_LINE_LEN;
3201 while (n_entries > 0) {
3202 struct intel_pipe_crc_entry *entry =
3203 &pipe_crc->entries[pipe_crc->tail];
3206 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3207 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3210 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3211 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3213 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3214 "%8u %8x %8x %8x %8x %8x\n",
3215 entry->frame, entry->crc[0],
3216 entry->crc[1], entry->crc[2],
3217 entry->crc[3], entry->crc[4]);
3219 spin_unlock_irq(&pipe_crc->lock);
3221 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3222 if (ret == PIPE_CRC_LINE_LEN)
3225 user_buf += PIPE_CRC_LINE_LEN;
3228 spin_lock_irq(&pipe_crc->lock);
3231 spin_unlock_irq(&pipe_crc->lock);
3236 static const struct file_operations i915_pipe_crc_fops = {
3237 .owner = THIS_MODULE,
3238 .open = i915_pipe_crc_open,
3239 .read = i915_pipe_crc_read,
3240 .release = i915_pipe_crc_release,
3243 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3245 .name = "i915_pipe_A_crc",
3249 .name = "i915_pipe_B_crc",
3253 .name = "i915_pipe_C_crc",
3258 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3261 struct drm_device *dev = minor->dev;
3263 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3266 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3267 &i915_pipe_crc_fops);
3271 return drm_add_fake_info_node(minor, ent, info);
3274 static const char * const pipe_crc_sources[] = {
3287 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3289 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3290 return pipe_crc_sources[source];
3293 static int display_crc_ctl_show(struct seq_file *m, void *data)
3295 struct drm_device *dev = m->private;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3299 for (i = 0; i < I915_MAX_PIPES; i++)
3300 seq_printf(m, "%c %s\n", pipe_name(i),
3301 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3306 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3308 struct drm_device *dev = inode->i_private;
3310 return single_open(file, display_crc_ctl_show, dev);
3313 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3316 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3317 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3320 case INTEL_PIPE_CRC_SOURCE_PIPE:
3321 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3323 case INTEL_PIPE_CRC_SOURCE_NONE:
3333 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3334 enum intel_pipe_crc_source *source)
3336 struct intel_encoder *encoder;
3337 struct intel_crtc *crtc;
3338 struct intel_digital_port *dig_port;
3341 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3343 drm_modeset_lock_all(dev);
3344 for_each_intel_encoder(dev, encoder) {
3345 if (!encoder->base.crtc)
3348 crtc = to_intel_crtc(encoder->base.crtc);
3350 if (crtc->pipe != pipe)
3353 switch (encoder->type) {
3354 case INTEL_OUTPUT_TVOUT:
3355 *source = INTEL_PIPE_CRC_SOURCE_TV;
3357 case INTEL_OUTPUT_DISPLAYPORT:
3358 case INTEL_OUTPUT_EDP:
3359 dig_port = enc_to_dig_port(&encoder->base);
3360 switch (dig_port->port) {
3362 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3365 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3368 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3371 WARN(1, "nonexisting DP port %c\n",
3372 port_name(dig_port->port));
3380 drm_modeset_unlock_all(dev);
3385 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3387 enum intel_pipe_crc_source *source,
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 bool need_stable_symbols = false;
3393 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3394 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3400 case INTEL_PIPE_CRC_SOURCE_PIPE:
3401 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3403 case INTEL_PIPE_CRC_SOURCE_DP_B:
3404 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3405 need_stable_symbols = true;
3407 case INTEL_PIPE_CRC_SOURCE_DP_C:
3408 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3409 need_stable_symbols = true;
3411 case INTEL_PIPE_CRC_SOURCE_DP_D:
3412 if (!IS_CHERRYVIEW(dev))
3414 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3415 need_stable_symbols = true;
3417 case INTEL_PIPE_CRC_SOURCE_NONE:
3425 * When the pipe CRC tap point is after the transcoders we need
3426 * to tweak symbol-level features to produce a deterministic series of
3427 * symbols for a given frame. We need to reset those features only once
3428 * a frame (instead of every nth symbol):
3429 * - DC-balance: used to ensure a better clock recovery from the data
3431 * - DisplayPort scrambling: used for EMI reduction
3433 if (need_stable_symbols) {
3434 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3436 tmp |= DC_BALANCE_RESET_VLV;
3439 tmp |= PIPE_A_SCRAMBLE_RESET;
3442 tmp |= PIPE_B_SCRAMBLE_RESET;
3445 tmp |= PIPE_C_SCRAMBLE_RESET;
3450 I915_WRITE(PORT_DFT2_G4X, tmp);
3456 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3458 enum intel_pipe_crc_source *source,
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 bool need_stable_symbols = false;
3464 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3465 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3471 case INTEL_PIPE_CRC_SOURCE_PIPE:
3472 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3474 case INTEL_PIPE_CRC_SOURCE_TV:
3475 if (!SUPPORTS_TV(dev))
3477 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3479 case INTEL_PIPE_CRC_SOURCE_DP_B:
3482 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3483 need_stable_symbols = true;
3485 case INTEL_PIPE_CRC_SOURCE_DP_C:
3488 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3489 need_stable_symbols = true;
3491 case INTEL_PIPE_CRC_SOURCE_DP_D:
3494 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3495 need_stable_symbols = true;
3497 case INTEL_PIPE_CRC_SOURCE_NONE:
3505 * When the pipe CRC tap point is after the transcoders we need
3506 * to tweak symbol-level features to produce a deterministic series of
3507 * symbols for a given frame. We need to reset those features only once
3508 * a frame (instead of every nth symbol):
3509 * - DC-balance: used to ensure a better clock recovery from the data
3511 * - DisplayPort scrambling: used for EMI reduction
3513 if (need_stable_symbols) {
3514 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3516 WARN_ON(!IS_G4X(dev));
3518 I915_WRITE(PORT_DFT_I9XX,
3519 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3522 tmp |= PIPE_A_SCRAMBLE_RESET;
3524 tmp |= PIPE_B_SCRAMBLE_RESET;
3526 I915_WRITE(PORT_DFT2_G4X, tmp);
3532 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3540 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3543 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3546 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3551 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3552 tmp &= ~DC_BALANCE_RESET_VLV;
3553 I915_WRITE(PORT_DFT2_G4X, tmp);
3557 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3564 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3566 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3567 I915_WRITE(PORT_DFT2_G4X, tmp);
3569 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3570 I915_WRITE(PORT_DFT_I9XX,
3571 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3575 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3578 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3579 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3582 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3583 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3585 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3586 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3588 case INTEL_PIPE_CRC_SOURCE_PIPE:
3589 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3591 case INTEL_PIPE_CRC_SOURCE_NONE:
3601 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc *crtc =
3605 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3607 drm_modeset_lock_all(dev);
3609 * If we use the eDP transcoder we need to make sure that we don't
3610 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3611 * relevant on hsw with pipe A when using the always-on power well
3614 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3615 !crtc->config->pch_pfit.enabled) {
3616 crtc->config->pch_pfit.force_thru = true;
3618 intel_display_power_get(dev_priv,
3619 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3621 intel_crtc_reset(crtc);
3623 drm_modeset_unlock_all(dev);
3626 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct intel_crtc *crtc =
3630 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3632 drm_modeset_lock_all(dev);
3634 * If we use the eDP transcoder we need to make sure that we don't
3635 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3636 * relevant on hsw with pipe A when using the always-on power well
3639 if (crtc->config->pch_pfit.force_thru) {
3640 crtc->config->pch_pfit.force_thru = false;
3642 intel_crtc_reset(crtc);
3644 intel_display_power_put(dev_priv,
3645 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3647 drm_modeset_unlock_all(dev);
3650 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3652 enum intel_pipe_crc_source *source,
3655 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3656 *source = INTEL_PIPE_CRC_SOURCE_PF;
3659 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3660 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3662 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3663 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3665 case INTEL_PIPE_CRC_SOURCE_PF:
3666 if (IS_HASWELL(dev) && pipe == PIPE_A)
3667 hsw_trans_edp_pipe_A_crc_wa(dev);
3669 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3671 case INTEL_PIPE_CRC_SOURCE_NONE:
3681 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3682 enum intel_pipe_crc_source source)
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3686 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3688 u32 val = 0; /* shut up gcc */
3691 if (pipe_crc->source == source)
3694 /* forbid changing the source without going back to 'none' */
3695 if (pipe_crc->source && source)
3698 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3699 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3704 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3705 else if (INTEL_INFO(dev)->gen < 5)
3706 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3707 else if (IS_VALLEYVIEW(dev))
3708 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3709 else if (IS_GEN5(dev) || IS_GEN6(dev))
3710 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3712 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3717 /* none -> real source transition */
3719 struct intel_pipe_crc_entry *entries;
3721 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3722 pipe_name(pipe), pipe_crc_source_name(source));
3724 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3725 sizeof(pipe_crc->entries[0]),
3731 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3732 * enabled and disabled dynamically based on package C states,
3733 * user space can't make reliable use of the CRCs, so let's just
3734 * completely disable it.
3736 hsw_disable_ips(crtc);
3738 spin_lock_irq(&pipe_crc->lock);
3739 kfree(pipe_crc->entries);
3740 pipe_crc->entries = entries;
3743 spin_unlock_irq(&pipe_crc->lock);
3746 pipe_crc->source = source;
3748 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3749 POSTING_READ(PIPE_CRC_CTL(pipe));
3751 /* real source -> none transition */
3752 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3753 struct intel_pipe_crc_entry *entries;
3754 struct intel_crtc *crtc =
3755 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3757 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3760 drm_modeset_lock(&crtc->base.mutex, NULL);
3762 intel_wait_for_vblank(dev, pipe);
3763 drm_modeset_unlock(&crtc->base.mutex);
3765 spin_lock_irq(&pipe_crc->lock);
3766 entries = pipe_crc->entries;
3767 pipe_crc->entries = NULL;
3770 spin_unlock_irq(&pipe_crc->lock);
3775 g4x_undo_pipe_scramble_reset(dev, pipe);
3776 else if (IS_VALLEYVIEW(dev))
3777 vlv_undo_pipe_scramble_reset(dev, pipe);
3778 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3779 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3781 hsw_enable_ips(crtc);
3788 * Parse pipe CRC command strings:
3789 * command: wsp* object wsp+ name wsp+ source wsp*
3792 * source: (none | plane1 | plane2 | pf)
3793 * wsp: (#0x20 | #0x9 | #0xA)+
3796 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3797 * "pipe A none" -> Stop CRC
3799 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3806 /* skip leading white space */
3807 buf = skip_spaces(buf);
3809 break; /* end of buffer */
3811 /* find end of word */
3812 for (end = buf; *end && !isspace(*end); end++)
3815 if (n_words == max_words) {
3816 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3818 return -EINVAL; /* ran out of words[] before bytes */
3823 words[n_words++] = buf;
3830 enum intel_pipe_crc_object {
3831 PIPE_CRC_OBJECT_PIPE,
3834 static const char * const pipe_crc_objects[] = {
3839 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3843 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3844 if (!strcmp(buf, pipe_crc_objects[i])) {
3852 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3854 const char name = buf[0];
3856 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3865 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3869 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3870 if (!strcmp(buf, pipe_crc_sources[i])) {
3878 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3882 char *words[N_WORDS];
3884 enum intel_pipe_crc_object object;
3885 enum intel_pipe_crc_source source;
3887 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3888 if (n_words != N_WORDS) {
3889 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3894 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3895 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3899 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3900 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3904 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3905 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3909 return pipe_crc_set_source(dev, pipe, source);
3912 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3913 size_t len, loff_t *offp)
3915 struct seq_file *m = file->private_data;
3916 struct drm_device *dev = m->private;
3923 if (len > PAGE_SIZE - 1) {
3924 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3929 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3933 if (copy_from_user(tmpbuf, ubuf, len)) {
3939 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3950 static const struct file_operations i915_display_crc_ctl_fops = {
3951 .owner = THIS_MODULE,
3952 .open = display_crc_ctl_open,
3954 .llseek = seq_lseek,
3955 .release = single_release,
3956 .write = display_crc_ctl_write
3959 static ssize_t i915_displayport_test_active_write(struct file *file,
3960 const char __user *ubuf,
3961 size_t len, loff_t *offp)
3966 struct drm_device *dev;
3967 struct drm_connector *connector;
3968 struct list_head *connector_list;
3969 struct intel_dp *intel_dp;
3972 m = file->private_data;
3983 connector_list = &dev->mode_config.connector_list;
3988 input_buffer = kmalloc(len + 1, GFP_KERNEL);
3992 if (copy_from_user(input_buffer, ubuf, len)) {
3997 input_buffer[len] = '\0';
3998 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4000 list_for_each_entry(connector, connector_list, head) {
4002 if (connector->connector_type !=
4003 DRM_MODE_CONNECTOR_DisplayPort)
4006 if (connector->connector_type ==
4007 DRM_MODE_CONNECTOR_DisplayPort &&
4008 connector->status == connector_status_connected &&
4009 connector->encoder != NULL) {
4010 intel_dp = enc_to_intel_dp(connector->encoder);
4011 status = kstrtoint(input_buffer, 10, &val);
4014 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4015 /* To prevent erroneous activation of the compliance
4016 * testing code, only accept an actual value of 1 here
4019 intel_dp->compliance_test_active = 1;
4021 intel_dp->compliance_test_active = 0;
4025 kfree(input_buffer);
4033 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4035 struct drm_device *dev = m->private;
4036 struct drm_connector *connector;
4037 struct list_head *connector_list = &dev->mode_config.connector_list;
4038 struct intel_dp *intel_dp;
4043 list_for_each_entry(connector, connector_list, head) {
4045 if (connector->connector_type !=
4046 DRM_MODE_CONNECTOR_DisplayPort)
4049 if (connector->status == connector_status_connected &&
4050 connector->encoder != NULL) {
4051 intel_dp = enc_to_intel_dp(connector->encoder);
4052 if (intel_dp->compliance_test_active)
4063 static int i915_displayport_test_active_open(struct inode *inode,
4066 struct drm_device *dev = inode->i_private;
4068 return single_open(file, i915_displayport_test_active_show, dev);
4071 static const struct file_operations i915_displayport_test_active_fops = {
4072 .owner = THIS_MODULE,
4073 .open = i915_displayport_test_active_open,
4075 .llseek = seq_lseek,
4076 .release = single_release,
4077 .write = i915_displayport_test_active_write
4080 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4082 struct drm_device *dev = m->private;
4083 struct drm_connector *connector;
4084 struct list_head *connector_list = &dev->mode_config.connector_list;
4085 struct intel_dp *intel_dp;
4090 list_for_each_entry(connector, connector_list, head) {
4092 if (connector->connector_type !=
4093 DRM_MODE_CONNECTOR_DisplayPort)
4096 if (connector->status == connector_status_connected &&
4097 connector->encoder != NULL) {
4098 intel_dp = enc_to_intel_dp(connector->encoder);
4099 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4106 static int i915_displayport_test_data_open(struct inode *inode,
4109 struct drm_device *dev = inode->i_private;
4111 return single_open(file, i915_displayport_test_data_show, dev);
4114 static const struct file_operations i915_displayport_test_data_fops = {
4115 .owner = THIS_MODULE,
4116 .open = i915_displayport_test_data_open,
4118 .llseek = seq_lseek,
4119 .release = single_release
4122 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4124 struct drm_device *dev = m->private;
4125 struct drm_connector *connector;
4126 struct list_head *connector_list = &dev->mode_config.connector_list;
4127 struct intel_dp *intel_dp;
4132 list_for_each_entry(connector, connector_list, head) {
4134 if (connector->connector_type !=
4135 DRM_MODE_CONNECTOR_DisplayPort)
4138 if (connector->status == connector_status_connected &&
4139 connector->encoder != NULL) {
4140 intel_dp = enc_to_intel_dp(connector->encoder);
4141 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4149 static int i915_displayport_test_type_open(struct inode *inode,
4152 struct drm_device *dev = inode->i_private;
4154 return single_open(file, i915_displayport_test_type_show, dev);
4157 static const struct file_operations i915_displayport_test_type_fops = {
4158 .owner = THIS_MODULE,
4159 .open = i915_displayport_test_type_open,
4161 .llseek = seq_lseek,
4162 .release = single_release
4165 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4167 struct drm_device *dev = m->private;
4168 int num_levels = ilk_wm_max_level(dev) + 1;
4171 drm_modeset_lock_all(dev);
4173 for (level = 0; level < num_levels; level++) {
4174 unsigned int latency = wm[level];
4177 * - WM1+ latency values in 0.5us units
4178 * - latencies are in us on gen9
4180 if (INTEL_INFO(dev)->gen >= 9)
4185 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4186 level, wm[level], latency / 10, latency % 10);
4189 drm_modeset_unlock_all(dev);
4192 static int pri_wm_latency_show(struct seq_file *m, void *data)
4194 struct drm_device *dev = m->private;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 const uint16_t *latencies;
4198 if (INTEL_INFO(dev)->gen >= 9)
4199 latencies = dev_priv->wm.skl_latency;
4201 latencies = to_i915(dev)->wm.pri_latency;
4203 wm_latency_show(m, latencies);
4208 static int spr_wm_latency_show(struct seq_file *m, void *data)
4210 struct drm_device *dev = m->private;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 const uint16_t *latencies;
4214 if (INTEL_INFO(dev)->gen >= 9)
4215 latencies = dev_priv->wm.skl_latency;
4217 latencies = to_i915(dev)->wm.spr_latency;
4219 wm_latency_show(m, latencies);
4224 static int cur_wm_latency_show(struct seq_file *m, void *data)
4226 struct drm_device *dev = m->private;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 const uint16_t *latencies;
4230 if (INTEL_INFO(dev)->gen >= 9)
4231 latencies = dev_priv->wm.skl_latency;
4233 latencies = to_i915(dev)->wm.cur_latency;
4235 wm_latency_show(m, latencies);
4240 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4242 struct drm_device *dev = inode->i_private;
4244 if (HAS_GMCH_DISPLAY(dev))
4247 return single_open(file, pri_wm_latency_show, dev);
4250 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4252 struct drm_device *dev = inode->i_private;
4254 if (HAS_GMCH_DISPLAY(dev))
4257 return single_open(file, spr_wm_latency_show, dev);
4260 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4262 struct drm_device *dev = inode->i_private;
4264 if (HAS_GMCH_DISPLAY(dev))
4267 return single_open(file, cur_wm_latency_show, dev);
4270 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4271 size_t len, loff_t *offp, uint16_t wm[8])
4273 struct seq_file *m = file->private_data;
4274 struct drm_device *dev = m->private;
4275 uint16_t new[8] = { 0 };
4276 int num_levels = ilk_wm_max_level(dev) + 1;
4281 if (len >= sizeof(tmp))
4284 if (copy_from_user(tmp, ubuf, len))
4289 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4290 &new[0], &new[1], &new[2], &new[3],
4291 &new[4], &new[5], &new[6], &new[7]);
4292 if (ret != num_levels)
4295 drm_modeset_lock_all(dev);
4297 for (level = 0; level < num_levels; level++)
4298 wm[level] = new[level];
4300 drm_modeset_unlock_all(dev);
4306 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4307 size_t len, loff_t *offp)
4309 struct seq_file *m = file->private_data;
4310 struct drm_device *dev = m->private;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312 uint16_t *latencies;
4314 if (INTEL_INFO(dev)->gen >= 9)
4315 latencies = dev_priv->wm.skl_latency;
4317 latencies = to_i915(dev)->wm.pri_latency;
4319 return wm_latency_write(file, ubuf, len, offp, latencies);
4322 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4323 size_t len, loff_t *offp)
4325 struct seq_file *m = file->private_data;
4326 struct drm_device *dev = m->private;
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 uint16_t *latencies;
4330 if (INTEL_INFO(dev)->gen >= 9)
4331 latencies = dev_priv->wm.skl_latency;
4333 latencies = to_i915(dev)->wm.spr_latency;
4335 return wm_latency_write(file, ubuf, len, offp, latencies);
4338 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4339 size_t len, loff_t *offp)
4341 struct seq_file *m = file->private_data;
4342 struct drm_device *dev = m->private;
4343 struct drm_i915_private *dev_priv = dev->dev_private;
4344 uint16_t *latencies;
4346 if (INTEL_INFO(dev)->gen >= 9)
4347 latencies = dev_priv->wm.skl_latency;
4349 latencies = to_i915(dev)->wm.cur_latency;
4351 return wm_latency_write(file, ubuf, len, offp, latencies);
4354 static const struct file_operations i915_pri_wm_latency_fops = {
4355 .owner = THIS_MODULE,
4356 .open = pri_wm_latency_open,
4358 .llseek = seq_lseek,
4359 .release = single_release,
4360 .write = pri_wm_latency_write
4363 static const struct file_operations i915_spr_wm_latency_fops = {
4364 .owner = THIS_MODULE,
4365 .open = spr_wm_latency_open,
4367 .llseek = seq_lseek,
4368 .release = single_release,
4369 .write = spr_wm_latency_write
4372 static const struct file_operations i915_cur_wm_latency_fops = {
4373 .owner = THIS_MODULE,
4374 .open = cur_wm_latency_open,
4376 .llseek = seq_lseek,
4377 .release = single_release,
4378 .write = cur_wm_latency_write
4382 i915_wedged_get(void *data, u64 *val)
4384 struct drm_device *dev = data;
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4387 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4393 i915_wedged_set(void *data, u64 val)
4395 struct drm_device *dev = data;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4399 * There is no safeguard against this debugfs entry colliding
4400 * with the hangcheck calling same i915_handle_error() in
4401 * parallel, causing an explosion. For now we assume that the
4402 * test harness is responsible enough not to inject gpu hangs
4403 * while it is writing to 'i915_wedged'
4406 if (i915_reset_in_progress(&dev_priv->gpu_error))
4409 intel_runtime_pm_get(dev_priv);
4411 i915_handle_error(dev, val,
4412 "Manually setting wedged to %llu", val);
4414 intel_runtime_pm_put(dev_priv);
4419 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4420 i915_wedged_get, i915_wedged_set,
4424 i915_ring_stop_get(void *data, u64 *val)
4426 struct drm_device *dev = data;
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4429 *val = dev_priv->gpu_error.stop_rings;
4435 i915_ring_stop_set(void *data, u64 val)
4437 struct drm_device *dev = data;
4438 struct drm_i915_private *dev_priv = dev->dev_private;
4441 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4443 ret = mutex_lock_interruptible(&dev->struct_mutex);
4447 dev_priv->gpu_error.stop_rings = val;
4448 mutex_unlock(&dev->struct_mutex);
4453 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4454 i915_ring_stop_get, i915_ring_stop_set,
4458 i915_ring_missed_irq_get(void *data, u64 *val)
4460 struct drm_device *dev = data;
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4463 *val = dev_priv->gpu_error.missed_irq_rings;
4468 i915_ring_missed_irq_set(void *data, u64 val)
4470 struct drm_device *dev = data;
4471 struct drm_i915_private *dev_priv = dev->dev_private;
4474 /* Lock against concurrent debugfs callers */
4475 ret = mutex_lock_interruptible(&dev->struct_mutex);
4478 dev_priv->gpu_error.missed_irq_rings = val;
4479 mutex_unlock(&dev->struct_mutex);
4484 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4485 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4489 i915_ring_test_irq_get(void *data, u64 *val)
4491 struct drm_device *dev = data;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4494 *val = dev_priv->gpu_error.test_irq_rings;
4500 i915_ring_test_irq_set(void *data, u64 val)
4502 struct drm_device *dev = data;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4506 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4508 /* Lock against concurrent debugfs callers */
4509 ret = mutex_lock_interruptible(&dev->struct_mutex);
4513 dev_priv->gpu_error.test_irq_rings = val;
4514 mutex_unlock(&dev->struct_mutex);
4519 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4520 i915_ring_test_irq_get, i915_ring_test_irq_set,
4523 #define DROP_UNBOUND 0x1
4524 #define DROP_BOUND 0x2
4525 #define DROP_RETIRE 0x4
4526 #define DROP_ACTIVE 0x8
4527 #define DROP_ALL (DROP_UNBOUND | \
4532 i915_drop_caches_get(void *data, u64 *val)
4540 i915_drop_caches_set(void *data, u64 val)
4542 struct drm_device *dev = data;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4546 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4548 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4549 * on ioctls on -EAGAIN. */
4550 ret = mutex_lock_interruptible(&dev->struct_mutex);
4554 if (val & DROP_ACTIVE) {
4555 ret = i915_gpu_idle(dev);
4560 if (val & (DROP_RETIRE | DROP_ACTIVE))
4561 i915_gem_retire_requests(dev);
4563 if (val & DROP_BOUND)
4564 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4566 if (val & DROP_UNBOUND)
4567 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4570 mutex_unlock(&dev->struct_mutex);
4575 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4576 i915_drop_caches_get, i915_drop_caches_set,
4580 i915_max_freq_get(void *data, u64 *val)
4582 struct drm_device *dev = data;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4586 if (INTEL_INFO(dev)->gen < 6)
4589 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4591 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4595 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4596 mutex_unlock(&dev_priv->rps.hw_lock);
4602 i915_max_freq_set(void *data, u64 val)
4604 struct drm_device *dev = data;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4609 if (INTEL_INFO(dev)->gen < 6)
4612 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4614 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4616 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4621 * Turbo will still be enabled, but won't go above the set value.
4623 val = intel_freq_opcode(dev_priv, val);
4625 hw_max = dev_priv->rps.max_freq;
4626 hw_min = dev_priv->rps.min_freq;
4628 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4629 mutex_unlock(&dev_priv->rps.hw_lock);
4633 dev_priv->rps.max_freq_softlimit = val;
4635 intel_set_rps(dev, val);
4637 mutex_unlock(&dev_priv->rps.hw_lock);
4642 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4643 i915_max_freq_get, i915_max_freq_set,
4647 i915_min_freq_get(void *data, u64 *val)
4649 struct drm_device *dev = data;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4653 if (INTEL_INFO(dev)->gen < 6)
4656 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4658 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4662 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4663 mutex_unlock(&dev_priv->rps.hw_lock);
4669 i915_min_freq_set(void *data, u64 val)
4671 struct drm_device *dev = data;
4672 struct drm_i915_private *dev_priv = dev->dev_private;
4676 if (INTEL_INFO(dev)->gen < 6)
4679 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4681 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4683 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4688 * Turbo will still be enabled, but won't go below the set value.
4690 val = intel_freq_opcode(dev_priv, val);
4692 hw_max = dev_priv->rps.max_freq;
4693 hw_min = dev_priv->rps.min_freq;
4695 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4696 mutex_unlock(&dev_priv->rps.hw_lock);
4700 dev_priv->rps.min_freq_softlimit = val;
4702 intel_set_rps(dev, val);
4704 mutex_unlock(&dev_priv->rps.hw_lock);
4709 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4710 i915_min_freq_get, i915_min_freq_set,
4714 i915_cache_sharing_get(void *data, u64 *val)
4716 struct drm_device *dev = data;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4721 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4724 ret = mutex_lock_interruptible(&dev->struct_mutex);
4727 intel_runtime_pm_get(dev_priv);
4729 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4731 intel_runtime_pm_put(dev_priv);
4732 mutex_unlock(&dev_priv->dev->struct_mutex);
4734 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4740 i915_cache_sharing_set(void *data, u64 val)
4742 struct drm_device *dev = data;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4746 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4752 intel_runtime_pm_get(dev_priv);
4753 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4755 /* Update the cache sharing policy here as well */
4756 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4757 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4758 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4759 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4761 intel_runtime_pm_put(dev_priv);
4765 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4766 i915_cache_sharing_get, i915_cache_sharing_set,
4769 struct sseu_dev_status {
4770 unsigned int slice_total;
4771 unsigned int subslice_total;
4772 unsigned int subslice_per_slice;
4773 unsigned int eu_total;
4774 unsigned int eu_per_subslice;
4777 static void cherryview_sseu_device_status(struct drm_device *dev,
4778 struct sseu_dev_status *stat)
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781 const int ss_max = 2;
4783 u32 sig1[ss_max], sig2[ss_max];
4785 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4786 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4787 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4788 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4790 for (ss = 0; ss < ss_max; ss++) {
4791 unsigned int eu_cnt;
4793 if (sig1[ss] & CHV_SS_PG_ENABLE)
4794 /* skip disabled subslice */
4797 stat->slice_total = 1;
4798 stat->subslice_per_slice++;
4799 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4800 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4801 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4802 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4803 stat->eu_total += eu_cnt;
4804 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4806 stat->subslice_total = stat->subslice_per_slice;
4809 static void gen9_sseu_device_status(struct drm_device *dev,
4810 struct sseu_dev_status *stat)
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 int s_max = 3, ss_max = 4;
4815 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4817 /* BXT has a single slice and at most 3 subslices. */
4818 if (IS_BROXTON(dev)) {
4823 for (s = 0; s < s_max; s++) {
4824 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4825 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4826 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4829 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4830 GEN9_PGCTL_SSA_EU19_ACK |
4831 GEN9_PGCTL_SSA_EU210_ACK |
4832 GEN9_PGCTL_SSA_EU311_ACK;
4833 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4834 GEN9_PGCTL_SSB_EU19_ACK |
4835 GEN9_PGCTL_SSB_EU210_ACK |
4836 GEN9_PGCTL_SSB_EU311_ACK;
4838 for (s = 0; s < s_max; s++) {
4839 unsigned int ss_cnt = 0;
4841 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4842 /* skip disabled slice */
4845 stat->slice_total++;
4847 if (IS_SKYLAKE(dev))
4848 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4850 for (ss = 0; ss < ss_max; ss++) {
4851 unsigned int eu_cnt;
4853 if (IS_BROXTON(dev) &&
4854 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4855 /* skip disabled subslice */
4858 if (IS_BROXTON(dev))
4861 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4863 stat->eu_total += eu_cnt;
4864 stat->eu_per_subslice = max(stat->eu_per_subslice,
4868 stat->subslice_total += ss_cnt;
4869 stat->subslice_per_slice = max(stat->subslice_per_slice,
4874 static int i915_sseu_status(struct seq_file *m, void *unused)
4876 struct drm_info_node *node = (struct drm_info_node *) m->private;
4877 struct drm_device *dev = node->minor->dev;
4878 struct sseu_dev_status stat;
4880 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4883 seq_puts(m, "SSEU Device Info\n");
4884 seq_printf(m, " Available Slice Total: %u\n",
4885 INTEL_INFO(dev)->slice_total);
4886 seq_printf(m, " Available Subslice Total: %u\n",
4887 INTEL_INFO(dev)->subslice_total);
4888 seq_printf(m, " Available Subslice Per Slice: %u\n",
4889 INTEL_INFO(dev)->subslice_per_slice);
4890 seq_printf(m, " Available EU Total: %u\n",
4891 INTEL_INFO(dev)->eu_total);
4892 seq_printf(m, " Available EU Per Subslice: %u\n",
4893 INTEL_INFO(dev)->eu_per_subslice);
4894 seq_printf(m, " Has Slice Power Gating: %s\n",
4895 yesno(INTEL_INFO(dev)->has_slice_pg));
4896 seq_printf(m, " Has Subslice Power Gating: %s\n",
4897 yesno(INTEL_INFO(dev)->has_subslice_pg));
4898 seq_printf(m, " Has EU Power Gating: %s\n",
4899 yesno(INTEL_INFO(dev)->has_eu_pg));
4901 seq_puts(m, "SSEU Device Status\n");
4902 memset(&stat, 0, sizeof(stat));
4903 if (IS_CHERRYVIEW(dev)) {
4904 cherryview_sseu_device_status(dev, &stat);
4905 } else if (INTEL_INFO(dev)->gen >= 9) {
4906 gen9_sseu_device_status(dev, &stat);
4908 seq_printf(m, " Enabled Slice Total: %u\n",
4910 seq_printf(m, " Enabled Subslice Total: %u\n",
4911 stat.subslice_total);
4912 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4913 stat.subslice_per_slice);
4914 seq_printf(m, " Enabled EU Total: %u\n",
4916 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4917 stat.eu_per_subslice);
4922 static int i915_forcewake_open(struct inode *inode, struct file *file)
4924 struct drm_device *dev = inode->i_private;
4925 struct drm_i915_private *dev_priv = dev->dev_private;
4927 if (INTEL_INFO(dev)->gen < 6)
4930 intel_runtime_pm_get(dev_priv);
4931 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4936 static int i915_forcewake_release(struct inode *inode, struct file *file)
4938 struct drm_device *dev = inode->i_private;
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4941 if (INTEL_INFO(dev)->gen < 6)
4944 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4945 intel_runtime_pm_put(dev_priv);
4950 static const struct file_operations i915_forcewake_fops = {
4951 .owner = THIS_MODULE,
4952 .open = i915_forcewake_open,
4953 .release = i915_forcewake_release,
4956 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4958 struct drm_device *dev = minor->dev;
4961 ent = debugfs_create_file("i915_forcewake_user",
4964 &i915_forcewake_fops);
4968 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4971 static int i915_debugfs_create(struct dentry *root,
4972 struct drm_minor *minor,
4974 const struct file_operations *fops)
4976 struct drm_device *dev = minor->dev;
4979 ent = debugfs_create_file(name,
4986 return drm_add_fake_info_node(minor, ent, fops);
4989 static const struct drm_info_list i915_debugfs_list[] = {
4990 {"i915_capabilities", i915_capabilities, 0},
4991 {"i915_gem_objects", i915_gem_object_info, 0},
4992 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4993 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4994 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4995 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4996 {"i915_gem_stolen", i915_gem_stolen_list_info },
4997 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4998 {"i915_gem_request", i915_gem_request_info, 0},
4999 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5000 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5001 {"i915_gem_interrupt", i915_interrupt_info, 0},
5002 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5003 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5004 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5005 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5006 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5007 {"i915_frequency_info", i915_frequency_info, 0},
5008 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5009 {"i915_drpc_info", i915_drpc_info, 0},
5010 {"i915_emon_status", i915_emon_status, 0},
5011 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5012 {"i915_fbc_status", i915_fbc_status, 0},
5013 {"i915_ips_status", i915_ips_status, 0},
5014 {"i915_sr_status", i915_sr_status, 0},
5015 {"i915_opregion", i915_opregion, 0},
5016 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5017 {"i915_context_status", i915_context_status, 0},
5018 {"i915_dump_lrc", i915_dump_lrc, 0},
5019 {"i915_execlists", i915_execlists, 0},
5020 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5021 {"i915_swizzle_info", i915_swizzle_info, 0},
5022 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5023 {"i915_llc", i915_llc, 0},
5024 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5025 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5026 {"i915_energy_uJ", i915_energy_uJ, 0},
5027 {"i915_pc8_status", i915_pc8_status, 0},
5028 {"i915_power_domain_info", i915_power_domain_info, 0},
5029 {"i915_display_info", i915_display_info, 0},
5030 {"i915_semaphore_status", i915_semaphore_status, 0},
5031 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5032 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5033 {"i915_wa_registers", i915_wa_registers, 0},
5034 {"i915_ddb_info", i915_ddb_info, 0},
5035 {"i915_sseu_status", i915_sseu_status, 0},
5036 {"i915_drrs_status", i915_drrs_status, 0},
5037 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5039 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5041 static const struct i915_debugfs_files {
5043 const struct file_operations *fops;
5044 } i915_debugfs_files[] = {
5045 {"i915_wedged", &i915_wedged_fops},
5046 {"i915_max_freq", &i915_max_freq_fops},
5047 {"i915_min_freq", &i915_min_freq_fops},
5048 {"i915_cache_sharing", &i915_cache_sharing_fops},
5049 {"i915_ring_stop", &i915_ring_stop_fops},
5050 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5051 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5052 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5053 {"i915_error_state", &i915_error_state_fops},
5054 {"i915_next_seqno", &i915_next_seqno_fops},
5055 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5056 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5057 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5058 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5059 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5060 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5061 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5062 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5065 void intel_display_crc_init(struct drm_device *dev)
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5070 for_each_pipe(dev_priv, pipe) {
5071 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5073 pipe_crc->opened = false;
5074 spin_lock_init(&pipe_crc->lock);
5075 init_waitqueue_head(&pipe_crc->wq);
5079 int i915_debugfs_init(struct drm_minor *minor)
5083 ret = i915_forcewake_create(minor->debugfs_root, minor);
5087 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5088 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5093 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5094 ret = i915_debugfs_create(minor->debugfs_root, minor,
5095 i915_debugfs_files[i].name,
5096 i915_debugfs_files[i].fops);
5101 return drm_debugfs_create_files(i915_debugfs_list,
5102 I915_DEBUGFS_ENTRIES,
5103 minor->debugfs_root, minor);
5106 void i915_debugfs_cleanup(struct drm_minor *minor)
5110 drm_debugfs_remove_files(i915_debugfs_list,
5111 I915_DEBUGFS_ENTRIES, minor);
5113 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5116 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5117 struct drm_info_list *info_list =
5118 (struct drm_info_list *)&i915_pipe_crc_data[i];
5120 drm_debugfs_remove_files(info_list, 1, minor);
5123 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5124 struct drm_info_list *info_list =
5125 (struct drm_info_list *) i915_debugfs_files[i].fops;
5127 drm_debugfs_remove_files(info_list, 1, minor);
5132 /* DPCD dump start address. */
5133 unsigned int offset;
5134 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5136 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5138 /* Only valid for eDP. */
5142 static const struct dpcd_block i915_dpcd_debug[] = {
5143 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5144 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5145 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5146 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5147 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5148 { .offset = DP_SET_POWER },
5149 { .offset = DP_EDP_DPCD_REV },
5150 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5151 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5152 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5155 static int i915_dpcd_show(struct seq_file *m, void *data)
5157 struct drm_connector *connector = m->private;
5158 struct intel_dp *intel_dp =
5159 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5164 if (connector->status != connector_status_connected)
5167 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5168 const struct dpcd_block *b = &i915_dpcd_debug[i];
5169 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5172 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5175 /* low tech for now */
5176 if (WARN_ON(size > sizeof(buf)))
5179 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5181 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5182 size, b->offset, err);
5186 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5192 static int i915_dpcd_open(struct inode *inode, struct file *file)
5194 return single_open(file, i915_dpcd_show, inode->i_private);
5197 static const struct file_operations i915_dpcd_fops = {
5198 .owner = THIS_MODULE,
5199 .open = i915_dpcd_open,
5201 .llseek = seq_lseek,
5202 .release = single_release,
5206 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5207 * @connector: pointer to a registered drm_connector
5209 * Cleanup will be done by drm_connector_unregister() through a call to
5210 * drm_debugfs_connector_remove().
5212 * Returns 0 on success, negative error codes on error.
5214 int i915_debugfs_connector_add(struct drm_connector *connector)
5216 struct dentry *root = connector->debugfs_entry;
5218 /* The connector must have been registered beforehands. */
5222 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5223 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5224 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,