2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_displayid.h>
39 #define version_greater(edid, maj, min) \
40 (((edid)->version > (maj)) || \
41 ((edid)->version == (maj) && (edid)->revision > (min)))
43 #define EDID_EST_TIMINGS 16
44 #define EDID_STD_TIMINGS 8
45 #define EDID_DETAILED_TIMINGS 4
48 * EDID blocks out in the wild have a variety of bugs, try to collect
49 * them here (note that userspace may work around broken monitors first,
50 * but fixes should make their way here so that the kernel "just works"
51 * on as many displays as possible).
54 /* First detailed mode wrong, use largest 60Hz mode */
55 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
56 /* Reported 135MHz pixel clock is too high, needs adjustment */
57 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
58 /* Prefer the largest mode at 75 Hz */
59 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
60 /* Detail timing is in cm not mm */
61 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
62 /* Detailed timing descriptors have bogus size values, so just take the
63 * maximum size and use that.
65 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
66 /* Monitor forgot to set the first detailed is preferred bit. */
67 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
68 /* use +hsync +vsync for detailed mode */
69 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
70 /* Force reduced-blanking timings for detailed modes */
71 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
73 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
75 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
77 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
79 struct detailed_mode_closure {
80 struct drm_connector *connector;
92 static struct edid_quirk {
96 } edid_quirk_list[] = {
98 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
100 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
102 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
104 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
105 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
107 /* Belinea 10 15 55 */
108 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
109 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
111 /* Envision Peripherals, Inc. EN-7100e */
112 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
113 /* Envision EN2028 */
114 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
116 /* Funai Electronics PM36B */
117 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
118 EDID_QUIRK_DETAILED_IN_CM },
120 /* LG Philips LCD LP154W01-A5 */
121 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
122 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
124 /* Philips 107p5 CRT */
125 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
128 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
130 /* Samsung SyncMaster 205BW. Note: irony */
131 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
132 /* Samsung SyncMaster 22[5-6]BW */
133 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
134 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
137 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
139 /* ViewSonic VA2026w */
140 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
142 /* Medion MD 30217 PG */
143 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
145 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
146 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
150 * Autogenerated from the DMT spec.
151 * This table is copied from xfree86/modes/xf86EdidModes.c.
153 static const struct drm_display_mode drm_dmt_modes[] = {
154 /* 0x01 - 640x350@85Hz */
155 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
156 736, 832, 0, 350, 382, 385, 445, 0,
157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
158 /* 0x02 - 640x400@85Hz */
159 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
160 736, 832, 0, 400, 401, 404, 445, 0,
161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
162 /* 0x03 - 720x400@85Hz */
163 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
164 828, 936, 0, 400, 401, 404, 446, 0,
165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
166 /* 0x04 - 640x480@60Hz */
167 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
168 752, 800, 0, 480, 490, 492, 525, 0,
169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
170 /* 0x05 - 640x480@72Hz */
171 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
172 704, 832, 0, 480, 489, 492, 520, 0,
173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
174 /* 0x06 - 640x480@75Hz */
175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
176 720, 840, 0, 480, 481, 484, 500, 0,
177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
178 /* 0x07 - 640x480@85Hz */
179 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
180 752, 832, 0, 480, 481, 484, 509, 0,
181 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
182 /* 0x08 - 800x600@56Hz */
183 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
184 896, 1024, 0, 600, 601, 603, 625, 0,
185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
186 /* 0x09 - 800x600@60Hz */
187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
188 968, 1056, 0, 600, 601, 605, 628, 0,
189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
190 /* 0x0a - 800x600@72Hz */
191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
192 976, 1040, 0, 600, 637, 643, 666, 0,
193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x0b - 800x600@75Hz */
195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
196 896, 1056, 0, 600, 601, 604, 625, 0,
197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
198 /* 0x0c - 800x600@85Hz */
199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
200 896, 1048, 0, 600, 601, 604, 631, 0,
201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
202 /* 0x0d - 800x600@120Hz RB */
203 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
204 880, 960, 0, 600, 603, 607, 636, 0,
205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
206 /* 0x0e - 848x480@60Hz */
207 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
208 976, 1088, 0, 480, 486, 494, 517, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
210 /* 0x0f - 1024x768@43Hz, interlace */
211 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
212 1208, 1264, 0, 768, 768, 772, 817, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
214 DRM_MODE_FLAG_INTERLACE) },
215 /* 0x10 - 1024x768@60Hz */
216 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
217 1184, 1344, 0, 768, 771, 777, 806, 0,
218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
219 /* 0x11 - 1024x768@70Hz */
220 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
221 1184, 1328, 0, 768, 771, 777, 806, 0,
222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
223 /* 0x12 - 1024x768@75Hz */
224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
225 1136, 1312, 0, 768, 769, 772, 800, 0,
226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
227 /* 0x13 - 1024x768@85Hz */
228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
229 1168, 1376, 0, 768, 769, 772, 808, 0,
230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
231 /* 0x14 - 1024x768@120Hz RB */
232 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
233 1104, 1184, 0, 768, 771, 775, 813, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
235 /* 0x15 - 1152x864@75Hz */
236 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
237 1344, 1600, 0, 864, 865, 868, 900, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
239 /* 0x55 - 1280x720@60Hz */
240 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
241 1430, 1650, 0, 720, 725, 730, 750, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
243 /* 0x16 - 1280x768@60Hz RB */
244 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
245 1360, 1440, 0, 768, 771, 778, 790, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
247 /* 0x17 - 1280x768@60Hz */
248 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
249 1472, 1664, 0, 768, 771, 778, 798, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
251 /* 0x18 - 1280x768@75Hz */
252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
253 1488, 1696, 0, 768, 771, 778, 805, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x19 - 1280x768@85Hz */
256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
257 1496, 1712, 0, 768, 771, 778, 809, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x1a - 1280x768@120Hz RB */
260 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
261 1360, 1440, 0, 768, 771, 778, 813, 0,
262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x1b - 1280x800@60Hz RB */
264 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
265 1360, 1440, 0, 800, 803, 809, 823, 0,
266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
267 /* 0x1c - 1280x800@60Hz */
268 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
269 1480, 1680, 0, 800, 803, 809, 831, 0,
270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
271 /* 0x1d - 1280x800@75Hz */
272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
273 1488, 1696, 0, 800, 803, 809, 838, 0,
274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
275 /* 0x1e - 1280x800@85Hz */
276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
277 1496, 1712, 0, 800, 803, 809, 843, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x1f - 1280x800@120Hz RB */
280 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
281 1360, 1440, 0, 800, 803, 809, 847, 0,
282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
283 /* 0x20 - 1280x960@60Hz */
284 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
285 1488, 1800, 0, 960, 961, 964, 1000, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x21 - 1280x960@85Hz */
288 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
289 1504, 1728, 0, 960, 961, 964, 1011, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x22 - 1280x960@120Hz RB */
292 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
293 1360, 1440, 0, 960, 963, 967, 1017, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
295 /* 0x23 - 1280x1024@60Hz */
296 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
297 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
299 /* 0x24 - 1280x1024@75Hz */
300 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
301 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x25 - 1280x1024@85Hz */
304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
305 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x26 - 1280x1024@120Hz RB */
308 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
309 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x27 - 1360x768@60Hz */
312 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
313 1536, 1792, 0, 768, 771, 777, 795, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x28 - 1360x768@120Hz RB */
316 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
317 1440, 1520, 0, 768, 771, 776, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
319 /* 0x51 - 1366x768@60Hz */
320 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
321 1579, 1792, 0, 768, 771, 774, 798, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x56 - 1366x768@60Hz */
324 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
325 1436, 1500, 0, 768, 769, 772, 800, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x29 - 1400x1050@60Hz RB */
328 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
329 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
331 /* 0x2a - 1400x1050@60Hz */
332 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
333 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x2b - 1400x1050@75Hz */
336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
337 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x2c - 1400x1050@85Hz */
340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
341 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x2d - 1400x1050@120Hz RB */
344 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
345 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x2e - 1440x900@60Hz RB */
348 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
349 1520, 1600, 0, 900, 903, 909, 926, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
351 /* 0x2f - 1440x900@60Hz */
352 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
353 1672, 1904, 0, 900, 903, 909, 934, 0,
354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x30 - 1440x900@75Hz */
356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
357 1688, 1936, 0, 900, 903, 909, 942, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x31 - 1440x900@85Hz */
360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
361 1696, 1952, 0, 900, 903, 909, 948, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x32 - 1440x900@120Hz RB */
364 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
365 1520, 1600, 0, 900, 903, 909, 953, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
367 /* 0x53 - 1600x900@60Hz */
368 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
369 1704, 1800, 0, 900, 901, 904, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x33 - 1600x1200@60Hz */
372 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
373 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x34 - 1600x1200@65Hz */
376 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
377 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x35 - 1600x1200@70Hz */
380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x36 - 1600x1200@75Hz */
384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x37 - 1600x1200@85Hz */
388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
389 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x38 - 1600x1200@120Hz RB */
392 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
393 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x39 - 1680x1050@60Hz RB */
396 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
397 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
399 /* 0x3a - 1680x1050@60Hz */
400 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
401 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x3b - 1680x1050@75Hz */
404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
405 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x3c - 1680x1050@85Hz */
408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
409 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x3d - 1680x1050@120Hz RB */
412 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
413 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
415 /* 0x3e - 1792x1344@60Hz */
416 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
417 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x3f - 1792x1344@75Hz */
420 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
421 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x40 - 1792x1344@120Hz RB */
424 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
425 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
427 /* 0x41 - 1856x1392@60Hz */
428 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
429 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x42 - 1856x1392@75Hz */
432 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
433 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
435 /* 0x43 - 1856x1392@120Hz RB */
436 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
437 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
439 /* 0x52 - 1920x1080@60Hz */
440 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
441 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
443 /* 0x44 - 1920x1200@60Hz RB */
444 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
445 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 0x45 - 1920x1200@60Hz */
448 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
449 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x46 - 1920x1200@75Hz */
452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
453 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x47 - 1920x1200@85Hz */
456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
457 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x48 - 1920x1200@120Hz RB */
460 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
461 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
463 /* 0x49 - 1920x1440@60Hz */
464 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
465 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x4a - 1920x1440@75Hz */
468 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
469 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x4b - 1920x1440@120Hz RB */
472 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
473 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
475 /* 0x54 - 2048x1152@60Hz */
476 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
477 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x4c - 2560x1600@60Hz RB */
480 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
481 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x4d - 2560x1600@60Hz */
484 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
485 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x4e - 2560x1600@75Hz */
488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
489 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x4f - 2560x1600@85Hz */
492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
493 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x50 - 2560x1600@120Hz RB */
496 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
497 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
499 /* 0x57 - 4096x2160@60Hz RB */
500 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
501 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x58 - 4096x2160@59.94Hz RB */
504 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
505 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 * These more or less come from the DMT spec. The 720x400 modes are
511 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
512 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
513 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
516 * The DMT modes have been fact-checked; the rest are mild guesses.
518 static const struct drm_display_mode edid_est_modes[] = {
519 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
520 968, 1056, 0, 600, 601, 605, 628, 0,
521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
522 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
523 896, 1024, 0, 600, 601, 603, 625, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
525 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
526 720, 840, 0, 480, 481, 484, 500, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
528 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
529 704, 832, 0, 480, 489, 491, 520, 0,
530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
531 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
532 768, 864, 0, 480, 483, 486, 525, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
534 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
535 752, 800, 0, 480, 490, 492, 525, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
537 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
538 846, 900, 0, 400, 421, 423, 449, 0,
539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
540 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
541 846, 900, 0, 400, 412, 414, 449, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
543 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
544 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
546 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
547 1136, 1312, 0, 768, 769, 772, 800, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
549 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
550 1184, 1328, 0, 768, 771, 777, 806, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
552 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
553 1184, 1344, 0, 768, 771, 777, 806, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
555 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
556 1208, 1264, 0, 768, 768, 776, 817, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
558 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
559 928, 1152, 0, 624, 625, 628, 667, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
561 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
562 896, 1056, 0, 600, 601, 604, 625, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
564 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
565 976, 1040, 0, 600, 637, 643, 666, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
567 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
568 1344, 1600, 0, 864, 865, 868, 900, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
579 static const struct minimode est3_modes[] = {
587 { 1024, 768, 85, 0 },
588 { 1152, 864, 75, 0 },
590 { 1280, 768, 60, 1 },
591 { 1280, 768, 60, 0 },
592 { 1280, 768, 75, 0 },
593 { 1280, 768, 85, 0 },
594 { 1280, 960, 60, 0 },
595 { 1280, 960, 85, 0 },
596 { 1280, 1024, 60, 0 },
597 { 1280, 1024, 85, 0 },
599 { 1360, 768, 60, 0 },
600 { 1440, 900, 60, 1 },
601 { 1440, 900, 60, 0 },
602 { 1440, 900, 75, 0 },
603 { 1440, 900, 85, 0 },
604 { 1400, 1050, 60, 1 },
605 { 1400, 1050, 60, 0 },
606 { 1400, 1050, 75, 0 },
608 { 1400, 1050, 85, 0 },
609 { 1680, 1050, 60, 1 },
610 { 1680, 1050, 60, 0 },
611 { 1680, 1050, 75, 0 },
612 { 1680, 1050, 85, 0 },
613 { 1600, 1200, 60, 0 },
614 { 1600, 1200, 65, 0 },
615 { 1600, 1200, 70, 0 },
617 { 1600, 1200, 75, 0 },
618 { 1600, 1200, 85, 0 },
619 { 1792, 1344, 60, 0 },
620 { 1792, 1344, 75, 0 },
621 { 1856, 1392, 60, 0 },
622 { 1856, 1392, 75, 0 },
623 { 1920, 1200, 60, 1 },
624 { 1920, 1200, 60, 0 },
626 { 1920, 1200, 75, 0 },
627 { 1920, 1200, 85, 0 },
628 { 1920, 1440, 60, 0 },
629 { 1920, 1440, 75, 0 },
632 static const struct minimode extra_modes[] = {
633 { 1024, 576, 60, 0 },
634 { 1366, 768, 60, 0 },
635 { 1600, 900, 60, 0 },
636 { 1680, 945, 60, 0 },
637 { 1920, 1080, 60, 0 },
638 { 2048, 1152, 60, 0 },
639 { 2048, 1536, 60, 0 },
643 * Probably taken from CEA-861 spec.
644 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
646 * Index using the VIC.
648 static const struct drm_display_mode edid_cea_modes[] = {
649 /* 0 - dummy, VICs start at 1 */
651 /* 1 - 640x480@60Hz */
652 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
653 752, 800, 0, 480, 490, 492, 525, 0,
654 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
655 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
656 /* 2 - 720x480@60Hz */
657 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
658 798, 858, 0, 480, 489, 495, 525, 0,
659 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
660 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
661 /* 3 - 720x480@60Hz */
662 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
663 798, 858, 0, 480, 489, 495, 525, 0,
664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
666 /* 4 - 1280x720@60Hz */
667 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
668 1430, 1650, 0, 720, 725, 730, 750, 0,
669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
671 /* 5 - 1920x1080i@60Hz */
672 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
673 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
675 DRM_MODE_FLAG_INTERLACE),
676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
677 /* 6 - 720(1440)x480i@60Hz */
678 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
679 801, 858, 0, 480, 488, 494, 525, 0,
680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
681 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
682 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
683 /* 7 - 720(1440)x480i@60Hz */
684 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
685 801, 858, 0, 480, 488, 494, 525, 0,
686 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
687 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
689 /* 8 - 720(1440)x240@60Hz */
690 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
691 801, 858, 0, 240, 244, 247, 262, 0,
692 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
693 DRM_MODE_FLAG_DBLCLK),
694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
695 /* 9 - 720(1440)x240@60Hz */
696 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
697 801, 858, 0, 240, 244, 247, 262, 0,
698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
699 DRM_MODE_FLAG_DBLCLK),
700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
701 /* 10 - 2880x480i@60Hz */
702 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
703 3204, 3432, 0, 480, 488, 494, 525, 0,
704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
705 DRM_MODE_FLAG_INTERLACE),
706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
707 /* 11 - 2880x480i@60Hz */
708 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
709 3204, 3432, 0, 480, 488, 494, 525, 0,
710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
711 DRM_MODE_FLAG_INTERLACE),
712 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
713 /* 12 - 2880x240@60Hz */
714 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
715 3204, 3432, 0, 240, 244, 247, 262, 0,
716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
717 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
718 /* 13 - 2880x240@60Hz */
719 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
720 3204, 3432, 0, 240, 244, 247, 262, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
723 /* 14 - 1440x480@60Hz */
724 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
725 1596, 1716, 0, 480, 489, 495, 525, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
728 /* 15 - 1440x480@60Hz */
729 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
730 1596, 1716, 0, 480, 489, 495, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
733 /* 16 - 1920x1080@60Hz */
734 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
735 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738 /* 17 - 720x576@50Hz */
739 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
740 796, 864, 0, 576, 581, 586, 625, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
742 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
743 /* 18 - 720x576@50Hz */
744 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
745 796, 864, 0, 576, 581, 586, 625, 0,
746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
748 /* 19 - 1280x720@50Hz */
749 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
750 1760, 1980, 0, 720, 725, 730, 750, 0,
751 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 20 - 1920x1080i@50Hz */
754 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
755 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
757 DRM_MODE_FLAG_INTERLACE),
758 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 21 - 720(1440)x576i@50Hz */
760 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
761 795, 864, 0, 576, 580, 586, 625, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
764 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
765 /* 22 - 720(1440)x576i@50Hz */
766 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
767 795, 864, 0, 576, 580, 586, 625, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
771 /* 23 - 720(1440)x288@50Hz */
772 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
773 795, 864, 0, 288, 290, 293, 312, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_DBLCLK),
776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
777 /* 24 - 720(1440)x288@50Hz */
778 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
779 795, 864, 0, 288, 290, 293, 312, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_DBLCLK),
782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
783 /* 25 - 2880x576i@50Hz */
784 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
785 3180, 3456, 0, 576, 580, 586, 625, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_INTERLACE),
788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
789 /* 26 - 2880x576i@50Hz */
790 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
791 3180, 3456, 0, 576, 580, 586, 625, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
793 DRM_MODE_FLAG_INTERLACE),
794 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
795 /* 27 - 2880x288@50Hz */
796 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
797 3180, 3456, 0, 288, 290, 293, 312, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
799 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
800 /* 28 - 2880x288@50Hz */
801 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
802 3180, 3456, 0, 288, 290, 293, 312, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
804 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
805 /* 29 - 1440x576@50Hz */
806 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
807 1592, 1728, 0, 576, 581, 586, 625, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
810 /* 30 - 1440x576@50Hz */
811 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
812 1592, 1728, 0, 576, 581, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
815 /* 31 - 1920x1080@50Hz */
816 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
817 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 32 - 1920x1080@24Hz */
821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
822 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
824 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
825 /* 33 - 1920x1080@25Hz */
826 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
827 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
829 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
830 /* 34 - 1920x1080@30Hz */
831 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
832 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
834 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 35 - 2880x480@60Hz */
836 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
837 3192, 3432, 0, 480, 489, 495, 525, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
839 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
840 /* 36 - 2880x480@60Hz */
841 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
842 3192, 3432, 0, 480, 489, 495, 525, 0,
843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
844 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
845 /* 37 - 2880x576@50Hz */
846 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
847 3184, 3456, 0, 576, 581, 586, 625, 0,
848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
850 /* 38 - 2880x576@50Hz */
851 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
852 3184, 3456, 0, 576, 581, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
854 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
855 /* 39 - 1920x1080i@50Hz */
856 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
857 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
859 DRM_MODE_FLAG_INTERLACE),
860 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
861 /* 40 - 1920x1080i@100Hz */
862 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
863 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
865 DRM_MODE_FLAG_INTERLACE),
866 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
867 /* 41 - 1280x720@100Hz */
868 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
869 1760, 1980, 0, 720, 725, 730, 750, 0,
870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
871 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
872 /* 42 - 720x576@100Hz */
873 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
874 796, 864, 0, 576, 581, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
876 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877 /* 43 - 720x576@100Hz */
878 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
879 796, 864, 0, 576, 581, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
881 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 44 - 720(1440)x576i@100Hz */
883 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
884 795, 864, 0, 576, 580, 586, 625, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
886 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 45 - 720(1440)x576i@100Hz */
889 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
890 795, 864, 0, 576, 580, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
892 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
893 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 46 - 1920x1080i@120Hz */
895 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
896 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
898 DRM_MODE_FLAG_INTERLACE),
899 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 47 - 1280x720@120Hz */
901 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
902 1430, 1650, 0, 720, 725, 730, 750, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
904 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 48 - 720x480@120Hz */
906 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
907 798, 858, 0, 480, 489, 495, 525, 0,
908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
909 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
910 /* 49 - 720x480@120Hz */
911 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
912 798, 858, 0, 480, 489, 495, 525, 0,
913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
914 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 50 - 720(1440)x480i@120Hz */
916 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
917 801, 858, 0, 480, 488, 494, 525, 0,
918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
919 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
921 /* 51 - 720(1440)x480i@120Hz */
922 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
923 801, 858, 0, 480, 488, 494, 525, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
925 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
926 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
927 /* 52 - 720x576@200Hz */
928 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
929 796, 864, 0, 576, 581, 586, 625, 0,
930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
931 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
932 /* 53 - 720x576@200Hz */
933 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
934 796, 864, 0, 576, 581, 586, 625, 0,
935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
936 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 54 - 720(1440)x576i@200Hz */
938 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
939 795, 864, 0, 576, 580, 586, 625, 0,
940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
942 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
943 /* 55 - 720(1440)x576i@200Hz */
944 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
945 795, 864, 0, 576, 580, 586, 625, 0,
946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
947 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
948 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 56 - 720x480@240Hz */
950 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
951 798, 858, 0, 480, 489, 495, 525, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
953 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
954 /* 57 - 720x480@240Hz */
955 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
956 798, 858, 0, 480, 489, 495, 525, 0,
957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
958 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
959 /* 58 - 720(1440)x480i@240 */
960 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
961 801, 858, 0, 480, 488, 494, 525, 0,
962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
963 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
964 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
965 /* 59 - 720(1440)x480i@240 */
966 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
967 801, 858, 0, 480, 488, 494, 525, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
970 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
971 /* 60 - 1280x720@24Hz */
972 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
973 3080, 3300, 0, 720, 725, 730, 750, 0,
974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
975 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 61 - 1280x720@25Hz */
977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
978 3740, 3960, 0, 720, 725, 730, 750, 0,
979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
980 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 62 - 1280x720@30Hz */
982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
983 3080, 3300, 0, 720, 725, 730, 750, 0,
984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
986 /* 63 - 1920x1080@120Hz */
987 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
988 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
990 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 64 - 1920x1080@100Hz */
992 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
993 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
995 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
996 /* 65 - 1280x720@24Hz */
997 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
998 3080, 3300, 0, 720, 725, 730, 750, 0,
999 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1000 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1001 /* 66 - 1280x720@25Hz */
1002 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1003 3740, 3960, 0, 720, 725, 730, 750, 0,
1004 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1005 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1006 /* 67 - 1280x720@30Hz */
1007 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1008 3080, 3300, 0, 720, 725, 730, 750, 0,
1009 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1010 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1011 /* 68 - 1280x720@50Hz */
1012 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1013 1760, 1980, 0, 720, 725, 730, 750, 0,
1014 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1015 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1016 /* 69 - 1280x720@60Hz */
1017 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1018 1430, 1650, 0, 720, 725, 730, 750, 0,
1019 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1020 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1021 /* 70 - 1280x720@100Hz */
1022 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1023 1760, 1980, 0, 720, 725, 730, 750, 0,
1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1025 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1026 /* 71 - 1280x720@120Hz */
1027 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1028 1430, 1650, 0, 720, 725, 730, 750, 0,
1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1030 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1031 /* 72 - 1920x1080@24Hz */
1032 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1033 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1034 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1035 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1036 /* 73 - 1920x1080@25Hz */
1037 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1038 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1040 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1041 /* 74 - 1920x1080@30Hz */
1042 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1043 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1045 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1046 /* 75 - 1920x1080@50Hz */
1047 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1048 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1050 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1051 /* 76 - 1920x1080@60Hz */
1052 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1053 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1055 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1056 /* 77 - 1920x1080@100Hz */
1057 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1058 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1061 /* 78 - 1920x1080@120Hz */
1062 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1063 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1066 /* 79 - 1680x720@24Hz */
1067 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1068 3080, 3300, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1071 /* 80 - 1680x720@25Hz */
1072 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1073 2948, 3168, 0, 720, 725, 730, 750, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1076 /* 81 - 1680x720@30Hz */
1077 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1078 2420, 2640, 0, 720, 725, 730, 750, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1081 /* 82 - 1680x720@50Hz */
1082 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1083 1980, 2200, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 83 - 1680x720@60Hz */
1087 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1088 1980, 2200, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 84 - 1680x720@100Hz */
1092 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1093 1780, 2000, 0, 720, 725, 730, 825, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 85 - 1680x720@120Hz */
1097 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1098 1780, 2000, 0, 720, 725, 730, 825, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 86 - 2560x1080@24Hz */
1102 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1103 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 87 - 2560x1080@25Hz */
1107 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1108 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 88 - 2560x1080@30Hz */
1112 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1113 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 89 - 2560x1080@50Hz */
1117 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1118 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 90 - 2560x1080@60Hz */
1122 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1123 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 91 - 2560x1080@100Hz */
1127 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1128 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 92 - 2560x1080@120Hz */
1132 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1133 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 93 - 3840x2160p@24Hz 16:9 */
1137 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1138 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,},
1141 /* 94 - 3840x2160p@25Hz 16:9 */
1142 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1143 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1146 /* 95 - 3840x2160p@30Hz 16:9 */
1147 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1148 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1151 /* 96 - 3840x2160p@50Hz 16:9 */
1152 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1153 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1156 /* 97 - 3840x2160p@60Hz 16:9 */
1157 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1158 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1161 /* 98 - 4096x2160p@24Hz 256:135 */
1162 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1163 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1166 /* 99 - 4096x2160p@25Hz 256:135 */
1167 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1168 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1171 /* 100 - 4096x2160p@30Hz 256:135 */
1172 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1173 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1176 /* 101 - 4096x2160p@50Hz 256:135 */
1177 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1178 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1181 /* 102 - 4096x2160p@60Hz 256:135 */
1182 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1183 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1186 /* 103 - 3840x2160p@24Hz 64:27 */
1187 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1188 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1191 /* 104 - 3840x2160p@25Hz 64:27 */
1192 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1193 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1196 /* 105 - 3840x2160p@30Hz 64:27 */
1197 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1198 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1201 /* 106 - 3840x2160p@50Hz 64:27 */
1202 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1203 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1206 /* 107 - 3840x2160p@60Hz 64:27 */
1207 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1208 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1214 * HDMI 1.4 4k modes. Index using the VIC.
1216 static const struct drm_display_mode edid_4k_modes[] = {
1217 /* 0 - dummy, VICs start at 1 */
1219 /* 1 - 3840x2160@30Hz */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1221 3840, 4016, 4104, 4400, 0,
1222 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 /* 2 - 3840x2160@25Hz */
1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1227 3840, 4896, 4984, 5280, 0,
1228 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 /* 3 - 3840x2160@24Hz */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1233 3840, 5116, 5204, 5500, 0,
1234 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 /* 4 - 4096x2160@24Hz (SMPTE) */
1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1239 4096, 5116, 5204, 5500, 0,
1240 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 /* 5 - 3840x2160@60Hz */
1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000,
1245 3840, 4016, 4104, 4400, 0,
1246 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1251 /*** DDC fetch and block validation ***/
1253 static const u8 edid_header[] = {
1254 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1258 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1259 * @raw_edid: pointer to raw base EDID block
1261 * Sanity check the header of the base EDID block.
1263 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1265 int drm_edid_header_is_valid(const u8 *raw_edid)
1269 for (i = 0; i < sizeof(edid_header); i++)
1270 if (raw_edid[i] == edid_header[i])
1275 EXPORT_SYMBOL(drm_edid_header_is_valid);
1277 static int edid_fixup __read_mostly = 6;
1278 module_param_named(edid_fixup, edid_fixup, int, 0400);
1279 MODULE_PARM_DESC(edid_fixup,
1280 "Minimum number of valid EDID header bytes (0-8, default 6)");
1282 static void drm_get_displayid(struct drm_connector *connector,
1285 static int drm_edid_block_checksum(const u8 *raw_edid)
1289 for (i = 0; i < EDID_LENGTH; i++)
1290 csum += raw_edid[i];
1295 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1297 if (memchr_inv(in_edid, 0, length))
1304 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1305 * @raw_edid: pointer to raw EDID block
1306 * @block: type of block to validate (0 for base, extension otherwise)
1307 * @print_bad_edid: if true, dump bad EDID blocks to the console
1308 * @edid_corrupt: if true, the header or checksum is invalid
1310 * Validate a base or extension EDID block and optionally dump bad blocks to
1313 * Return: True if the block is valid, false otherwise.
1315 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1319 struct edid *edid = (struct edid *)raw_edid;
1321 if (WARN_ON(!raw_edid))
1324 if (edid_fixup > 8 || edid_fixup < 0)
1328 int score = drm_edid_header_is_valid(raw_edid);
1331 *edid_corrupt = false;
1332 } else if (score >= edid_fixup) {
1333 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1334 * The corrupt flag needs to be set here otherwise, the
1335 * fix-up code here will correct the problem, the
1336 * checksum is correct and the test fails
1339 *edid_corrupt = true;
1340 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1341 memcpy(raw_edid, edid_header, sizeof(edid_header));
1344 *edid_corrupt = true;
1349 csum = drm_edid_block_checksum(raw_edid);
1351 if (print_bad_edid) {
1352 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1356 *edid_corrupt = true;
1358 /* allow CEA to slide through, switches mangle this */
1359 if (raw_edid[0] != 0x02)
1363 /* per-block-type checks */
1364 switch (raw_edid[0]) {
1366 if (edid->version != 1) {
1367 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1371 if (edid->revision > 4)
1372 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1382 if (print_bad_edid) {
1383 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1384 printk(KERN_ERR "EDID block is all zeroes\n");
1386 printk(KERN_ERR "Raw EDID:\n");
1387 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1388 raw_edid, EDID_LENGTH, false);
1393 EXPORT_SYMBOL(drm_edid_block_valid);
1396 * drm_edid_is_valid - sanity check EDID data
1399 * Sanity-check an entire EDID record (including extensions)
1401 * Return: True if the EDID data is valid, false otherwise.
1403 bool drm_edid_is_valid(struct edid *edid)
1406 u8 *raw = (u8 *)edid;
1411 for (i = 0; i <= edid->extensions; i++)
1412 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1417 EXPORT_SYMBOL(drm_edid_is_valid);
1419 #define DDC_SEGMENT_ADDR 0x30
1421 * drm_do_probe_ddc_edid() - get EDID information via I2C
1422 * @data: I2C device adapter
1423 * @buf: EDID data buffer to be filled
1424 * @block: 128 byte EDID block to start fetching from
1425 * @len: EDID data buffer length to fetch
1427 * Try to fetch EDID information by calling I2C driver functions.
1429 * Return: 0 on success or -1 on failure.
1432 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1434 struct i2c_adapter *adapter = data;
1435 unsigned char start = block * EDID_LENGTH;
1436 unsigned char segment = block >> 1;
1437 unsigned char xfers = segment ? 3 : 2;
1438 int ret, retries = 5;
1441 * The core I2C driver will automatically retry the transfer if the
1442 * adapter reports EAGAIN. However, we find that bit-banging transfers
1443 * are susceptible to errors under a heavily loaded machine and
1444 * generate spurious NAKs and timeouts. Retrying the transfer
1445 * of the individual block a few times seems to overcome this.
1448 struct i2c_msg msgs[] = {
1450 .addr = DDC_SEGMENT_ADDR,
1468 * Avoid sending the segment addr to not upset non-compliant
1471 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1473 if (ret == -ENXIO) {
1474 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1478 } while (ret != xfers && --retries);
1480 return ret == xfers ? 0 : -1;
1484 * drm_do_get_edid - get EDID data using a custom EDID block read function
1485 * @connector: connector we're probing
1486 * @get_edid_block: EDID block read function
1487 * @data: private data passed to the block read function
1489 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1490 * exposes a different interface to read EDID blocks this function can be used
1491 * to get EDID data using a custom block read function.
1493 * As in the general case the DDC bus is accessible by the kernel at the I2C
1494 * level, drivers must make all reasonable efforts to expose it as an I2C
1495 * adapter and use drm_get_edid() instead of abusing this function.
1497 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1499 struct edid *drm_do_get_edid(struct drm_connector *connector,
1500 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1504 int i, j = 0, valid_extensions = 0;
1506 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1508 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1511 /* base block fetch */
1512 for (i = 0; i < 4; i++) {
1513 if (get_edid_block(data, block, 0, EDID_LENGTH))
1515 if (drm_edid_block_valid(block, 0, print_bad_edid,
1516 &connector->edid_corrupt))
1518 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1519 connector->null_edid_counter++;
1526 /* if there's no extensions, we're done */
1527 if (block[0x7e] == 0)
1528 return (struct edid *)block;
1530 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1535 for (j = 1; j <= block[0x7e]; j++) {
1536 for (i = 0; i < 4; i++) {
1537 if (get_edid_block(data,
1538 block + (valid_extensions + 1) * EDID_LENGTH,
1541 if (drm_edid_block_valid(block + (valid_extensions + 1)
1550 if (i == 4 && print_bad_edid) {
1551 dev_warn(connector->dev->dev,
1552 "%s: Ignoring invalid EDID block %d.\n",
1553 connector->name, j);
1555 connector->bad_edid_counter++;
1559 if (valid_extensions != block[0x7e]) {
1560 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1561 block[0x7e] = valid_extensions;
1562 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1568 return (struct edid *)block;
1571 if (print_bad_edid) {
1572 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1573 connector->name, j);
1575 connector->bad_edid_counter++;
1581 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1584 * drm_probe_ddc() - probe DDC presence
1585 * @adapter: I2C adapter to probe
1587 * Return: True on success, false on failure.
1590 drm_probe_ddc(struct i2c_adapter *adapter)
1594 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1596 EXPORT_SYMBOL(drm_probe_ddc);
1599 * drm_get_edid - get EDID data, if available
1600 * @connector: connector we're probing
1601 * @adapter: I2C adapter to use for DDC
1603 * Poke the given I2C channel to grab EDID data if possible. If found,
1604 * attach it to the connector.
1606 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1608 struct edid *drm_get_edid(struct drm_connector *connector,
1609 struct i2c_adapter *adapter)
1613 if (!drm_probe_ddc(adapter))
1616 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1618 drm_get_displayid(connector, edid);
1621 EXPORT_SYMBOL(drm_get_edid);
1624 * drm_edid_duplicate - duplicate an EDID and the extensions
1625 * @edid: EDID to duplicate
1627 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1629 struct edid *drm_edid_duplicate(const struct edid *edid)
1631 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1633 EXPORT_SYMBOL(drm_edid_duplicate);
1635 /*** EDID parsing ***/
1638 * edid_vendor - match a string against EDID's obfuscated vendor field
1639 * @edid: EDID to match
1640 * @vendor: vendor string
1642 * Returns true if @vendor is in @edid, false otherwise
1644 static bool edid_vendor(struct edid *edid, char *vendor)
1646 char edid_vendor[3];
1648 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1649 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1650 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1651 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1653 return !strncmp(edid_vendor, vendor, 3);
1657 * edid_get_quirks - return quirk flags for a given EDID
1658 * @edid: EDID to process
1660 * This tells subsequent routines what fixes they need to apply.
1662 static u32 edid_get_quirks(struct edid *edid)
1664 struct edid_quirk *quirk;
1667 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1668 quirk = &edid_quirk_list[i];
1670 if (edid_vendor(edid, quirk->vendor) &&
1671 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1672 return quirk->quirks;
1678 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1679 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1682 * edid_fixup_preferred - set preferred modes based on quirk list
1683 * @connector: has mode list to fix up
1684 * @quirks: quirks list
1686 * Walk the mode list for @connector, clearing the preferred status
1687 * on existing modes and setting it anew for the right mode ala @quirks.
1689 static void edid_fixup_preferred(struct drm_connector *connector,
1692 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1693 int target_refresh = 0;
1694 int cur_vrefresh, preferred_vrefresh;
1696 if (list_empty(&connector->probed_modes))
1699 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1700 target_refresh = 60;
1701 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1702 target_refresh = 75;
1704 preferred_mode = list_first_entry(&connector->probed_modes,
1705 struct drm_display_mode, head);
1707 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1708 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1710 if (cur_mode == preferred_mode)
1713 /* Largest mode is preferred */
1714 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1715 preferred_mode = cur_mode;
1717 cur_vrefresh = cur_mode->vrefresh ?
1718 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1719 preferred_vrefresh = preferred_mode->vrefresh ?
1720 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1721 /* At a given size, try to get closest to target refresh */
1722 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1723 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1724 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1725 preferred_mode = cur_mode;
1729 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1733 mode_is_rb(const struct drm_display_mode *mode)
1735 return (mode->htotal - mode->hdisplay == 160) &&
1736 (mode->hsync_end - mode->hdisplay == 80) &&
1737 (mode->hsync_end - mode->hsync_start == 32) &&
1738 (mode->vsync_start - mode->vdisplay == 3);
1742 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1743 * @dev: Device to duplicate against
1744 * @hsize: Mode width
1745 * @vsize: Mode height
1746 * @fresh: Mode refresh rate
1747 * @rb: Mode reduced-blanking-ness
1749 * Walk the DMT mode list looking for a match for the given parameters.
1751 * Return: A newly allocated copy of the mode, or NULL if not found.
1753 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1754 int hsize, int vsize, int fresh,
1759 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1760 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1761 if (hsize != ptr->hdisplay)
1763 if (vsize != ptr->vdisplay)
1765 if (fresh != drm_mode_vrefresh(ptr))
1767 if (rb != mode_is_rb(ptr))
1770 return drm_mode_duplicate(dev, ptr);
1775 EXPORT_SYMBOL(drm_mode_find_dmt);
1777 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1780 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1784 u8 *det_base = ext + d;
1787 for (i = 0; i < n; i++)
1788 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1792 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1794 unsigned int i, n = min((int)ext[0x02], 6);
1795 u8 *det_base = ext + 5;
1798 return; /* unknown version */
1800 for (i = 0; i < n; i++)
1801 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1805 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1808 struct edid *edid = (struct edid *)raw_edid;
1813 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1814 cb(&(edid->detailed_timings[i]), closure);
1816 for (i = 1; i <= raw_edid[0x7e]; i++) {
1817 u8 *ext = raw_edid + (i * EDID_LENGTH);
1820 cea_for_each_detailed_block(ext, cb, closure);
1823 vtb_for_each_detailed_block(ext, cb, closure);
1832 is_rb(struct detailed_timing *t, void *data)
1835 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1837 *(bool *)data = true;
1840 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1842 drm_monitor_supports_rb(struct edid *edid)
1844 if (edid->revision >= 4) {
1846 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1850 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1854 find_gtf2(struct detailed_timing *t, void *data)
1857 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1861 /* Secondary GTF curve kicks in above some break frequency */
1863 drm_gtf2_hbreak(struct edid *edid)
1866 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1867 return r ? (r[12] * 2) : 0;
1871 drm_gtf2_2c(struct edid *edid)
1874 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1875 return r ? r[13] : 0;
1879 drm_gtf2_m(struct edid *edid)
1882 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1883 return r ? (r[15] << 8) + r[14] : 0;
1887 drm_gtf2_k(struct edid *edid)
1890 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1891 return r ? r[16] : 0;
1895 drm_gtf2_2j(struct edid *edid)
1898 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1899 return r ? r[17] : 0;
1903 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1904 * @edid: EDID block to scan
1906 static int standard_timing_level(struct edid *edid)
1908 if (edid->revision >= 2) {
1909 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1911 if (drm_gtf2_hbreak(edid))
1919 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1920 * monitors fill with ascii space (0x20) instead.
1923 bad_std_timing(u8 a, u8 b)
1925 return (a == 0x00 && b == 0x00) ||
1926 (a == 0x01 && b == 0x01) ||
1927 (a == 0x20 && b == 0x20);
1931 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1932 * @connector: connector of for the EDID block
1933 * @edid: EDID block to scan
1934 * @t: standard timing params
1936 * Take the standard timing params (in this case width, aspect, and refresh)
1937 * and convert them into a real mode using CVT/GTF/DMT.
1939 static struct drm_display_mode *
1940 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1941 struct std_timing *t)
1943 struct drm_device *dev = connector->dev;
1944 struct drm_display_mode *m, *mode = NULL;
1947 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1948 >> EDID_TIMING_ASPECT_SHIFT;
1949 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1950 >> EDID_TIMING_VFREQ_SHIFT;
1951 int timing_level = standard_timing_level(edid);
1953 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1956 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1957 hsize = t->hsize * 8 + 248;
1958 /* vrefresh_rate = vfreq + 60 */
1959 vrefresh_rate = vfreq + 60;
1960 /* the vdisplay is calculated based on the aspect ratio */
1961 if (aspect_ratio == 0) {
1962 if (edid->revision < 3)
1965 vsize = (hsize * 10) / 16;
1966 } else if (aspect_ratio == 1)
1967 vsize = (hsize * 3) / 4;
1968 else if (aspect_ratio == 2)
1969 vsize = (hsize * 4) / 5;
1971 vsize = (hsize * 9) / 16;
1973 /* HDTV hack, part 1 */
1974 if (vrefresh_rate == 60 &&
1975 ((hsize == 1360 && vsize == 765) ||
1976 (hsize == 1368 && vsize == 769))) {
1982 * If this connector already has a mode for this size and refresh
1983 * rate (because it came from detailed or CVT info), use that
1984 * instead. This way we don't have to guess at interlace or
1987 list_for_each_entry(m, &connector->probed_modes, head)
1988 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1989 drm_mode_vrefresh(m) == vrefresh_rate)
1992 /* HDTV hack, part 2 */
1993 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1994 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1996 mode->hdisplay = 1366;
1997 mode->hsync_start = mode->hsync_start - 1;
1998 mode->hsync_end = mode->hsync_end - 1;
2002 /* check whether it can be found in default mode table */
2003 if (drm_monitor_supports_rb(edid)) {
2004 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2009 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2013 /* okay, generate it */
2014 switch (timing_level) {
2018 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2022 * This is potentially wrong if there's ever a monitor with
2023 * more than one ranges section, each claiming a different
2024 * secondary GTF curve. Please don't do that.
2026 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2029 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2030 drm_mode_destroy(dev, mode);
2031 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2032 vrefresh_rate, 0, 0,
2040 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2048 * EDID is delightfully ambiguous about how interlaced modes are to be
2049 * encoded. Our internal representation is of frame height, but some
2050 * HDTV detailed timings are encoded as field height.
2052 * The format list here is from CEA, in frame size. Technically we
2053 * should be checking refresh rate too. Whatever.
2056 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2057 struct detailed_pixel_timing *pt)
2060 static const struct {
2062 } cea_interlaced[] = {
2072 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2075 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2076 if ((mode->hdisplay == cea_interlaced[i].w) &&
2077 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2078 mode->vdisplay *= 2;
2079 mode->vsync_start *= 2;
2080 mode->vsync_end *= 2;
2086 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2090 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2091 * @dev: DRM device (needed to create new mode)
2093 * @timing: EDID detailed timing info
2094 * @quirks: quirks to apply
2096 * An EDID detailed timing block contains enough info for us to create and
2097 * return a new struct drm_display_mode.
2099 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2101 struct detailed_timing *timing,
2104 struct drm_display_mode *mode;
2105 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2106 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2107 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2108 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2109 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2110 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2111 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2112 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2113 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2115 /* ignore tiny modes */
2116 if (hactive < 64 || vactive < 64)
2119 if (pt->misc & DRM_EDID_PT_STEREO) {
2120 DRM_DEBUG_KMS("stereo mode not supported\n");
2123 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2124 DRM_DEBUG_KMS("composite sync not supported\n");
2127 /* it is incorrect if hsync/vsync width is zero */
2128 if (!hsync_pulse_width || !vsync_pulse_width) {
2129 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2130 "Wrong Hsync/Vsync pulse width\n");
2134 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2135 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2142 mode = drm_mode_create(dev);
2146 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2147 timing->pixel_clock = cpu_to_le16(1088);
2149 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2151 mode->hdisplay = hactive;
2152 mode->hsync_start = mode->hdisplay + hsync_offset;
2153 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2154 mode->htotal = mode->hdisplay + hblank;
2156 mode->vdisplay = vactive;
2157 mode->vsync_start = mode->vdisplay + vsync_offset;
2158 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2159 mode->vtotal = mode->vdisplay + vblank;
2161 /* Some EDIDs have bogus h/vtotal values */
2162 if (mode->hsync_end > mode->htotal)
2163 mode->htotal = mode->hsync_end + 1;
2164 if (mode->vsync_end > mode->vtotal)
2165 mode->vtotal = mode->vsync_end + 1;
2167 drm_mode_do_interlace_quirk(mode, pt);
2169 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2170 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2173 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2174 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2175 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2176 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2179 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2180 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2182 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2183 mode->width_mm *= 10;
2184 mode->height_mm *= 10;
2187 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2188 mode->width_mm = edid->width_cm * 10;
2189 mode->height_mm = edid->height_cm * 10;
2192 mode->type = DRM_MODE_TYPE_DRIVER;
2193 mode->vrefresh = drm_mode_vrefresh(mode);
2194 drm_mode_set_name(mode);
2200 mode_in_hsync_range(const struct drm_display_mode *mode,
2201 struct edid *edid, u8 *t)
2203 int hsync, hmin, hmax;
2206 if (edid->revision >= 4)
2207 hmin += ((t[4] & 0x04) ? 255 : 0);
2209 if (edid->revision >= 4)
2210 hmax += ((t[4] & 0x08) ? 255 : 0);
2211 hsync = drm_mode_hsync(mode);
2213 return (hsync <= hmax && hsync >= hmin);
2217 mode_in_vsync_range(const struct drm_display_mode *mode,
2218 struct edid *edid, u8 *t)
2220 int vsync, vmin, vmax;
2223 if (edid->revision >= 4)
2224 vmin += ((t[4] & 0x01) ? 255 : 0);
2226 if (edid->revision >= 4)
2227 vmax += ((t[4] & 0x02) ? 255 : 0);
2228 vsync = drm_mode_vrefresh(mode);
2230 return (vsync <= vmax && vsync >= vmin);
2234 range_pixel_clock(struct edid *edid, u8 *t)
2237 if (t[9] == 0 || t[9] == 255)
2240 /* 1.4 with CVT support gives us real precision, yay */
2241 if (edid->revision >= 4 && t[10] == 0x04)
2242 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2244 /* 1.3 is pathetic, so fuzz up a bit */
2245 return t[9] * 10000 + 5001;
2249 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2250 struct detailed_timing *timing)
2253 u8 *t = (u8 *)timing;
2255 if (!mode_in_hsync_range(mode, edid, t))
2258 if (!mode_in_vsync_range(mode, edid, t))
2261 if ((max_clock = range_pixel_clock(edid, t)))
2262 if (mode->clock > max_clock)
2265 /* 1.4 max horizontal check */
2266 if (edid->revision >= 4 && t[10] == 0x04)
2267 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2270 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2276 static bool valid_inferred_mode(const struct drm_connector *connector,
2277 const struct drm_display_mode *mode)
2279 const struct drm_display_mode *m;
2282 list_for_each_entry(m, &connector->probed_modes, head) {
2283 if (mode->hdisplay == m->hdisplay &&
2284 mode->vdisplay == m->vdisplay &&
2285 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2286 return false; /* duplicated */
2287 if (mode->hdisplay <= m->hdisplay &&
2288 mode->vdisplay <= m->vdisplay)
2295 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2296 struct detailed_timing *timing)
2299 struct drm_display_mode *newmode;
2300 struct drm_device *dev = connector->dev;
2302 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2303 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2304 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2305 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2307 drm_mode_probed_add(connector, newmode);
2316 /* fix up 1366x768 mode from 1368x768;
2317 * GFT/CVT can't express 1366 width which isn't dividable by 8
2319 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2321 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2322 mode->hdisplay = 1366;
2323 mode->hsync_start--;
2325 drm_mode_set_name(mode);
2330 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2331 struct detailed_timing *timing)
2334 struct drm_display_mode *newmode;
2335 struct drm_device *dev = connector->dev;
2337 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2338 const struct minimode *m = &extra_modes[i];
2339 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2343 fixup_mode_1366x768(newmode);
2344 if (!mode_in_range(newmode, edid, timing) ||
2345 !valid_inferred_mode(connector, newmode)) {
2346 drm_mode_destroy(dev, newmode);
2350 drm_mode_probed_add(connector, newmode);
2358 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2359 struct detailed_timing *timing)
2362 struct drm_display_mode *newmode;
2363 struct drm_device *dev = connector->dev;
2364 bool rb = drm_monitor_supports_rb(edid);
2366 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2367 const struct minimode *m = &extra_modes[i];
2368 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2372 fixup_mode_1366x768(newmode);
2373 if (!mode_in_range(newmode, edid, timing) ||
2374 !valid_inferred_mode(connector, newmode)) {
2375 drm_mode_destroy(dev, newmode);
2379 drm_mode_probed_add(connector, newmode);
2387 do_inferred_modes(struct detailed_timing *timing, void *c)
2389 struct detailed_mode_closure *closure = c;
2390 struct detailed_non_pixel *data = &timing->data.other_data;
2391 struct detailed_data_monitor_range *range = &data->data.range;
2393 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2396 closure->modes += drm_dmt_modes_for_range(closure->connector,
2400 if (!version_greater(closure->edid, 1, 1))
2401 return; /* GTF not defined yet */
2403 switch (range->flags) {
2404 case 0x02: /* secondary gtf, XXX could do more */
2405 case 0x00: /* default gtf */
2406 closure->modes += drm_gtf_modes_for_range(closure->connector,
2410 case 0x04: /* cvt, only in 1.4+ */
2411 if (!version_greater(closure->edid, 1, 3))
2414 closure->modes += drm_cvt_modes_for_range(closure->connector,
2418 case 0x01: /* just the ranges, no formula */
2425 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2427 struct detailed_mode_closure closure = {
2428 .connector = connector,
2432 if (version_greater(edid, 1, 0))
2433 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2436 return closure.modes;
2440 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2442 int i, j, m, modes = 0;
2443 struct drm_display_mode *mode;
2444 u8 *est = ((u8 *)timing) + 5;
2446 for (i = 0; i < 6; i++) {
2447 for (j = 7; j >= 0; j--) {
2448 m = (i * 8) + (7 - j);
2449 if (m >= ARRAY_SIZE(est3_modes))
2451 if (est[i] & (1 << j)) {
2452 mode = drm_mode_find_dmt(connector->dev,
2458 drm_mode_probed_add(connector, mode);
2469 do_established_modes(struct detailed_timing *timing, void *c)
2471 struct detailed_mode_closure *closure = c;
2472 struct detailed_non_pixel *data = &timing->data.other_data;
2474 if (data->type == EDID_DETAIL_EST_TIMINGS)
2475 closure->modes += drm_est3_modes(closure->connector, timing);
2479 * add_established_modes - get est. modes from EDID and add them
2480 * @connector: connector to add mode(s) to
2481 * @edid: EDID block to scan
2483 * Each EDID block contains a bitmap of the supported "established modes" list
2484 * (defined above). Tease them out and add them to the global modes list.
2487 add_established_modes(struct drm_connector *connector, struct edid *edid)
2489 struct drm_device *dev = connector->dev;
2490 unsigned long est_bits = edid->established_timings.t1 |
2491 (edid->established_timings.t2 << 8) |
2492 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2494 struct detailed_mode_closure closure = {
2495 .connector = connector,
2499 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2500 if (est_bits & (1<<i)) {
2501 struct drm_display_mode *newmode;
2502 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2504 drm_mode_probed_add(connector, newmode);
2510 if (version_greater(edid, 1, 0))
2511 drm_for_each_detailed_block((u8 *)edid,
2512 do_established_modes, &closure);
2514 return modes + closure.modes;
2518 do_standard_modes(struct detailed_timing *timing, void *c)
2520 struct detailed_mode_closure *closure = c;
2521 struct detailed_non_pixel *data = &timing->data.other_data;
2522 struct drm_connector *connector = closure->connector;
2523 struct edid *edid = closure->edid;
2525 if (data->type == EDID_DETAIL_STD_MODES) {
2527 for (i = 0; i < 6; i++) {
2528 struct std_timing *std;
2529 struct drm_display_mode *newmode;
2531 std = &data->data.timings[i];
2532 newmode = drm_mode_std(connector, edid, std);
2534 drm_mode_probed_add(connector, newmode);
2542 * add_standard_modes - get std. modes from EDID and add them
2543 * @connector: connector to add mode(s) to
2544 * @edid: EDID block to scan
2546 * Standard modes can be calculated using the appropriate standard (DMT,
2547 * GTF or CVT. Grab them from @edid and add them to the list.
2550 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2553 struct detailed_mode_closure closure = {
2554 .connector = connector,
2558 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2559 struct drm_display_mode *newmode;
2561 newmode = drm_mode_std(connector, edid,
2562 &edid->standard_timings[i]);
2564 drm_mode_probed_add(connector, newmode);
2569 if (version_greater(edid, 1, 0))
2570 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2573 /* XXX should also look for standard codes in VTB blocks */
2575 return modes + closure.modes;
2578 static int drm_cvt_modes(struct drm_connector *connector,
2579 struct detailed_timing *timing)
2581 int i, j, modes = 0;
2582 struct drm_display_mode *newmode;
2583 struct drm_device *dev = connector->dev;
2584 struct cvt_timing *cvt;
2585 const int rates[] = { 60, 85, 75, 60, 50 };
2586 const u8 empty[3] = { 0, 0, 0 };
2588 for (i = 0; i < 4; i++) {
2589 int uninitialized_var(width), height;
2590 cvt = &(timing->data.other_data.data.cvt[i]);
2592 if (!memcmp(cvt->code, empty, 3))
2595 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2596 switch (cvt->code[1] & 0x0c) {
2598 width = height * 4 / 3;
2601 width = height * 16 / 9;
2604 width = height * 16 / 10;
2607 width = height * 15 / 9;
2611 for (j = 1; j < 5; j++) {
2612 if (cvt->code[2] & (1 << j)) {
2613 newmode = drm_cvt_mode(dev, width, height,
2617 drm_mode_probed_add(connector, newmode);
2628 do_cvt_mode(struct detailed_timing *timing, void *c)
2630 struct detailed_mode_closure *closure = c;
2631 struct detailed_non_pixel *data = &timing->data.other_data;
2633 if (data->type == EDID_DETAIL_CVT_3BYTE)
2634 closure->modes += drm_cvt_modes(closure->connector, timing);
2638 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2640 struct detailed_mode_closure closure = {
2641 .connector = connector,
2645 if (version_greater(edid, 1, 2))
2646 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2648 /* XXX should also look for CVT codes in VTB blocks */
2650 return closure.modes;
2653 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2656 do_detailed_mode(struct detailed_timing *timing, void *c)
2658 struct detailed_mode_closure *closure = c;
2659 struct drm_display_mode *newmode;
2661 if (timing->pixel_clock) {
2662 newmode = drm_mode_detailed(closure->connector->dev,
2663 closure->edid, timing,
2668 if (closure->preferred)
2669 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2672 * Detailed modes are limited to 10kHz pixel clock resolution,
2673 * so fix up anything that looks like CEA/HDMI mode, but the clock
2674 * is just slightly off.
2676 fixup_detailed_cea_mode_clock(newmode);
2678 drm_mode_probed_add(closure->connector, newmode);
2680 closure->preferred = 0;
2685 * add_detailed_modes - Add modes from detailed timings
2686 * @connector: attached connector
2687 * @edid: EDID block to scan
2688 * @quirks: quirks to apply
2691 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2694 struct detailed_mode_closure closure = {
2695 .connector = connector,
2701 if (closure.preferred && !version_greater(edid, 1, 3))
2703 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2705 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2707 return closure.modes;
2710 #define AUDIO_BLOCK 0x01
2711 #define VIDEO_BLOCK 0x02
2712 #define VENDOR_BLOCK 0x03
2713 #define SPEAKER_BLOCK 0x04
2714 #define VIDEO_CAPABILITY_BLOCK 0x07
2715 #define EDID_BASIC_AUDIO (1 << 6)
2716 #define EDID_CEA_YCRCB444 (1 << 5)
2717 #define EDID_CEA_YCRCB422 (1 << 4)
2718 #define EDID_CEA_VCDB_QS (1 << 6)
2721 * Search EDID for CEA extension block.
2723 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2725 u8 *edid_ext = NULL;
2728 /* No EDID or EDID extensions */
2729 if (edid == NULL || edid->extensions == 0)
2732 /* Find CEA extension */
2733 for (i = 0; i < edid->extensions; i++) {
2734 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2735 if (edid_ext[0] == ext_id)
2739 if (i == edid->extensions)
2745 static u8 *drm_find_cea_extension(struct edid *edid)
2747 return drm_find_edid_extension(edid, CEA_EXT);
2750 static u8 *drm_find_displayid_extension(struct edid *edid)
2752 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2756 * Calculate the alternate clock for the CEA mode
2757 * (60Hz vs. 59.94Hz etc.)
2760 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2762 unsigned int clock = cea_mode->clock;
2764 if (cea_mode->vrefresh % 6 != 0)
2768 * edid_cea_modes contains the 59.94Hz
2769 * variant for 240 and 480 line modes,
2770 * and the 60Hz variant otherwise.
2772 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2773 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2775 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2780 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2781 unsigned int clock_tolerance)
2785 if (!to_match->clock)
2788 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2789 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2790 unsigned int clock1, clock2;
2792 /* Check both 60Hz and 59.94Hz */
2793 clock1 = cea_mode->clock;
2794 clock2 = cea_mode_alternate_clock(cea_mode);
2796 if (abs(to_match->clock - clock1) > clock_tolerance &&
2797 abs(to_match->clock - clock2) > clock_tolerance)
2800 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2808 * drm_match_cea_mode - look for a CEA mode matching given mode
2809 * @to_match: display mode
2811 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2814 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2818 if (!to_match->clock)
2821 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2822 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2823 unsigned int clock1, clock2;
2825 /* Check both 60Hz and 59.94Hz */
2826 clock1 = cea_mode->clock;
2827 clock2 = cea_mode_alternate_clock(cea_mode);
2829 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2830 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2831 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2836 EXPORT_SYMBOL(drm_match_cea_mode);
2838 static bool drm_valid_cea_vic(u8 vic)
2840 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2844 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2845 * the input VIC from the CEA mode list
2846 * @video_code: ID given to each of the CEA modes
2848 * Returns picture aspect ratio
2850 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2852 return edid_cea_modes[video_code].picture_aspect_ratio;
2854 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2857 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2860 * It's almost like cea_mode_alternate_clock(), we just need to add an
2861 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2865 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2867 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2868 return hdmi_mode->clock;
2870 return cea_mode_alternate_clock(hdmi_mode);
2873 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2874 unsigned int clock_tolerance)
2878 if (!to_match->clock)
2881 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2882 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2883 unsigned int clock1, clock2;
2885 /* Make sure to also match alternate clocks */
2886 clock1 = hdmi_mode->clock;
2887 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2889 if (abs(to_match->clock - clock1) > clock_tolerance &&
2890 abs(to_match->clock - clock2) > clock_tolerance)
2893 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2901 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2902 * @to_match: display mode
2904 * An HDMI mode is one defined in the HDMI vendor specific block.
2906 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2908 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2912 if (!to_match->clock)
2915 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2916 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2917 unsigned int clock1, clock2;
2919 /* Make sure to also match alternate clocks */
2920 clock1 = hdmi_mode->clock;
2921 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2923 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2924 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2925 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2931 static bool drm_valid_hdmi_vic(u8 vic)
2933 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2937 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2939 struct drm_device *dev = connector->dev;
2940 struct drm_display_mode *mode, *tmp;
2944 /* Don't add CEA modes if the CEA extension block is missing */
2945 if (!drm_find_cea_extension(edid))
2949 * Go through all probed modes and create a new mode
2950 * with the alternate clock for certain CEA modes.
2952 list_for_each_entry(mode, &connector->probed_modes, head) {
2953 const struct drm_display_mode *cea_mode = NULL;
2954 struct drm_display_mode *newmode;
2955 u8 vic = drm_match_cea_mode(mode);
2956 unsigned int clock1, clock2;
2958 if (drm_valid_cea_vic(vic)) {
2959 cea_mode = &edid_cea_modes[vic];
2960 clock2 = cea_mode_alternate_clock(cea_mode);
2962 vic = drm_match_hdmi_mode(mode);
2963 if (drm_valid_hdmi_vic(vic)) {
2964 cea_mode = &edid_4k_modes[vic];
2965 clock2 = hdmi_mode_alternate_clock(cea_mode);
2972 clock1 = cea_mode->clock;
2974 if (clock1 == clock2)
2977 if (mode->clock != clock1 && mode->clock != clock2)
2980 newmode = drm_mode_duplicate(dev, cea_mode);
2984 /* Carry over the stereo flags */
2985 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2988 * The current mode could be either variant. Make
2989 * sure to pick the "other" clock for the new mode.
2991 if (mode->clock != clock1)
2992 newmode->clock = clock1;
2994 newmode->clock = clock2;
2996 list_add_tail(&newmode->head, &list);
2999 list_for_each_entry_safe(mode, tmp, &list, head) {
3000 list_del(&mode->head);
3001 drm_mode_probed_add(connector, mode);
3008 static struct drm_display_mode *
3009 drm_display_mode_from_vic_index(struct drm_connector *connector,
3010 const u8 *video_db, u8 video_len,
3013 struct drm_device *dev = connector->dev;
3014 struct drm_display_mode *newmode;
3017 if (video_db == NULL || video_index >= video_len)
3020 /* CEA modes are numbered 1..127 */
3021 vic = (video_db[video_index] & 127);
3022 if (!drm_valid_cea_vic(vic))
3025 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3029 newmode->vrefresh = 0;
3035 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3039 for (i = 0; i < len; i++) {
3040 struct drm_display_mode *mode;
3041 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3043 drm_mode_probed_add(connector, mode);
3051 struct stereo_mandatory_mode {
3052 int width, height, vrefresh;
3056 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3057 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3058 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3060 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3063 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3064 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3065 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3066 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3070 stereo_match_mandatory(const struct drm_display_mode *mode,
3071 const struct stereo_mandatory_mode *stereo_mode)
3073 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3075 return mode->hdisplay == stereo_mode->width &&
3076 mode->vdisplay == stereo_mode->height &&
3077 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3078 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3081 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3083 struct drm_device *dev = connector->dev;
3084 const struct drm_display_mode *mode;
3085 struct list_head stereo_modes;
3088 INIT_LIST_HEAD(&stereo_modes);
3090 list_for_each_entry(mode, &connector->probed_modes, head) {
3091 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3092 const struct stereo_mandatory_mode *mandatory;
3093 struct drm_display_mode *new_mode;
3095 if (!stereo_match_mandatory(mode,
3096 &stereo_mandatory_modes[i]))
3099 mandatory = &stereo_mandatory_modes[i];
3100 new_mode = drm_mode_duplicate(dev, mode);
3104 new_mode->flags |= mandatory->flags;
3105 list_add_tail(&new_mode->head, &stereo_modes);
3110 list_splice_tail(&stereo_modes, &connector->probed_modes);
3115 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3117 struct drm_device *dev = connector->dev;
3118 struct drm_display_mode *newmode;
3120 if (!drm_valid_hdmi_vic(vic)) {
3121 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3125 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3129 drm_mode_probed_add(connector, newmode);
3134 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3135 const u8 *video_db, u8 video_len, u8 video_index)
3137 struct drm_display_mode *newmode;
3140 if (structure & (1 << 0)) {
3141 newmode = drm_display_mode_from_vic_index(connector, video_db,
3145 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3146 drm_mode_probed_add(connector, newmode);
3150 if (structure & (1 << 6)) {
3151 newmode = drm_display_mode_from_vic_index(connector, video_db,
3155 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3156 drm_mode_probed_add(connector, newmode);
3160 if (structure & (1 << 8)) {
3161 newmode = drm_display_mode_from_vic_index(connector, video_db,
3165 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3166 drm_mode_probed_add(connector, newmode);
3175 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3176 * @connector: connector corresponding to the HDMI sink
3177 * @db: start of the CEA vendor specific block
3178 * @len: length of the CEA block payload, ie. one can access up to db[len]
3180 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3181 * also adds the stereo 3d modes when applicable.
3184 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3185 const u8 *video_db, u8 video_len)
3187 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3188 u8 vic_len, hdmi_3d_len = 0;
3195 /* no HDMI_Video_Present */
3196 if (!(db[8] & (1 << 5)))
3199 /* Latency_Fields_Present */
3200 if (db[8] & (1 << 7))
3203 /* I_Latency_Fields_Present */
3204 if (db[8] & (1 << 6))
3207 /* the declared length is not long enough for the 2 first bytes
3208 * of additional video format capabilities */
3209 if (len < (8 + offset + 2))
3214 if (db[8 + offset] & (1 << 7)) {
3215 modes += add_hdmi_mandatory_stereo_modes(connector);
3217 /* 3D_Multi_present */
3218 multi_present = (db[8 + offset] & 0x60) >> 5;
3222 vic_len = db[8 + offset] >> 5;
3223 hdmi_3d_len = db[8 + offset] & 0x1f;
3225 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3228 vic = db[9 + offset + i];
3229 modes += add_hdmi_mode(connector, vic);
3231 offset += 1 + vic_len;
3233 if (multi_present == 1)
3235 else if (multi_present == 2)
3240 if (len < (8 + offset + hdmi_3d_len - 1))
3243 if (hdmi_3d_len < multi_len)
3246 if (multi_present == 1 || multi_present == 2) {
3247 /* 3D_Structure_ALL */
3248 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3250 /* check if 3D_MASK is present */
3251 if (multi_present == 2)
3252 mask = (db[10 + offset] << 8) | db[11 + offset];
3256 for (i = 0; i < 16; i++) {
3257 if (mask & (1 << i))
3258 modes += add_3d_struct_modes(connector,
3265 offset += multi_len;
3267 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3269 struct drm_display_mode *newmode = NULL;
3270 unsigned int newflag = 0;
3271 bool detail_present;
3273 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3275 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3278 /* 2D_VIC_order_X */
3279 vic_index = db[8 + offset + i] >> 4;
3281 /* 3D_Structure_X */
3282 switch (db[8 + offset + i] & 0x0f) {
3284 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3287 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3291 if ((db[9 + offset + i] >> 4) == 1)
3292 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3297 newmode = drm_display_mode_from_vic_index(connector,
3303 newmode->flags |= newflag;
3304 drm_mode_probed_add(connector, newmode);
3318 cea_db_payload_len(const u8 *db)
3320 return db[0] & 0x1f;
3324 cea_db_tag(const u8 *db)
3330 cea_revision(const u8 *cea)
3336 cea_db_offsets(const u8 *cea, int *start, int *end)
3338 /* Data block offset in CEA extension block */
3343 if (*end < 4 || *end > 127)
3348 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3352 if (cea_db_tag(db) != VENDOR_BLOCK)
3355 if (cea_db_payload_len(db) < 5)
3358 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3360 return hdmi_id == HDMI_IEEE_OUI;
3363 static bool cea_db_is_hdmi_hf_vsdb(const u8 *db)
3367 if (cea_db_tag(db) != VENDOR_BLOCK)
3370 if (cea_db_payload_len(db) < 7)
3373 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3375 return hdmi_id == HDMI_IEEE_OUI_HF;
3378 #define for_each_cea_db(cea, i, start, end) \
3379 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3382 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3384 const u8 *cea = drm_find_cea_extension(edid);
3385 const u8 *db, *hdmi = NULL, *video = NULL;
3386 u8 dbl, hdmi_len, video_len = 0;
3389 if (cea && cea_revision(cea) >= 3) {
3392 if (cea_db_offsets(cea, &start, &end))
3395 for_each_cea_db(cea, i, start, end) {
3397 dbl = cea_db_payload_len(db);
3399 if (cea_db_tag(db) == VIDEO_BLOCK) {
3402 modes += do_cea_modes(connector, video, dbl);
3404 else if (cea_db_is_hdmi_vsdb(db)) {
3412 * We parse the HDMI VSDB after having added the cea modes as we will
3413 * be patching their flags when the sink supports stereo 3D.
3416 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3422 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3424 const struct drm_display_mode *cea_mode;
3425 int clock1, clock2, clock;
3430 * allow 5kHz clock difference either way to account for
3431 * the 10kHz clock resolution limit of detailed timings.
3433 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3434 if (drm_valid_cea_vic(vic)) {
3436 cea_mode = &edid_cea_modes[vic];
3437 clock1 = cea_mode->clock;
3438 clock2 = cea_mode_alternate_clock(cea_mode);
3440 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3441 if (drm_valid_hdmi_vic(vic)) {
3443 cea_mode = &edid_4k_modes[vic];
3444 clock1 = cea_mode->clock;
3445 clock2 = hdmi_mode_alternate_clock(cea_mode);
3451 /* pick whichever is closest */
3452 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3457 if (mode->clock == clock)
3460 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3461 type, vic, mode->clock, clock);
3462 mode->clock = clock;
3466 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3468 u8 len = cea_db_payload_len(db);
3471 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3472 connector->dvi_dual = db[6] & 1;
3475 connector->max_tmds_clock = db[7] * 5;
3477 connector->latency_present[0] = db[8] >> 7;
3478 connector->latency_present[1] = (db[8] >> 6) & 1;
3481 connector->video_latency[0] = db[9];
3483 connector->audio_latency[0] = db[10];
3485 connector->video_latency[1] = db[11];
3487 connector->audio_latency[1] = db[12];
3489 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3490 "max TMDS clock %d, "
3491 "latency present %d %d, "
3492 "video latency %d %d, "
3493 "audio latency %d %d\n",
3494 connector->dvi_dual,
3495 connector->max_tmds_clock,
3496 (int) connector->latency_present[0],
3497 (int) connector->latency_present[1],
3498 connector->video_latency[0],
3499 connector->video_latency[1],
3500 connector->audio_latency[0],
3501 connector->audio_latency[1]);
3505 parse_hdmi_hf_vsdb(struct drm_connector *connector, const u8 *db)
3507 u8 len = cea_db_payload_len(db);
3513 return; /* invalid version */
3515 connector->max_tmds_char = db[5] * 5;
3516 connector->scdc_present = db[6] & (1 << 7);
3517 connector->rr_capable = db[6] & (1 << 6);
3518 connector->flags_3d = db[6] & 0x7;
3519 connector->lte_340mcsc_scramble = db[6] & (1 << 3);
3521 DRM_DEBUG_KMS("HDMI v2: max TMDS clock %d, "
3526 connector->max_tmds_char,
3527 connector->scdc_present ? "available" : "not available",
3528 connector->rr_capable ? "capable" : "not capable",
3529 connector->flags_3d,
3530 connector->lte_340mcsc_scramble ?
3531 "supported" : "not supported");
3535 monitor_name(struct detailed_timing *t, void *data)
3537 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3538 *(u8 **)data = t->data.other_data.data.str.str;
3542 * drm_edid_to_eld - build ELD from EDID
3543 * @connector: connector corresponding to the HDMI/DP sink
3544 * @edid: EDID to parse
3546 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3547 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3550 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3552 uint8_t *eld = connector->eld;
3560 memset(eld, 0, sizeof(connector->eld));
3562 cea = drm_find_cea_extension(edid);
3564 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3569 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3570 for (mnl = 0; name && mnl < 13; mnl++) {
3571 if (name[mnl] == 0x0a)
3573 eld[20 + mnl] = name[mnl];
3575 eld[4] = (cea[1] << 5) | mnl;
3576 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3578 eld[0] = 2 << 3; /* ELD version: 2 */
3580 eld[16] = edid->mfg_id[0];
3581 eld[17] = edid->mfg_id[1];
3582 eld[18] = edid->prod_code[0];
3583 eld[19] = edid->prod_code[1];
3585 if (cea_revision(cea) >= 3) {
3588 if (cea_db_offsets(cea, &start, &end)) {
3593 for_each_cea_db(cea, i, start, end) {
3595 dbl = cea_db_payload_len(db);
3597 switch (cea_db_tag(db)) {
3599 /* Audio Data Block, contains SADs */
3600 sad_count = dbl / 3;
3602 memcpy(eld + 20 + mnl, &db[1], dbl);
3605 /* Speaker Allocation Data Block */
3610 /* HDMI Vendor-Specific Data Block */
3611 if (cea_db_is_hdmi_vsdb(db))
3612 parse_hdmi_vsdb(connector, db);
3613 /* HDMI Forum Vendor-Specific Data Block */
3614 else if (cea_db_is_hdmi_hf_vsdb(db))
3615 parse_hdmi_hf_vsdb(connector, db);
3622 eld[5] |= sad_count << 4;
3624 eld[DRM_ELD_BASELINE_ELD_LEN] =
3625 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3627 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3628 drm_eld_size(eld), sad_count);
3630 EXPORT_SYMBOL(drm_edid_to_eld);
3633 * drm_edid_to_sad - extracts SADs from EDID
3634 * @edid: EDID to parse
3635 * @sads: pointer that will be set to the extracted SADs
3637 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3639 * Note: The returned pointer needs to be freed using kfree().
3641 * Return: The number of found SADs or negative number on error.
3643 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3646 int i, start, end, dbl;
3649 cea = drm_find_cea_extension(edid);
3651 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3655 if (cea_revision(cea) < 3) {
3656 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3660 if (cea_db_offsets(cea, &start, &end)) {
3661 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3665 for_each_cea_db(cea, i, start, end) {
3668 if (cea_db_tag(db) == AUDIO_BLOCK) {
3670 dbl = cea_db_payload_len(db);
3672 count = dbl / 3; /* SAD is 3B */
3673 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3676 for (j = 0; j < count; j++) {
3677 u8 *sad = &db[1 + j * 3];
3679 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3680 (*sads)[j].channels = sad[0] & 0x7;
3681 (*sads)[j].freq = sad[1] & 0x7F;
3682 (*sads)[j].byte2 = sad[2];
3690 EXPORT_SYMBOL(drm_edid_to_sad);
3693 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3694 * @edid: EDID to parse
3695 * @sadb: pointer to the speaker block
3697 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3699 * Note: The returned pointer needs to be freed using kfree().
3701 * Return: The number of found Speaker Allocation Blocks or negative number on
3704 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3707 int i, start, end, dbl;
3710 cea = drm_find_cea_extension(edid);
3712 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3716 if (cea_revision(cea) < 3) {
3717 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3721 if (cea_db_offsets(cea, &start, &end)) {
3722 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3726 for_each_cea_db(cea, i, start, end) {
3727 const u8 *db = &cea[i];
3729 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3730 dbl = cea_db_payload_len(db);
3732 /* Speaker Allocation Data Block */
3734 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3745 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3748 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3749 * @connector: connector associated with the HDMI/DP sink
3750 * @mode: the display mode
3752 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3753 * the sink doesn't support audio or video.
3755 int drm_av_sync_delay(struct drm_connector *connector,
3756 const struct drm_display_mode *mode)
3758 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3761 if (!connector->latency_present[0])
3763 if (!connector->latency_present[1])
3766 a = connector->audio_latency[i];
3767 v = connector->video_latency[i];
3770 * HDMI/DP sink doesn't support audio or video?
3772 if (a == 255 || v == 255)
3776 * Convert raw EDID values to millisecond.
3777 * Treat unknown latency as 0ms.
3780 a = min(2 * (a - 1), 500);
3782 v = min(2 * (v - 1), 500);
3784 return max(v - a, 0);
3786 EXPORT_SYMBOL(drm_av_sync_delay);
3789 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3790 * @encoder: the encoder just changed display mode
3792 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3793 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3795 * Return: The connector associated with the first HDMI/DP sink that has ELD
3798 struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3800 struct drm_connector *connector;
3801 struct drm_device *dev = encoder->dev;
3803 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3804 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3806 drm_for_each_connector(connector, dev)
3807 if (connector->encoder == encoder && connector->eld[0])
3812 EXPORT_SYMBOL(drm_select_eld);
3815 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3816 * @edid: monitor EDID information
3818 * Parse the CEA extension according to CEA-861-B.
3820 * Return: True if the monitor is HDMI, false if not or unknown.
3822 bool drm_detect_hdmi_monitor(struct edid *edid)
3826 int start_offset, end_offset;
3828 edid_ext = drm_find_cea_extension(edid);
3832 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3836 * Because HDMI identifier is in Vendor Specific Block,
3837 * search it from all data blocks of CEA extension.
3839 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3840 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3846 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3849 * drm_detect_monitor_audio - check monitor audio capability
3850 * @edid: EDID block to scan
3852 * Monitor should have CEA extension block.
3853 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3854 * audio' only. If there is any audio extension block and supported
3855 * audio format, assume at least 'basic audio' support, even if 'basic
3856 * audio' is not defined in EDID.
3858 * Return: True if the monitor supports audio, false otherwise.
3860 bool drm_detect_monitor_audio(struct edid *edid)
3864 bool has_audio = false;
3865 int start_offset, end_offset;
3867 edid_ext = drm_find_cea_extension(edid);
3871 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3874 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3878 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3881 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3882 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3884 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3885 DRM_DEBUG_KMS("CEA audio format %d\n",
3886 (edid_ext[i + j] >> 3) & 0xf);
3893 EXPORT_SYMBOL(drm_detect_monitor_audio);
3896 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3897 * @edid: EDID block to scan
3899 * Check whether the monitor reports the RGB quantization range selection
3900 * as supported. The AVI infoframe can then be used to inform the monitor
3901 * which quantization range (full or limited) is used.
3903 * Return: True if the RGB quantization range is selectable, false otherwise.
3905 bool drm_rgb_quant_range_selectable(struct edid *edid)
3910 edid_ext = drm_find_cea_extension(edid);
3914 if (cea_db_offsets(edid_ext, &start, &end))
3917 for_each_cea_db(edid_ext, i, start, end) {
3918 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3919 cea_db_payload_len(&edid_ext[i]) == 2) {
3920 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3921 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3927 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3930 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3931 * hdmi deep color modes and update drm_display_info if so.
3932 * @edid: monitor EDID information
3933 * @info: Updated with maximum supported deep color bpc and color format
3934 * if deep color supported.
3935 * @connector: DRM connector, used only for debug output
3937 * Parse the CEA extension according to CEA-861-B.
3938 * Return true if HDMI deep color supported, false if not or unknown.
3940 static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3941 struct drm_display_info *info,
3942 struct drm_connector *connector)
3944 u8 *edid_ext, *hdmi;
3946 int start_offset, end_offset;
3947 unsigned int dc_bpc = 0;
3949 edid_ext = drm_find_cea_extension(edid);
3953 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3957 * Because HDMI identifier is in Vendor Specific Block,
3958 * search it from all data blocks of CEA extension.
3960 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3961 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3962 /* HDMI supports at least 8 bpc */
3965 hdmi = &edid_ext[i];
3966 if (cea_db_payload_len(hdmi) < 6)
3969 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3971 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3972 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3976 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3978 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3979 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3983 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3985 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3986 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3991 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3992 connector->name, dc_bpc);
3996 * Deep color support mandates RGB444 support for all video
3997 * modes and forbids YCRCB422 support for all video modes per
4000 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4002 /* YCRCB444 is optional according to spec. */
4003 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4004 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4005 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4010 * Spec says that if any deep color mode is supported at all,
4011 * then deep color 36 bit must be supported.
4013 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4014 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4021 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4031 * drm_add_display_info - pull display info out if present
4033 * @info: display info (attached to connector)
4034 * @connector: connector whose edid is used to build display info
4036 * Grab any available display info and stuff it into the drm_display_info
4037 * structure that's part of the connector. Useful for tracking bpp and
4040 static void drm_add_display_info(struct edid *edid,
4041 struct drm_display_info *info,
4042 struct drm_connector *connector)
4046 info->width_mm = edid->width_cm * 10;
4047 info->height_mm = edid->height_cm * 10;
4049 /* driver figures it out in this case */
4051 info->color_formats = 0;
4053 if (edid->revision < 3)
4056 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4059 /* Get data from CEA blocks if present */
4060 edid_ext = drm_find_cea_extension(edid);
4062 info->cea_rev = edid_ext[1];
4064 /* The existence of a CEA block should imply RGB support */
4065 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4066 if (edid_ext[3] & EDID_CEA_YCRCB444)
4067 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4068 if (edid_ext[3] & EDID_CEA_YCRCB422)
4069 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4072 /* HDMI deep color modes supported? Assign to info, if so */
4073 drm_assign_hdmi_deep_color_info(edid, info, connector);
4075 /* Only defined for 1.4 with digital displays */
4076 if (edid->revision < 4)
4079 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4080 case DRM_EDID_DIGITAL_DEPTH_6:
4083 case DRM_EDID_DIGITAL_DEPTH_8:
4086 case DRM_EDID_DIGITAL_DEPTH_10:
4089 case DRM_EDID_DIGITAL_DEPTH_12:
4092 case DRM_EDID_DIGITAL_DEPTH_14:
4095 case DRM_EDID_DIGITAL_DEPTH_16:
4098 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4104 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4105 connector->name, info->bpc);
4107 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4108 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4109 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4110 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4111 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4115 * drm_add_edid_modes - add modes from EDID data, if available
4116 * @connector: connector we're probing
4119 * Add the specified modes to the connector's mode list.
4121 * Return: The number of modes added or 0 if we couldn't find any.
4123 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4131 if (!drm_edid_is_valid(edid)) {
4132 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4137 quirks = edid_get_quirks(edid);
4140 * EDID spec says modes should be preferred in this order:
4141 * - preferred detailed mode
4142 * - other detailed modes from base block
4143 * - detailed modes from extension blocks
4144 * - CVT 3-byte code modes
4145 * - standard timing codes
4146 * - established timing codes
4147 * - modes inferred from GTF or CVT range information
4149 * We get this pretty much right.
4151 * XXX order for additional mode types in extension blocks?
4153 num_modes += add_detailed_modes(connector, edid, quirks);
4154 num_modes += add_cvt_modes(connector, edid);
4155 num_modes += add_standard_modes(connector, edid);
4156 num_modes += add_established_modes(connector, edid);
4157 num_modes += add_cea_modes(connector, edid);
4158 num_modes += add_alternate_cea_modes(connector, edid);
4159 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4160 num_modes += add_inferred_modes(connector, edid);
4162 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4163 edid_fixup_preferred(connector, quirks);
4165 drm_add_display_info(edid, &connector->display_info, connector);
4167 if (quirks & EDID_QUIRK_FORCE_6BPC)
4168 connector->display_info.bpc = 6;
4170 if (quirks & EDID_QUIRK_FORCE_8BPC)
4171 connector->display_info.bpc = 8;
4173 if (quirks & EDID_QUIRK_FORCE_12BPC)
4174 connector->display_info.bpc = 12;
4178 EXPORT_SYMBOL(drm_add_edid_modes);
4181 * drm_add_modes_noedid - add modes for the connectors without EDID
4182 * @connector: connector we're probing
4183 * @hdisplay: the horizontal display limit
4184 * @vdisplay: the vertical display limit
4186 * Add the specified modes to the connector's mode list. Only when the
4187 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4189 * Return: The number of modes added or 0 if we couldn't find any.
4191 int drm_add_modes_noedid(struct drm_connector *connector,
4192 int hdisplay, int vdisplay)
4194 int i, count, num_modes = 0;
4195 struct drm_display_mode *mode;
4196 struct drm_device *dev = connector->dev;
4198 count = ARRAY_SIZE(drm_dmt_modes);
4204 for (i = 0; i < count; i++) {
4205 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4206 if (hdisplay && vdisplay) {
4208 * Only when two are valid, they will be used to check
4209 * whether the mode should be added to the mode list of
4212 if (ptr->hdisplay > hdisplay ||
4213 ptr->vdisplay > vdisplay)
4216 if (drm_mode_vrefresh(ptr) > 61)
4218 mode = drm_mode_duplicate(dev, ptr);
4220 drm_mode_probed_add(connector, mode);
4226 EXPORT_SYMBOL(drm_add_modes_noedid);
4229 * drm_set_preferred_mode - Sets the preferred mode of a connector
4230 * @connector: connector whose mode list should be processed
4231 * @hpref: horizontal resolution of preferred mode
4232 * @vpref: vertical resolution of preferred mode
4234 * Marks a mode as preferred if it matches the resolution specified by @hpref
4237 void drm_set_preferred_mode(struct drm_connector *connector,
4238 int hpref, int vpref)
4240 struct drm_display_mode *mode;
4242 list_for_each_entry(mode, &connector->probed_modes, head) {
4243 if (mode->hdisplay == hpref &&
4244 mode->vdisplay == vpref)
4245 mode->type |= DRM_MODE_TYPE_PREFERRED;
4248 EXPORT_SYMBOL(drm_set_preferred_mode);
4251 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4252 * data from a DRM display mode
4253 * @frame: HDMI AVI infoframe
4254 * @mode: DRM display mode
4256 * Return: 0 on success or a negative error code on failure.
4259 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4260 const struct drm_display_mode *mode)
4264 if (!frame || !mode)
4267 err = hdmi_avi_infoframe_init(frame);
4271 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4272 frame->pixel_repeat = 1;
4274 frame->video_code = drm_match_cea_mode(mode);
4276 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4279 * Populate picture aspect ratio from either
4280 * user input (if specified) or from the CEA mode list.
4282 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4283 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4284 frame->picture_aspect = mode->picture_aspect_ratio;
4285 else if (frame->video_code > 0)
4286 frame->picture_aspect = drm_get_cea_aspect_ratio(
4289 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4290 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4294 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4296 static enum hdmi_3d_structure
4297 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4299 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4302 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4303 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4304 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4305 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4306 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4307 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4308 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4309 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4310 case DRM_MODE_FLAG_3D_L_DEPTH:
4311 return HDMI_3D_STRUCTURE_L_DEPTH;
4312 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4313 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4314 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4315 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4316 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4317 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4319 return HDMI_3D_STRUCTURE_INVALID;
4324 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4325 * data from a DRM display mode
4326 * @frame: HDMI vendor infoframe
4327 * @mode: DRM display mode
4329 * Note that there's is a need to send HDMI vendor infoframes only when using a
4330 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4331 * function will return -EINVAL, error that can be safely ignored.
4333 * Return: 0 on success or a negative error code on failure.
4336 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4337 const struct drm_display_mode *mode)
4343 if (!frame || !mode)
4346 vic = drm_match_hdmi_mode(mode);
4347 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4349 if (!vic && !s3d_flags)
4352 if (vic && s3d_flags)
4355 err = hdmi_vendor_infoframe_init(frame);
4362 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4366 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4368 static int drm_parse_display_id(struct drm_connector *connector,
4369 u8 *displayid, int length,
4370 bool is_edid_extension)
4372 /* if this is an EDID extension the first byte will be 0x70 */
4374 struct displayid_hdr *base;
4375 struct displayid_block *block;
4379 if (is_edid_extension)
4382 base = (struct displayid_hdr *)&displayid[idx];
4384 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4385 base->rev, base->bytes, base->prod_id, base->ext_count);
4387 if (base->bytes + 5 > length - idx)
4390 for (i = idx; i <= base->bytes + 5; i++) {
4391 csum += displayid[i];
4394 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4398 block = (struct displayid_block *)&displayid[idx + 4];
4399 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
4400 block->tag, block->rev, block->num_bytes);
4402 switch (block->tag) {
4403 case DATA_BLOCK_TILED_DISPLAY: {
4404 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4407 u8 tile_v_loc, tile_h_loc;
4408 u8 num_v_tile, num_h_tile;
4409 struct drm_tile_group *tg;
4411 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4412 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4414 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4415 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4416 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4417 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4419 connector->has_tile = true;
4420 if (tile->tile_cap & 0x80)
4421 connector->tile_is_single_monitor = true;
4423 connector->num_h_tile = num_h_tile + 1;
4424 connector->num_v_tile = num_v_tile + 1;
4425 connector->tile_h_loc = tile_h_loc;
4426 connector->tile_v_loc = tile_v_loc;
4427 connector->tile_h_size = w + 1;
4428 connector->tile_v_size = h + 1;
4430 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4431 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4432 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4433 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4434 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4436 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4438 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4443 if (connector->tile_group != tg) {
4444 /* if we haven't got a pointer,
4445 take the reference, drop ref to old tile group */
4446 if (connector->tile_group) {
4447 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4449 connector->tile_group = tg;
4451 /* if same tile group, then release the ref we just took. */
4452 drm_mode_put_tile_group(connector->dev, tg);
4456 printk("unknown displayid tag %d\n", block->tag);
4462 static void drm_get_displayid(struct drm_connector *connector,
4465 void *displayid = NULL;
4467 connector->has_tile = false;
4468 displayid = drm_find_displayid_extension(edid);
4470 /* drop reference to any tile group we had */
4474 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4477 if (!connector->has_tile)
4481 if (connector->tile_group) {
4482 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4483 connector->tile_group = NULL;
projects / firefly-linux-kernel-4.4.55.git / blob