drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/bridge/dw_hdmi.h>
  33
  34 #include "dw-hdmi.h"
  35 #include "dw-hdmi-audio.h"
  36
  37 #define HDMI_EDID_LEN           512
  38
  39 #define RGB                     0
  40 #define YCBCR444                1
  41 #define YCBCR422_16BITS         2
  42 #define YCBCR422_8BITS          3
  43 #define XVYCC444                4
  44
  45 enum hdmi_datamap {
  46         RGB444_8B = 0x01,
  47         RGB444_10B = 0x03,
  48         RGB444_12B = 0x05,
  49         RGB444_16B = 0x07,
  50         YCbCr444_8B = 0x09,
  51         YCbCr444_10B = 0x0B,
  52         YCbCr444_12B = 0x0D,
  53         YCbCr444_16B = 0x0F,
  54         YCbCr422_8B = 0x16,
  55         YCbCr422_10B = 0x14,
  56         YCbCr422_12B = 0x12,
  57 };
  58
  59 /*
  60  * Unless otherwise noted, entries in this table are 100% optimization.
  61  * Values can be obtained from hdmi_compute_n() but that function is
  62  * slow so we pre-compute values we expect to see.
  63  *
  64  * All 32k and 48k values are expected to be the same (due to the way
  65  * the math works) for any rate that's an exact kHz.
  66  */
  67 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  68         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  69         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  70         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  71         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  72         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  73         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  74         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  75         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  76         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  77         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  78         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  79         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  80         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  81         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  82         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  83         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  84         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  85         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  86         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  87         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  88         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  89         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  90         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  91         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  92         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  93         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  94         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  95         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  96         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  97         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  98         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
  99         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 100         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 101         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 102         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 103         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 104         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 105
 106         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 107         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 108         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 109
 110         /* End of table */
 111         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 112 };
 113
 114
 115 static const u16 csc_coeff_default[3][4] = {
 116         { 0x2000, 0x0000, 0x0000, 0x0000 },
 117         { 0x0000, 0x2000, 0x0000, 0x0000 },
 118         { 0x0000, 0x0000, 0x2000, 0x0000 }
 119 };
 120
 121 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 122         { 0x2000, 0x6926, 0x74fd, 0x010e },
 123         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 124         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 125 };
 126
 127 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 128         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 129         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 130         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 131 };
 132
 133 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 134         { 0x2591, 0x1322, 0x074b, 0x0000 },
 135         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 136         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 137 };
 138
 139 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 140         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 141         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 142         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 143 };
 144
 145 struct hdmi_vmode {
 146         bool mdataenablepolarity;
 147
 148         unsigned int mpixelclock;
 149         unsigned int mpixelrepetitioninput;
 150         unsigned int mpixelrepetitionoutput;
 151 };
 152
 153 struct hdmi_data_info {
 154         unsigned int enc_in_format;
 155         unsigned int enc_out_format;
 156         unsigned int enc_color_depth;
 157         unsigned int colorimetry;
 158         unsigned int pix_repet_factor;
 159         unsigned int hdcp_enable;
 160         struct hdmi_vmode video_mode;
 161 };
 162
 163 struct dw_hdmi_i2c {
 164         struct i2c_adapter      adap;
 165
 166         struct mutex            lock;
 167         struct completion       cmp;
 168         u8                      stat;
 169
 170         u8                      slave_reg;
 171         bool                    is_regaddr;
 172 };
 173
 174 struct dw_hdmi {
 175         struct drm_connector connector;
 176         struct drm_encoder *encoder;
 177         struct drm_bridge *bridge;
 178
 179         struct platform_device *audio;
 180         enum dw_hdmi_devtype dev_type;
 181         struct device *dev;
 182         struct clk *isfr_clk;
 183         struct clk *iahb_clk;
 184         struct dw_hdmi_i2c *i2c;
 185
 186         struct hdmi_data_info hdmi_data;
 187         const struct dw_hdmi_plat_data *plat_data;
 188
 189         int vic;
 190
 191         u8 edid[HDMI_EDID_LEN];
 192         bool cable_plugin;
 193
 194         bool phy_enabled;
 195         struct drm_display_mode previous_mode;
 196
 197         struct i2c_adapter *ddc;
 198         void __iomem *regs;
 199         bool sink_is_hdmi;
 200         bool sink_has_audio;
 201
 202         struct mutex mutex;             /* for state below and previous_mode */
 203         enum drm_connector_force force; /* mutex-protected force state */
 204         bool disabled;                  /* DRM has disabled our bridge */
 205         bool bridge_is_on;              /* indicates the bridge is on */
 206         bool rxsense;                   /* rxsense state */
 207         u8 phy_mask;                    /* desired phy int mask settings */
 208
 209         spinlock_t audio_lock;
 210         struct mutex audio_mutex;
 211         unsigned int sample_rate;
 212         unsigned int audio_cts;
 213         unsigned int audio_n;
 214         bool audio_enable;
 215
 216         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 217         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 218 };
 219
 220 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 221         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 222          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 223
 224 #define HDMI_PHY_RX_SENSE \
 225         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 226          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 227
 228 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 229 {
 230         writel(val, hdmi->regs + (offset << 2));
 231 }
 232
 233 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 234 {
 235         return readl(hdmi->regs + (offset << 2));
 236 }
 237
 238 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 239 {
 240         writeb(val, hdmi->regs + offset);
 241 }
 242
 243 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 244 {
 245         return readb(hdmi->regs + offset);
 246 }
 247
 248 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 249 {
 250         hdmi->write(hdmi, val, offset);
 251 }
 252
 253 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 254 {
 255         return hdmi->read(hdmi, offset);
 256 }
 257
 258 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 259 {
 260         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 261
 262         val |= data & mask;
 263         hdmi_writeb(hdmi, val, reg);
 264 }
 265
 266 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 267                              u8 shift, u8 mask)
 268 {
 269         hdmi_modb(hdmi, data << shift, mask, reg);
 270 }
 271
 272 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 273 {
 274         /* Software reset */
 275         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 276
 277         /* Set Standard Mode speed */
 278         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 279                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 280
 281         /* Set done, not acknowledged and arbitration interrupt polarities */
 282         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 283         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 284                     HDMI_I2CM_CTLINT);
 285
 286         /* Clear DONE and ERROR interrupts */
 287         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 288                     HDMI_IH_I2CM_STAT0);
 289
 290         /* Mute DONE and ERROR interrupts */
 291         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 292                     HDMI_IH_MUTE_I2CM_STAT0);
 293 }
 294
 295 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 296                             unsigned char *buf, unsigned int length)
 297 {
 298         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 299         int stat;
 300
 301         if (!i2c->is_regaddr) {
 302                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 303                 i2c->slave_reg = 0x00;
 304                 i2c->is_regaddr = true;
 305         }
 306
 307         while (length--) {
 308                 reinit_completion(&i2c->cmp);
 309
 310                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 311                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 312                             HDMI_I2CM_OPERATION);
 313
 314                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 315                 if (!stat)
 316                         return -EAGAIN;
 317
 318                 /* Check for error condition on the bus */
 319                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 320                         return -EIO;
 321
 322                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 323         }
 324
 325         return 0;
 326 }
 327
 328 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 329                              unsigned char *buf, unsigned int length)
 330 {
 331         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 332         int stat;
 333
 334         if (!i2c->is_regaddr) {
 335                 /* Use the first write byte as register address */
 336                 i2c->slave_reg = buf[0];
 337                 length--;
 338                 buf++;
 339                 i2c->is_regaddr = true;
 340         }
 341
 342         while (length--) {
 343                 reinit_completion(&i2c->cmp);
 344
 345                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 346                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 347                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 348                             HDMI_I2CM_OPERATION);
 349
 350         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 351                 if (!stat)
 352                         return -EAGAIN;
 353
 354                 /* Check for error condition on the bus */
 355                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 356                         return -EIO;
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 363                             struct i2c_msg *msgs, int num)
 364 {
 365         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 366         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 367         u8 addr = msgs[0].addr;
 368         int i, ret = 0;
 369
 370         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 371
 372         for (i = 0; i < num; i++) {
 373                 if (msgs[i].addr != addr) {
 374                         dev_warn(hdmi->dev,
 375                                  "unsupported transfer, changed slave address\n");
 376                         return -EOPNOTSUPP;
 377                 }
 378
 379                 if (msgs[i].len == 0) {
 380                         dev_dbg(hdmi->dev,
 381                                 "unsupported transfer %d/%d, no data\n",
 382                                 i + 1, num);
 383                         return -EOPNOTSUPP;
 384                 }
 385         }
 386
 387         mutex_lock(&i2c->lock);
 388
 389         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 390
 391         /* Set slave device address taken from the first I2C message */
 392         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 393
 394         /* Set slave device register address on transfer */
 395         i2c->is_regaddr = false;
 396
 397         for (i = 0; i < num; i++) {
 398                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 399                         i + 1, num, msgs[i].len, msgs[i].flags);
 400
 401                 if (msgs[i].flags & I2C_M_RD)
 402                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
 403                 else
 404                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
 405
 406                 if (ret < 0)
 407                         break;
 408         }
 409
 410         if (!ret)
 411                 ret = num;
 412
 413         /* Mute DONE and ERROR interrupts */
 414         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 415                     HDMI_IH_MUTE_I2CM_STAT0);
 416
 417         mutex_unlock(&i2c->lock);
 418
 419         return ret;
 420 }
 421
 422 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 423 {
 424         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 425 }
 426
 427 static const struct i2c_algorithm dw_hdmi_algorithm = {
 428         .master_xfer    = dw_hdmi_i2c_xfer,
 429         .functionality  = dw_hdmi_i2c_func,
 430 };
 431
 432 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 433 {
 434         struct i2c_adapter *adap;
 435         struct dw_hdmi_i2c *i2c;
 436         int ret;
 437
 438         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 439         if (!i2c)
 440                 return ERR_PTR(-ENOMEM);
 441
 442         mutex_init(&i2c->lock);
 443         init_completion(&i2c->cmp);
 444
 445         adap = &i2c->adap;
 446         adap->class = I2C_CLASS_DDC;
 447         adap->owner = THIS_MODULE;
 448         adap->dev.parent = hdmi->dev;
 449         adap->dev.of_node = hdmi->dev->of_node;
 450         adap->algo = &dw_hdmi_algorithm;
 451         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 452         i2c_set_adapdata(adap, hdmi);
 453
 454         ret = i2c_add_adapter(adap);
 455         if (ret) {
 456                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 457                 devm_kfree(hdmi->dev, i2c);
 458                 return ERR_PTR(ret);
 459         }
 460
 461         hdmi->i2c = i2c;
 462
 463         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 464
 465         return adap;
 466 }
 467
 468 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 469                            unsigned int n)
 470 {
 471         /* Must be set/cleared first */
 472         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 473
 474         /* nshift factor = 0 */
 475         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 476
 477         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 478                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 479         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 480         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 481
 482         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 483         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 484         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 485 }
 486
 487 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 488                                    unsigned long pixel_clk,
 489                                    unsigned long freq)
 490 {
 491         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 492         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 493         int i;
 494
 495         if (plat_data->tmds_n_table) {
 496                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 497                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 498                                 tmds_n = &plat_data->tmds_n_table[i];
 499                                 break;
 500                         }
 501                 }
 502         }
 503
 504         if (tmds_n == NULL) {
 505                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 506                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 507                                 tmds_n = &common_tmds_n_table[i];
 508                                 break;
 509                         }
 510                 }
 511         }
 512
 513         if (tmds_n == NULL)
 514                 return -ENOENT;
 515
 516         switch (freq) {
 517         case 32000:
 518                 return tmds_n->n_32k;
 519         case 44100:
 520         case 88200:
 521         case 176400:
 522                 return (freq / 44100) * tmds_n->n_44k1;
 523         case 48000:
 524         case 96000:
 525         case 192000:
 526                 return (freq / 48000) * tmds_n->n_48k;
 527         default:
 528                 return -ENOENT;
 529         }
 530 }
 531
 532 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 533                                 unsigned int pixel_clk)
 534 {
 535         u64 final, diff;
 536         u64 cts;
 537
 538         final = (u64)pixel_clk * n;
 539
 540         cts = final;
 541         do_div(cts, 128 * freq);
 542
 543         diff = final - (u64)cts * (128 * freq);
 544
 545         return diff;
 546 }
 547
 548 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 549                                    unsigned long pixel_clk,
 550                                    unsigned long freq)
 551 {
 552         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 553         unsigned int max_n = (128 * freq) / 300;
 554         unsigned int ideal_n = (128 * freq) / 1000;
 555         unsigned int best_n_distance = ideal_n;
 556         unsigned int best_n = 0;
 557         u64 best_diff = U64_MAX;
 558         int n;
 559
 560         /* If the ideal N could satisfy the audio math, then just take it */
 561         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 562                 return ideal_n;
 563
 564         for (n = min_n; n <= max_n; n++) {
 565                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 566
 567                 if (diff < best_diff || (diff == best_diff &&
 568                     abs(n - ideal_n) < best_n_distance)) {
 569                         best_n = n;
 570                         best_diff = diff;
 571                         best_n_distance = abs(best_n - ideal_n);
 572                 }
 573
 574                 /*
 575                  * The best N already satisfy the audio math, and also be
 576                  * the closest value to ideal N, so just cut the loop.
 577                  */
 578                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 579                         break;
 580         }
 581
 582         return best_n;
 583 }
 584
 585 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 586                                 unsigned long sample_rate)
 587 {
 588         int n;
 589
 590         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 591         if (n > 0)
 592                 return n;
 593
 594         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 595                  pixel_clk);
 596
 597         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 598 }
 599
 600 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 601         unsigned long pixel_clk, unsigned int sample_rate)
 602 {
 603         unsigned long ftdms = pixel_clk;
 604         unsigned int n, cts;
 605         u64 tmp;
 606
 607         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 608
 609         /*
 610          * Compute the CTS value from the N value.  Note that CTS and N
 611          * can be up to 20 bits in total, so we need 64-bit math.  Also
 612          * note that our TDMS clock is not fully accurate; it is accurate
 613          * to kHz.  This can introduce an unnecessary remainder in the
 614          * calculation below, so we don't try to warn about that.
 615          */
 616         tmp = (u64)ftdms * n;
 617         do_div(tmp, 128 * sample_rate);
 618         cts = tmp;
 619
 620         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 621                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 622                 n, cts);
 623
 624         spin_lock_irq(&hdmi->audio_lock);
 625         hdmi->audio_n = n;
 626         hdmi->audio_cts = cts;
 627         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 628         spin_unlock_irq(&hdmi->audio_lock);
 629 }
 630
 631 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 632 {
 633         mutex_lock(&hdmi->audio_mutex);
 634         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 635         mutex_unlock(&hdmi->audio_mutex);
 636 }
 637
 638 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 639 {
 640         mutex_lock(&hdmi->audio_mutex);
 641         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 642                                  hdmi->sample_rate);
 643         mutex_unlock(&hdmi->audio_mutex);
 644 }
 645
 646 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 647 {
 648         mutex_lock(&hdmi->audio_mutex);
 649         hdmi->sample_rate = rate;
 650         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 651                                  hdmi->sample_rate);
 652         mutex_unlock(&hdmi->audio_mutex);
 653 }
 654 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 655
 656 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 657 {
 658         unsigned long flags;
 659
 660         spin_lock_irqsave(&hdmi->audio_lock, flags);
 661         hdmi->audio_enable = true;
 662         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 663         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 664 }
 665 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 666
 667 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 668 {
 669         unsigned long flags;
 670
 671         spin_lock_irqsave(&hdmi->audio_lock, flags);
 672         hdmi->audio_enable = false;
 673         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 674         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 675 }
 676 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 677
 678 /*
 679  * this submodule is responsible for the video data synchronization.
 680  * for example, for RGB 4:4:4 input, the data map is defined as
 681  *                      pin{47~40} <==> R[7:0]
 682  *                      pin{31~24} <==> G[7:0]
 683  *                      pin{15~8}  <==> B[7:0]
 684  */
 685 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 686 {
 687         int color_format = 0;
 688         u8 val;
 689
 690         if (hdmi->hdmi_data.enc_in_format == RGB) {
 691                 if (hdmi->hdmi_data.enc_color_depth == 8)
 692                         color_format = 0x01;
 693                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 694                         color_format = 0x03;
 695                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 696                         color_format = 0x05;
 697                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 698                         color_format = 0x07;
 699                 else
 700                         return;
 701         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 702                 if (hdmi->hdmi_data.enc_color_depth == 8)
 703                         color_format = 0x09;
 704                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 705                         color_format = 0x0B;
 706                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 707                         color_format = 0x0D;
 708                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 709                         color_format = 0x0F;
 710                 else
 711                         return;
 712         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 713                 if (hdmi->hdmi_data.enc_color_depth == 8)
 714                         color_format = 0x16;
 715                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 716                         color_format = 0x14;
 717                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 718                         color_format = 0x12;
 719                 else
 720                         return;
 721         }
 722
 723         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 724                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 725                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 726         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 727
 728         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 729         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 730                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 731                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 732         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 733         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 734         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 735         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 736         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 737         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 738         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 739 }
 740
 741 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 742 {
 743         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 744 }
 745
 746 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 747 {
 748         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 749                 return 0;
 750         if (hdmi->hdmi_data.enc_in_format == RGB ||
 751             hdmi->hdmi_data.enc_in_format == YCBCR444)
 752                 return 1;
 753         return 0;
 754 }
 755
 756 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 757 {
 758         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 759                 return 0;
 760         if (hdmi->hdmi_data.enc_out_format == RGB ||
 761             hdmi->hdmi_data.enc_out_format == YCBCR444)
 762                 return 1;
 763         return 0;
 764 }
 765
 766 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 767 {
 768         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 769         unsigned i;
 770         u32 csc_scale = 1;
 771
 772         if (is_color_space_conversion(hdmi)) {
 773                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 774                         if (hdmi->hdmi_data.colorimetry ==
 775                                         HDMI_COLORIMETRY_ITU_601)
 776                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 777                         else
 778                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 779                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 780                         if (hdmi->hdmi_data.colorimetry ==
 781                                         HDMI_COLORIMETRY_ITU_601)
 782                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 783                         else
 784                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 785                         csc_scale = 0;
 786                 }
 787         }
 788
 789         /* The CSC registers are sequential, alternating MSB then LSB */
 790         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 791                 u16 coeff_a = (*csc_coeff)[0][i];
 792                 u16 coeff_b = (*csc_coeff)[1][i];
 793                 u16 coeff_c = (*csc_coeff)[2][i];
 794
 795                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 796                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 797                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 798                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 799                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 800                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 801         }
 802
 803         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 804                   HDMI_CSC_SCALE);
 805 }
 806
 807 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 808 {
 809         int color_depth = 0;
 810         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 811         int decimation = 0;
 812
 813         /* YCC422 interpolation to 444 mode */
 814         if (is_color_space_interpolation(hdmi))
 815                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 816         else if (is_color_space_decimation(hdmi))
 817                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 818
 819         if (hdmi->hdmi_data.enc_color_depth == 8)
 820                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 821         else if (hdmi->hdmi_data.enc_color_depth == 10)
 822                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 823         else if (hdmi->hdmi_data.enc_color_depth == 12)
 824                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 825         else if (hdmi->hdmi_data.enc_color_depth == 16)
 826                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 827         else
 828                 return;
 829
 830         /* Configure the CSC registers */
 831         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 832         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 833                   HDMI_CSC_SCALE);
 834
 835         dw_hdmi_update_csc_coeffs(hdmi);
 836 }
 837
 838 /*
 839  * HDMI video packetizer is used to packetize the data.
 840  * for example, if input is YCC422 mode or repeater is used,
 841  * data should be repacked this module can be bypassed.
 842  */
 843 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 844 {
 845         unsigned int color_depth = 0;
 846         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 847         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 848         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 849         u8 val, vp_conf;
 850
 851         if (hdmi_data->enc_out_format == RGB ||
 852             hdmi_data->enc_out_format == YCBCR444) {
 853                 if (!hdmi_data->enc_color_depth) {
 854                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 855                 } else if (hdmi_data->enc_color_depth == 8) {
 856                         color_depth = 4;
 857                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 858                 } else if (hdmi_data->enc_color_depth == 10) {
 859                         color_depth = 5;
 860                 } else if (hdmi_data->enc_color_depth == 12) {
 861                         color_depth = 6;
 862                 } else if (hdmi_data->enc_color_depth == 16) {
 863                         color_depth = 7;
 864                 } else {
 865                         return;
 866                 }
 867         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 868                 if (!hdmi_data->enc_color_depth ||
 869                     hdmi_data->enc_color_depth == 8)
 870                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 871                 else if (hdmi_data->enc_color_depth == 10)
 872                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 873                 else if (hdmi_data->enc_color_depth == 12)
 874                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 875                 else
 876                         return;
 877                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 878         } else {
 879                 return;
 880         }
 881
 882         /* set the packetizer registers */
 883         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 884                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 885                 ((hdmi_data->pix_repet_factor <<
 886                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 887                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 888         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 889
 890         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 891                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 892
 893         /* Data from pixel repeater block */
 894         if (hdmi_data->pix_repet_factor > 1) {
 895                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 896                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 897         } else { /* data from packetizer block */
 898                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 899                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 900         }
 901
 902         hdmi_modb(hdmi, vp_conf,
 903                   HDMI_VP_CONF_PR_EN_MASK |
 904                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 905
 906         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 907                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 908
 909         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 910
 911         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 912                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 913                           HDMI_VP_CONF_PP_EN_ENABLE |
 914                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 915         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 916                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 917                           HDMI_VP_CONF_PP_EN_DISABLE |
 918                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 919         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 920                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 921                           HDMI_VP_CONF_PP_EN_DISABLE |
 922                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 923         } else {
 924                 return;
 925         }
 926
 927         hdmi_modb(hdmi, vp_conf,
 928                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 929                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 930
 931         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 932                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 933                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 934                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 935
 936         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 937                   HDMI_VP_CONF);
 938 }
 939
 940 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 941                                        unsigned char bit)
 942 {
 943         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 944                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 945 }
 946
 947 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 948                                         unsigned char bit)
 949 {
 950         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 951                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 952 }
 953
 954 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 955                                        unsigned char bit)
 956 {
 957         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 958                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 959 }
 960
 961 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 962                                      unsigned char bit)
 963 {
 964         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 965 }
 966
 967 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 968                                       unsigned char bit)
 969 {
 970         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 971 }
 972
 973 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 974 {
 975         u32 val;
 976
 977         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 978                 if (msec-- == 0)
 979                         return false;
 980                 udelay(1000);
 981         }
 982         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 983
 984         return true;
 985 }
 986
 987 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 988                                  unsigned char addr)
 989 {
 990         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 991         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 992         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 993                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 994         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 995                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 996         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 997                     HDMI_PHY_I2CM_OPERATION_ADDR);
 998         hdmi_phy_wait_i2c_done(hdmi, 1000);
 999 }
1000
1001 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1002                               unsigned char addr)
1003 {
1004         __hdmi_phy_i2c_write(hdmi, data, addr);
1005         return 0;
1006 }
1007
1008 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1009 {
1010         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1011                          HDMI_PHY_CONF0_PDZ_OFFSET,
1012                          HDMI_PHY_CONF0_PDZ_MASK);
1013 }
1014
1015 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1016 {
1017         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1018                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1019                          HDMI_PHY_CONF0_ENTMDS_MASK);
1020 }
1021
1022 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1023 {
1024         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1025                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1026                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1027 }
1028
1029 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1030 {
1031         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1032                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1033                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1034 }
1035
1036 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1037 {
1038         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1039                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1040                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1041 }
1042
1043 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1044 {
1045         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1046                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1047                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1048 }
1049
1050 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1051 {
1052         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1053                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1054                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1055 }
1056
1057 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1058                               unsigned char res, int cscon)
1059 {
1060         unsigned res_idx;
1061         u8 val, msec;
1062         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1063         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1064         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1065         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1066
1067         if (prep)
1068                 return -EINVAL;
1069
1070         switch (res) {
1071         case 0: /* color resolution 0 is 8 bit colour depth */
1072         case 8:
1073                 res_idx = DW_HDMI_RES_8;
1074                 break;
1075         case 10:
1076                 res_idx = DW_HDMI_RES_10;
1077                 break;
1078         case 12:
1079                 res_idx = DW_HDMI_RES_12;
1080                 break;
1081         default:
1082                 return -EINVAL;
1083         }
1084
1085         /* PLL/MPLL Cfg - always match on final entry */
1086         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1087                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1088                     mpll_config->mpixelclock)
1089                         break;
1090
1091         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1092                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1093                     curr_ctrl->mpixelclock)
1094                         break;
1095
1096         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1097                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1098                     phy_config->mpixelclock)
1099                         break;
1100
1101         if (mpll_config->mpixelclock == ~0UL ||
1102             curr_ctrl->mpixelclock == ~0UL ||
1103             phy_config->mpixelclock == ~0UL) {
1104                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1105                         hdmi->hdmi_data.video_mode.mpixelclock);
1106                 return -EINVAL;
1107         }
1108
1109         /* Enable csc path */
1110         if (cscon)
1111                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1112         else
1113                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1114
1115         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1116
1117         /* gen2 tx power off */
1118         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1119
1120         /* gen2 pddq */
1121         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1122
1123         /* PHY reset */
1124         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1125         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1126
1127         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1128
1129         hdmi_phy_test_clear(hdmi, 1);
1130         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1131                     HDMI_PHY_I2CM_SLAVE_ADDR);
1132         hdmi_phy_test_clear(hdmi, 0);
1133
1134         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1135         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1136
1137         /* CURRCTRL */
1138         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1139
1140         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1141         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1142
1143         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1144         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1145         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1146
1147         /* REMOVE CLK TERM */
1148         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1149
1150         dw_hdmi_phy_enable_powerdown(hdmi, false);
1151
1152         /* toggle TMDS enable */
1153         dw_hdmi_phy_enable_tmds(hdmi, 0);
1154         dw_hdmi_phy_enable_tmds(hdmi, 1);
1155
1156         /* gen2 tx power on */
1157         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1158         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1159
1160         if (is_rockchip(hdmi->dev_type))
1161                 dw_hdmi_phy_enable_spare(hdmi, 1);
1162
1163         /*Wait for PHY PLL lock */
1164         msec = 5;
1165         do {
1166                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1167                 if (!val)
1168                         break;
1169
1170                 if (msec == 0) {
1171                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1172                         return -ETIMEDOUT;
1173                 }
1174
1175                 udelay(1000);
1176                 msec--;
1177         } while (1);
1178
1179         return 0;
1180 }
1181
1182 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1183 {
1184         int i, ret;
1185         bool cscon;
1186
1187         /*check csc whether needed activated in HDMI mode */
1188         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1189
1190         /* HDMI Phy spec says to do the phy initialization sequence twice */
1191         for (i = 0; i < 2; i++) {
1192                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1193                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1194                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1195                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1196
1197                 /* Enable CSC */
1198                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1199                 if (ret)
1200                         return ret;
1201         }
1202
1203         hdmi->phy_enabled = true;
1204         return 0;
1205 }
1206
1207 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1208 {
1209         u8 de;
1210
1211         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1212                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1213         else
1214                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1215
1216         /* disable rx detect */
1217         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1218                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1219
1220         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1221
1222         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1223                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1224 }
1225
1226 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1227 {
1228         struct hdmi_avi_infoframe frame;
1229         u8 val;
1230
1231         /* Initialise info frame from DRM mode */
1232         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1233
1234         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1235                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1236         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1237                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1238         else
1239                 frame.colorspace = HDMI_COLORSPACE_RGB;
1240
1241         /* Set up colorimetry */
1242         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1243                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1244                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1245                         frame.extended_colorimetry =
1246                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1247                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1248                         frame.extended_colorimetry =
1249                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1250         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1251                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1252                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1253         } else { /* Carries no data */
1254                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1255                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1256         }
1257
1258         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1259
1260         /*
1261          * The Designware IP uses a different byte format from standard
1262          * AVI info frames, though generally the bits are in the correct
1263          * bytes.
1264          */
1265
1266         /*
1267          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1268          * active aspect present in bit 6 rather than 4.
1269          */
1270         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1271         if (frame.active_aspect & 15)
1272                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1273         if (frame.top_bar || frame.bottom_bar)
1274                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1275         if (frame.left_bar || frame.right_bar)
1276                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1277         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1278
1279         /* AVI data byte 2 differences: none */
1280         val = ((frame.colorimetry & 0x3) << 6) |
1281               ((frame.picture_aspect & 0x3) << 4) |
1282               (frame.active_aspect & 0xf);
1283         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1284
1285         /* AVI data byte 3 differences: none */
1286         val = ((frame.extended_colorimetry & 0x7) << 4) |
1287               ((frame.quantization_range & 0x3) << 2) |
1288               (frame.nups & 0x3);
1289         if (frame.itc)
1290                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1291         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1292
1293         /* AVI data byte 4 differences: none */
1294         val = frame.video_code & 0x7f;
1295         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1296
1297         /* AVI Data Byte 5- set up input and output pixel repetition */
1298         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1299                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1300                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1301                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1302                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1303                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1304         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1305
1306         /*
1307          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1308          * ycc range in bits 2,3 rather than 6,7
1309          */
1310         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1311               (frame.content_type & 0x3);
1312         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1313
1314         /* AVI Data Bytes 6-13 */
1315         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1316         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1317         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1318         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1319         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1320         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1321         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1322         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1323 }
1324
1325 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1326                              const struct drm_display_mode *mode)
1327 {
1328         u8 inv_val;
1329         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1330         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1331         unsigned int vdisplay;
1332
1333         vmode->mpixelclock = mode->clock * 1000;
1334
1335         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1336
1337         /* Set up HDMI_FC_INVIDCONF */
1338         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1339                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1340                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1341
1342         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1343                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1344                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1345
1346         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1347                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1348                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1349
1350         inv_val |= (vmode->mdataenablepolarity ?
1351                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1352                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1353
1354         if (hdmi->vic == 39)
1355                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1356         else
1357                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1358                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1359                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1360
1361         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1362                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1363                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1364
1365         inv_val |= hdmi->sink_is_hdmi ?
1366                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1367                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1368
1369         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1370
1371         vdisplay = mode->vdisplay;
1372         vblank = mode->vtotal - mode->vdisplay;
1373         v_de_vs = mode->vsync_start - mode->vdisplay;
1374         vsync_len = mode->vsync_end - mode->vsync_start;
1375
1376         /*
1377          * When we're setting an interlaced mode, we need
1378          * to adjust the vertical timing to suit.
1379          */
1380         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1381                 vdisplay /= 2;
1382                 vblank /= 2;
1383                 v_de_vs /= 2;
1384                 vsync_len /= 2;
1385         }
1386
1387         /* Set up horizontal active pixel width */
1388         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1389         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1390
1391         /* Set up vertical active lines */
1392         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1393         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1394
1395         /* Set up horizontal blanking pixel region width */
1396         hblank = mode->htotal - mode->hdisplay;
1397         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1398         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1399
1400         /* Set up vertical blanking pixel region width */
1401         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1402
1403         /* Set up HSYNC active edge delay width (in pixel clks) */
1404         h_de_hs = mode->hsync_start - mode->hdisplay;
1405         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1406         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1407
1408         /* Set up VSYNC active edge delay (in lines) */
1409         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1410
1411         /* Set up HSYNC active pulse width (in pixel clks) */
1412         hsync_len = mode->hsync_end - mode->hsync_start;
1413         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1414         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1415
1416         /* Set up VSYNC active edge delay (in lines) */
1417         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1418 }
1419
1420 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1421 {
1422         if (!hdmi->phy_enabled)
1423                 return;
1424
1425         dw_hdmi_phy_enable_tmds(hdmi, 0);
1426         dw_hdmi_phy_enable_powerdown(hdmi, true);
1427
1428         hdmi->phy_enabled = false;
1429 }
1430
1431 /* HDMI Initialization Step B.4 */
1432 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1433 {
1434         u8 clkdis;
1435
1436         /* control period minimum duration */
1437         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1438         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1439         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1440
1441         /* Set to fill TMDS data channels */
1442         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1443         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1444         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1445
1446         /* Enable pixel clock and tmds data path */
1447         clkdis = 0x7F;
1448         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1449         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1450
1451         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1452         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1453
1454         /* Enable csc path */
1455         if (is_color_space_conversion(hdmi)) {
1456                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1457                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1458         }
1459 }
1460
1461 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1462 {
1463         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1464 }
1465
1466 /* Workaround to clear the overflow condition */
1467 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1468 {
1469         int count;
1470         u8 val;
1471
1472         /* TMDS software reset */
1473         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1474
1475         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1476         if (hdmi->dev_type == IMX6DL_HDMI) {
1477                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1478                 return;
1479         }
1480
1481         for (count = 0; count < 4; count++)
1482                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1483 }
1484
1485 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1486 {
1487         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1488         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1489 }
1490
1491 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1492 {
1493         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1494                     HDMI_IH_MUTE_FC_STAT2);
1495 }
1496
1497 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1498 {
1499         int ret;
1500
1501         hdmi_disable_overflow_interrupts(hdmi);
1502
1503         hdmi->vic = drm_match_cea_mode(mode);
1504
1505         if (!hdmi->vic) {
1506                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1507         } else {
1508                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1509         }
1510
1511         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1512             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1513             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1514             (hdmi->vic == 17) || (hdmi->vic == 18))
1515                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1516         else
1517                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1518
1519         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1520         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1521
1522         /* TODO: Get input format from IPU (via FB driver interface) */
1523         hdmi->hdmi_data.enc_in_format = RGB;
1524
1525         hdmi->hdmi_data.enc_out_format = RGB;
1526
1527         hdmi->hdmi_data.enc_color_depth = 8;
1528         hdmi->hdmi_data.pix_repet_factor = 0;
1529         hdmi->hdmi_data.hdcp_enable = 0;
1530         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1531
1532         /* HDMI Initialization Step B.1 */
1533         hdmi_av_composer(hdmi, mode);
1534
1535         /* HDMI Initializateion Step B.2 */
1536         ret = dw_hdmi_phy_init(hdmi);
1537         if (ret)
1538                 return ret;
1539
1540         /* HDMI Initialization Step B.3 */
1541         dw_hdmi_enable_video_path(hdmi);
1542
1543         if (hdmi->sink_has_audio) {
1544                 dev_dbg(hdmi->dev, "sink has audio support\n");
1545
1546                 /* HDMI Initialization Step E - Configure audio */
1547                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1548                 hdmi_enable_audio_clk(hdmi);
1549         }
1550
1551         /* not for DVI mode */
1552         if (hdmi->sink_is_hdmi) {
1553                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1554
1555                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1556                 hdmi_config_AVI(hdmi, mode);
1557         } else {
1558                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1559         }
1560
1561         hdmi_video_packetize(hdmi);
1562         hdmi_video_csc(hdmi);
1563         hdmi_video_sample(hdmi);
1564         hdmi_tx_hdcp_config(hdmi);
1565
1566         dw_hdmi_clear_overflow(hdmi);
1567         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1568                 hdmi_enable_overflow_interrupts(hdmi);
1569
1570         return 0;
1571 }
1572
1573 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1574 {
1575         u8 ih_mute;
1576
1577         /*
1578          * Boot up defaults are:
1579          * HDMI_IH_MUTE   = 0x03 (disabled)
1580          * HDMI_IH_MUTE_* = 0x00 (enabled)
1581          *
1582          * Disable top level interrupt bits in HDMI block
1583          */
1584         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1585                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1586                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1587
1588         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1589
1590         /* by default mask all interrupts */
1591         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1592         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1593         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1594         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1595         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1596         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1597         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1598         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1599         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1600         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1601         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1602         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1603         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1604         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1605         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1606
1607         /* Disable interrupts in the IH_MUTE_* registers */
1608         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1609         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1610         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1611         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1612         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1613         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1614         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1615         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1616         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1617         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1618
1619         /* Enable top level interrupt bits in HDMI block */
1620         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1621                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1622         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1623 }
1624
1625 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1626 {
1627         hdmi->bridge_is_on = true;
1628         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1629 }
1630
1631 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1632 {
1633         dw_hdmi_phy_disable(hdmi);
1634         hdmi->bridge_is_on = false;
1635 }
1636
1637 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1638 {
1639         int force = hdmi->force;
1640
1641         if (hdmi->disabled) {
1642                 force = DRM_FORCE_OFF;
1643         } else if (force == DRM_FORCE_UNSPECIFIED) {
1644                 if (hdmi->rxsense)
1645                         force = DRM_FORCE_ON;
1646                 else
1647                         force = DRM_FORCE_OFF;
1648         }
1649
1650         if (force == DRM_FORCE_OFF) {
1651                 if (hdmi->bridge_is_on)
1652                         dw_hdmi_poweroff(hdmi);
1653         } else {
1654                 if (!hdmi->bridge_is_on)
1655                         dw_hdmi_poweron(hdmi);
1656         }
1657 }
1658
1659 /*
1660  * Adjust the detection of RXSENSE according to whether we have a forced
1661  * connection mode enabled, or whether we have been disabled.  There is
1662  * no point processing RXSENSE interrupts if we have a forced connection
1663  * state, or DRM has us disabled.
1664  *
1665  * We also disable rxsense interrupts when we think we're disconnected
1666  * to avoid floating TDMS signals giving false rxsense interrupts.
1667  *
1668  * Note: we still need to listen for HPD interrupts even when DRM has us
1669  * disabled so that we can detect a connect event.
1670  */
1671 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1672 {
1673         u8 old_mask = hdmi->phy_mask;
1674
1675         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1676                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1677         else
1678                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1679
1680         if (old_mask != hdmi->phy_mask)
1681                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1682 }
1683
1684 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1685                                     struct drm_display_mode *orig_mode,
1686                                     struct drm_display_mode *mode)
1687 {
1688         struct dw_hdmi *hdmi = bridge->driver_private;
1689
1690         mutex_lock(&hdmi->mutex);
1691
1692         /* Store the display mode for plugin/DKMS poweron events */
1693         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1694
1695         mutex_unlock(&hdmi->mutex);
1696 }
1697
1698 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1699 {
1700         struct dw_hdmi *hdmi = bridge->driver_private;
1701
1702         mutex_lock(&hdmi->mutex);
1703         hdmi->disabled = true;
1704         dw_hdmi_update_power(hdmi);
1705         dw_hdmi_update_phy_mask(hdmi);
1706         mutex_unlock(&hdmi->mutex);
1707 }
1708
1709 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1710 {
1711         struct dw_hdmi *hdmi = bridge->driver_private;
1712
1713         mutex_lock(&hdmi->mutex);
1714         hdmi->disabled = false;
1715         dw_hdmi_update_power(hdmi);
1716         dw_hdmi_update_phy_mask(hdmi);
1717         mutex_unlock(&hdmi->mutex);
1718 }
1719
1720 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1721 {
1722         /* do nothing */
1723 }
1724
1725 static enum drm_connector_status
1726 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1727 {
1728         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1729                                              connector);
1730
1731         mutex_lock(&hdmi->mutex);
1732         hdmi->force = DRM_FORCE_UNSPECIFIED;
1733         dw_hdmi_update_power(hdmi);
1734         dw_hdmi_update_phy_mask(hdmi);
1735         mutex_unlock(&hdmi->mutex);
1736
1737         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1738                 connector_status_connected : connector_status_disconnected;
1739 }
1740
1741 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1742 {
1743         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1744                                              connector);
1745         struct edid *edid;
1746         int ret = 0;
1747
1748         if (!hdmi->ddc)
1749                 return 0;
1750
1751         edid = drm_get_edid(connector, hdmi->ddc);
1752         if (edid) {
1753                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1754                         edid->width_cm, edid->height_cm);
1755
1756                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1757                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1758                 drm_mode_connector_update_edid_property(connector, edid);
1759                 ret = drm_add_edid_modes(connector, edid);
1760                 /* Store the ELD */
1761                 drm_edid_to_eld(connector, edid);
1762                 kfree(edid);
1763         } else {
1764                 dev_dbg(hdmi->dev, "failed to get edid\n");
1765         }
1766
1767         return ret;
1768 }
1769
1770 static enum drm_mode_status
1771 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1772                              struct drm_display_mode *mode)
1773 {
1774         struct dw_hdmi *hdmi = container_of(connector,
1775                                            struct dw_hdmi, connector);
1776         enum drm_mode_status mode_status = MODE_OK;
1777
1778         /* We don't support double-clocked modes */
1779         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1780                 return MODE_BAD;
1781
1782         if (hdmi->plat_data->mode_valid)
1783                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1784
1785         return mode_status;
1786 }
1787
1788 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1789                                                            *connector)
1790 {
1791         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1792                                              connector);
1793
1794         return hdmi->encoder;
1795 }
1796
1797 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1798 {
1799         drm_connector_unregister(connector);
1800         drm_connector_cleanup(connector);
1801 }
1802
1803 static void dw_hdmi_connector_force(struct drm_connector *connector)
1804 {
1805         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1806                                              connector);
1807
1808         mutex_lock(&hdmi->mutex);
1809         hdmi->force = connector->force;
1810         dw_hdmi_update_power(hdmi);
1811         dw_hdmi_update_phy_mask(hdmi);
1812         mutex_unlock(&hdmi->mutex);
1813 }
1814
1815 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1816         .dpms = drm_helper_connector_dpms,
1817         .fill_modes = drm_helper_probe_single_connector_modes,
1818         .detect = dw_hdmi_connector_detect,
1819         .destroy = dw_hdmi_connector_destroy,
1820         .force = dw_hdmi_connector_force,
1821 };
1822
1823 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1824         .dpms = drm_atomic_helper_connector_dpms,
1825         .fill_modes = drm_helper_probe_single_connector_modes,
1826         .detect = dw_hdmi_connector_detect,
1827         .destroy = dw_hdmi_connector_destroy,
1828         .force = dw_hdmi_connector_force,
1829         .reset = drm_atomic_helper_connector_reset,
1830         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1831         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1832 };
1833
1834 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1835         .get_modes = dw_hdmi_connector_get_modes,
1836         .mode_valid = dw_hdmi_connector_mode_valid,
1837         .best_encoder = dw_hdmi_connector_best_encoder,
1838 };
1839
1840 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1841         .enable = dw_hdmi_bridge_enable,
1842         .disable = dw_hdmi_bridge_disable,
1843         .pre_enable = dw_hdmi_bridge_nop,
1844         .post_disable = dw_hdmi_bridge_nop,
1845         .mode_set = dw_hdmi_bridge_mode_set,
1846 };
1847
1848 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1849 {
1850         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1851         unsigned int stat;
1852
1853         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1854         if (!stat)
1855                 return IRQ_NONE;
1856
1857         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1858
1859         i2c->stat = stat;
1860
1861         complete(&i2c->cmp);
1862
1863         return IRQ_HANDLED;
1864 }
1865
1866 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1867 {
1868         struct dw_hdmi *hdmi = dev_id;
1869         u8 intr_stat;
1870         irqreturn_t ret = IRQ_NONE;
1871
1872         if (hdmi->i2c)
1873                 ret = dw_hdmi_i2c_irq(hdmi);
1874
1875         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1876         if (intr_stat) {
1877                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1878                 return IRQ_WAKE_THREAD;
1879         }
1880
1881         return ret;
1882 }
1883
1884 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1885 {
1886         struct dw_hdmi *hdmi = dev_id;
1887         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1888
1889         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1890         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1891         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1892
1893         phy_pol_mask = 0;
1894         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1895                 phy_pol_mask |= HDMI_PHY_HPD;
1896         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1897                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1898         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1899                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1900         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1901                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1902         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1903                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1904
1905         if (phy_pol_mask)
1906                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1907
1908         /*
1909          * RX sense tells us whether the TDMS transmitters are detecting
1910          * load - in other words, there's something listening on the
1911          * other end of the link.  Use this to decide whether we should
1912          * power on the phy as HPD may be toggled by the sink to merely
1913          * ask the source to re-read the EDID.
1914          */
1915         if (intr_stat &
1916             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1917                 mutex_lock(&hdmi->mutex);
1918                 if (!hdmi->bridge_is_on && !hdmi->force) {
1919                         /*
1920                          * If the RX sense status indicates we're disconnected,
1921                          * clear the software rxsense status.
1922                          */
1923                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1924                                 hdmi->rxsense = false;
1925
1926                         /*
1927                          * Only set the software rxsense status when both
1928                          * rxsense and hpd indicates we're connected.
1929                          * This avoids what seems to be bad behaviour in
1930                          * at least iMX6S versions of the phy.
1931                          */
1932                         if (phy_stat & HDMI_PHY_HPD)
1933                                 hdmi->rxsense = true;
1934
1935                         dw_hdmi_update_power(hdmi);
1936                         dw_hdmi_update_phy_mask(hdmi);
1937                 }
1938                 mutex_unlock(&hdmi->mutex);
1939         }
1940
1941         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1942                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1943                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1944                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1945         }
1946
1947         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1948         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1949                     HDMI_IH_MUTE_PHY_STAT0);
1950
1951         return IRQ_HANDLED;
1952 }
1953
1954 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1955 {
1956         struct drm_encoder *encoder = hdmi->encoder;
1957         struct drm_bridge *bridge;
1958         int ret;
1959
1960         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1961         if (!bridge) {
1962                 DRM_ERROR("Failed to allocate drm bridge\n");
1963                 return -ENOMEM;
1964         }
1965
1966         hdmi->bridge = bridge;
1967         bridge->driver_private = hdmi;
1968         bridge->funcs = &dw_hdmi_bridge_funcs;
1969         ret = drm_bridge_attach(drm, bridge);
1970         if (ret) {
1971                 DRM_ERROR("Failed to initialize bridge with drm\n");
1972                 return -EINVAL;
1973         }
1974
1975         encoder->bridge = bridge;
1976         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1977         hdmi->connector.port = hdmi->dev->of_node;
1978
1979         drm_connector_helper_add(&hdmi->connector,
1980                                  &dw_hdmi_connector_helper_funcs);
1981
1982         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
1983                 drm_connector_init(drm, &hdmi->connector,
1984                                    &dw_hdmi_atomic_connector_funcs,
1985                                    DRM_MODE_CONNECTOR_HDMIA);
1986         else
1987                 drm_connector_init(drm, &hdmi->connector,
1988                                    &dw_hdmi_connector_funcs,
1989                                    DRM_MODE_CONNECTOR_HDMIA);
1990
1991         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1992
1993         return 0;
1994 }
1995
1996 int dw_hdmi_bind(struct device *dev, struct device *master,
1997                  void *data, struct drm_encoder *encoder,
1998                  struct resource *iores, int irq,
1999                  const struct dw_hdmi_plat_data *plat_data)
2000 {
2001         struct drm_device *drm = data;
2002         struct device_node *np = dev->of_node;
2003         struct platform_device_info pdevinfo;
2004         struct device_node *ddc_node;
2005         struct dw_hdmi *hdmi;
2006         int ret;
2007         u32 val = 1;
2008         u8 config0;
2009         u8 config1;
2010
2011         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2012         if (!hdmi)
2013                 return -ENOMEM;
2014
2015         hdmi->connector.interlace_allowed = 1;
2016
2017         hdmi->plat_data = plat_data;
2018         hdmi->dev = dev;
2019         hdmi->dev_type = plat_data->dev_type;
2020         hdmi->sample_rate = 48000;
2021         hdmi->encoder = encoder;
2022         hdmi->disabled = true;
2023         hdmi->rxsense = true;
2024         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2025
2026         mutex_init(&hdmi->mutex);
2027         mutex_init(&hdmi->audio_mutex);
2028         spin_lock_init(&hdmi->audio_lock);
2029
2030         of_property_read_u32(np, "reg-io-width", &val);
2031
2032         switch (val) {
2033         case 4:
2034                 hdmi->write = dw_hdmi_writel;
2035                 hdmi->read = dw_hdmi_readl;
2036                 break;
2037         case 1:
2038                 hdmi->write = dw_hdmi_writeb;
2039                 hdmi->read = dw_hdmi_readb;
2040                 break;
2041         default:
2042                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2043                 return -EINVAL;
2044         }
2045
2046         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2047         if (ddc_node) {
2048                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2049                 of_node_put(ddc_node);
2050                 if (!hdmi->ddc) {
2051                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2052                         return -EPROBE_DEFER;
2053                 }
2054
2055         } else {
2056                 dev_dbg(hdmi->dev, "no ddc property found\n");
2057         }
2058
2059         /* If DDC bus is not specified, try to register HDMI I2C bus */
2060         if (!hdmi->ddc) {
2061                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2062                 if (IS_ERR(hdmi->ddc))
2063                         hdmi->ddc = NULL;
2064         }
2065
2066         hdmi->regs = devm_ioremap_resource(dev, iores);
2067         if (IS_ERR(hdmi->regs))
2068                 return PTR_ERR(hdmi->regs);
2069
2070         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2071         if (IS_ERR(hdmi->isfr_clk)) {
2072                 ret = PTR_ERR(hdmi->isfr_clk);
2073                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2074                 return ret;
2075         }
2076
2077         ret = clk_prepare_enable(hdmi->isfr_clk);
2078         if (ret) {
2079                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2080                 return ret;
2081         }
2082
2083         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2084         if (IS_ERR(hdmi->iahb_clk)) {
2085                 ret = PTR_ERR(hdmi->iahb_clk);
2086                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2087                 goto err_isfr;
2088         }
2089
2090         ret = clk_prepare_enable(hdmi->iahb_clk);
2091         if (ret) {
2092                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2093                 goto err_isfr;
2094         }
2095
2096         /* Product and revision IDs */
2097         dev_info(dev,
2098                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2099                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2100                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2101                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2102                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2103
2104         initialize_hdmi_ih_mutes(hdmi);
2105
2106         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2107                                         dw_hdmi_irq, IRQF_SHARED,
2108                                         dev_name(dev), hdmi);
2109         if (ret)
2110                 goto err_iahb;
2111
2112         /*
2113          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2114          * N and cts values before enabling phy
2115          */
2116         hdmi_init_clk_regenerator(hdmi);
2117
2118         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2119                     HDMI_PHY_I2CM_INT_ADDR);
2120
2121         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2122                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2123                     HDMI_PHY_I2CM_CTLINT_ADDR);
2124
2125         /* Re-init HPD polarity */
2126         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2127
2128         /* Unmask HPD, clear transitory interrupts, then unmute */
2129         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2130
2131         ret = dw_hdmi_register(drm, hdmi);
2132         if (ret)
2133                 goto err_iahb;
2134
2135         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2136                     HDMI_IH_MUTE_PHY_STAT0);
2137
2138         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2139         if (hdmi->i2c)
2140                 dw_hdmi_i2c_init(hdmi);
2141
2142         memset(&pdevinfo, 0, sizeof(pdevinfo));
2143         pdevinfo.parent = dev;
2144         pdevinfo.id = PLATFORM_DEVID_AUTO;
2145
2146         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2147         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2148
2149         if (config1 & HDMI_CONFIG1_AHB) {
2150                 struct dw_hdmi_audio_data audio;
2151
2152                 audio.phys = iores->start;
2153                 audio.base = hdmi->regs;
2154                 audio.irq = irq;
2155                 audio.hdmi = hdmi;
2156                 audio.eld = hdmi->connector.eld;
2157
2158                 pdevinfo.name = "dw-hdmi-ahb-audio";
2159                 pdevinfo.data = &audio;
2160                 pdevinfo.size_data = sizeof(audio);
2161                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2162                 hdmi->audio = platform_device_register_full(&pdevinfo);
2163         } else if (config0 & HDMI_CONFIG0_I2S) {
2164                 struct dw_hdmi_i2s_audio_data audio;
2165
2166                 audio.hdmi      = hdmi;
2167                 audio.write     = hdmi_writeb;
2168                 audio.read      = hdmi_readb;
2169
2170                 pdevinfo.name = "dw-hdmi-i2s-audio";
2171                 pdevinfo.data = &audio;
2172                 pdevinfo.size_data = sizeof(audio);
2173                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2174                 hdmi->audio = platform_device_register_full(&pdevinfo);
2175         }
2176
2177         dev_set_drvdata(dev, hdmi);
2178
2179         return 0;
2180
2181 err_iahb:
2182         if (hdmi->i2c)
2183                 i2c_del_adapter(&hdmi->i2c->adap);
2184
2185         clk_disable_unprepare(hdmi->iahb_clk);
2186 err_isfr:
2187         clk_disable_unprepare(hdmi->isfr_clk);
2188
2189         return ret;
2190 }
2191 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2192
2193 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2194 {
2195         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2196
2197         if (hdmi->audio && !IS_ERR(hdmi->audio))
2198                 platform_device_unregister(hdmi->audio);
2199
2200         /* Disable all interrupts */
2201         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2202
2203         hdmi->connector.funcs->destroy(&hdmi->connector);
2204         hdmi->encoder->funcs->destroy(hdmi->encoder);
2205
2206         clk_disable_unprepare(hdmi->iahb_clk);
2207         clk_disable_unprepare(hdmi->isfr_clk);
2208
2209         if (hdmi->i2c)
2210                 i2c_del_adapter(&hdmi->i2c->adap);
2211         else
2212                 i2c_put_adapter(hdmi->ddc);
2213 }
2214 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2215
2216 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2217 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2218 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2219 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2220 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2221 MODULE_LICENSE("GPL");
2222 MODULE_ALIAS("platform:dw-hdmi");