drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/bridge/dw_hdmi.h>
  33 #ifdef CONFIG_SWITCH
  34 #include <linux/switch.h>
  35 #endif
  36
  37 #include "dw-hdmi.h"
  38 #include "dw-hdmi-audio.h"
  39
  40 #define HDMI_EDID_LEN           512
  41
  42 #define RGB                     0
  43 #define YCBCR444                1
  44 #define YCBCR422_16BITS         2
  45 #define YCBCR422_8BITS          3
  46 #define XVYCC444                4
  47
  48 enum hdmi_datamap {
  49         RGB444_8B = 0x01,
  50         RGB444_10B = 0x03,
  51         RGB444_12B = 0x05,
  52         RGB444_16B = 0x07,
  53         YCbCr444_8B = 0x09,
  54         YCbCr444_10B = 0x0B,
  55         YCbCr444_12B = 0x0D,
  56         YCbCr444_16B = 0x0F,
  57         YCbCr422_8B = 0x16,
  58         YCbCr422_10B = 0x14,
  59         YCbCr422_12B = 0x12,
  60 };
  61
  62 /*
  63  * Unless otherwise noted, entries in this table are 100% optimization.
  64  * Values can be obtained from hdmi_compute_n() but that function is
  65  * slow so we pre-compute values we expect to see.
  66  *
  67  * All 32k and 48k values are expected to be the same (due to the way
  68  * the math works) for any rate that's an exact kHz.
  69  */
  70 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  71         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  72         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  73         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  74         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  75         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  76         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  77         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  78         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  79         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  80         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  81         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  82         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  83         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  84         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  85         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  86         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  87         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  88         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  89         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  90         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  91         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  92         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  93         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  94         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  95         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  96         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  97         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  98         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  99         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 100         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 101         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 102         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 103         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 104         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 105         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 106         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 107         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 108
 109         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 110         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 111         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 112
 113         /* End of table */
 114         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 115 };
 116
 117
 118 static const u16 csc_coeff_default[3][4] = {
 119         { 0x2000, 0x0000, 0x0000, 0x0000 },
 120         { 0x0000, 0x2000, 0x0000, 0x0000 },
 121         { 0x0000, 0x0000, 0x2000, 0x0000 }
 122 };
 123
 124 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 125         { 0x2000, 0x6926, 0x74fd, 0x010e },
 126         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 127         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 128 };
 129
 130 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 131         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 132         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 133         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 134 };
 135
 136 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 137         { 0x2591, 0x1322, 0x074b, 0x0000 },
 138         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 139         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 140 };
 141
 142 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 143         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 144         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 145         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 146 };
 147
 148 struct hdmi_vmode {
 149         bool mdataenablepolarity;
 150
 151         unsigned int mpixelclock;
 152         unsigned int mpixelrepetitioninput;
 153         unsigned int mpixelrepetitionoutput;
 154 };
 155
 156 struct hdmi_data_info {
 157         unsigned int enc_in_format;
 158         unsigned int enc_out_format;
 159         unsigned int enc_color_depth;
 160         unsigned int colorimetry;
 161         unsigned int pix_repet_factor;
 162         unsigned int hdcp_enable;
 163         struct hdmi_vmode video_mode;
 164 };
 165
 166 struct dw_hdmi_i2c {
 167         struct i2c_adapter      adap;
 168
 169         struct mutex            lock;
 170         struct completion       cmp;
 171         u8                      stat;
 172
 173         u8                      slave_reg;
 174         bool                    is_regaddr;
 175 };
 176
 177 struct dw_hdmi {
 178         struct drm_connector connector;
 179         struct drm_encoder *encoder;
 180         struct drm_bridge *bridge;
 181
 182         struct platform_device *audio;
 183         enum dw_hdmi_devtype dev_type;
 184         struct device *dev;
 185         struct clk *isfr_clk;
 186         struct clk *iahb_clk;
 187         struct dw_hdmi_i2c *i2c;
 188
 189         struct hdmi_data_info hdmi_data;
 190         const struct dw_hdmi_plat_data *plat_data;
 191
 192         int vic;
 193
 194         u8 edid[HDMI_EDID_LEN];
 195         bool cable_plugin;
 196
 197         bool phy_enabled;
 198         struct drm_display_mode previous_mode;
 199
 200         struct i2c_adapter *ddc;
 201         void __iomem *regs;
 202         bool sink_is_hdmi;
 203         bool sink_has_audio;
 204
 205         struct mutex mutex;             /* for state below and previous_mode */
 206         enum drm_connector_force force; /* mutex-protected force state */
 207         bool disabled;                  /* DRM has disabled our bridge */
 208         bool bridge_is_on;              /* indicates the bridge is on */
 209         bool rxsense;                   /* rxsense state */
 210         u8 phy_mask;                    /* desired phy int mask settings */
 211
 212         spinlock_t audio_lock;
 213         struct mutex audio_mutex;
 214         unsigned int sample_rate;
 215         unsigned int audio_cts;
 216         unsigned int audio_n;
 217         bool audio_enable;
 218
 219 #ifdef CONFIG_SWITCH
 220         struct switch_dev switchdev;
 221 #endif
 222
 223         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 224         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 225 };
 226
 227 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 228         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 229          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 230
 231 #define HDMI_PHY_RX_SENSE \
 232         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 233          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 234
 235 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 236 {
 237         writel(val, hdmi->regs + (offset << 2));
 238 }
 239
 240 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 241 {
 242         return readl(hdmi->regs + (offset << 2));
 243 }
 244
 245 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 246 {
 247         writeb(val, hdmi->regs + offset);
 248 }
 249
 250 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 251 {
 252         return readb(hdmi->regs + offset);
 253 }
 254
 255 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 256 {
 257         hdmi->write(hdmi, val, offset);
 258 }
 259
 260 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 261 {
 262         return hdmi->read(hdmi, offset);
 263 }
 264
 265 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 266 {
 267         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 268
 269         val |= data & mask;
 270         hdmi_writeb(hdmi, val, reg);
 271 }
 272
 273 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 274                              u8 shift, u8 mask)
 275 {
 276         hdmi_modb(hdmi, data << shift, mask, reg);
 277 }
 278
 279 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 280 {
 281         /* Software reset */
 282         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 283
 284         /* Set Standard Mode speed */
 285         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 286                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 287
 288         /* Set done, not acknowledged and arbitration interrupt polarities */
 289         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 290         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 291                     HDMI_I2CM_CTLINT);
 292
 293         /* Clear DONE and ERROR interrupts */
 294         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 295                     HDMI_IH_I2CM_STAT0);
 296
 297         /* Mute DONE and ERROR interrupts */
 298         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 299                     HDMI_IH_MUTE_I2CM_STAT0);
 300 }
 301
 302 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 303                             unsigned char *buf, unsigned int length)
 304 {
 305         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 306         int stat;
 307
 308         if (!i2c->is_regaddr) {
 309                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 310                 i2c->slave_reg = 0x00;
 311                 i2c->is_regaddr = true;
 312         }
 313
 314         while (length--) {
 315                 reinit_completion(&i2c->cmp);
 316
 317                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 318                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 319                             HDMI_I2CM_OPERATION);
 320
 321                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 322                 if (!stat)
 323                         return -EAGAIN;
 324
 325                 /* Check for error condition on the bus */
 326                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 327                         return -EIO;
 328
 329                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 336                              unsigned char *buf, unsigned int length)
 337 {
 338         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 339         int stat;
 340
 341         if (!i2c->is_regaddr) {
 342                 /* Use the first write byte as register address */
 343                 i2c->slave_reg = buf[0];
 344                 length--;
 345                 buf++;
 346                 i2c->is_regaddr = true;
 347         }
 348
 349         while (length--) {
 350                 reinit_completion(&i2c->cmp);
 351
 352                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 353                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 354                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 355                             HDMI_I2CM_OPERATION);
 356
 357         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 358                 if (!stat)
 359                         return -EAGAIN;
 360
 361                 /* Check for error condition on the bus */
 362                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 363                         return -EIO;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 370                             struct i2c_msg *msgs, int num)
 371 {
 372         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 373         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 374         u8 addr = msgs[0].addr;
 375         int i, ret = 0;
 376
 377         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 378
 379         for (i = 0; i < num; i++) {
 380                 if (msgs[i].addr != addr) {
 381                         dev_warn(hdmi->dev,
 382                                  "unsupported transfer, changed slave address\n");
 383                         return -EOPNOTSUPP;
 384                 }
 385
 386                 if (msgs[i].len == 0) {
 387                         dev_dbg(hdmi->dev,
 388                                 "unsupported transfer %d/%d, no data\n",
 389                                 i + 1, num);
 390                         return -EOPNOTSUPP;
 391                 }
 392         }
 393
 394         mutex_lock(&i2c->lock);
 395
 396         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 397
 398         /* Set slave device address taken from the first I2C message */
 399         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 400
 401         /* Set slave device register address on transfer */
 402         i2c->is_regaddr = false;
 403
 404         for (i = 0; i < num; i++) {
 405                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 406                         i + 1, num, msgs[i].len, msgs[i].flags);
 407
 408                 if (msgs[i].flags & I2C_M_RD)
 409                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
 410                 else
 411                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
 412
 413                 if (ret < 0)
 414                         break;
 415         }
 416
 417         if (!ret)
 418                 ret = num;
 419
 420         /* Mute DONE and ERROR interrupts */
 421         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 422                     HDMI_IH_MUTE_I2CM_STAT0);
 423
 424         mutex_unlock(&i2c->lock);
 425
 426         return ret;
 427 }
 428
 429 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 430 {
 431         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 432 }
 433
 434 static const struct i2c_algorithm dw_hdmi_algorithm = {
 435         .master_xfer    = dw_hdmi_i2c_xfer,
 436         .functionality  = dw_hdmi_i2c_func,
 437 };
 438
 439 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 440 {
 441         struct i2c_adapter *adap;
 442         struct dw_hdmi_i2c *i2c;
 443         int ret;
 444
 445         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 446         if (!i2c)
 447                 return ERR_PTR(-ENOMEM);
 448
 449         mutex_init(&i2c->lock);
 450         init_completion(&i2c->cmp);
 451
 452         adap = &i2c->adap;
 453         adap->class = I2C_CLASS_DDC;
 454         adap->owner = THIS_MODULE;
 455         adap->dev.parent = hdmi->dev;
 456         adap->dev.of_node = hdmi->dev->of_node;
 457         adap->algo = &dw_hdmi_algorithm;
 458         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 459         i2c_set_adapdata(adap, hdmi);
 460
 461         ret = i2c_add_adapter(adap);
 462         if (ret) {
 463                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 464                 devm_kfree(hdmi->dev, i2c);
 465                 return ERR_PTR(ret);
 466         }
 467
 468         hdmi->i2c = i2c;
 469
 470         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 471
 472         return adap;
 473 }
 474
 475 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 476                            unsigned int n)
 477 {
 478         /* Must be set/cleared first */
 479         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 480
 481         /* nshift factor = 0 */
 482         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 483
 484         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 485                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 486         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 487         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 488
 489         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 490         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 491         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 492 }
 493
 494 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 495                                    unsigned long pixel_clk,
 496                                    unsigned long freq)
 497 {
 498         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 499         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 500         int i;
 501
 502         if (plat_data->tmds_n_table) {
 503                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 504                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 505                                 tmds_n = &plat_data->tmds_n_table[i];
 506                                 break;
 507                         }
 508                 }
 509         }
 510
 511         if (tmds_n == NULL) {
 512                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 513                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 514                                 tmds_n = &common_tmds_n_table[i];
 515                                 break;
 516                         }
 517                 }
 518         }
 519
 520         if (tmds_n == NULL)
 521                 return -ENOENT;
 522
 523         switch (freq) {
 524         case 32000:
 525                 return tmds_n->n_32k;
 526         case 44100:
 527         case 88200:
 528         case 176400:
 529                 return (freq / 44100) * tmds_n->n_44k1;
 530         case 48000:
 531         case 96000:
 532         case 192000:
 533                 return (freq / 48000) * tmds_n->n_48k;
 534         default:
 535                 return -ENOENT;
 536         }
 537 }
 538
 539 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 540                                 unsigned int pixel_clk)
 541 {
 542         u64 final, diff;
 543         u64 cts;
 544
 545         final = (u64)pixel_clk * n;
 546
 547         cts = final;
 548         do_div(cts, 128 * freq);
 549
 550         diff = final - (u64)cts * (128 * freq);
 551
 552         return diff;
 553 }
 554
 555 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 556                                    unsigned long pixel_clk,
 557                                    unsigned long freq)
 558 {
 559         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 560         unsigned int max_n = (128 * freq) / 300;
 561         unsigned int ideal_n = (128 * freq) / 1000;
 562         unsigned int best_n_distance = ideal_n;
 563         unsigned int best_n = 0;
 564         u64 best_diff = U64_MAX;
 565         int n;
 566
 567         /* If the ideal N could satisfy the audio math, then just take it */
 568         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 569                 return ideal_n;
 570
 571         for (n = min_n; n <= max_n; n++) {
 572                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 573
 574                 if (diff < best_diff || (diff == best_diff &&
 575                     abs(n - ideal_n) < best_n_distance)) {
 576                         best_n = n;
 577                         best_diff = diff;
 578                         best_n_distance = abs(best_n - ideal_n);
 579                 }
 580
 581                 /*
 582                  * The best N already satisfy the audio math, and also be
 583                  * the closest value to ideal N, so just cut the loop.
 584                  */
 585                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 586                         break;
 587         }
 588
 589         return best_n;
 590 }
 591
 592 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 593                                 unsigned long sample_rate)
 594 {
 595         int n;
 596
 597         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 598         if (n > 0)
 599                 return n;
 600
 601         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 602                  pixel_clk);
 603
 604         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 605 }
 606
 607 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 608         unsigned long pixel_clk, unsigned int sample_rate)
 609 {
 610         unsigned long ftdms = pixel_clk;
 611         unsigned int n, cts;
 612         u64 tmp;
 613
 614         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 615
 616         /*
 617          * Compute the CTS value from the N value.  Note that CTS and N
 618          * can be up to 20 bits in total, so we need 64-bit math.  Also
 619          * note that our TDMS clock is not fully accurate; it is accurate
 620          * to kHz.  This can introduce an unnecessary remainder in the
 621          * calculation below, so we don't try to warn about that.
 622          */
 623         tmp = (u64)ftdms * n;
 624         do_div(tmp, 128 * sample_rate);
 625         cts = tmp;
 626
 627         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 628                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 629                 n, cts);
 630
 631         spin_lock_irq(&hdmi->audio_lock);
 632         hdmi->audio_n = n;
 633         hdmi->audio_cts = cts;
 634         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 635         spin_unlock_irq(&hdmi->audio_lock);
 636 }
 637
 638 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 639 {
 640         mutex_lock(&hdmi->audio_mutex);
 641         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 642         mutex_unlock(&hdmi->audio_mutex);
 643 }
 644
 645 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 646 {
 647         mutex_lock(&hdmi->audio_mutex);
 648         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 649                                  hdmi->sample_rate);
 650         mutex_unlock(&hdmi->audio_mutex);
 651 }
 652
 653 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 654 {
 655         mutex_lock(&hdmi->audio_mutex);
 656         hdmi->sample_rate = rate;
 657         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 658                                  hdmi->sample_rate);
 659         mutex_unlock(&hdmi->audio_mutex);
 660 }
 661 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 662
 663 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 664 {
 665         unsigned long flags;
 666
 667         spin_lock_irqsave(&hdmi->audio_lock, flags);
 668         hdmi->audio_enable = true;
 669         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 670         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 671 }
 672 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 673
 674 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 675 {
 676         unsigned long flags;
 677
 678         spin_lock_irqsave(&hdmi->audio_lock, flags);
 679         hdmi->audio_enable = false;
 680         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 681         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 682 }
 683 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 684
 685 /*
 686  * this submodule is responsible for the video data synchronization.
 687  * for example, for RGB 4:4:4 input, the data map is defined as
 688  *                      pin{47~40} <==> R[7:0]
 689  *                      pin{31~24} <==> G[7:0]
 690  *                      pin{15~8}  <==> B[7:0]
 691  */
 692 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 693 {
 694         int color_format = 0;
 695         u8 val;
 696
 697         if (hdmi->hdmi_data.enc_in_format == RGB) {
 698                 if (hdmi->hdmi_data.enc_color_depth == 8)
 699                         color_format = 0x01;
 700                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 701                         color_format = 0x03;
 702                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 703                         color_format = 0x05;
 704                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 705                         color_format = 0x07;
 706                 else
 707                         return;
 708         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 709                 if (hdmi->hdmi_data.enc_color_depth == 8)
 710                         color_format = 0x09;
 711                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 712                         color_format = 0x0B;
 713                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 714                         color_format = 0x0D;
 715                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 716                         color_format = 0x0F;
 717                 else
 718                         return;
 719         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 720                 if (hdmi->hdmi_data.enc_color_depth == 8)
 721                         color_format = 0x16;
 722                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 723                         color_format = 0x14;
 724                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 725                         color_format = 0x12;
 726                 else
 727                         return;
 728         }
 729
 730         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 731                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 732                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 733         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 734
 735         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 736         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 737                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 738                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 739         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 740         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 741         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 742         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 743         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 744         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 745         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 746 }
 747
 748 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 749 {
 750         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 751 }
 752
 753 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 754 {
 755         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 756                 return 0;
 757         if (hdmi->hdmi_data.enc_in_format == RGB ||
 758             hdmi->hdmi_data.enc_in_format == YCBCR444)
 759                 return 1;
 760         return 0;
 761 }
 762
 763 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 764 {
 765         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 766                 return 0;
 767         if (hdmi->hdmi_data.enc_out_format == RGB ||
 768             hdmi->hdmi_data.enc_out_format == YCBCR444)
 769                 return 1;
 770         return 0;
 771 }
 772
 773 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 774 {
 775         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 776         unsigned i;
 777         u32 csc_scale = 1;
 778
 779         if (is_color_space_conversion(hdmi)) {
 780                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 781                         if (hdmi->hdmi_data.colorimetry ==
 782                                         HDMI_COLORIMETRY_ITU_601)
 783                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 784                         else
 785                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 786                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 787                         if (hdmi->hdmi_data.colorimetry ==
 788                                         HDMI_COLORIMETRY_ITU_601)
 789                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 790                         else
 791                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 792                         csc_scale = 0;
 793                 }
 794         }
 795
 796         /* The CSC registers are sequential, alternating MSB then LSB */
 797         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 798                 u16 coeff_a = (*csc_coeff)[0][i];
 799                 u16 coeff_b = (*csc_coeff)[1][i];
 800                 u16 coeff_c = (*csc_coeff)[2][i];
 801
 802                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 803                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 804                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 805                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 806                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 807                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 808         }
 809
 810         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 811                   HDMI_CSC_SCALE);
 812 }
 813
 814 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 815 {
 816         int color_depth = 0;
 817         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 818         int decimation = 0;
 819
 820         /* YCC422 interpolation to 444 mode */
 821         if (is_color_space_interpolation(hdmi))
 822                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 823         else if (is_color_space_decimation(hdmi))
 824                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 825
 826         if (hdmi->hdmi_data.enc_color_depth == 8)
 827                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 828         else if (hdmi->hdmi_data.enc_color_depth == 10)
 829                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 830         else if (hdmi->hdmi_data.enc_color_depth == 12)
 831                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 832         else if (hdmi->hdmi_data.enc_color_depth == 16)
 833                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 834         else
 835                 return;
 836
 837         /* Configure the CSC registers */
 838         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 839         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 840                   HDMI_CSC_SCALE);
 841
 842         dw_hdmi_update_csc_coeffs(hdmi);
 843 }
 844
 845 /*
 846  * HDMI video packetizer is used to packetize the data.
 847  * for example, if input is YCC422 mode or repeater is used,
 848  * data should be repacked this module can be bypassed.
 849  */
 850 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 851 {
 852         unsigned int color_depth = 0;
 853         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 854         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 855         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 856         u8 val, vp_conf;
 857
 858         if (hdmi_data->enc_out_format == RGB ||
 859             hdmi_data->enc_out_format == YCBCR444) {
 860                 if (!hdmi_data->enc_color_depth) {
 861                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 862                 } else if (hdmi_data->enc_color_depth == 8) {
 863                         color_depth = 4;
 864                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 865                 } else if (hdmi_data->enc_color_depth == 10) {
 866                         color_depth = 5;
 867                 } else if (hdmi_data->enc_color_depth == 12) {
 868                         color_depth = 6;
 869                 } else if (hdmi_data->enc_color_depth == 16) {
 870                         color_depth = 7;
 871                 } else {
 872                         return;
 873                 }
 874         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 875                 if (!hdmi_data->enc_color_depth ||
 876                     hdmi_data->enc_color_depth == 8)
 877                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 878                 else if (hdmi_data->enc_color_depth == 10)
 879                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 880                 else if (hdmi_data->enc_color_depth == 12)
 881                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 882                 else
 883                         return;
 884                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 885         } else {
 886                 return;
 887         }
 888
 889         /* set the packetizer registers */
 890         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 891                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 892                 ((hdmi_data->pix_repet_factor <<
 893                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 894                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 895         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 896
 897         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 898                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 899
 900         /* Data from pixel repeater block */
 901         if (hdmi_data->pix_repet_factor > 1) {
 902                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 903                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 904         } else { /* data from packetizer block */
 905                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 906                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 907         }
 908
 909         hdmi_modb(hdmi, vp_conf,
 910                   HDMI_VP_CONF_PR_EN_MASK |
 911                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 912
 913         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 914                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 915
 916         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 917
 918         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 919                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 920                           HDMI_VP_CONF_PP_EN_ENABLE |
 921                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 922         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 923                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 924                           HDMI_VP_CONF_PP_EN_DISABLE |
 925                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 926         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 927                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 928                           HDMI_VP_CONF_PP_EN_DISABLE |
 929                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 930         } else {
 931                 return;
 932         }
 933
 934         hdmi_modb(hdmi, vp_conf,
 935                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 936                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 937
 938         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 939                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 940                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 941                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 942
 943         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 944                   HDMI_VP_CONF);
 945 }
 946
 947 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 948                                        unsigned char bit)
 949 {
 950         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 951                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 952 }
 953
 954 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 955                                         unsigned char bit)
 956 {
 957         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 958                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 959 }
 960
 961 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 962                                        unsigned char bit)
 963 {
 964         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 965                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 966 }
 967
 968 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 969                                      unsigned char bit)
 970 {
 971         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 972 }
 973
 974 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 975                                       unsigned char bit)
 976 {
 977         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 978 }
 979
 980 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 981 {
 982         u32 val;
 983
 984         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 985                 if (msec-- == 0)
 986                         return false;
 987                 udelay(1000);
 988         }
 989         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 990
 991         return true;
 992 }
 993
 994 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 995                                  unsigned char addr)
 996 {
 997         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 998         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 999         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1000                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1001         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1002                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1003         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1004                     HDMI_PHY_I2CM_OPERATION_ADDR);
1005         hdmi_phy_wait_i2c_done(hdmi, 1000);
1006 }
1007
1008 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1009                               unsigned char addr)
1010 {
1011         __hdmi_phy_i2c_write(hdmi, data, addr);
1012         return 0;
1013 }
1014
1015 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1016 {
1017         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1018                          HDMI_PHY_CONF0_PDZ_OFFSET,
1019                          HDMI_PHY_CONF0_PDZ_MASK);
1020 }
1021
1022 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1023 {
1024         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1025                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1026                          HDMI_PHY_CONF0_ENTMDS_MASK);
1027 }
1028
1029 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1030 {
1031         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1032                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1033                          HDMI_PHY_CONF0_SPARECTRL_MASK);
1034 }
1035
1036 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1037 {
1038         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1039                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1040                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1041 }
1042
1043 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1044 {
1045         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1046                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1047                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1048 }
1049
1050 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1051 {
1052         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1053                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1054                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1055 }
1056
1057 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1058 {
1059         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1060                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1061                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1062 }
1063
1064 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1065                               unsigned char res, int cscon)
1066 {
1067         unsigned res_idx;
1068         u8 val, msec;
1069         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1070         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1071         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1072         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1073
1074         if (prep)
1075                 return -EINVAL;
1076
1077         switch (res) {
1078         case 0: /* color resolution 0 is 8 bit colour depth */
1079         case 8:
1080                 res_idx = DW_HDMI_RES_8;
1081                 break;
1082         case 10:
1083                 res_idx = DW_HDMI_RES_10;
1084                 break;
1085         case 12:
1086                 res_idx = DW_HDMI_RES_12;
1087                 break;
1088         default:
1089                 return -EINVAL;
1090         }
1091
1092         /* PLL/MPLL Cfg - always match on final entry */
1093         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1094                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1095                     mpll_config->mpixelclock)
1096                         break;
1097
1098         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1099                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1100                     curr_ctrl->mpixelclock)
1101                         break;
1102
1103         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1104                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1105                     phy_config->mpixelclock)
1106                         break;
1107
1108         if (mpll_config->mpixelclock == ~0UL ||
1109             curr_ctrl->mpixelclock == ~0UL ||
1110             phy_config->mpixelclock == ~0UL) {
1111                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1112                         hdmi->hdmi_data.video_mode.mpixelclock);
1113                 return -EINVAL;
1114         }
1115
1116         /* Enable csc path */
1117         if (cscon)
1118                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1119         else
1120                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1121
1122         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1123
1124         /* gen2 tx power off */
1125         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1126
1127         /* gen2 pddq */
1128         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1129
1130         /* PHY reset */
1131         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1132         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1133
1134         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1135
1136         hdmi_phy_test_clear(hdmi, 1);
1137         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1138                     HDMI_PHY_I2CM_SLAVE_ADDR);
1139         hdmi_phy_test_clear(hdmi, 0);
1140
1141         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1142         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1143
1144         /* CURRCTRL */
1145         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1146
1147         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1148         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1149
1150         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
1151         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1152         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1153
1154         /* REMOVE CLK TERM */
1155         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1156
1157         dw_hdmi_phy_enable_powerdown(hdmi, false);
1158
1159         /* toggle TMDS enable */
1160         dw_hdmi_phy_enable_tmds(hdmi, 0);
1161         dw_hdmi_phy_enable_tmds(hdmi, 1);
1162
1163         /* gen2 tx power on */
1164         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1165         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1166
1167         if (is_rockchip(hdmi->dev_type))
1168                 dw_hdmi_phy_enable_spare(hdmi, 1);
1169
1170         /*Wait for PHY PLL lock */
1171         msec = 5;
1172         do {
1173                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1174                 if (!val)
1175                         break;
1176
1177                 if (msec == 0) {
1178                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1179                         return -ETIMEDOUT;
1180                 }
1181
1182                 udelay(1000);
1183                 msec--;
1184         } while (1);
1185
1186         return 0;
1187 }
1188
1189 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1190 {
1191         int i, ret;
1192         bool cscon;
1193
1194         /*check csc whether needed activated in HDMI mode */
1195         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1196
1197         /* HDMI Phy spec says to do the phy initialization sequence twice */
1198         for (i = 0; i < 2; i++) {
1199                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1200                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1201                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1202                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1203
1204                 /* Enable CSC */
1205                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1206                 if (ret)
1207                         return ret;
1208         }
1209
1210         hdmi->phy_enabled = true;
1211         return 0;
1212 }
1213
1214 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1215 {
1216         u8 de;
1217
1218         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1219                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1220         else
1221                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1222
1223         /* disable rx detect */
1224         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1225                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1226
1227         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1228
1229         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1230                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1231 }
1232
1233 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1234 {
1235         struct hdmi_avi_infoframe frame;
1236         u8 val;
1237
1238         /* Initialise info frame from DRM mode */
1239         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1240
1241         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1242                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1243         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1244                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1245         else
1246                 frame.colorspace = HDMI_COLORSPACE_RGB;
1247
1248         /* Set up colorimetry */
1249         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1250                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1251                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1252                         frame.extended_colorimetry =
1253                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1254                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1255                         frame.extended_colorimetry =
1256                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1257         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1258                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1259                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1260         } else { /* Carries no data */
1261                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1262                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1263         }
1264
1265         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1266
1267         /*
1268          * The Designware IP uses a different byte format from standard
1269          * AVI info frames, though generally the bits are in the correct
1270          * bytes.
1271          */
1272
1273         /*
1274          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1275          * active aspect present in bit 6 rather than 4.
1276          */
1277         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1278         if (frame.active_aspect & 15)
1279                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1280         if (frame.top_bar || frame.bottom_bar)
1281                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1282         if (frame.left_bar || frame.right_bar)
1283                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1284         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1285
1286         /* AVI data byte 2 differences: none */
1287         val = ((frame.colorimetry & 0x3) << 6) |
1288               ((frame.picture_aspect & 0x3) << 4) |
1289               (frame.active_aspect & 0xf);
1290         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1291
1292         /* AVI data byte 3 differences: none */
1293         val = ((frame.extended_colorimetry & 0x7) << 4) |
1294               ((frame.quantization_range & 0x3) << 2) |
1295               (frame.nups & 0x3);
1296         if (frame.itc)
1297                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1298         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1299
1300         /* AVI data byte 4 differences: none */
1301         val = frame.video_code & 0x7f;
1302         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1303
1304         /* AVI Data Byte 5- set up input and output pixel repetition */
1305         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1306                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1307                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1308                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1309                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1310                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1311         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1312
1313         /*
1314          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1315          * ycc range in bits 2,3 rather than 6,7
1316          */
1317         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1318               (frame.content_type & 0x3);
1319         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1320
1321         /* AVI Data Bytes 6-13 */
1322         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1323         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1324         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1325         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1326         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1327         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1328         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1329         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1330 }
1331
1332 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1333                              const struct drm_display_mode *mode)
1334 {
1335         u8 inv_val;
1336         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1337         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1338         unsigned int vdisplay;
1339
1340         vmode->mpixelclock = mode->clock * 1000;
1341
1342         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1343
1344         /* Set up HDMI_FC_INVIDCONF */
1345         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1346                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1347                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1348
1349         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1350                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1351                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1352
1353         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1354                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1355                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1356
1357         inv_val |= (vmode->mdataenablepolarity ?
1358                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1359                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1360
1361         if (hdmi->vic == 39)
1362                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1363         else
1364                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1365                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1366                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1367
1368         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1369                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1370                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1371
1372         inv_val |= hdmi->sink_is_hdmi ?
1373                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1374                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1375
1376         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1377
1378         vdisplay = mode->vdisplay;
1379         vblank = mode->vtotal - mode->vdisplay;
1380         v_de_vs = mode->vsync_start - mode->vdisplay;
1381         vsync_len = mode->vsync_end - mode->vsync_start;
1382
1383         /*
1384          * When we're setting an interlaced mode, we need
1385          * to adjust the vertical timing to suit.
1386          */
1387         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1388                 vdisplay /= 2;
1389                 vblank /= 2;
1390                 v_de_vs /= 2;
1391                 vsync_len /= 2;
1392         }
1393
1394         /* Set up horizontal active pixel width */
1395         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1396         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1397
1398         /* Set up vertical active lines */
1399         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1400         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1401
1402         /* Set up horizontal blanking pixel region width */
1403         hblank = mode->htotal - mode->hdisplay;
1404         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1405         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1406
1407         /* Set up vertical blanking pixel region width */
1408         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1409
1410         /* Set up HSYNC active edge delay width (in pixel clks) */
1411         h_de_hs = mode->hsync_start - mode->hdisplay;
1412         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1413         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1414
1415         /* Set up VSYNC active edge delay (in lines) */
1416         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1417
1418         /* Set up HSYNC active pulse width (in pixel clks) */
1419         hsync_len = mode->hsync_end - mode->hsync_start;
1420         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1421         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1422
1423         /* Set up VSYNC active edge delay (in lines) */
1424         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1425 }
1426
1427 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1428 {
1429         if (!hdmi->phy_enabled)
1430                 return;
1431
1432         dw_hdmi_phy_enable_tmds(hdmi, 0);
1433         dw_hdmi_phy_enable_powerdown(hdmi, true);
1434
1435         hdmi->phy_enabled = false;
1436 }
1437
1438 /* HDMI Initialization Step B.4 */
1439 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1440 {
1441         u8 clkdis;
1442
1443         /* control period minimum duration */
1444         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1445         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1446         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1447
1448         /* Set to fill TMDS data channels */
1449         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1450         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1451         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1452
1453         /* Enable pixel clock and tmds data path */
1454         clkdis = 0x7F;
1455         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1456         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1457
1458         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1459         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1460
1461         /* Enable csc path */
1462         if (is_color_space_conversion(hdmi)) {
1463                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1464                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1465         }
1466 }
1467
1468 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1469 {
1470         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1471 }
1472
1473 /* Workaround to clear the overflow condition */
1474 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1475 {
1476         int count;
1477         u8 val;
1478
1479         /* TMDS software reset */
1480         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1481
1482         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1483         if (hdmi->dev_type == IMX6DL_HDMI) {
1484                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1485                 return;
1486         }
1487
1488         for (count = 0; count < 4; count++)
1489                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1490 }
1491
1492 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1493 {
1494         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1495         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1496 }
1497
1498 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1499 {
1500         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1501                     HDMI_IH_MUTE_FC_STAT2);
1502 }
1503
1504 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1505 {
1506         int ret;
1507
1508         hdmi_disable_overflow_interrupts(hdmi);
1509
1510         hdmi->vic = drm_match_cea_mode(mode);
1511
1512         if (!hdmi->vic) {
1513                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1514         } else {
1515                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1516         }
1517
1518         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1519             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1520             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1521             (hdmi->vic == 17) || (hdmi->vic == 18))
1522                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1523         else
1524                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1525
1526         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1527         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1528
1529         /* TODO: Get input format from IPU (via FB driver interface) */
1530         hdmi->hdmi_data.enc_in_format = RGB;
1531
1532         hdmi->hdmi_data.enc_out_format = RGB;
1533
1534         hdmi->hdmi_data.enc_color_depth = 8;
1535         hdmi->hdmi_data.pix_repet_factor = 0;
1536         hdmi->hdmi_data.hdcp_enable = 0;
1537         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1538
1539         /* HDMI Initialization Step B.1 */
1540         hdmi_av_composer(hdmi, mode);
1541
1542         /* HDMI Initializateion Step B.2 */
1543         ret = dw_hdmi_phy_init(hdmi);
1544         if (ret)
1545                 return ret;
1546
1547         /* HDMI Initialization Step B.3 */
1548         dw_hdmi_enable_video_path(hdmi);
1549
1550         if (hdmi->sink_has_audio) {
1551                 dev_dbg(hdmi->dev, "sink has audio support\n");
1552
1553                 /* HDMI Initialization Step E - Configure audio */
1554                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1555                 hdmi_enable_audio_clk(hdmi);
1556         }
1557
1558         /* not for DVI mode */
1559         if (hdmi->sink_is_hdmi) {
1560                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1561
1562                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1563                 hdmi_config_AVI(hdmi, mode);
1564         } else {
1565                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1566         }
1567
1568         hdmi_video_packetize(hdmi);
1569         hdmi_video_csc(hdmi);
1570         hdmi_video_sample(hdmi);
1571         hdmi_tx_hdcp_config(hdmi);
1572
1573         dw_hdmi_clear_overflow(hdmi);
1574         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1575                 hdmi_enable_overflow_interrupts(hdmi);
1576
1577         return 0;
1578 }
1579
1580 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1581 {
1582         u8 ih_mute;
1583
1584         /*
1585          * Boot up defaults are:
1586          * HDMI_IH_MUTE   = 0x03 (disabled)
1587          * HDMI_IH_MUTE_* = 0x00 (enabled)
1588          *
1589          * Disable top level interrupt bits in HDMI block
1590          */
1591         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1592                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1593                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1594
1595         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1596
1597         /* by default mask all interrupts */
1598         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1599         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1600         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1601         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1602         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1603         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1604         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1605         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1606         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1607         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1608         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1609         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1610         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1611         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1612         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1613
1614         /* Disable interrupts in the IH_MUTE_* registers */
1615         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1616         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1617         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1618         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1619         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1620         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1621         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1622         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1623         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1624         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1625
1626         /* Enable top level interrupt bits in HDMI block */
1627         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1628                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1629         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1630 }
1631
1632 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1633 {
1634         hdmi->bridge_is_on = true;
1635         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1636 }
1637
1638 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1639 {
1640         dw_hdmi_phy_disable(hdmi);
1641         hdmi->bridge_is_on = false;
1642 }
1643
1644 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1645 {
1646         int force = hdmi->force;
1647
1648         if (hdmi->disabled) {
1649                 force = DRM_FORCE_OFF;
1650         } else if (force == DRM_FORCE_UNSPECIFIED) {
1651                 if (hdmi->rxsense)
1652                         force = DRM_FORCE_ON;
1653                 else
1654                         force = DRM_FORCE_OFF;
1655         }
1656
1657         if (force == DRM_FORCE_OFF) {
1658                 if (hdmi->bridge_is_on)
1659                         dw_hdmi_poweroff(hdmi);
1660         } else {
1661                 if (!hdmi->bridge_is_on)
1662                         dw_hdmi_poweron(hdmi);
1663         }
1664 }
1665
1666 /*
1667  * Adjust the detection of RXSENSE according to whether we have a forced
1668  * connection mode enabled, or whether we have been disabled.  There is
1669  * no point processing RXSENSE interrupts if we have a forced connection
1670  * state, or DRM has us disabled.
1671  *
1672  * We also disable rxsense interrupts when we think we're disconnected
1673  * to avoid floating TDMS signals giving false rxsense interrupts.
1674  *
1675  * Note: we still need to listen for HPD interrupts even when DRM has us
1676  * disabled so that we can detect a connect event.
1677  */
1678 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1679 {
1680         u8 old_mask = hdmi->phy_mask;
1681
1682         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1683                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1684         else
1685                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1686
1687         if (old_mask != hdmi->phy_mask)
1688                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1689 }
1690
1691 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1692                                     struct drm_display_mode *orig_mode,
1693                                     struct drm_display_mode *mode)
1694 {
1695         struct dw_hdmi *hdmi = bridge->driver_private;
1696
1697         mutex_lock(&hdmi->mutex);
1698
1699         /* Store the display mode for plugin/DKMS poweron events */
1700         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1701
1702         mutex_unlock(&hdmi->mutex);
1703 }
1704
1705 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1706 {
1707         struct dw_hdmi *hdmi = bridge->driver_private;
1708
1709         mutex_lock(&hdmi->mutex);
1710         hdmi->disabled = true;
1711         dw_hdmi_update_power(hdmi);
1712         dw_hdmi_update_phy_mask(hdmi);
1713         mutex_unlock(&hdmi->mutex);
1714 }
1715
1716 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1717 {
1718         struct dw_hdmi *hdmi = bridge->driver_private;
1719
1720         mutex_lock(&hdmi->mutex);
1721         hdmi->disabled = false;
1722         dw_hdmi_update_power(hdmi);
1723         dw_hdmi_update_phy_mask(hdmi);
1724         mutex_unlock(&hdmi->mutex);
1725 }
1726
1727 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1728 {
1729         /* do nothing */
1730 }
1731
1732 static enum drm_connector_status
1733 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1734 {
1735         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1736                                              connector);
1737
1738         mutex_lock(&hdmi->mutex);
1739         hdmi->force = DRM_FORCE_UNSPECIFIED;
1740         dw_hdmi_update_power(hdmi);
1741         dw_hdmi_update_phy_mask(hdmi);
1742         mutex_unlock(&hdmi->mutex);
1743
1744         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1745                 connector_status_connected : connector_status_disconnected;
1746 }
1747
1748 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1749 {
1750         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1751                                              connector);
1752         struct edid *edid;
1753         int ret = 0;
1754
1755         if (!hdmi->ddc)
1756                 return 0;
1757
1758         edid = drm_get_edid(connector, hdmi->ddc);
1759         if (edid) {
1760                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1761                         edid->width_cm, edid->height_cm);
1762
1763                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1764                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1765                 drm_mode_connector_update_edid_property(connector, edid);
1766                 ret = drm_add_edid_modes(connector, edid);
1767                 /* Store the ELD */
1768                 drm_edid_to_eld(connector, edid);
1769                 kfree(edid);
1770         } else {
1771                 dev_dbg(hdmi->dev, "failed to get edid\n");
1772         }
1773
1774         return ret;
1775 }
1776
1777 static enum drm_mode_status
1778 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1779                              struct drm_display_mode *mode)
1780 {
1781         struct dw_hdmi *hdmi = container_of(connector,
1782                                            struct dw_hdmi, connector);
1783         enum drm_mode_status mode_status = MODE_OK;
1784
1785         /* We don't support double-clocked modes */
1786         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1787                 return MODE_BAD;
1788
1789         if (hdmi->plat_data->mode_valid)
1790                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1791
1792         return mode_status;
1793 }
1794
1795 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1796                                                            *connector)
1797 {
1798         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1799                                              connector);
1800
1801         return hdmi->encoder;
1802 }
1803
1804 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1805 {
1806         drm_connector_unregister(connector);
1807         drm_connector_cleanup(connector);
1808 }
1809
1810 static void dw_hdmi_connector_force(struct drm_connector *connector)
1811 {
1812         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1813                                              connector);
1814
1815         mutex_lock(&hdmi->mutex);
1816         hdmi->force = connector->force;
1817         dw_hdmi_update_power(hdmi);
1818         dw_hdmi_update_phy_mask(hdmi);
1819         mutex_unlock(&hdmi->mutex);
1820 }
1821
1822 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1823         .dpms = drm_helper_connector_dpms,
1824         .fill_modes = drm_helper_probe_single_connector_modes,
1825         .detect = dw_hdmi_connector_detect,
1826         .destroy = dw_hdmi_connector_destroy,
1827         .force = dw_hdmi_connector_force,
1828 };
1829
1830 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1831         .dpms = drm_atomic_helper_connector_dpms,
1832         .fill_modes = drm_helper_probe_single_connector_modes,
1833         .detect = dw_hdmi_connector_detect,
1834         .destroy = dw_hdmi_connector_destroy,
1835         .force = dw_hdmi_connector_force,
1836         .reset = drm_atomic_helper_connector_reset,
1837         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1838         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1839 };
1840
1841 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1842         .get_modes = dw_hdmi_connector_get_modes,
1843         .mode_valid = dw_hdmi_connector_mode_valid,
1844         .best_encoder = dw_hdmi_connector_best_encoder,
1845 };
1846
1847 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1848         .enable = dw_hdmi_bridge_enable,
1849         .disable = dw_hdmi_bridge_disable,
1850         .pre_enable = dw_hdmi_bridge_nop,
1851         .post_disable = dw_hdmi_bridge_nop,
1852         .mode_set = dw_hdmi_bridge_mode_set,
1853 };
1854
1855 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1856 {
1857         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1858         unsigned int stat;
1859
1860         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1861         if (!stat)
1862                 return IRQ_NONE;
1863
1864         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1865
1866         i2c->stat = stat;
1867
1868         complete(&i2c->cmp);
1869
1870         return IRQ_HANDLED;
1871 }
1872
1873 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1874 {
1875         struct dw_hdmi *hdmi = dev_id;
1876         u8 intr_stat;
1877         irqreturn_t ret = IRQ_NONE;
1878
1879         if (hdmi->i2c)
1880                 ret = dw_hdmi_i2c_irq(hdmi);
1881
1882         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1883         if (intr_stat) {
1884                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1885                 return IRQ_WAKE_THREAD;
1886         }
1887
1888         return ret;
1889 }
1890
1891 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1892 {
1893         struct dw_hdmi *hdmi = dev_id;
1894         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1895
1896         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1897         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1898         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1899
1900         phy_pol_mask = 0;
1901         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1902                 phy_pol_mask |= HDMI_PHY_HPD;
1903         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1904                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1905         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1906                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1907         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1908                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1909         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1910                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1911
1912         if (phy_pol_mask)
1913                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1914
1915         /*
1916          * RX sense tells us whether the TDMS transmitters are detecting
1917          * load - in other words, there's something listening on the
1918          * other end of the link.  Use this to decide whether we should
1919          * power on the phy as HPD may be toggled by the sink to merely
1920          * ask the source to re-read the EDID.
1921          */
1922         if (intr_stat &
1923             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1924                 mutex_lock(&hdmi->mutex);
1925                 if (!hdmi->bridge_is_on && !hdmi->force) {
1926                         /*
1927                          * If the RX sense status indicates we're disconnected,
1928                          * clear the software rxsense status.
1929                          */
1930                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1931                                 hdmi->rxsense = false;
1932
1933                         /*
1934                          * Only set the software rxsense status when both
1935                          * rxsense and hpd indicates we're connected.
1936                          * This avoids what seems to be bad behaviour in
1937                          * at least iMX6S versions of the phy.
1938                          */
1939                         if (phy_stat & HDMI_PHY_HPD)
1940                                 hdmi->rxsense = true;
1941
1942                         dw_hdmi_update_power(hdmi);
1943                         dw_hdmi_update_phy_mask(hdmi);
1944                 }
1945                 mutex_unlock(&hdmi->mutex);
1946         }
1947
1948         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1949                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1950                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1951                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1952 #ifdef CONFIG_SWITCH
1953                 if (phy_int_pol & HDMI_PHY_HPD)
1954                         switch_set_state(&hdmi->switchdev, 1);
1955                 else
1956                         switch_set_state(&hdmi->switchdev, 0);
1957 #endif
1958         }
1959
1960         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1961         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1962                     HDMI_IH_MUTE_PHY_STAT0);
1963
1964         return IRQ_HANDLED;
1965 }
1966
1967 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1968 {
1969         struct drm_encoder *encoder = hdmi->encoder;
1970         struct drm_bridge *bridge;
1971         int ret;
1972
1973         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1974         if (!bridge) {
1975                 DRM_ERROR("Failed to allocate drm bridge\n");
1976                 return -ENOMEM;
1977         }
1978
1979         hdmi->bridge = bridge;
1980         bridge->driver_private = hdmi;
1981         bridge->funcs = &dw_hdmi_bridge_funcs;
1982         ret = drm_bridge_attach(drm, bridge);
1983         if (ret) {
1984                 DRM_ERROR("Failed to initialize bridge with drm\n");
1985                 return -EINVAL;
1986         }
1987
1988         encoder->bridge = bridge;
1989         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1990         hdmi->connector.port = hdmi->dev->of_node;
1991
1992         drm_connector_helper_add(&hdmi->connector,
1993                                  &dw_hdmi_connector_helper_funcs);
1994
1995         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
1996                 drm_connector_init(drm, &hdmi->connector,
1997                                    &dw_hdmi_atomic_connector_funcs,
1998                                    DRM_MODE_CONNECTOR_HDMIA);
1999         else
2000                 drm_connector_init(drm, &hdmi->connector,
2001                                    &dw_hdmi_connector_funcs,
2002                                    DRM_MODE_CONNECTOR_HDMIA);
2003
2004         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2005
2006         return 0;
2007 }
2008
2009 int dw_hdmi_bind(struct device *dev, struct device *master,
2010                  void *data, struct drm_encoder *encoder,
2011                  struct resource *iores, int irq,
2012                  const struct dw_hdmi_plat_data *plat_data)
2013 {
2014         struct drm_device *drm = data;
2015         struct device_node *np = dev->of_node;
2016         struct platform_device_info pdevinfo;
2017         struct device_node *ddc_node;
2018         struct dw_hdmi *hdmi;
2019         int ret;
2020         u32 val = 1;
2021         u8 config0;
2022         u8 config1;
2023
2024         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2025         if (!hdmi)
2026                 return -ENOMEM;
2027
2028         hdmi->connector.interlace_allowed = 1;
2029
2030         hdmi->plat_data = plat_data;
2031         hdmi->dev = dev;
2032         hdmi->dev_type = plat_data->dev_type;
2033         hdmi->sample_rate = 48000;
2034         hdmi->encoder = encoder;
2035         hdmi->disabled = true;
2036         hdmi->rxsense = true;
2037         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2038
2039         mutex_init(&hdmi->mutex);
2040         mutex_init(&hdmi->audio_mutex);
2041         spin_lock_init(&hdmi->audio_lock);
2042
2043         of_property_read_u32(np, "reg-io-width", &val);
2044
2045         switch (val) {
2046         case 4:
2047                 hdmi->write = dw_hdmi_writel;
2048                 hdmi->read = dw_hdmi_readl;
2049                 break;
2050         case 1:
2051                 hdmi->write = dw_hdmi_writeb;
2052                 hdmi->read = dw_hdmi_readb;
2053                 break;
2054         default:
2055                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2056                 return -EINVAL;
2057         }
2058
2059         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2060         if (ddc_node) {
2061                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2062                 of_node_put(ddc_node);
2063                 if (!hdmi->ddc) {
2064                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2065                         return -EPROBE_DEFER;
2066                 }
2067
2068         } else {
2069                 dev_dbg(hdmi->dev, "no ddc property found\n");
2070         }
2071
2072         /* If DDC bus is not specified, try to register HDMI I2C bus */
2073         if (!hdmi->ddc) {
2074                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2075                 if (IS_ERR(hdmi->ddc))
2076                         hdmi->ddc = NULL;
2077         }
2078
2079         hdmi->regs = devm_ioremap_resource(dev, iores);
2080         if (IS_ERR(hdmi->regs))
2081                 return PTR_ERR(hdmi->regs);
2082
2083         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2084         if (IS_ERR(hdmi->isfr_clk)) {
2085                 ret = PTR_ERR(hdmi->isfr_clk);
2086                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2087                 return ret;
2088         }
2089
2090         ret = clk_prepare_enable(hdmi->isfr_clk);
2091         if (ret) {
2092                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2093                 return ret;
2094         }
2095
2096         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2097         if (IS_ERR(hdmi->iahb_clk)) {
2098                 ret = PTR_ERR(hdmi->iahb_clk);
2099                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2100                 goto err_isfr;
2101         }
2102
2103         ret = clk_prepare_enable(hdmi->iahb_clk);
2104         if (ret) {
2105                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2106                 goto err_isfr;
2107         }
2108
2109         /* Product and revision IDs */
2110         dev_info(dev,
2111                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2112                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
2113                  hdmi_readb(hdmi, HDMI_REVISION_ID),
2114                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2115                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2116
2117         initialize_hdmi_ih_mutes(hdmi);
2118
2119         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2120                                         dw_hdmi_irq, IRQF_SHARED,
2121                                         dev_name(dev), hdmi);
2122         if (ret)
2123                 goto err_iahb;
2124
2125         /*
2126          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2127          * N and cts values before enabling phy
2128          */
2129         hdmi_init_clk_regenerator(hdmi);
2130
2131         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2132                     HDMI_PHY_I2CM_INT_ADDR);
2133
2134         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2135                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2136                     HDMI_PHY_I2CM_CTLINT_ADDR);
2137
2138         /* Re-init HPD polarity */
2139         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2140
2141         /* Unmask HPD, clear transitory interrupts, then unmute */
2142         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2143
2144         ret = dw_hdmi_register(drm, hdmi);
2145         if (ret)
2146                 goto err_iahb;
2147
2148 #ifdef CONFIG_SWITCH
2149         hdmi->switchdev.name = "hdmi";
2150         switch_dev_register(&hdmi->switchdev);
2151 #endif
2152
2153         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2154                     HDMI_IH_MUTE_PHY_STAT0);
2155
2156         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2157         if (hdmi->i2c)
2158                 dw_hdmi_i2c_init(hdmi);
2159
2160         memset(&pdevinfo, 0, sizeof(pdevinfo));
2161         pdevinfo.parent = dev;
2162         pdevinfo.id = PLATFORM_DEVID_AUTO;
2163
2164         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2165         config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2166
2167         if (config1 & HDMI_CONFIG1_AHB) {
2168                 struct dw_hdmi_audio_data audio;
2169
2170                 audio.phys = iores->start;
2171                 audio.base = hdmi->regs;
2172                 audio.irq = irq;
2173                 audio.hdmi = hdmi;
2174                 audio.eld = hdmi->connector.eld;
2175
2176                 pdevinfo.name = "dw-hdmi-ahb-audio";
2177                 pdevinfo.data = &audio;
2178                 pdevinfo.size_data = sizeof(audio);
2179                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2180                 hdmi->audio = platform_device_register_full(&pdevinfo);
2181         } else if (config0 & HDMI_CONFIG0_I2S) {
2182                 struct dw_hdmi_i2s_audio_data audio;
2183
2184                 audio.hdmi      = hdmi;
2185                 audio.write     = hdmi_writeb;
2186                 audio.read      = hdmi_readb;
2187
2188                 pdevinfo.name = "dw-hdmi-i2s-audio";
2189                 pdevinfo.data = &audio;
2190                 pdevinfo.size_data = sizeof(audio);
2191                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2192                 hdmi->audio = platform_device_register_full(&pdevinfo);
2193         }
2194
2195         dev_set_drvdata(dev, hdmi);
2196
2197         return 0;
2198
2199 err_iahb:
2200         if (hdmi->i2c)
2201                 i2c_del_adapter(&hdmi->i2c->adap);
2202
2203         clk_disable_unprepare(hdmi->iahb_clk);
2204 err_isfr:
2205         clk_disable_unprepare(hdmi->isfr_clk);
2206
2207         return ret;
2208 }
2209 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2210
2211 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2212 {
2213         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2214
2215         if (hdmi->audio && !IS_ERR(hdmi->audio))
2216                 platform_device_unregister(hdmi->audio);
2217
2218         /* Disable all interrupts */
2219         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2220
2221 #ifdef CONFIG_SWITCH
2222         switch_dev_unregister(&hdmi->switchdev);
2223 #endif
2224         hdmi->connector.funcs->destroy(&hdmi->connector);
2225         hdmi->encoder->funcs->destroy(hdmi->encoder);
2226
2227         clk_disable_unprepare(hdmi->iahb_clk);
2228         clk_disable_unprepare(hdmi->isfr_clk);
2229
2230         if (hdmi->i2c)
2231                 i2c_del_adapter(&hdmi->i2c->adap);
2232         else
2233                 i2c_put_adapter(hdmi->ddc);
2234 }
2235 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2236
2237 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2238 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2239 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2240 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2241 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2242 MODULE_LICENSE("GPL");
2243 MODULE_ALIAS("platform:dw-hdmi");